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TARGET_EFM32PG12_STK3402/TOOLCHAIN_GCC_ARM/efm32pg12b_timer.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32pg12b_timer.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32PG12B_TIMER register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32PG12B_TIMER |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32PG12B_TIMER Register Declaration |
| AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | __IOM uint32_t CMD; /**< Command Register */ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IM uint32_t STATUS; /**< Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | __IOM uint32_t TOP; /**< Counter Top Value Register */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IOM uint32_t CNT; /**< Counter Value Register */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 54 | __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 58 | __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | uint32_t RESERVED2[8]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | __IOM uint32_t DTCTRL; /**< DTI Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | __IOM uint32_t DTTIME; /**< DTI Time Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | __IM uint32_t DTFAULT; /**< DTI Fault Register */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | } TIMER_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | |
| AnnaBridge | 171:3a7713b1edbc | 72 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 73 | * @defgroup EFM32PG12B_TIMER_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 74 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 75 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | /* Bit fields for TIMER CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | #define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | |
| AnnaBridge | 171:3a7713b1edbc | 197 | /* Bit fields for TIMER CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | |
| AnnaBridge | 171:3a7713b1edbc | 211 | /* Bit fields for TIMER STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | |
| AnnaBridge | 171:3a7713b1edbc | 310 | /* Bit fields for TIMER IF */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | |
| AnnaBridge | 171:3a7713b1edbc | 369 | /* Bit fields for TIMER IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | |
| AnnaBridge | 171:3a7713b1edbc | 428 | /* Bit fields for TIMER IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | |
| AnnaBridge | 171:3a7713b1edbc | 487 | /* Bit fields for TIMER IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | #define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | #define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | #define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 504 | #define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | #define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | #define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | #define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | #define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | #define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 514 | #define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | #define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | #define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 517 | #define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | #define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | #define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | #define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | #define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | #define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | #define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | |
| AnnaBridge | 171:3a7713b1edbc | 546 | /* Bit fields for TIMER TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | |
| AnnaBridge | 171:3a7713b1edbc | 554 | /* Bit fields for TIMER TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | #define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | |
| AnnaBridge | 171:3a7713b1edbc | 562 | /* Bit fields for TIMER CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | |
| AnnaBridge | 171:3a7713b1edbc | 570 | /* Bit fields for TIMER LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | #define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | #define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | #define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | #define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 585 | |
| AnnaBridge | 171:3a7713b1edbc | 586 | /* Bit fields for TIMER ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 597 | #define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | #define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | #define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 602 | #define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | #define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | #define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | #define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 616 | #define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | #define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | #define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 619 | #define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 620 | #define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | #define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | #define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | |
| AnnaBridge | 171:3a7713b1edbc | 625 | /* Bit fields for TIMER ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 632 | #define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 635 | #define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 636 | #define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | #define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 639 | #define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 640 | #define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 641 | #define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 642 | #define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 644 | #define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 645 | #define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | #define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 649 | #define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 651 | #define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 653 | #define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | #define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 655 | #define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 656 | #define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 657 | #define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 658 | #define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 659 | #define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | #define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 661 | #define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 663 | #define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 664 | #define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 666 | #define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 668 | #define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 670 | #define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 672 | #define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 673 | #define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 674 | #define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 675 | #define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | #define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | #define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 678 | #define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 679 | #define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 680 | #define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 681 | #define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 683 | #define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 684 | #define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 685 | #define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | #define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 687 | #define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 688 | #define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 689 | #define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 690 | #define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 691 | #define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 692 | #define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 693 | #define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 694 | #define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 695 | #define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 696 | #define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 697 | #define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 698 | #define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 701 | #define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 702 | #define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 703 | #define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 704 | #define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 705 | #define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 706 | #define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 707 | #define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 708 | #define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | #define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | #define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | #define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 714 | #define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 715 | #define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 717 | #define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 718 | #define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 719 | #define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | #define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | #define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 723 | #define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 725 | #define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 727 | #define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 728 | #define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | #define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 730 | #define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 731 | #define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 732 | #define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 734 | #define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 735 | #define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 736 | #define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 739 | #define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 740 | #define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 741 | #define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 742 | #define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 744 | #define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | #define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 746 | #define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 747 | #define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 748 | #define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 749 | #define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 750 | #define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 751 | #define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 752 | #define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 754 | #define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 755 | #define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 757 | #define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 758 | #define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 759 | #define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | #define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 762 | #define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 763 | #define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | #define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 766 | #define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 768 | #define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 769 | #define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 770 | #define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 771 | #define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 772 | #define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 773 | #define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 774 | #define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 775 | #define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 777 | #define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 779 | #define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 780 | #define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 781 | #define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 782 | #define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 783 | #define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 784 | #define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 785 | #define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 787 | #define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 789 | #define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 790 | #define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 791 | #define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 792 | #define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 793 | #define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | #define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 795 | #define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 796 | #define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 797 | #define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 798 | #define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 799 | #define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 800 | #define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 801 | #define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 802 | #define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 803 | #define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 804 | #define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 805 | #define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 806 | #define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 807 | #define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 808 | #define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 809 | #define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 810 | #define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 811 | #define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 812 | #define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 813 | #define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 814 | #define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 816 | #define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 817 | #define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 818 | #define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 820 | #define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 821 | #define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 822 | #define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 823 | #define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 825 | #define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 826 | #define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 827 | #define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 828 | #define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 829 | #define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 831 | #define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 832 | #define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 833 | #define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 834 | #define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 835 | #define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 836 | #define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 837 | #define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 838 | #define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 839 | #define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 840 | #define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 841 | #define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 842 | #define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 843 | #define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 844 | #define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 845 | #define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 846 | #define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 847 | #define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 848 | #define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 849 | #define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 850 | #define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 851 | #define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 852 | #define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 853 | #define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 854 | #define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 855 | #define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 856 | #define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 857 | #define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 858 | #define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 859 | #define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 860 | #define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 861 | #define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 862 | #define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 863 | #define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 864 | #define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 865 | #define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 866 | #define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 867 | #define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 868 | #define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 869 | #define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 870 | #define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 871 | #define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 872 | #define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 873 | #define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 874 | #define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 875 | #define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 876 | #define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 877 | #define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 878 | #define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 879 | #define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 880 | #define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 881 | #define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 882 | #define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 883 | #define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 884 | #define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 885 | #define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 886 | #define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 887 | #define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 888 | #define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 889 | #define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 890 | #define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 891 | #define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 892 | #define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 893 | #define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 894 | #define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 895 | #define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 896 | #define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 897 | #define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 898 | #define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 899 | #define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 900 | |
| AnnaBridge | 171:3a7713b1edbc | 901 | /* Bit fields for TIMER ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 902 | #define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 903 | #define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 904 | #define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 905 | #define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 906 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 907 | #define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 908 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 909 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 910 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 911 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 912 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 913 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 914 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 915 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 916 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 917 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 918 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 919 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 920 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 921 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 922 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 923 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 924 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 925 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 926 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 927 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 928 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 929 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 930 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 931 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 932 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 933 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 934 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 935 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 936 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 937 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 938 | #define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 939 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 940 | #define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 941 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 942 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 943 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 944 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 945 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 946 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 947 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 948 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 949 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 950 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 951 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 952 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 953 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 954 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 955 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 956 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 957 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 958 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 959 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 960 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 961 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 962 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 963 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 964 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 965 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 966 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 967 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 968 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 969 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 970 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 971 | #define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 972 | #define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 973 | #define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 974 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 975 | #define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 976 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 977 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 978 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 979 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 980 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 981 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 982 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 983 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 984 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 985 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 986 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 987 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 988 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 989 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 990 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 991 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 992 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 993 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 994 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 995 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 996 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 997 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 998 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 999 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1000 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1001 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1002 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1003 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1004 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1005 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1006 | #define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1007 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1008 | #define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1009 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1010 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1011 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1012 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1013 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1014 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1015 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1016 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1017 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1018 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1019 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1020 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1021 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1022 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1023 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1024 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1025 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1026 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1027 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1028 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1029 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1030 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1031 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1032 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1033 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1034 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1035 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1036 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1037 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1038 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1039 | #define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1040 | #define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 1041 | #define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ |
| AnnaBridge | 171:3a7713b1edbc | 1042 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1043 | #define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1044 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1045 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1046 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1047 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1048 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1049 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1050 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1051 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1052 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1053 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1054 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1055 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1056 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1057 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1058 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1059 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1060 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1061 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1062 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1063 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1064 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1065 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1066 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1067 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1068 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1069 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1070 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1071 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1072 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1073 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1074 | #define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1075 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1076 | #define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1077 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1078 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1079 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1080 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1081 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1082 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1083 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1084 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1085 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1086 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1087 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1088 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1089 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1090 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1091 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1092 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1093 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1094 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1095 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1096 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1097 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1098 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1099 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1100 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1101 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1102 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1103 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1104 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1105 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1106 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1107 | #define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1108 | |
| AnnaBridge | 171:3a7713b1edbc | 1109 | /* Bit fields for TIMER CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1110 | #define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1111 | #define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1112 | #define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 1113 | #define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 1114 | #define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1115 | #define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1116 | #define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1117 | #define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1118 | #define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1119 | #define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1120 | #define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1121 | #define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1122 | #define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1123 | #define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1124 | #define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ |
| AnnaBridge | 171:3a7713b1edbc | 1125 | #define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ |
| AnnaBridge | 171:3a7713b1edbc | 1126 | #define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ |
| AnnaBridge | 171:3a7713b1edbc | 1127 | #define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1128 | #define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1129 | #define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ |
| AnnaBridge | 171:3a7713b1edbc | 1130 | #define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ |
| AnnaBridge | 171:3a7713b1edbc | 1131 | #define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ |
| AnnaBridge | 171:3a7713b1edbc | 1132 | #define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1133 | #define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1134 | #define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ |
| AnnaBridge | 171:3a7713b1edbc | 1135 | #define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ |
| AnnaBridge | 171:3a7713b1edbc | 1136 | #define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1137 | #define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1138 | #define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1139 | #define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1140 | #define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1141 | #define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1142 | #define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1143 | #define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1144 | #define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1145 | #define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1146 | #define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ |
| AnnaBridge | 171:3a7713b1edbc | 1147 | #define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ |
| AnnaBridge | 171:3a7713b1edbc | 1148 | #define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1149 | #define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1150 | #define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1151 | #define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1152 | #define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1153 | #define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1154 | #define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1155 | #define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1156 | #define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1157 | #define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1158 | #define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ |
| AnnaBridge | 171:3a7713b1edbc | 1159 | #define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ |
| AnnaBridge | 171:3a7713b1edbc | 1160 | #define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1161 | #define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1162 | #define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1163 | #define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1164 | #define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1165 | #define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1166 | #define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1167 | #define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1168 | #define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1169 | #define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1170 | #define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1171 | #define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1172 | #define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1173 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1174 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1175 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1176 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1177 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1178 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1179 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1180 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1181 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1182 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1183 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1184 | #define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1185 | #define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1186 | #define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1187 | #define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1188 | #define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1189 | #define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1190 | #define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1191 | #define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1192 | #define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1193 | #define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1194 | #define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1195 | #define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1196 | #define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1197 | #define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1198 | #define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ |
| AnnaBridge | 171:3a7713b1edbc | 1199 | #define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ |
| AnnaBridge | 171:3a7713b1edbc | 1200 | #define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1201 | #define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1202 | #define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1203 | #define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1204 | #define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1205 | #define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1206 | #define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1207 | #define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1208 | #define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1209 | #define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1210 | #define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1211 | #define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1212 | #define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1213 | #define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1214 | #define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1215 | #define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1216 | #define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1217 | #define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1218 | #define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1219 | #define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1220 | #define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1221 | #define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1222 | #define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 1223 | #define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ |
| AnnaBridge | 171:3a7713b1edbc | 1224 | #define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ |
| AnnaBridge | 171:3a7713b1edbc | 1225 | #define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1226 | #define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1227 | #define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1228 | #define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1229 | #define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1230 | #define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1231 | #define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ |
| AnnaBridge | 171:3a7713b1edbc | 1232 | #define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1233 | #define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1234 | #define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1235 | #define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1236 | #define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1237 | #define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1238 | #define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1239 | #define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1240 | #define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ |
| AnnaBridge | 171:3a7713b1edbc | 1241 | #define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ |
| AnnaBridge | 171:3a7713b1edbc | 1242 | #define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ |
| AnnaBridge | 171:3a7713b1edbc | 1243 | #define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1244 | #define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1245 | #define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1246 | #define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1247 | #define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1248 | #define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1249 | |
| AnnaBridge | 171:3a7713b1edbc | 1250 | /* Bit fields for TIMER CC_CCV */ |
| AnnaBridge | 171:3a7713b1edbc | 1251 | #define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ |
| AnnaBridge | 171:3a7713b1edbc | 1252 | #define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ |
| AnnaBridge | 171:3a7713b1edbc | 1253 | #define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ |
| AnnaBridge | 171:3a7713b1edbc | 1254 | #define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ |
| AnnaBridge | 171:3a7713b1edbc | 1255 | #define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ |
| AnnaBridge | 171:3a7713b1edbc | 1256 | #define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ |
| AnnaBridge | 171:3a7713b1edbc | 1257 | |
| AnnaBridge | 171:3a7713b1edbc | 1258 | /* Bit fields for TIMER CC_CCVP */ |
| AnnaBridge | 171:3a7713b1edbc | 1259 | #define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ |
| AnnaBridge | 171:3a7713b1edbc | 1260 | #define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ |
| AnnaBridge | 171:3a7713b1edbc | 1261 | #define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ |
| AnnaBridge | 171:3a7713b1edbc | 1262 | #define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ |
| AnnaBridge | 171:3a7713b1edbc | 1263 | #define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ |
| AnnaBridge | 171:3a7713b1edbc | 1264 | #define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ |
| AnnaBridge | 171:3a7713b1edbc | 1265 | |
| AnnaBridge | 171:3a7713b1edbc | 1266 | /* Bit fields for TIMER CC_CCVB */ |
| AnnaBridge | 171:3a7713b1edbc | 1267 | #define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ |
| AnnaBridge | 171:3a7713b1edbc | 1268 | #define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ |
| AnnaBridge | 171:3a7713b1edbc | 1269 | #define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ |
| AnnaBridge | 171:3a7713b1edbc | 1270 | #define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ |
| AnnaBridge | 171:3a7713b1edbc | 1271 | #define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ |
| AnnaBridge | 171:3a7713b1edbc | 1272 | #define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ |
| AnnaBridge | 171:3a7713b1edbc | 1273 | |
| AnnaBridge | 171:3a7713b1edbc | 1274 | /* Bit fields for TIMER DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1275 | #define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1276 | #define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1277 | #define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1278 | #define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1279 | #define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1280 | #define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1281 | #define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1282 | #define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ |
| AnnaBridge | 171:3a7713b1edbc | 1283 | #define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ |
| AnnaBridge | 171:3a7713b1edbc | 1284 | #define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ |
| AnnaBridge | 171:3a7713b1edbc | 1285 | #define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1286 | #define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1287 | #define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1288 | #define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1289 | #define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1290 | #define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1291 | #define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 1292 | #define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1293 | #define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1294 | #define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1295 | #define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1296 | #define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ |
| AnnaBridge | 171:3a7713b1edbc | 1297 | #define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ |
| AnnaBridge | 171:3a7713b1edbc | 1298 | #define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ |
| AnnaBridge | 171:3a7713b1edbc | 1299 | #define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1300 | #define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1301 | #define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1302 | #define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1303 | #define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1304 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1305 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1306 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1307 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1308 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1309 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1310 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1311 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1312 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1313 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1314 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1315 | #define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1316 | #define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1317 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1318 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1319 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1320 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1321 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1322 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1323 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1324 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1325 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1326 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1327 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1328 | #define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1329 | #define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ |
| AnnaBridge | 171:3a7713b1edbc | 1330 | #define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ |
| AnnaBridge | 171:3a7713b1edbc | 1331 | #define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ |
| AnnaBridge | 171:3a7713b1edbc | 1332 | #define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1333 | #define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1334 | #define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ |
| AnnaBridge | 171:3a7713b1edbc | 1335 | #define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ |
| AnnaBridge | 171:3a7713b1edbc | 1336 | #define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ |
| AnnaBridge | 171:3a7713b1edbc | 1337 | #define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1338 | #define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1339 | #define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1340 | #define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1341 | #define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1342 | #define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1343 | #define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1344 | |
| AnnaBridge | 171:3a7713b1edbc | 1345 | /* Bit fields for TIMER DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1346 | #define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1347 | #define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1348 | #define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ |
| AnnaBridge | 171:3a7713b1edbc | 1349 | #define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ |
| AnnaBridge | 171:3a7713b1edbc | 1350 | #define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1351 | #define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1352 | #define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1353 | #define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1354 | #define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1355 | #define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1356 | #define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1357 | #define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1358 | #define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1359 | #define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1360 | #define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1361 | #define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1362 | #define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1363 | #define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1364 | #define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1365 | #define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1366 | #define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1367 | #define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1368 | #define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1369 | #define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1370 | #define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1371 | #define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1372 | #define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1373 | #define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1374 | #define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ |
| AnnaBridge | 171:3a7713b1edbc | 1375 | #define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ |
| AnnaBridge | 171:3a7713b1edbc | 1376 | #define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1377 | #define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1378 | #define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ |
| AnnaBridge | 171:3a7713b1edbc | 1379 | #define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ |
| AnnaBridge | 171:3a7713b1edbc | 1380 | #define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1381 | #define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ |
| AnnaBridge | 171:3a7713b1edbc | 1382 | |
| AnnaBridge | 171:3a7713b1edbc | 1383 | /* Bit fields for TIMER DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1384 | #define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1385 | #define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1386 | #define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1387 | #define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1388 | #define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1389 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1390 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1391 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1392 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1393 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1394 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1395 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1396 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1397 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1398 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1399 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1400 | #define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1401 | #define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1402 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1403 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1404 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1405 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1406 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1407 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1408 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1409 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1410 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1411 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1412 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1413 | #define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1414 | #define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1415 | #define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1416 | #define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1417 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1418 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1419 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1420 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1421 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1422 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1423 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1424 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1425 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1426 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1427 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1428 | #define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1429 | #define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1430 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1431 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1432 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1433 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1434 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1435 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1436 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1437 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1438 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1439 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1440 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1441 | #define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1442 | #define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ |
| AnnaBridge | 171:3a7713b1edbc | 1443 | #define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ |
| AnnaBridge | 171:3a7713b1edbc | 1444 | #define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1445 | #define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1446 | #define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1447 | #define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1448 | #define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1449 | #define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1450 | #define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1451 | #define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1452 | #define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1453 | #define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1454 | #define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1455 | #define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1456 | #define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1457 | #define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1458 | #define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1459 | #define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1460 | #define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1461 | #define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1462 | #define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1463 | #define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1464 | #define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1465 | #define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1466 | #define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1467 | #define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1468 | #define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1469 | #define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1470 | #define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1471 | #define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1472 | #define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1473 | #define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1474 | |
| AnnaBridge | 171:3a7713b1edbc | 1475 | /* Bit fields for TIMER DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1476 | #define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1477 | #define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1478 | #define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1479 | #define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1480 | #define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1481 | #define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1482 | #define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1483 | #define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1484 | #define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1485 | #define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1486 | #define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1487 | #define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1488 | #define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1489 | #define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1490 | #define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1491 | #define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1492 | #define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1493 | #define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1494 | #define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1495 | #define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1496 | #define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1497 | #define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1498 | #define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1499 | #define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1500 | #define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1501 | #define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1502 | #define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1503 | #define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1504 | #define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1505 | #define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1506 | #define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1507 | #define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1508 | |
| AnnaBridge | 171:3a7713b1edbc | 1509 | /* Bit fields for TIMER DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1510 | #define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1511 | #define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1512 | #define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ |
| AnnaBridge | 171:3a7713b1edbc | 1513 | #define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ |
| AnnaBridge | 171:3a7713b1edbc | 1514 | #define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ |
| AnnaBridge | 171:3a7713b1edbc | 1515 | #define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1516 | #define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1517 | #define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ |
| AnnaBridge | 171:3a7713b1edbc | 1518 | #define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ |
| AnnaBridge | 171:3a7713b1edbc | 1519 | #define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ |
| AnnaBridge | 171:3a7713b1edbc | 1520 | #define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1521 | #define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1522 | #define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ |
| AnnaBridge | 171:3a7713b1edbc | 1523 | #define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ |
| AnnaBridge | 171:3a7713b1edbc | 1524 | #define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ |
| AnnaBridge | 171:3a7713b1edbc | 1525 | #define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1526 | #define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1527 | #define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ |
| AnnaBridge | 171:3a7713b1edbc | 1528 | #define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ |
| AnnaBridge | 171:3a7713b1edbc | 1529 | #define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ |
| AnnaBridge | 171:3a7713b1edbc | 1530 | #define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1531 | #define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ |
| AnnaBridge | 171:3a7713b1edbc | 1532 | |
| AnnaBridge | 171:3a7713b1edbc | 1533 | /* Bit fields for TIMER DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1534 | #define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1535 | #define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1536 | #define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1537 | #define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ |
| AnnaBridge | 171:3a7713b1edbc | 1538 | #define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ |
| AnnaBridge | 171:3a7713b1edbc | 1539 | #define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1540 | #define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1541 | #define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1542 | #define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ |
| AnnaBridge | 171:3a7713b1edbc | 1543 | #define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ |
| AnnaBridge | 171:3a7713b1edbc | 1544 | #define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1545 | #define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1546 | #define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1547 | #define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1548 | #define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1549 | #define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1550 | #define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1551 | #define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1552 | #define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1553 | #define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1554 | #define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1555 | #define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ |
| AnnaBridge | 171:3a7713b1edbc | 1556 | |
| AnnaBridge | 171:3a7713b1edbc | 1557 | /* Bit fields for TIMER DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1558 | #define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1559 | #define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1560 | #define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 1561 | #define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 1562 | #define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1563 | #define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1564 | #define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1565 | #define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1566 | #define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1567 | #define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1568 | #define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1569 | #define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1570 | #define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1571 | #define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1572 | |
| AnnaBridge | 171:3a7713b1edbc | 1573 | /** @} End of group EFM32PG12B_TIMER */ |
| AnnaBridge | 171:3a7713b1edbc | 1574 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 1575 |
