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TARGET_ARM_MPS2_M7/TOOLCHAIN_ARM_STD/CMSDK_CM7.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /* MPS2 CMSIS Library
AnnaBridge 171:3a7713b1edbc 2 *
AnnaBridge 171:3a7713b1edbc 3 * Copyright (c) 2006-2016 ARM Limited
AnnaBridge 171:3a7713b1edbc 4 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 7 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 10 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 13 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 14 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * 3. Neither the name of the copyright holder nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 17 * may be used to endorse or promote products derived from this software without
AnnaBridge 171:3a7713b1edbc 18 * specific prior written permission.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 171:3a7713b1edbc 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
AnnaBridge 171:3a7713b1edbc 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 171:3a7713b1edbc 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 171:3a7713b1edbc 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 171:3a7713b1edbc 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 171:3a7713b1edbc 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 171:3a7713b1edbc 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 30 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 * @file CMSDK_CM7.h
AnnaBridge 171:3a7713b1edbc 33 * @brief CMSIS Core Peripheral Access Layer Header File for
AnnaBridge 171:3a7713b1edbc 34 * CMSDK_CM7 Device
AnnaBridge 171:3a7713b1edbc 35 *
AnnaBridge 171:3a7713b1edbc 36 *******************************************************************************/
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 #ifndef CMSDK_CM7_H
AnnaBridge 171:3a7713b1edbc 40 #define CMSDK_CM7_H
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 43 extern "C" {
AnnaBridge 171:3a7713b1edbc 44 #endif
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ------------------------- Interrupt Number Definition ------------------------ */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 50 {
AnnaBridge 171:3a7713b1edbc 51 /* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
AnnaBridge 171:3a7713b1edbc 52 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 53 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
AnnaBridge 171:3a7713b1edbc 54 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 55 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 56 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 57 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 58 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 59 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 60 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */
AnnaBridge 171:3a7713b1edbc 63 UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
AnnaBridge 171:3a7713b1edbc 64 UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 65 UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
AnnaBridge 171:3a7713b1edbc 66 UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 67 UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
AnnaBridge 171:3a7713b1edbc 68 UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 69 PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 70 PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 71 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 72 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 73 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 74 SPI_IRQn = 11, /* SPI Interrupt */
AnnaBridge 171:3a7713b1edbc 75 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
AnnaBridge 171:3a7713b1edbc 76 ETHERNET_IRQn = 13, /* Ethernet Interrupt */
AnnaBridge 171:3a7713b1edbc 77 I2S_IRQn = 14, /* I2S Interrupt */
AnnaBridge 171:3a7713b1edbc 78 TSC_IRQn = 15, /* Touch Screen Interrupt */
AnnaBridge 171:3a7713b1edbc 79 PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 80 PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 81 UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */
AnnaBridge 171:3a7713b1edbc 82 UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 83 UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */
AnnaBridge 171:3a7713b1edbc 84 UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 85 ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */
AnnaBridge 171:3a7713b1edbc 86 SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */
AnnaBridge 171:3a7713b1edbc 87 PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 88 PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 89 PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 90 PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 91 PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */
AnnaBridge 171:3a7713b1edbc 92 PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */
AnnaBridge 171:3a7713b1edbc 93 PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */
AnnaBridge 171:3a7713b1edbc 94 PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */
AnnaBridge 171:3a7713b1edbc 95 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 99 /* ================ Processor and Core Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 100 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 /* -------- Configuration of the CM7 Processor and Core Peripherals --------- */
AnnaBridge 171:3a7713b1edbc 103 #define __CM7_REV 0x0101 /* Core revision r1p1 */
AnnaBridge 171:3a7713b1edbc 104 #define __MPU_PRESENT 1 /* MPU present or not */
AnnaBridge 171:3a7713b1edbc 105 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 106 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 107 #define __FPU_PRESENT 1 /* no FPU present */
AnnaBridge 171:3a7713b1edbc 108 #define __FPU_DP 1 /* unused */
AnnaBridge 171:3a7713b1edbc 109 #define __ICACHE_PRESENT 1
AnnaBridge 171:3a7713b1edbc 110 #define __DCACHE_PRESENT 1
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 #include "core_cm7.h" /* Processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 113 #include "system_CMSDK_CM7.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 117 /* ================ Device Specific Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 118 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120 /* ------------------- Start of section using anonymous unions ------------------ */
AnnaBridge 171:3a7713b1edbc 121 #if defined (__CC_ARM)
AnnaBridge 171:3a7713b1edbc 122 #pragma push
AnnaBridge 171:3a7713b1edbc 123 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 124 #elif defined (__ICCARM__)
AnnaBridge 171:3a7713b1edbc 125 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 126 #elif defined (__GNUC__)
AnnaBridge 171:3a7713b1edbc 127 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 128 #elif defined (__TMS470__)
AnnaBridge 171:3a7713b1edbc 129 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 130 #elif defined (__TASKING__)
AnnaBridge 171:3a7713b1edbc 131 #pragma warning 586
AnnaBridge 171:3a7713b1edbc 132 #elif defined (__CSMC__)
AnnaBridge 171:3a7713b1edbc 133 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 134 #else
AnnaBridge 171:3a7713b1edbc 135 #warning Not supported compiler type
AnnaBridge 171:3a7713b1edbc 136 #endif
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
AnnaBridge 171:3a7713b1edbc 139 typedef struct
AnnaBridge 171:3a7713b1edbc 140 {
AnnaBridge 171:3a7713b1edbc 141 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
AnnaBridge 171:3a7713b1edbc 142 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
AnnaBridge 171:3a7713b1edbc 143 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
AnnaBridge 171:3a7713b1edbc 144 union {
AnnaBridge 171:3a7713b1edbc 145 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 146 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
AnnaBridge 171:3a7713b1edbc 147 };
AnnaBridge 171:3a7713b1edbc 148 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 } CMSDK_UART_TypeDef;
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /* CMSDK_UART DATA Register Definitions */
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
AnnaBridge 171:3a7713b1edbc 155 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
AnnaBridge 171:3a7713b1edbc 158 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
AnnaBridge 171:3a7713b1edbc 161 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
AnnaBridge 171:3a7713b1edbc 164 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
AnnaBridge 171:3a7713b1edbc 167 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
AnnaBridge 171:3a7713b1edbc 170 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
AnnaBridge 171:3a7713b1edbc 173 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
AnnaBridge 171:3a7713b1edbc 176 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
AnnaBridge 171:3a7713b1edbc 179 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
AnnaBridge 171:3a7713b1edbc 182 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
AnnaBridge 171:3a7713b1edbc 185 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
AnnaBridge 171:3a7713b1edbc 188 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
AnnaBridge 171:3a7713b1edbc 191 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
AnnaBridge 171:3a7713b1edbc 194 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
AnnaBridge 171:3a7713b1edbc 197 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
AnnaBridge 171:3a7713b1edbc 200 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
AnnaBridge 171:3a7713b1edbc 203 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 /*----------------------------- Timer (TIMER) -------------------------------*/
AnnaBridge 171:3a7713b1edbc 207 typedef struct
AnnaBridge 171:3a7713b1edbc 208 {
AnnaBridge 171:3a7713b1edbc 209 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
AnnaBridge 171:3a7713b1edbc 212 union {
AnnaBridge 171:3a7713b1edbc 213 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 214 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
AnnaBridge 171:3a7713b1edbc 215 };
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 } CMSDK_TIMER_TypeDef;
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /* CMSDK_TIMER CTRL Register Definitions */
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
AnnaBridge 171:3a7713b1edbc 222 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
AnnaBridge 171:3a7713b1edbc 225 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
AnnaBridge 171:3a7713b1edbc 228 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
AnnaBridge 171:3a7713b1edbc 231 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
AnnaBridge 171:3a7713b1edbc 234 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
AnnaBridge 171:3a7713b1edbc 237 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
AnnaBridge 171:3a7713b1edbc 240 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
AnnaBridge 171:3a7713b1edbc 243 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
AnnaBridge 171:3a7713b1edbc 244
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /*------------- Timer (TIM) --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 247 typedef struct
AnnaBridge 171:3a7713b1edbc 248 {
AnnaBridge 171:3a7713b1edbc 249 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
AnnaBridge 171:3a7713b1edbc 250 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
AnnaBridge 171:3a7713b1edbc 251 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
AnnaBridge 171:3a7713b1edbc 252 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 253 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
AnnaBridge 171:3a7713b1edbc 254 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
AnnaBridge 171:3a7713b1edbc 256 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
AnnaBridge 171:3a7713b1edbc 258 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
AnnaBridge 171:3a7713b1edbc 259 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
AnnaBridge 171:3a7713b1edbc 260 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 261 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
AnnaBridge 171:3a7713b1edbc 262 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
AnnaBridge 171:3a7713b1edbc 263 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
AnnaBridge 171:3a7713b1edbc 264 uint32_t RESERVED1[945];
AnnaBridge 171:3a7713b1edbc 265 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
AnnaBridge 171:3a7713b1edbc 266 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
AnnaBridge 171:3a7713b1edbc 267 } CMSDK_DUALTIMER_BOTH_TypeDef;
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 270 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 273 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
AnnaBridge 171:3a7713b1edbc 276 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
AnnaBridge 171:3a7713b1edbc 279 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
AnnaBridge 171:3a7713b1edbc 282 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
AnnaBridge 171:3a7713b1edbc 285 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
AnnaBridge 171:3a7713b1edbc 288 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
AnnaBridge 171:3a7713b1edbc 289
AnnaBridge 171:3a7713b1edbc 290 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
AnnaBridge 171:3a7713b1edbc 291 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
AnnaBridge 171:3a7713b1edbc 294 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 297 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 300 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
AnnaBridge 171:3a7713b1edbc 303 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 306 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 309 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
AnnaBridge 171:3a7713b1edbc 312 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
AnnaBridge 171:3a7713b1edbc 313
AnnaBridge 171:3a7713b1edbc 314 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
AnnaBridge 171:3a7713b1edbc 315 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
AnnaBridge 171:3a7713b1edbc 318 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
AnnaBridge 171:3a7713b1edbc 321 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
AnnaBridge 171:3a7713b1edbc 324 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
AnnaBridge 171:3a7713b1edbc 327 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
AnnaBridge 171:3a7713b1edbc 328
AnnaBridge 171:3a7713b1edbc 329 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
AnnaBridge 171:3a7713b1edbc 330 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 333 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 336 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
AnnaBridge 171:3a7713b1edbc 339 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 typedef struct
AnnaBridge 171:3a7713b1edbc 343 {
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
AnnaBridge 171:3a7713b1edbc 345 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
AnnaBridge 171:3a7713b1edbc 347 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 348 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
AnnaBridge 171:3a7713b1edbc 349 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
AnnaBridge 171:3a7713b1edbc 350 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
AnnaBridge 171:3a7713b1edbc 351 } CMSDK_DUALTIMER_SINGLE_TypeDef;
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 354 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 357 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
AnnaBridge 171:3a7713b1edbc 360 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
AnnaBridge 171:3a7713b1edbc 363 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
AnnaBridge 171:3a7713b1edbc 366 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
AnnaBridge 171:3a7713b1edbc 369 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
AnnaBridge 171:3a7713b1edbc 372 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
AnnaBridge 171:3a7713b1edbc 375 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
AnnaBridge 171:3a7713b1edbc 378 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
AnnaBridge 171:3a7713b1edbc 379
AnnaBridge 171:3a7713b1edbc 380 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 381 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 384 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
AnnaBridge 171:3a7713b1edbc 387 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
AnnaBridge 171:3a7713b1edbc 391 typedef struct
AnnaBridge 171:3a7713b1edbc 392 {
AnnaBridge 171:3a7713b1edbc 393 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
AnnaBridge 171:3a7713b1edbc 394 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
AnnaBridge 171:3a7713b1edbc 395 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 396 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
AnnaBridge 171:3a7713b1edbc 397 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 398 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
AnnaBridge 171:3a7713b1edbc 399 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
AnnaBridge 171:3a7713b1edbc 400 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
AnnaBridge 171:3a7713b1edbc 401 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 402 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
AnnaBridge 171:3a7713b1edbc 403 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
AnnaBridge 171:3a7713b1edbc 404 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
AnnaBridge 171:3a7713b1edbc 405 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
AnnaBridge 171:3a7713b1edbc 406 union {
AnnaBridge 171:3a7713b1edbc 407 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 408 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
AnnaBridge 171:3a7713b1edbc 409 };
AnnaBridge 171:3a7713b1edbc 410 uint32_t RESERVED1[241];
AnnaBridge 171:3a7713b1edbc 411 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
AnnaBridge 171:3a7713b1edbc 412 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
AnnaBridge 171:3a7713b1edbc 413 } CMSDK_GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
AnnaBridge 171:3a7713b1edbc 416 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
AnnaBridge 171:3a7713b1edbc 419 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
AnnaBridge 171:3a7713b1edbc 420
AnnaBridge 171:3a7713b1edbc 421 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
AnnaBridge 171:3a7713b1edbc 422 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
AnnaBridge 171:3a7713b1edbc 425 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
AnnaBridge 171:3a7713b1edbc 428 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
AnnaBridge 171:3a7713b1edbc 431 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
AnnaBridge 171:3a7713b1edbc 434 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
AnnaBridge 171:3a7713b1edbc 437 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
AnnaBridge 171:3a7713b1edbc 440 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
AnnaBridge 171:3a7713b1edbc 443 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
AnnaBridge 171:3a7713b1edbc 444
AnnaBridge 171:3a7713b1edbc 445 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
AnnaBridge 171:3a7713b1edbc 446 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
AnnaBridge 171:3a7713b1edbc 449 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
AnnaBridge 171:3a7713b1edbc 452 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
AnnaBridge 171:3a7713b1edbc 455 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
AnnaBridge 171:3a7713b1edbc 458 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
AnnaBridge 171:3a7713b1edbc 461 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
AnnaBridge 171:3a7713b1edbc 462
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /*------------- System Control (SYSCON) --------------------------------------*/
AnnaBridge 171:3a7713b1edbc 465 typedef struct
AnnaBridge 171:3a7713b1edbc 466 {
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
AnnaBridge 171:3a7713b1edbc 468 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
AnnaBridge 171:3a7713b1edbc 469 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
AnnaBridge 171:3a7713b1edbc 472 } CMSDK_SYSCON_TypeDef;
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 #define CMSDK_SYSCON_REMAP_Pos 0
AnnaBridge 171:3a7713b1edbc 475 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
AnnaBridge 171:3a7713b1edbc 478 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
AnnaBridge 171:3a7713b1edbc 481 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
AnnaBridge 171:3a7713b1edbc 484 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
AnnaBridge 171:3a7713b1edbc 487 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
AnnaBridge 171:3a7713b1edbc 490 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
AnnaBridge 171:3a7713b1edbc 493 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
AnnaBridge 171:3a7713b1edbc 496 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
AnnaBridge 171:3a7713b1edbc 497
AnnaBridge 171:3a7713b1edbc 498 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
AnnaBridge 171:3a7713b1edbc 499 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
AnnaBridge 171:3a7713b1edbc 502 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
AnnaBridge 171:3a7713b1edbc 503
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /*------------- PL230 uDMA (PL230) --------------------------------------*/
AnnaBridge 171:3a7713b1edbc 506 typedef struct
AnnaBridge 171:3a7713b1edbc 507 {
AnnaBridge 171:3a7713b1edbc 508 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
AnnaBridge 171:3a7713b1edbc 509 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
AnnaBridge 171:3a7713b1edbc 510 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 511 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 512 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
AnnaBridge 171:3a7713b1edbc 513 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
AnnaBridge 171:3a7713b1edbc 514 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
AnnaBridge 171:3a7713b1edbc 515 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
AnnaBridge 171:3a7713b1edbc 516 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
AnnaBridge 171:3a7713b1edbc 517 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
AnnaBridge 171:3a7713b1edbc 518 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
AnnaBridge 171:3a7713b1edbc 519 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 520 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
AnnaBridge 171:3a7713b1edbc 521 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
AnnaBridge 171:3a7713b1edbc 523 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
AnnaBridge 171:3a7713b1edbc 524 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 525 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 } CMSDK_PL230_TypeDef;
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 #define PL230_DMA_CHNL_BITS 0
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
AnnaBridge 171:3a7713b1edbc 532 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
AnnaBridge 171:3a7713b1edbc 535 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
AnnaBridge 171:3a7713b1edbc 538 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
AnnaBridge 171:3a7713b1edbc 539
AnnaBridge 171:3a7713b1edbc 540 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
AnnaBridge 171:3a7713b1edbc 541 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
AnnaBridge 171:3a7713b1edbc 544 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
AnnaBridge 171:3a7713b1edbc 545
AnnaBridge 171:3a7713b1edbc 546 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
AnnaBridge 171:3a7713b1edbc 547 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
AnnaBridge 171:3a7713b1edbc 550 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
AnnaBridge 171:3a7713b1edbc 553 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
AnnaBridge 171:3a7713b1edbc 556 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
AnnaBridge 171:3a7713b1edbc 559 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
AnnaBridge 171:3a7713b1edbc 562 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
AnnaBridge 171:3a7713b1edbc 565 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
AnnaBridge 171:3a7713b1edbc 568 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
AnnaBridge 171:3a7713b1edbc 569
AnnaBridge 171:3a7713b1edbc 570 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
AnnaBridge 171:3a7713b1edbc 571 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
AnnaBridge 171:3a7713b1edbc 572
AnnaBridge 171:3a7713b1edbc 573 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
AnnaBridge 171:3a7713b1edbc 574 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
AnnaBridge 171:3a7713b1edbc 575
AnnaBridge 171:3a7713b1edbc 576 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
AnnaBridge 171:3a7713b1edbc 577 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
AnnaBridge 171:3a7713b1edbc 578
AnnaBridge 171:3a7713b1edbc 579 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
AnnaBridge 171:3a7713b1edbc 580 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
AnnaBridge 171:3a7713b1edbc 583 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
AnnaBridge 171:3a7713b1edbc 586 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
AnnaBridge 171:3a7713b1edbc 589 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
AnnaBridge 171:3a7713b1edbc 592 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
AnnaBridge 171:3a7713b1edbc 595 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
AnnaBridge 171:3a7713b1edbc 598 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 /*------------------- Watchdog ----------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 602 typedef struct
AnnaBridge 171:3a7713b1edbc 603 {
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
AnnaBridge 171:3a7713b1edbc 606 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
AnnaBridge 171:3a7713b1edbc 607 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
AnnaBridge 171:3a7713b1edbc 608 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
AnnaBridge 171:3a7713b1edbc 609 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 610 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 611 uint32_t RESERVED0[762];
AnnaBridge 171:3a7713b1edbc 612 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
AnnaBridge 171:3a7713b1edbc 613 uint32_t RESERVED1[191];
AnnaBridge 171:3a7713b1edbc 614 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
AnnaBridge 171:3a7713b1edbc 615 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
AnnaBridge 171:3a7713b1edbc 616 }CMSDK_WATCHDOG_TypeDef;
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 619 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 622 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
AnnaBridge 171:3a7713b1edbc 625 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
AnnaBridge 171:3a7713b1edbc 628 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
AnnaBridge 171:3a7713b1edbc 631 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
AnnaBridge 171:3a7713b1edbc 632
AnnaBridge 171:3a7713b1edbc 633 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 634 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 637 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
AnnaBridge 171:3a7713b1edbc 640 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
AnnaBridge 171:3a7713b1edbc 643 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
AnnaBridge 171:3a7713b1edbc 644
AnnaBridge 171:3a7713b1edbc 645 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
AnnaBridge 171:3a7713b1edbc 646 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
AnnaBridge 171:3a7713b1edbc 647
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /* -------------------- End of section using anonymous unions ------------------- */
AnnaBridge 171:3a7713b1edbc 651 #if defined (__CC_ARM)
AnnaBridge 171:3a7713b1edbc 652 #pragma pop
AnnaBridge 171:3a7713b1edbc 653 #elif defined (__ICCARM__)
AnnaBridge 171:3a7713b1edbc 654 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 655 #elif defined (__GNUC__)
AnnaBridge 171:3a7713b1edbc 656 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 657 #elif defined (__TMS470__)
AnnaBridge 171:3a7713b1edbc 658 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 659 #elif defined (__TASKING__)
AnnaBridge 171:3a7713b1edbc 660 #pragma warning restore
AnnaBridge 171:3a7713b1edbc 661 #elif defined (__CSMC__)
AnnaBridge 171:3a7713b1edbc 662 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 663 #else
AnnaBridge 171:3a7713b1edbc 664 #warning Not supported compiler type
AnnaBridge 171:3a7713b1edbc 665 #endif
AnnaBridge 171:3a7713b1edbc 666
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 671 /* ================ Peripheral memory map ================ */
AnnaBridge 171:3a7713b1edbc 672 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 673
AnnaBridge 171:3a7713b1edbc 674 /* Peripheral and SRAM base address */
AnnaBridge 171:3a7713b1edbc 675 #define CMSDK_FLASH_BASE (0x00000000UL)
AnnaBridge 171:3a7713b1edbc 676 #define CMSDK_SRAM_BASE (0x20000000UL)
AnnaBridge 171:3a7713b1edbc 677 #define CMSDK_PERIPH_BASE (0x40000000UL)
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 #define CMSDK_RAM_BASE (0x20000000UL)
AnnaBridge 171:3a7713b1edbc 680 #define CMSDK_APB_BASE (0x40000000UL)
AnnaBridge 171:3a7713b1edbc 681 #define CMSDK_AHB_BASE (0x40010000UL)
AnnaBridge 171:3a7713b1edbc 682
AnnaBridge 171:3a7713b1edbc 683 /* APB peripherals */
AnnaBridge 171:3a7713b1edbc 684 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
AnnaBridge 171:3a7713b1edbc 685 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
AnnaBridge 171:3a7713b1edbc 686 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
AnnaBridge 171:3a7713b1edbc 687 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
AnnaBridge 171:3a7713b1edbc 688 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
AnnaBridge 171:3a7713b1edbc 689 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
AnnaBridge 171:3a7713b1edbc 690 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
AnnaBridge 171:3a7713b1edbc 691 #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
AnnaBridge 171:3a7713b1edbc 692 #define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
AnnaBridge 171:3a7713b1edbc 693 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
AnnaBridge 171:3a7713b1edbc 694 #define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
AnnaBridge 171:3a7713b1edbc 695 #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697 /* AHB peripherals */
AnnaBridge 171:3a7713b1edbc 698 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
AnnaBridge 171:3a7713b1edbc 699 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
AnnaBridge 171:3a7713b1edbc 700 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
AnnaBridge 171:3a7713b1edbc 701 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
AnnaBridge 171:3a7713b1edbc 702 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
AnnaBridge 171:3a7713b1edbc 703
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 706 /* ================ Peripheral declaration ================ */
AnnaBridge 171:3a7713b1edbc 707 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 708
AnnaBridge 171:3a7713b1edbc 709 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
AnnaBridge 171:3a7713b1edbc 710 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
AnnaBridge 171:3a7713b1edbc 711 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
AnnaBridge 171:3a7713b1edbc 712 #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
AnnaBridge 171:3a7713b1edbc 713 #define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
AnnaBridge 171:3a7713b1edbc 714 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
AnnaBridge 171:3a7713b1edbc 715 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
AnnaBridge 171:3a7713b1edbc 716 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
AnnaBridge 171:3a7713b1edbc 717 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
AnnaBridge 171:3a7713b1edbc 718 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
AnnaBridge 171:3a7713b1edbc 719 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
AnnaBridge 171:3a7713b1edbc 720 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
AnnaBridge 171:3a7713b1edbc 721 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
AnnaBridge 171:3a7713b1edbc 722 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
AnnaBridge 171:3a7713b1edbc 723 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
AnnaBridge 171:3a7713b1edbc 724 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
AnnaBridge 171:3a7713b1edbc 725 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
AnnaBridge 171:3a7713b1edbc 726
AnnaBridge 171:3a7713b1edbc 727
AnnaBridge 171:3a7713b1edbc 728 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 729 }
AnnaBridge 171:3a7713b1edbc 730 #endif
AnnaBridge 171:3a7713b1edbc 731
AnnaBridge 171:3a7713b1edbc 732 #endif /* CMSDK_CM7_H */