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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RZ_A1H/core_cmInstr.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Child:
110:165afa46840b
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_cmInstr.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
bogdanm 92:4fc01daae5a5 4 * @version V3.20
bogdanm 92:4fc01daae5a5 5 * @date 05. March 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
bogdanm 92:4fc01daae5a5 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #ifndef __CORE_CMINSTR_H
bogdanm 92:4fc01daae5a5 39 #define __CORE_CMINSTR_H
bogdanm 92:4fc01daae5a5 40
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 /* ########################## Core Instruction Access ######################### */
bogdanm 92:4fc01daae5a5 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
bogdanm 92:4fc01daae5a5 44 Access to dedicated instructions
bogdanm 92:4fc01daae5a5 45 @{
bogdanm 92:4fc01daae5a5 46 */
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 92:4fc01daae5a5 49 /* ARM armcc specific functions */
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 #if (__ARMCC_VERSION < 400677)
bogdanm 92:4fc01daae5a5 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
bogdanm 92:4fc01daae5a5 53 #endif
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55
bogdanm 92:4fc01daae5a5 56 /** \brief No Operation
bogdanm 92:4fc01daae5a5 57
bogdanm 92:4fc01daae5a5 58 No Operation does nothing. This instruction can be used for code alignment purposes.
bogdanm 92:4fc01daae5a5 59 */
bogdanm 92:4fc01daae5a5 60 #define __NOP __nop
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 /** \brief Wait For Interrupt
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 Wait For Interrupt is a hint instruction that suspends execution
bogdanm 92:4fc01daae5a5 66 until one of a number of events occurs.
bogdanm 92:4fc01daae5a5 67 */
bogdanm 92:4fc01daae5a5 68 #define __WFI __wfi
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70
bogdanm 92:4fc01daae5a5 71 /** \brief Wait For Event
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 Wait For Event is a hint instruction that permits the processor to enter
bogdanm 92:4fc01daae5a5 74 a low-power state until one of a number of events occurs.
bogdanm 92:4fc01daae5a5 75 */
bogdanm 92:4fc01daae5a5 76 #define __WFE __wfe
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 /** \brief Send Event
bogdanm 92:4fc01daae5a5 80
bogdanm 92:4fc01daae5a5 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
bogdanm 92:4fc01daae5a5 82 */
bogdanm 92:4fc01daae5a5 83 #define __SEV __sev
bogdanm 92:4fc01daae5a5 84
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 /** \brief Instruction Synchronization Barrier
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
bogdanm 92:4fc01daae5a5 89 so that all instructions following the ISB are fetched from cache or
bogdanm 92:4fc01daae5a5 90 memory, after the instruction has been completed.
bogdanm 92:4fc01daae5a5 91 */
bogdanm 92:4fc01daae5a5 92 #define __ISB() __isb(0xF)
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95 /** \brief Data Synchronization Barrier
bogdanm 92:4fc01daae5a5 96
bogdanm 92:4fc01daae5a5 97 This function acts as a special kind of Data Memory Barrier.
bogdanm 92:4fc01daae5a5 98 It completes when all explicit memory accesses before this instruction complete.
bogdanm 92:4fc01daae5a5 99 */
bogdanm 92:4fc01daae5a5 100 #define __DSB() __dsb(0xF)
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 /** \brief Data Memory Barrier
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 This function ensures the apparent order of the explicit memory operations before
bogdanm 92:4fc01daae5a5 106 and after the instruction, without ensuring their completion.
bogdanm 92:4fc01daae5a5 107 */
bogdanm 92:4fc01daae5a5 108 #define __DMB() __dmb(0xF)
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110
bogdanm 92:4fc01daae5a5 111 /** \brief Reverse byte order (32 bit)
bogdanm 92:4fc01daae5a5 112
bogdanm 92:4fc01daae5a5 113 This function reverses the byte order in integer value.
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 116 \return Reversed value
bogdanm 92:4fc01daae5a5 117 */
bogdanm 92:4fc01daae5a5 118 #define __REV __rev
bogdanm 92:4fc01daae5a5 119
bogdanm 92:4fc01daae5a5 120
bogdanm 92:4fc01daae5a5 121 /** \brief Reverse byte order (16 bit)
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 This function reverses the byte order in two unsigned short values.
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 126 \return Reversed value
bogdanm 92:4fc01daae5a5 127 */
bogdanm 92:4fc01daae5a5 128 #ifndef __NO_EMBEDDED_ASM
bogdanm 92:4fc01daae5a5 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
bogdanm 92:4fc01daae5a5 130 {
bogdanm 92:4fc01daae5a5 131 rev16 r0, r0
bogdanm 92:4fc01daae5a5 132 bx lr
bogdanm 92:4fc01daae5a5 133 }
bogdanm 92:4fc01daae5a5 134 #endif
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 /** \brief Reverse byte order in signed short value
bogdanm 92:4fc01daae5a5 137
bogdanm 92:4fc01daae5a5 138 This function reverses the byte order in a signed short value with sign extension to integer.
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 141 \return Reversed value
bogdanm 92:4fc01daae5a5 142 */
bogdanm 92:4fc01daae5a5 143 #ifndef __NO_EMBEDDED_ASM
bogdanm 92:4fc01daae5a5 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
bogdanm 92:4fc01daae5a5 145 {
bogdanm 92:4fc01daae5a5 146 revsh r0, r0
bogdanm 92:4fc01daae5a5 147 bx lr
bogdanm 92:4fc01daae5a5 148 }
bogdanm 92:4fc01daae5a5 149 #endif
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 /** \brief Rotate Right in unsigned value (32 bit)
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 \param [in] value Value to rotate
bogdanm 92:4fc01daae5a5 157 \param [in] value Number of Bits to rotate
bogdanm 92:4fc01daae5a5 158 \return Rotated value
bogdanm 92:4fc01daae5a5 159 */
bogdanm 92:4fc01daae5a5 160 #define __ROR __ror
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162
bogdanm 92:4fc01daae5a5 163 /** \brief Breakpoint
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 This function causes the processor to enter Debug state.
bogdanm 92:4fc01daae5a5 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
bogdanm 92:4fc01daae5a5 167
bogdanm 92:4fc01daae5a5 168 \param [in] value is ignored by the processor.
bogdanm 92:4fc01daae5a5 169 If required, a debugger can use it to store additional information about the breakpoint.
bogdanm 92:4fc01daae5a5 170 */
bogdanm 92:4fc01daae5a5 171 #define __BKPT(value) __breakpoint(value)
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 #if (__CORTEX_M >= 0x03)
bogdanm 92:4fc01daae5a5 175
bogdanm 92:4fc01daae5a5 176 /** \brief Reverse bit order of value
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 This function reverses the bit order of the given value.
bogdanm 92:4fc01daae5a5 179
bogdanm 92:4fc01daae5a5 180 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 181 \return Reversed value
bogdanm 92:4fc01daae5a5 182 */
bogdanm 92:4fc01daae5a5 183 #define __RBIT __rbit
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185
bogdanm 92:4fc01daae5a5 186 /** \brief LDR Exclusive (8 bit)
bogdanm 92:4fc01daae5a5 187
bogdanm 92:4fc01daae5a5 188 This function performs a exclusive LDR command for 8 bit value.
bogdanm 92:4fc01daae5a5 189
bogdanm 92:4fc01daae5a5 190 \param [in] ptr Pointer to data
bogdanm 92:4fc01daae5a5 191 \return value of type uint8_t at (*ptr)
bogdanm 92:4fc01daae5a5 192 */
bogdanm 92:4fc01daae5a5 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195
bogdanm 92:4fc01daae5a5 196 /** \brief LDR Exclusive (16 bit)
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 This function performs a exclusive LDR command for 16 bit values.
bogdanm 92:4fc01daae5a5 199
bogdanm 92:4fc01daae5a5 200 \param [in] ptr Pointer to data
bogdanm 92:4fc01daae5a5 201 \return value of type uint16_t at (*ptr)
bogdanm 92:4fc01daae5a5 202 */
bogdanm 92:4fc01daae5a5 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
bogdanm 92:4fc01daae5a5 204
bogdanm 92:4fc01daae5a5 205
bogdanm 92:4fc01daae5a5 206 /** \brief LDR Exclusive (32 bit)
bogdanm 92:4fc01daae5a5 207
bogdanm 92:4fc01daae5a5 208 This function performs a exclusive LDR command for 32 bit values.
bogdanm 92:4fc01daae5a5 209
bogdanm 92:4fc01daae5a5 210 \param [in] ptr Pointer to data
bogdanm 92:4fc01daae5a5 211 \return value of type uint32_t at (*ptr)
bogdanm 92:4fc01daae5a5 212 */
bogdanm 92:4fc01daae5a5 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215
bogdanm 92:4fc01daae5a5 216 /** \brief STR Exclusive (8 bit)
bogdanm 92:4fc01daae5a5 217
bogdanm 92:4fc01daae5a5 218 This function performs a exclusive STR command for 8 bit values.
bogdanm 92:4fc01daae5a5 219
bogdanm 92:4fc01daae5a5 220 \param [in] value Value to store
bogdanm 92:4fc01daae5a5 221 \param [in] ptr Pointer to location
bogdanm 92:4fc01daae5a5 222 \return 0 Function succeeded
bogdanm 92:4fc01daae5a5 223 \return 1 Function failed
bogdanm 92:4fc01daae5a5 224 */
bogdanm 92:4fc01daae5a5 225 #define __STREXB(value, ptr) __strex(value, ptr)
bogdanm 92:4fc01daae5a5 226
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228 /** \brief STR Exclusive (16 bit)
bogdanm 92:4fc01daae5a5 229
bogdanm 92:4fc01daae5a5 230 This function performs a exclusive STR command for 16 bit values.
bogdanm 92:4fc01daae5a5 231
bogdanm 92:4fc01daae5a5 232 \param [in] value Value to store
bogdanm 92:4fc01daae5a5 233 \param [in] ptr Pointer to location
bogdanm 92:4fc01daae5a5 234 \return 0 Function succeeded
bogdanm 92:4fc01daae5a5 235 \return 1 Function failed
bogdanm 92:4fc01daae5a5 236 */
bogdanm 92:4fc01daae5a5 237 #define __STREXH(value, ptr) __strex(value, ptr)
bogdanm 92:4fc01daae5a5 238
bogdanm 92:4fc01daae5a5 239
bogdanm 92:4fc01daae5a5 240 /** \brief STR Exclusive (32 bit)
bogdanm 92:4fc01daae5a5 241
bogdanm 92:4fc01daae5a5 242 This function performs a exclusive STR command for 32 bit values.
bogdanm 92:4fc01daae5a5 243
bogdanm 92:4fc01daae5a5 244 \param [in] value Value to store
bogdanm 92:4fc01daae5a5 245 \param [in] ptr Pointer to location
bogdanm 92:4fc01daae5a5 246 \return 0 Function succeeded
bogdanm 92:4fc01daae5a5 247 \return 1 Function failed
bogdanm 92:4fc01daae5a5 248 */
bogdanm 92:4fc01daae5a5 249 #define __STREXW(value, ptr) __strex(value, ptr)
bogdanm 92:4fc01daae5a5 250
bogdanm 92:4fc01daae5a5 251
bogdanm 92:4fc01daae5a5 252 /** \brief Remove the exclusive lock
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254 This function removes the exclusive lock which is created by LDREX.
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256 */
bogdanm 92:4fc01daae5a5 257 #define __CLREX __clrex
bogdanm 92:4fc01daae5a5 258
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 /** \brief Signed Saturate
bogdanm 92:4fc01daae5a5 261
bogdanm 92:4fc01daae5a5 262 This function saturates a signed value.
bogdanm 92:4fc01daae5a5 263
bogdanm 92:4fc01daae5a5 264 \param [in] value Value to be saturated
bogdanm 92:4fc01daae5a5 265 \param [in] sat Bit position to saturate to (1..32)
bogdanm 92:4fc01daae5a5 266 \return Saturated value
bogdanm 92:4fc01daae5a5 267 */
bogdanm 92:4fc01daae5a5 268 #define __SSAT __ssat
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270
bogdanm 92:4fc01daae5a5 271 /** \brief Unsigned Saturate
bogdanm 92:4fc01daae5a5 272
bogdanm 92:4fc01daae5a5 273 This function saturates an unsigned value.
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 \param [in] value Value to be saturated
bogdanm 92:4fc01daae5a5 276 \param [in] sat Bit position to saturate to (0..31)
bogdanm 92:4fc01daae5a5 277 \return Saturated value
bogdanm 92:4fc01daae5a5 278 */
bogdanm 92:4fc01daae5a5 279 #define __USAT __usat
bogdanm 92:4fc01daae5a5 280
bogdanm 92:4fc01daae5a5 281
bogdanm 92:4fc01daae5a5 282 /** \brief Count leading zeros
bogdanm 92:4fc01daae5a5 283
bogdanm 92:4fc01daae5a5 284 This function counts the number of leading zeros of a data value.
bogdanm 92:4fc01daae5a5 285
bogdanm 92:4fc01daae5a5 286 \param [in] value Value to count the leading zeros
bogdanm 92:4fc01daae5a5 287 \return number of leading zeros in value
bogdanm 92:4fc01daae5a5 288 */
bogdanm 92:4fc01daae5a5 289 #define __CLZ __clz
bogdanm 92:4fc01daae5a5 290
bogdanm 92:4fc01daae5a5 291 #endif /* (__CORTEX_M >= 0x03) */
bogdanm 92:4fc01daae5a5 292
bogdanm 92:4fc01daae5a5 293
bogdanm 92:4fc01daae5a5 294
bogdanm 92:4fc01daae5a5 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
bogdanm 92:4fc01daae5a5 296 /* IAR iccarm specific functions */
bogdanm 92:4fc01daae5a5 297
bogdanm 92:4fc01daae5a5 298 #include <cmsis_iar.h>
bogdanm 92:4fc01daae5a5 299
bogdanm 92:4fc01daae5a5 300
bogdanm 92:4fc01daae5a5 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
bogdanm 92:4fc01daae5a5 302 /* TI CCS specific functions */
bogdanm 92:4fc01daae5a5 303
bogdanm 92:4fc01daae5a5 304 #include <cmsis_ccs.h>
bogdanm 92:4fc01daae5a5 305
bogdanm 92:4fc01daae5a5 306
bogdanm 92:4fc01daae5a5 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
bogdanm 92:4fc01daae5a5 308 /* GNU gcc specific functions */
bogdanm 92:4fc01daae5a5 309
bogdanm 92:4fc01daae5a5 310 /* Define macros for porting to both thumb1 and thumb2.
bogdanm 92:4fc01daae5a5 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
bogdanm 92:4fc01daae5a5 312 * Otherwise, use general registers, specified by constrant "r" */
bogdanm 92:4fc01daae5a5 313 #if defined (__thumb__) && !defined (__thumb2__)
bogdanm 92:4fc01daae5a5 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
bogdanm 92:4fc01daae5a5 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
bogdanm 92:4fc01daae5a5 316 #else
bogdanm 92:4fc01daae5a5 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
bogdanm 92:4fc01daae5a5 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
bogdanm 92:4fc01daae5a5 319 #endif
bogdanm 92:4fc01daae5a5 320
bogdanm 92:4fc01daae5a5 321 /** \brief No Operation
bogdanm 92:4fc01daae5a5 322
bogdanm 92:4fc01daae5a5 323 No Operation does nothing. This instruction can be used for code alignment purposes.
bogdanm 92:4fc01daae5a5 324 */
bogdanm 92:4fc01daae5a5 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
bogdanm 92:4fc01daae5a5 326 {
bogdanm 92:4fc01daae5a5 327 __ASM volatile ("nop");
bogdanm 92:4fc01daae5a5 328 }
bogdanm 92:4fc01daae5a5 329
bogdanm 92:4fc01daae5a5 330
bogdanm 92:4fc01daae5a5 331 /** \brief Wait For Interrupt
bogdanm 92:4fc01daae5a5 332
bogdanm 92:4fc01daae5a5 333 Wait For Interrupt is a hint instruction that suspends execution
bogdanm 92:4fc01daae5a5 334 until one of a number of events occurs.
bogdanm 92:4fc01daae5a5 335 */
bogdanm 92:4fc01daae5a5 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
bogdanm 92:4fc01daae5a5 337 {
bogdanm 92:4fc01daae5a5 338 __ASM volatile ("wfi");
bogdanm 92:4fc01daae5a5 339 }
bogdanm 92:4fc01daae5a5 340
bogdanm 92:4fc01daae5a5 341
bogdanm 92:4fc01daae5a5 342 /** \brief Wait For Event
bogdanm 92:4fc01daae5a5 343
bogdanm 92:4fc01daae5a5 344 Wait For Event is a hint instruction that permits the processor to enter
bogdanm 92:4fc01daae5a5 345 a low-power state until one of a number of events occurs.
bogdanm 92:4fc01daae5a5 346 */
bogdanm 92:4fc01daae5a5 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
bogdanm 92:4fc01daae5a5 348 {
bogdanm 92:4fc01daae5a5 349 __ASM volatile ("wfe");
bogdanm 92:4fc01daae5a5 350 }
bogdanm 92:4fc01daae5a5 351
bogdanm 92:4fc01daae5a5 352
bogdanm 92:4fc01daae5a5 353 /** \brief Send Event
bogdanm 92:4fc01daae5a5 354
bogdanm 92:4fc01daae5a5 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
bogdanm 92:4fc01daae5a5 356 */
bogdanm 92:4fc01daae5a5 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
bogdanm 92:4fc01daae5a5 358 {
bogdanm 92:4fc01daae5a5 359 __ASM volatile ("sev");
bogdanm 92:4fc01daae5a5 360 }
bogdanm 92:4fc01daae5a5 361
bogdanm 92:4fc01daae5a5 362
bogdanm 92:4fc01daae5a5 363 /** \brief Instruction Synchronization Barrier
bogdanm 92:4fc01daae5a5 364
bogdanm 92:4fc01daae5a5 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
bogdanm 92:4fc01daae5a5 366 so that all instructions following the ISB are fetched from cache or
bogdanm 92:4fc01daae5a5 367 memory, after the instruction has been completed.
bogdanm 92:4fc01daae5a5 368 */
bogdanm 92:4fc01daae5a5 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
bogdanm 92:4fc01daae5a5 370 {
bogdanm 92:4fc01daae5a5 371 __ASM volatile ("isb");
bogdanm 92:4fc01daae5a5 372 }
bogdanm 92:4fc01daae5a5 373
bogdanm 92:4fc01daae5a5 374
bogdanm 92:4fc01daae5a5 375 /** \brief Data Synchronization Barrier
bogdanm 92:4fc01daae5a5 376
bogdanm 92:4fc01daae5a5 377 This function acts as a special kind of Data Memory Barrier.
bogdanm 92:4fc01daae5a5 378 It completes when all explicit memory accesses before this instruction complete.
bogdanm 92:4fc01daae5a5 379 */
bogdanm 92:4fc01daae5a5 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
bogdanm 92:4fc01daae5a5 381 {
bogdanm 92:4fc01daae5a5 382 __ASM volatile ("dsb");
bogdanm 92:4fc01daae5a5 383 }
bogdanm 92:4fc01daae5a5 384
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386 /** \brief Data Memory Barrier
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 This function ensures the apparent order of the explicit memory operations before
bogdanm 92:4fc01daae5a5 389 and after the instruction, without ensuring their completion.
bogdanm 92:4fc01daae5a5 390 */
bogdanm 92:4fc01daae5a5 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
bogdanm 92:4fc01daae5a5 392 {
bogdanm 92:4fc01daae5a5 393 __ASM volatile ("dmb");
bogdanm 92:4fc01daae5a5 394 }
bogdanm 92:4fc01daae5a5 395
bogdanm 92:4fc01daae5a5 396
bogdanm 92:4fc01daae5a5 397 /** \brief Reverse byte order (32 bit)
bogdanm 92:4fc01daae5a5 398
bogdanm 92:4fc01daae5a5 399 This function reverses the byte order in integer value.
bogdanm 92:4fc01daae5a5 400
bogdanm 92:4fc01daae5a5 401 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 402 \return Reversed value
bogdanm 92:4fc01daae5a5 403 */
bogdanm 92:4fc01daae5a5 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
bogdanm 92:4fc01daae5a5 405 {
bogdanm 92:4fc01daae5a5 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
bogdanm 92:4fc01daae5a5 407 return __builtin_bswap32(value);
bogdanm 92:4fc01daae5a5 408 #else
bogdanm 92:4fc01daae5a5 409 uint32_t result;
bogdanm 92:4fc01daae5a5 410
bogdanm 92:4fc01daae5a5 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
bogdanm 92:4fc01daae5a5 412 return(result);
bogdanm 92:4fc01daae5a5 413 #endif
bogdanm 92:4fc01daae5a5 414 }
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416
bogdanm 92:4fc01daae5a5 417 /** \brief Reverse byte order (16 bit)
bogdanm 92:4fc01daae5a5 418
bogdanm 92:4fc01daae5a5 419 This function reverses the byte order in two unsigned short values.
bogdanm 92:4fc01daae5a5 420
bogdanm 92:4fc01daae5a5 421 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 422 \return Reversed value
bogdanm 92:4fc01daae5a5 423 */
bogdanm 92:4fc01daae5a5 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
bogdanm 92:4fc01daae5a5 425 {
bogdanm 92:4fc01daae5a5 426 uint32_t result;
bogdanm 92:4fc01daae5a5 427
bogdanm 92:4fc01daae5a5 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
bogdanm 92:4fc01daae5a5 429 return(result);
bogdanm 92:4fc01daae5a5 430 }
bogdanm 92:4fc01daae5a5 431
bogdanm 92:4fc01daae5a5 432
bogdanm 92:4fc01daae5a5 433 /** \brief Reverse byte order in signed short value
bogdanm 92:4fc01daae5a5 434
bogdanm 92:4fc01daae5a5 435 This function reverses the byte order in a signed short value with sign extension to integer.
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 438 \return Reversed value
bogdanm 92:4fc01daae5a5 439 */
bogdanm 92:4fc01daae5a5 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
bogdanm 92:4fc01daae5a5 441 {
bogdanm 92:4fc01daae5a5 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
bogdanm 92:4fc01daae5a5 443 return (short)__builtin_bswap16(value);
bogdanm 92:4fc01daae5a5 444 #else
bogdanm 92:4fc01daae5a5 445 uint32_t result;
bogdanm 92:4fc01daae5a5 446
bogdanm 92:4fc01daae5a5 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
bogdanm 92:4fc01daae5a5 448 return(result);
bogdanm 92:4fc01daae5a5 449 #endif
bogdanm 92:4fc01daae5a5 450 }
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452
bogdanm 92:4fc01daae5a5 453 /** \brief Rotate Right in unsigned value (32 bit)
bogdanm 92:4fc01daae5a5 454
bogdanm 92:4fc01daae5a5 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
bogdanm 92:4fc01daae5a5 456
bogdanm 92:4fc01daae5a5 457 \param [in] value Value to rotate
bogdanm 92:4fc01daae5a5 458 \param [in] value Number of Bits to rotate
bogdanm 92:4fc01daae5a5 459 \return Rotated value
bogdanm 92:4fc01daae5a5 460 */
bogdanm 92:4fc01daae5a5 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 462 {
bogdanm 92:4fc01daae5a5 463 return (op1 >> op2) | (op1 << (32 - op2));
bogdanm 92:4fc01daae5a5 464 }
bogdanm 92:4fc01daae5a5 465
bogdanm 92:4fc01daae5a5 466
bogdanm 92:4fc01daae5a5 467 /** \brief Breakpoint
bogdanm 92:4fc01daae5a5 468
bogdanm 92:4fc01daae5a5 469 This function causes the processor to enter Debug state.
bogdanm 92:4fc01daae5a5 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
bogdanm 92:4fc01daae5a5 471
bogdanm 92:4fc01daae5a5 472 \param [in] value is ignored by the processor.
bogdanm 92:4fc01daae5a5 473 If required, a debugger can use it to store additional information about the breakpoint.
bogdanm 92:4fc01daae5a5 474 */
bogdanm 92:4fc01daae5a5 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477
bogdanm 92:4fc01daae5a5 478 #if (__CORTEX_M >= 0x03)
bogdanm 92:4fc01daae5a5 479
bogdanm 92:4fc01daae5a5 480 /** \brief Reverse bit order of value
bogdanm 92:4fc01daae5a5 481
bogdanm 92:4fc01daae5a5 482 This function reverses the bit order of the given value.
bogdanm 92:4fc01daae5a5 483
bogdanm 92:4fc01daae5a5 484 \param [in] value Value to reverse
bogdanm 92:4fc01daae5a5 485 \return Reversed value
bogdanm 92:4fc01daae5a5 486 */
bogdanm 92:4fc01daae5a5 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
bogdanm 92:4fc01daae5a5 488 {
bogdanm 92:4fc01daae5a5 489 uint32_t result;
bogdanm 92:4fc01daae5a5 490
bogdanm 92:4fc01daae5a5 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
bogdanm 92:4fc01daae5a5 492 return(result);
bogdanm 92:4fc01daae5a5 493 }
bogdanm 92:4fc01daae5a5 494
bogdanm 92:4fc01daae5a5 495
bogdanm 92:4fc01daae5a5 496 /** \brief LDR Exclusive (8 bit)
bogdanm 92:4fc01daae5a5 497
bogdanm 92:4fc01daae5a5 498 This function performs a exclusive LDR command for 8 bit value.
bogdanm 92:4fc01daae5a5 499
bogdanm 92:4fc01daae5a5 500 \param [in] ptr Pointer to data
bogdanm 92:4fc01daae5a5 501 \return value of type uint8_t at (*ptr)
bogdanm 92:4fc01daae5a5 502 */
bogdanm 92:4fc01daae5a5 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
bogdanm 92:4fc01daae5a5 504 {
bogdanm 92:4fc01daae5a5 505 uint32_t result;
bogdanm 92:4fc01daae5a5 506
bogdanm 92:4fc01daae5a5 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
bogdanm 92:4fc01daae5a5 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
bogdanm 92:4fc01daae5a5 509 #else
bogdanm 92:4fc01daae5a5 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
bogdanm 92:4fc01daae5a5 511 accepted by assembler. So has to use following less efficient pattern.
bogdanm 92:4fc01daae5a5 512 */
bogdanm 92:4fc01daae5a5 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
bogdanm 92:4fc01daae5a5 514 #endif
bogdanm 92:4fc01daae5a5 515 return(result);
bogdanm 92:4fc01daae5a5 516 }
bogdanm 92:4fc01daae5a5 517
bogdanm 92:4fc01daae5a5 518
bogdanm 92:4fc01daae5a5 519 /** \brief LDR Exclusive (16 bit)
bogdanm 92:4fc01daae5a5 520
bogdanm 92:4fc01daae5a5 521 This function performs a exclusive LDR command for 16 bit values.
bogdanm 92:4fc01daae5a5 522
bogdanm 92:4fc01daae5a5 523 \param [in] ptr Pointer to data
bogdanm 92:4fc01daae5a5 524 \return value of type uint16_t at (*ptr)
bogdanm 92:4fc01daae5a5 525 */
bogdanm 92:4fc01daae5a5 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
bogdanm 92:4fc01daae5a5 527 {
bogdanm 92:4fc01daae5a5 528 uint32_t result;
bogdanm 92:4fc01daae5a5 529
bogdanm 92:4fc01daae5a5 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
bogdanm 92:4fc01daae5a5 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
bogdanm 92:4fc01daae5a5 532 #else
bogdanm 92:4fc01daae5a5 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
bogdanm 92:4fc01daae5a5 534 accepted by assembler. So has to use following less efficient pattern.
bogdanm 92:4fc01daae5a5 535 */
bogdanm 92:4fc01daae5a5 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
bogdanm 92:4fc01daae5a5 537 #endif
bogdanm 92:4fc01daae5a5 538 return(result);
bogdanm 92:4fc01daae5a5 539 }
bogdanm 92:4fc01daae5a5 540
bogdanm 92:4fc01daae5a5 541
bogdanm 92:4fc01daae5a5 542 /** \brief LDR Exclusive (32 bit)
bogdanm 92:4fc01daae5a5 543
bogdanm 92:4fc01daae5a5 544 This function performs a exclusive LDR command for 32 bit values.
bogdanm 92:4fc01daae5a5 545
bogdanm 92:4fc01daae5a5 546 \param [in] ptr Pointer to data
bogdanm 92:4fc01daae5a5 547 \return value of type uint32_t at (*ptr)
bogdanm 92:4fc01daae5a5 548 */
bogdanm 92:4fc01daae5a5 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
bogdanm 92:4fc01daae5a5 550 {
bogdanm 92:4fc01daae5a5 551 uint32_t result;
bogdanm 92:4fc01daae5a5 552
bogdanm 92:4fc01daae5a5 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
bogdanm 92:4fc01daae5a5 554 return(result);
bogdanm 92:4fc01daae5a5 555 }
bogdanm 92:4fc01daae5a5 556
bogdanm 92:4fc01daae5a5 557
bogdanm 92:4fc01daae5a5 558 /** \brief STR Exclusive (8 bit)
bogdanm 92:4fc01daae5a5 559
bogdanm 92:4fc01daae5a5 560 This function performs a exclusive STR command for 8 bit values.
bogdanm 92:4fc01daae5a5 561
bogdanm 92:4fc01daae5a5 562 \param [in] value Value to store
bogdanm 92:4fc01daae5a5 563 \param [in] ptr Pointer to location
bogdanm 92:4fc01daae5a5 564 \return 0 Function succeeded
bogdanm 92:4fc01daae5a5 565 \return 1 Function failed
bogdanm 92:4fc01daae5a5 566 */
bogdanm 92:4fc01daae5a5 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
bogdanm 92:4fc01daae5a5 568 {
bogdanm 92:4fc01daae5a5 569 uint32_t result;
bogdanm 92:4fc01daae5a5 570
bogdanm 92:4fc01daae5a5 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
bogdanm 92:4fc01daae5a5 572 return(result);
bogdanm 92:4fc01daae5a5 573 }
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575
bogdanm 92:4fc01daae5a5 576 /** \brief STR Exclusive (16 bit)
bogdanm 92:4fc01daae5a5 577
bogdanm 92:4fc01daae5a5 578 This function performs a exclusive STR command for 16 bit values.
bogdanm 92:4fc01daae5a5 579
bogdanm 92:4fc01daae5a5 580 \param [in] value Value to store
bogdanm 92:4fc01daae5a5 581 \param [in] ptr Pointer to location
bogdanm 92:4fc01daae5a5 582 \return 0 Function succeeded
bogdanm 92:4fc01daae5a5 583 \return 1 Function failed
bogdanm 92:4fc01daae5a5 584 */
bogdanm 92:4fc01daae5a5 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
bogdanm 92:4fc01daae5a5 586 {
bogdanm 92:4fc01daae5a5 587 uint32_t result;
bogdanm 92:4fc01daae5a5 588
bogdanm 92:4fc01daae5a5 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
bogdanm 92:4fc01daae5a5 590 return(result);
bogdanm 92:4fc01daae5a5 591 }
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593
bogdanm 92:4fc01daae5a5 594 /** \brief STR Exclusive (32 bit)
bogdanm 92:4fc01daae5a5 595
bogdanm 92:4fc01daae5a5 596 This function performs a exclusive STR command for 32 bit values.
bogdanm 92:4fc01daae5a5 597
bogdanm 92:4fc01daae5a5 598 \param [in] value Value to store
bogdanm 92:4fc01daae5a5 599 \param [in] ptr Pointer to location
bogdanm 92:4fc01daae5a5 600 \return 0 Function succeeded
bogdanm 92:4fc01daae5a5 601 \return 1 Function failed
bogdanm 92:4fc01daae5a5 602 */
bogdanm 92:4fc01daae5a5 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
bogdanm 92:4fc01daae5a5 604 {
bogdanm 92:4fc01daae5a5 605 uint32_t result;
bogdanm 92:4fc01daae5a5 606
bogdanm 92:4fc01daae5a5 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
bogdanm 92:4fc01daae5a5 608 return(result);
bogdanm 92:4fc01daae5a5 609 }
bogdanm 92:4fc01daae5a5 610
bogdanm 92:4fc01daae5a5 611
bogdanm 92:4fc01daae5a5 612 /** \brief Remove the exclusive lock
bogdanm 92:4fc01daae5a5 613
bogdanm 92:4fc01daae5a5 614 This function removes the exclusive lock which is created by LDREX.
bogdanm 92:4fc01daae5a5 615
bogdanm 92:4fc01daae5a5 616 */
bogdanm 92:4fc01daae5a5 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
bogdanm 92:4fc01daae5a5 618 {
bogdanm 92:4fc01daae5a5 619 __ASM volatile ("clrex" ::: "memory");
bogdanm 92:4fc01daae5a5 620 }
bogdanm 92:4fc01daae5a5 621
bogdanm 92:4fc01daae5a5 622
bogdanm 92:4fc01daae5a5 623 /** \brief Signed Saturate
bogdanm 92:4fc01daae5a5 624
bogdanm 92:4fc01daae5a5 625 This function saturates a signed value.
bogdanm 92:4fc01daae5a5 626
bogdanm 92:4fc01daae5a5 627 \param [in] value Value to be saturated
bogdanm 92:4fc01daae5a5 628 \param [in] sat Bit position to saturate to (1..32)
bogdanm 92:4fc01daae5a5 629 \return Saturated value
bogdanm 92:4fc01daae5a5 630 */
bogdanm 92:4fc01daae5a5 631 #define __SSAT(ARG1,ARG2) \
bogdanm 92:4fc01daae5a5 632 ({ \
bogdanm 92:4fc01daae5a5 633 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 92:4fc01daae5a5 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 92:4fc01daae5a5 635 __RES; \
bogdanm 92:4fc01daae5a5 636 })
bogdanm 92:4fc01daae5a5 637
bogdanm 92:4fc01daae5a5 638
bogdanm 92:4fc01daae5a5 639 /** \brief Unsigned Saturate
bogdanm 92:4fc01daae5a5 640
bogdanm 92:4fc01daae5a5 641 This function saturates an unsigned value.
bogdanm 92:4fc01daae5a5 642
bogdanm 92:4fc01daae5a5 643 \param [in] value Value to be saturated
bogdanm 92:4fc01daae5a5 644 \param [in] sat Bit position to saturate to (0..31)
bogdanm 92:4fc01daae5a5 645 \return Saturated value
bogdanm 92:4fc01daae5a5 646 */
bogdanm 92:4fc01daae5a5 647 #define __USAT(ARG1,ARG2) \
bogdanm 92:4fc01daae5a5 648 ({ \
bogdanm 92:4fc01daae5a5 649 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 92:4fc01daae5a5 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 92:4fc01daae5a5 651 __RES; \
bogdanm 92:4fc01daae5a5 652 })
bogdanm 92:4fc01daae5a5 653
bogdanm 92:4fc01daae5a5 654
bogdanm 92:4fc01daae5a5 655 /** \brief Count leading zeros
bogdanm 92:4fc01daae5a5 656
bogdanm 92:4fc01daae5a5 657 This function counts the number of leading zeros of a data value.
bogdanm 92:4fc01daae5a5 658
bogdanm 92:4fc01daae5a5 659 \param [in] value Value to count the leading zeros
bogdanm 92:4fc01daae5a5 660 \return number of leading zeros in value
bogdanm 92:4fc01daae5a5 661 */
bogdanm 92:4fc01daae5a5 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
bogdanm 92:4fc01daae5a5 663 {
bogdanm 92:4fc01daae5a5 664 uint32_t result;
bogdanm 92:4fc01daae5a5 665
bogdanm 92:4fc01daae5a5 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
bogdanm 92:4fc01daae5a5 667 return(result);
bogdanm 92:4fc01daae5a5 668 }
bogdanm 92:4fc01daae5a5 669
bogdanm 92:4fc01daae5a5 670 #endif /* (__CORTEX_M >= 0x03) */
bogdanm 92:4fc01daae5a5 671
bogdanm 92:4fc01daae5a5 672
bogdanm 92:4fc01daae5a5 673
bogdanm 92:4fc01daae5a5 674
bogdanm 92:4fc01daae5a5 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
bogdanm 92:4fc01daae5a5 676 /* TASKING carm specific functions */
bogdanm 92:4fc01daae5a5 677
bogdanm 92:4fc01daae5a5 678 /*
bogdanm 92:4fc01daae5a5 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
bogdanm 92:4fc01daae5a5 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
bogdanm 92:4fc01daae5a5 681 * Including the CMSIS ones.
bogdanm 92:4fc01daae5a5 682 */
bogdanm 92:4fc01daae5a5 683
bogdanm 92:4fc01daae5a5 684 #endif
bogdanm 92:4fc01daae5a5 685
bogdanm 92:4fc01daae5a5 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
bogdanm 92:4fc01daae5a5 687
bogdanm 92:4fc01daae5a5 688 #endif /* __CORE_CMINSTR_H */