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TARGET_WIZwiki_W7500/core_caFunc.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Parent:
101:7cff1c4259d7
Child:
115:87f2f5183dfb
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**************************************************************************//**
Kojto 101:7cff1c4259d7 2 * @file core_caFunc.h
Kojto 101:7cff1c4259d7 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 101:7cff1c4259d7 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 101:7cff1c4259d7 6 *
Kojto 101:7cff1c4259d7 7 * @note
Kojto 101:7cff1c4259d7 8 *
Kojto 101:7cff1c4259d7 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 101:7cff1c4259d7 11
Kojto 101:7cff1c4259d7 12 All rights reserved.
Kojto 101:7cff1c4259d7 13 Redistribution and use in source and binary forms, with or without
Kojto 101:7cff1c4259d7 14 modification, are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 15 - Redistributions of source code must retain the above copyright
Kojto 101:7cff1c4259d7 16 notice, this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 101:7cff1c4259d7 18 notice, this list of conditions and the following disclaimer in the
Kojto 101:7cff1c4259d7 19 documentation and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 101:7cff1c4259d7 21 to endorse or promote products derived from this software without
Kojto 101:7cff1c4259d7 22 specific prior written permission.
Kojto 101:7cff1c4259d7 23 *
Kojto 101:7cff1c4259d7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 101:7cff1c4259d7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 101:7cff1c4259d7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 101:7cff1c4259d7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 101:7cff1c4259d7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 101:7cff1c4259d7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 101:7cff1c4259d7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 101:7cff1c4259d7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 101:7cff1c4259d7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 35 ---------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 #ifndef __CORE_CAFUNC_H__
Kojto 101:7cff1c4259d7 39 #define __CORE_CAFUNC_H__
Kojto 101:7cff1c4259d7 40
Kojto 101:7cff1c4259d7 41
Kojto 101:7cff1c4259d7 42 /* ########################### Core Function Access ########################### */
Kojto 101:7cff1c4259d7 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 101:7cff1c4259d7 45 @{
Kojto 101:7cff1c4259d7 46 */
Kojto 101:7cff1c4259d7 47
Kojto 101:7cff1c4259d7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 101:7cff1c4259d7 49 /* ARM armcc specific functions */
Kojto 101:7cff1c4259d7 50
Kojto 101:7cff1c4259d7 51 #if (__ARMCC_VERSION < 400677)
Kojto 101:7cff1c4259d7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 101:7cff1c4259d7 53 #endif
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 #define MODE_USR 0x10
Kojto 101:7cff1c4259d7 56 #define MODE_FIQ 0x11
Kojto 101:7cff1c4259d7 57 #define MODE_IRQ 0x12
Kojto 101:7cff1c4259d7 58 #define MODE_SVC 0x13
Kojto 101:7cff1c4259d7 59 #define MODE_MON 0x16
Kojto 101:7cff1c4259d7 60 #define MODE_ABT 0x17
Kojto 101:7cff1c4259d7 61 #define MODE_HYP 0x1A
Kojto 101:7cff1c4259d7 62 #define MODE_UND 0x1B
Kojto 101:7cff1c4259d7 63 #define MODE_SYS 0x1F
Kojto 101:7cff1c4259d7 64
Kojto 101:7cff1c4259d7 65 /** \brief Get APSR Register
Kojto 101:7cff1c4259d7 66
Kojto 101:7cff1c4259d7 67 This function returns the content of the APSR Register.
Kojto 101:7cff1c4259d7 68
Kojto 101:7cff1c4259d7 69 \return APSR Register value
Kojto 101:7cff1c4259d7 70 */
Kojto 101:7cff1c4259d7 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 101:7cff1c4259d7 72 {
Kojto 101:7cff1c4259d7 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 101:7cff1c4259d7 74 return(__regAPSR);
Kojto 101:7cff1c4259d7 75 }
Kojto 101:7cff1c4259d7 76
Kojto 101:7cff1c4259d7 77
Kojto 101:7cff1c4259d7 78 /** \brief Get CPSR Register
Kojto 101:7cff1c4259d7 79
Kojto 101:7cff1c4259d7 80 This function returns the content of the CPSR Register.
Kojto 101:7cff1c4259d7 81
Kojto 101:7cff1c4259d7 82 \return CPSR Register value
Kojto 101:7cff1c4259d7 83 */
Kojto 101:7cff1c4259d7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 101:7cff1c4259d7 85 {
Kojto 101:7cff1c4259d7 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 101:7cff1c4259d7 87 return(__regCPSR);
Kojto 101:7cff1c4259d7 88 }
Kojto 101:7cff1c4259d7 89
Kojto 101:7cff1c4259d7 90 /** \brief Set Stack Pointer
Kojto 101:7cff1c4259d7 91
Kojto 101:7cff1c4259d7 92 This function assigns the given value to the current stack pointer.
Kojto 101:7cff1c4259d7 93
Kojto 101:7cff1c4259d7 94 \param [in] topOfStack Stack Pointer value to set
Kojto 101:7cff1c4259d7 95 */
Kojto 101:7cff1c4259d7 96 register uint32_t __regSP __ASM("sp");
Kojto 101:7cff1c4259d7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 101:7cff1c4259d7 98 {
Kojto 101:7cff1c4259d7 99 __regSP = topOfStack;
Kojto 101:7cff1c4259d7 100 }
Kojto 101:7cff1c4259d7 101
Kojto 101:7cff1c4259d7 102
Kojto 101:7cff1c4259d7 103 /** \brief Get link register
Kojto 101:7cff1c4259d7 104
Kojto 101:7cff1c4259d7 105 This function returns the value of the link register
Kojto 101:7cff1c4259d7 106
Kojto 101:7cff1c4259d7 107 \return Value of link register
Kojto 101:7cff1c4259d7 108 */
Kojto 101:7cff1c4259d7 109 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 101:7cff1c4259d7 111 {
Kojto 101:7cff1c4259d7 112 return(__reglr);
Kojto 101:7cff1c4259d7 113 }
Kojto 101:7cff1c4259d7 114
Kojto 101:7cff1c4259d7 115 /** \brief Set link register
Kojto 101:7cff1c4259d7 116
Kojto 101:7cff1c4259d7 117 This function sets the value of the link register
Kojto 101:7cff1c4259d7 118
Kojto 101:7cff1c4259d7 119 \param [in] lr LR value to set
Kojto 101:7cff1c4259d7 120 */
Kojto 101:7cff1c4259d7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 101:7cff1c4259d7 122 {
Kojto 101:7cff1c4259d7 123 __reglr = lr;
Kojto 101:7cff1c4259d7 124 }
Kojto 101:7cff1c4259d7 125
Kojto 101:7cff1c4259d7 126 /** \brief Set Process Stack Pointer
Kojto 101:7cff1c4259d7 127
Kojto 101:7cff1c4259d7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 101:7cff1c4259d7 129
Kojto 101:7cff1c4259d7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 131 */
Kojto 101:7cff1c4259d7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 101:7cff1c4259d7 133 {
Kojto 101:7cff1c4259d7 134 ARM
Kojto 101:7cff1c4259d7 135 PRESERVE8
Kojto 101:7cff1c4259d7 136
Kojto 101:7cff1c4259d7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 101:7cff1c4259d7 138 MRS R1, CPSR
Kojto 101:7cff1c4259d7 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 101:7cff1c4259d7 140 MOV SP, R0
Kojto 101:7cff1c4259d7 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 101:7cff1c4259d7 142 ISB
Kojto 101:7cff1c4259d7 143 BX LR
Kojto 101:7cff1c4259d7 144
Kojto 101:7cff1c4259d7 145 }
Kojto 101:7cff1c4259d7 146
Kojto 101:7cff1c4259d7 147 /** \brief Set User Mode
Kojto 101:7cff1c4259d7 148
Kojto 101:7cff1c4259d7 149 This function changes the processor state to User Mode
Kojto 101:7cff1c4259d7 150 */
Kojto 101:7cff1c4259d7 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 101:7cff1c4259d7 152 {
Kojto 101:7cff1c4259d7 153 ARM
Kojto 101:7cff1c4259d7 154
Kojto 101:7cff1c4259d7 155 CPS #MODE_USR
Kojto 101:7cff1c4259d7 156 BX LR
Kojto 101:7cff1c4259d7 157 }
Kojto 101:7cff1c4259d7 158
Kojto 101:7cff1c4259d7 159
Kojto 101:7cff1c4259d7 160 /** \brief Enable FIQ
Kojto 101:7cff1c4259d7 161
Kojto 101:7cff1c4259d7 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 163 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 164 */
Kojto 101:7cff1c4259d7 165 #define __enable_fault_irq __enable_fiq
Kojto 101:7cff1c4259d7 166
Kojto 101:7cff1c4259d7 167
Kojto 101:7cff1c4259d7 168 /** \brief Disable FIQ
Kojto 101:7cff1c4259d7 169
Kojto 101:7cff1c4259d7 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 171 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 172 */
Kojto 101:7cff1c4259d7 173 #define __disable_fault_irq __disable_fiq
Kojto 101:7cff1c4259d7 174
Kojto 101:7cff1c4259d7 175
Kojto 101:7cff1c4259d7 176 /** \brief Get FPSCR
Kojto 101:7cff1c4259d7 177
Kojto 101:7cff1c4259d7 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 179
Kojto 101:7cff1c4259d7 180 \return Floating Point Status/Control register value
Kojto 101:7cff1c4259d7 181 */
Kojto 101:7cff1c4259d7 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 101:7cff1c4259d7 183 {
Kojto 101:7cff1c4259d7 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 186 return(__regfpscr);
Kojto 101:7cff1c4259d7 187 #else
Kojto 101:7cff1c4259d7 188 return(0);
Kojto 101:7cff1c4259d7 189 #endif
Kojto 101:7cff1c4259d7 190 }
Kojto 101:7cff1c4259d7 191
Kojto 101:7cff1c4259d7 192
Kojto 101:7cff1c4259d7 193 /** \brief Set FPSCR
Kojto 101:7cff1c4259d7 194
Kojto 101:7cff1c4259d7 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 196
Kojto 101:7cff1c4259d7 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 101:7cff1c4259d7 198 */
Kojto 101:7cff1c4259d7 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 101:7cff1c4259d7 200 {
Kojto 101:7cff1c4259d7 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 203 __regfpscr = (fpscr);
Kojto 101:7cff1c4259d7 204 #endif
Kojto 101:7cff1c4259d7 205 }
Kojto 101:7cff1c4259d7 206
Kojto 101:7cff1c4259d7 207 /** \brief Get FPEXC
Kojto 101:7cff1c4259d7 208
Kojto 101:7cff1c4259d7 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 210
Kojto 101:7cff1c4259d7 211 \return Floating Point Exception Control register value
Kojto 101:7cff1c4259d7 212 */
Kojto 101:7cff1c4259d7 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 101:7cff1c4259d7 214 {
Kojto 101:7cff1c4259d7 215 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 217 return(__regfpexc);
Kojto 101:7cff1c4259d7 218 #else
Kojto 101:7cff1c4259d7 219 return(0);
Kojto 101:7cff1c4259d7 220 #endif
Kojto 101:7cff1c4259d7 221 }
Kojto 101:7cff1c4259d7 222
Kojto 101:7cff1c4259d7 223
Kojto 101:7cff1c4259d7 224 /** \brief Set FPEXC
Kojto 101:7cff1c4259d7 225
Kojto 101:7cff1c4259d7 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 227
Kojto 101:7cff1c4259d7 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 101:7cff1c4259d7 229 */
Kojto 101:7cff1c4259d7 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 101:7cff1c4259d7 231 {
Kojto 101:7cff1c4259d7 232 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 234 __regfpexc = (fpexc);
Kojto 101:7cff1c4259d7 235 #endif
Kojto 101:7cff1c4259d7 236 }
Kojto 101:7cff1c4259d7 237
Kojto 101:7cff1c4259d7 238 /** \brief Get CPACR
Kojto 101:7cff1c4259d7 239
Kojto 101:7cff1c4259d7 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 241
Kojto 101:7cff1c4259d7 242 \return Coprocessor Access Control register value
Kojto 101:7cff1c4259d7 243 */
Kojto 101:7cff1c4259d7 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 101:7cff1c4259d7 245 {
Kojto 101:7cff1c4259d7 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 247 return __regCPACR;
Kojto 101:7cff1c4259d7 248 }
Kojto 101:7cff1c4259d7 249
Kojto 101:7cff1c4259d7 250 /** \brief Set CPACR
Kojto 101:7cff1c4259d7 251
Kojto 101:7cff1c4259d7 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 101:7cff1c4259d7 255 */
Kojto 101:7cff1c4259d7 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 101:7cff1c4259d7 257 {
Kojto 101:7cff1c4259d7 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 259 __regCPACR = cpacr;
Kojto 101:7cff1c4259d7 260 __ISB();
Kojto 101:7cff1c4259d7 261 }
Kojto 101:7cff1c4259d7 262
Kojto 101:7cff1c4259d7 263 /** \brief Get CBAR
Kojto 101:7cff1c4259d7 264
Kojto 101:7cff1c4259d7 265 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 266
Kojto 101:7cff1c4259d7 267 \return Configuration Base Address register value
Kojto 101:7cff1c4259d7 268 */
Kojto 101:7cff1c4259d7 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 101:7cff1c4259d7 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 101:7cff1c4259d7 271 return(__regCBAR);
Kojto 101:7cff1c4259d7 272 }
Kojto 101:7cff1c4259d7 273
Kojto 101:7cff1c4259d7 274 /** \brief Get TTBR0
Kojto 101:7cff1c4259d7 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 277
Kojto 101:7cff1c4259d7 278 \return Translation Table Base Register 0 value
Kojto 101:7cff1c4259d7 279 */
Kojto 101:7cff1c4259d7 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 101:7cff1c4259d7 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 282 return(__regTTBR0);
Kojto 101:7cff1c4259d7 283 }
Kojto 101:7cff1c4259d7 284
Kojto 101:7cff1c4259d7 285 /** \brief Set TTBR0
Kojto 101:7cff1c4259d7 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 288
Kojto 101:7cff1c4259d7 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 101:7cff1c4259d7 290 */
Kojto 101:7cff1c4259d7 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 101:7cff1c4259d7 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 293 __regTTBR0 = ttbr0;
Kojto 101:7cff1c4259d7 294 __ISB();
Kojto 101:7cff1c4259d7 295 }
Kojto 101:7cff1c4259d7 296
Kojto 101:7cff1c4259d7 297 /** \brief Get DACR
Kojto 101:7cff1c4259d7 298
Kojto 101:7cff1c4259d7 299 This function returns the value of the Domain Access Control Register.
Kojto 101:7cff1c4259d7 300
Kojto 101:7cff1c4259d7 301 \return Domain Access Control Register value
Kojto 101:7cff1c4259d7 302 */
Kojto 101:7cff1c4259d7 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 101:7cff1c4259d7 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 305 return(__regDACR);
Kojto 101:7cff1c4259d7 306 }
Kojto 101:7cff1c4259d7 307
Kojto 101:7cff1c4259d7 308 /** \brief Set DACR
Kojto 101:7cff1c4259d7 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 101:7cff1c4259d7 311
Kojto 101:7cff1c4259d7 312 \param [in] dacr Domain Access Control Register value to set
Kojto 101:7cff1c4259d7 313 */
Kojto 101:7cff1c4259d7 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 101:7cff1c4259d7 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 316 __regDACR = dacr;
Kojto 101:7cff1c4259d7 317 __ISB();
Kojto 101:7cff1c4259d7 318 }
Kojto 101:7cff1c4259d7 319
Kojto 101:7cff1c4259d7 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 101:7cff1c4259d7 321
Kojto 101:7cff1c4259d7 322 /** \brief Set SCTLR
Kojto 101:7cff1c4259d7 323
Kojto 101:7cff1c4259d7 324 This function assigns the given value to the System Control Register.
Kojto 101:7cff1c4259d7 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 101:7cff1c4259d7 327 */
Kojto 101:7cff1c4259d7 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 101:7cff1c4259d7 329 {
Kojto 101:7cff1c4259d7 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 331 __regSCTLR = sctlr;
Kojto 101:7cff1c4259d7 332 }
Kojto 101:7cff1c4259d7 333
Kojto 101:7cff1c4259d7 334 /** \brief Get SCTLR
Kojto 101:7cff1c4259d7 335
Kojto 101:7cff1c4259d7 336 This function returns the value of the System Control Register.
Kojto 101:7cff1c4259d7 337
Kojto 101:7cff1c4259d7 338 \return System Control Register value
Kojto 101:7cff1c4259d7 339 */
Kojto 101:7cff1c4259d7 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 101:7cff1c4259d7 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 342 return(__regSCTLR);
Kojto 101:7cff1c4259d7 343 }
Kojto 101:7cff1c4259d7 344
Kojto 101:7cff1c4259d7 345 /** \brief Enable Caches
Kojto 101:7cff1c4259d7 346
Kojto 101:7cff1c4259d7 347 Enable Caches
Kojto 101:7cff1c4259d7 348 */
Kojto 101:7cff1c4259d7 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 101:7cff1c4259d7 350 // Set I bit 12 to enable I Cache
Kojto 101:7cff1c4259d7 351 // Set C bit 2 to enable D Cache
Kojto 101:7cff1c4259d7 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 101:7cff1c4259d7 353 }
Kojto 101:7cff1c4259d7 354
Kojto 101:7cff1c4259d7 355 /** \brief Disable Caches
Kojto 101:7cff1c4259d7 356
Kojto 101:7cff1c4259d7 357 Disable Caches
Kojto 101:7cff1c4259d7 358 */
Kojto 101:7cff1c4259d7 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 101:7cff1c4259d7 360 // Clear I bit 12 to disable I Cache
Kojto 101:7cff1c4259d7 361 // Clear C bit 2 to disable D Cache
Kojto 101:7cff1c4259d7 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 101:7cff1c4259d7 363 __ISB();
Kojto 101:7cff1c4259d7 364 }
Kojto 101:7cff1c4259d7 365
Kojto 101:7cff1c4259d7 366 /** \brief Enable BTAC
Kojto 101:7cff1c4259d7 367
Kojto 101:7cff1c4259d7 368 Enable BTAC
Kojto 101:7cff1c4259d7 369 */
Kojto 101:7cff1c4259d7 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 101:7cff1c4259d7 371 // Set Z bit 11 to enable branch prediction
Kojto 101:7cff1c4259d7 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 101:7cff1c4259d7 373 __ISB();
Kojto 101:7cff1c4259d7 374 }
Kojto 101:7cff1c4259d7 375
Kojto 101:7cff1c4259d7 376 /** \brief Disable BTAC
Kojto 101:7cff1c4259d7 377
Kojto 101:7cff1c4259d7 378 Disable BTAC
Kojto 101:7cff1c4259d7 379 */
Kojto 101:7cff1c4259d7 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 101:7cff1c4259d7 381 // Clear Z bit 11 to disable branch prediction
Kojto 101:7cff1c4259d7 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 101:7cff1c4259d7 383 }
Kojto 101:7cff1c4259d7 384
Kojto 101:7cff1c4259d7 385
Kojto 101:7cff1c4259d7 386 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 387
Kojto 101:7cff1c4259d7 388 Enable MMU
Kojto 101:7cff1c4259d7 389 */
Kojto 101:7cff1c4259d7 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 101:7cff1c4259d7 391 // Set M bit 0 to enable the MMU
Kojto 101:7cff1c4259d7 392 // Set AFE bit to enable simplified access permissions model
Kojto 101:7cff1c4259d7 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 101:7cff1c4259d7 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 101:7cff1c4259d7 395 __ISB();
Kojto 101:7cff1c4259d7 396 }
Kojto 101:7cff1c4259d7 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 101:7cff1c4259d7 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 101:7cff1c4259d7 401 */
Kojto 101:7cff1c4259d7 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 101:7cff1c4259d7 403 // Clear M bit 0 to disable the MMU
Kojto 101:7cff1c4259d7 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 101:7cff1c4259d7 405 __ISB();
Kojto 101:7cff1c4259d7 406 }
Kojto 101:7cff1c4259d7 407
Kojto 101:7cff1c4259d7 408 /******************************** TLB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 409 /** \brief Invalidate the whole tlb
Kojto 101:7cff1c4259d7 410
Kojto 101:7cff1c4259d7 411 TLBIALL. Invalidate the whole tlb
Kojto 101:7cff1c4259d7 412 */
Kojto 101:7cff1c4259d7 413
Kojto 101:7cff1c4259d7 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 101:7cff1c4259d7 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 101:7cff1c4259d7 416 __TLBIALL = 0;
Kojto 101:7cff1c4259d7 417 __DSB();
Kojto 101:7cff1c4259d7 418 __ISB();
Kojto 101:7cff1c4259d7 419 }
Kojto 101:7cff1c4259d7 420
Kojto 101:7cff1c4259d7 421 /******************************** BTB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 422 /** \brief Invalidate entire branch predictor array
Kojto 101:7cff1c4259d7 423
Kojto 101:7cff1c4259d7 424 BPIALL. Branch Predictor Invalidate All.
Kojto 101:7cff1c4259d7 425 */
Kojto 101:7cff1c4259d7 426
Kojto 101:7cff1c4259d7 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 101:7cff1c4259d7 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 101:7cff1c4259d7 429 __BPIALL = 0;
Kojto 101:7cff1c4259d7 430 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 101:7cff1c4259d7 432 }
Kojto 101:7cff1c4259d7 433
Kojto 101:7cff1c4259d7 434
Kojto 101:7cff1c4259d7 435 /******************************** L1 cache operations ******************************************************/
Kojto 101:7cff1c4259d7 436
Kojto 101:7cff1c4259d7 437 /** \brief Invalidate the whole I$
Kojto 101:7cff1c4259d7 438
Kojto 101:7cff1c4259d7 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 101:7cff1c4259d7 440 */
Kojto 101:7cff1c4259d7 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 101:7cff1c4259d7 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 101:7cff1c4259d7 443 __ICIALLU = 0;
Kojto 101:7cff1c4259d7 444 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 101:7cff1c4259d7 446 }
Kojto 101:7cff1c4259d7 447
Kojto 101:7cff1c4259d7 448 /** \brief Clean D$ by MVA
Kojto 101:7cff1c4259d7 449
Kojto 101:7cff1c4259d7 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 101:7cff1c4259d7 451 */
Kojto 101:7cff1c4259d7 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 101:7cff1c4259d7 454 __DCCMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 456 }
Kojto 101:7cff1c4259d7 457
Kojto 101:7cff1c4259d7 458 /** \brief Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 459
Kojto 101:7cff1c4259d7 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 461 */
Kojto 101:7cff1c4259d7 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 101:7cff1c4259d7 464 __DCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 466 }
Kojto 101:7cff1c4259d7 467
Kojto 101:7cff1c4259d7 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 469
Kojto 101:7cff1c4259d7 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 471 */
Kojto 101:7cff1c4259d7 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 101:7cff1c4259d7 474 __DCCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 476 }
Kojto 101:7cff1c4259d7 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 101:7cff1c4259d7 481 */
Kojto 101:7cff1c4259d7 482 #pragma push
Kojto 101:7cff1c4259d7 483 #pragma arm
Kojto 101:7cff1c4259d7 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 101:7cff1c4259d7 485 ARM
Kojto 101:7cff1c4259d7 486
Kojto 101:7cff1c4259d7 487 PUSH {R4-R11}
Kojto 101:7cff1c4259d7 488
Kojto 101:7cff1c4259d7 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 101:7cff1c4259d7 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 101:7cff1c4259d7 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 101:7cff1c4259d7 492 BEQ Finished // If 0, no need to clean
Kojto 101:7cff1c4259d7 493
Kojto 101:7cff1c4259d7 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 101:7cff1c4259d7 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 101:7cff1c4259d7 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 101:7cff1c4259d7 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 101:7cff1c4259d7 498 CMP R1, #2
Kojto 101:7cff1c4259d7 499 BLT Skip // No cache or only instruction cache at this level
Kojto 101:7cff1c4259d7 500
Kojto 101:7cff1c4259d7 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 101:7cff1c4259d7 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 101:7cff1c4259d7 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 101:7cff1c4259d7 504 AND R2, R1, #7 // Extract the line length field
Kojto 101:7cff1c4259d7 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 101:7cff1c4259d7 506 LDR R4, =0x3FF
Kojto 101:7cff1c4259d7 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 101:7cff1c4259d7 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 101:7cff1c4259d7 509 LDR R7, =0x7FFF
Kojto 101:7cff1c4259d7 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 101:7cff1c4259d7 511
Kojto 101:7cff1c4259d7 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 101:7cff1c4259d7 513
Kojto 101:7cff1c4259d7 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 101:7cff1c4259d7 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 101:7cff1c4259d7 516 CMP R0, #0
Kojto 101:7cff1c4259d7 517 BNE Dccsw
Kojto 101:7cff1c4259d7 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 519 B cont
Kojto 101:7cff1c4259d7 520 Dccsw CMP R0, #1
Kojto 101:7cff1c4259d7 521 BNE Dccisw
Kojto 101:7cff1c4259d7 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 101:7cff1c4259d7 526 BGE Loop3
Kojto 101:7cff1c4259d7 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 101:7cff1c4259d7 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 101:7cff1c4259d7 530 CMP R3, R10
Kojto 101:7cff1c4259d7 531 BGT Loop1
Kojto 101:7cff1c4259d7 532
Kojto 101:7cff1c4259d7 533 Finished
Kojto 101:7cff1c4259d7 534 DSB
Kojto 101:7cff1c4259d7 535 POP {R4-R11}
Kojto 101:7cff1c4259d7 536 BX lr
Kojto 101:7cff1c4259d7 537
Kojto 101:7cff1c4259d7 538 }
Kojto 101:7cff1c4259d7 539 #pragma pop
Kojto 101:7cff1c4259d7 540
Kojto 101:7cff1c4259d7 541
Kojto 101:7cff1c4259d7 542 /** \brief Invalidate the whole D$
Kojto 101:7cff1c4259d7 543
Kojto 101:7cff1c4259d7 544 DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 545 */
Kojto 101:7cff1c4259d7 546
Kojto 101:7cff1c4259d7 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 548 __v7_all_cache(0);
Kojto 101:7cff1c4259d7 549 }
Kojto 101:7cff1c4259d7 550
Kojto 101:7cff1c4259d7 551 /** \brief Clean the whole D$
Kojto 101:7cff1c4259d7 552
Kojto 101:7cff1c4259d7 553 DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 554 */
Kojto 101:7cff1c4259d7 555
Kojto 101:7cff1c4259d7 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 101:7cff1c4259d7 557 __v7_all_cache(1);
Kojto 101:7cff1c4259d7 558 }
Kojto 101:7cff1c4259d7 559
Kojto 101:7cff1c4259d7 560 /** \brief Clean and invalidate the whole D$
Kojto 101:7cff1c4259d7 561
Kojto 101:7cff1c4259d7 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 563 */
Kojto 101:7cff1c4259d7 564
Kojto 101:7cff1c4259d7 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 566 __v7_all_cache(2);
Kojto 101:7cff1c4259d7 567 }
Kojto 101:7cff1c4259d7 568
Kojto 101:7cff1c4259d7 569 #include "core_ca_mmu.h"
Kojto 101:7cff1c4259d7 570
Kojto 101:7cff1c4259d7 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 101:7cff1c4259d7 572
Kojto 101:7cff1c4259d7 573 #error IAR Compiler support not implemented for Cortex-A
Kojto 101:7cff1c4259d7 574
Kojto 101:7cff1c4259d7 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 101:7cff1c4259d7 576 /* GNU gcc specific functions */
Kojto 101:7cff1c4259d7 577
Kojto 101:7cff1c4259d7 578 #define MODE_USR 0x10
Kojto 101:7cff1c4259d7 579 #define MODE_FIQ 0x11
Kojto 101:7cff1c4259d7 580 #define MODE_IRQ 0x12
Kojto 101:7cff1c4259d7 581 #define MODE_SVC 0x13
Kojto 101:7cff1c4259d7 582 #define MODE_MON 0x16
Kojto 101:7cff1c4259d7 583 #define MODE_ABT 0x17
Kojto 101:7cff1c4259d7 584 #define MODE_HYP 0x1A
Kojto 101:7cff1c4259d7 585 #define MODE_UND 0x1B
Kojto 101:7cff1c4259d7 586 #define MODE_SYS 0x1F
Kojto 101:7cff1c4259d7 587
Kojto 101:7cff1c4259d7 588
Kojto 101:7cff1c4259d7 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 101:7cff1c4259d7 590 {
Kojto 101:7cff1c4259d7 591 __ASM volatile ("cpsie i");
Kojto 101:7cff1c4259d7 592 }
Kojto 101:7cff1c4259d7 593
Kojto 101:7cff1c4259d7 594 /** \brief Disable IRQ Interrupts
Kojto 101:7cff1c4259d7 595
Kojto 101:7cff1c4259d7 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 101:7cff1c4259d7 597 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 598 */
Kojto 101:7cff1c4259d7 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 101:7cff1c4259d7 600 {
Kojto 101:7cff1c4259d7 601 uint32_t result;
Kojto 101:7cff1c4259d7 602
Kojto 101:7cff1c4259d7 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 101:7cff1c4259d7 604 __ASM volatile ("cpsid i");
Kojto 101:7cff1c4259d7 605 return(result & 0x80);
Kojto 101:7cff1c4259d7 606 }
Kojto 101:7cff1c4259d7 607
Kojto 101:7cff1c4259d7 608
Kojto 101:7cff1c4259d7 609 /** \brief Get APSR Register
Kojto 101:7cff1c4259d7 610
Kojto 101:7cff1c4259d7 611 This function returns the content of the APSR Register.
Kojto 101:7cff1c4259d7 612
Kojto 101:7cff1c4259d7 613 \return APSR Register value
Kojto 101:7cff1c4259d7 614 */
Kojto 101:7cff1c4259d7 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 101:7cff1c4259d7 616 {
Kojto 101:7cff1c4259d7 617 #if 1
Kojto 108:34e6b704fe68 618 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 101:7cff1c4259d7 620 #else
Kojto 101:7cff1c4259d7 621 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 622 #endif
Kojto 101:7cff1c4259d7 623 return(__regAPSR);
Kojto 101:7cff1c4259d7 624 }
Kojto 101:7cff1c4259d7 625
Kojto 101:7cff1c4259d7 626
Kojto 101:7cff1c4259d7 627 /** \brief Get CPSR Register
Kojto 101:7cff1c4259d7 628
Kojto 101:7cff1c4259d7 629 This function returns the content of the CPSR Register.
Kojto 101:7cff1c4259d7 630
Kojto 101:7cff1c4259d7 631 \return CPSR Register value
Kojto 101:7cff1c4259d7 632 */
Kojto 101:7cff1c4259d7 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 101:7cff1c4259d7 634 {
Kojto 101:7cff1c4259d7 635 #if 1
Kojto 101:7cff1c4259d7 636 register uint32_t __regCPSR;
Kojto 101:7cff1c4259d7 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 101:7cff1c4259d7 638 #else
Kojto 101:7cff1c4259d7 639 register uint32_t __regCPSR __ASM("cpsr");
Kojto 101:7cff1c4259d7 640 #endif
Kojto 101:7cff1c4259d7 641 return(__regCPSR);
Kojto 101:7cff1c4259d7 642 }
Kojto 101:7cff1c4259d7 643
Kojto 101:7cff1c4259d7 644 #if 0
Kojto 101:7cff1c4259d7 645 /** \brief Set Stack Pointer
Kojto 101:7cff1c4259d7 646
Kojto 101:7cff1c4259d7 647 This function assigns the given value to the current stack pointer.
Kojto 101:7cff1c4259d7 648
Kojto 101:7cff1c4259d7 649 \param [in] topOfStack Stack Pointer value to set
Kojto 101:7cff1c4259d7 650 */
Kojto 101:7cff1c4259d7 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 101:7cff1c4259d7 652 {
Kojto 101:7cff1c4259d7 653 register uint32_t __regSP __ASM("sp");
Kojto 101:7cff1c4259d7 654 __regSP = topOfStack;
Kojto 101:7cff1c4259d7 655 }
Kojto 101:7cff1c4259d7 656 #endif
Kojto 101:7cff1c4259d7 657
Kojto 101:7cff1c4259d7 658 /** \brief Get link register
Kojto 101:7cff1c4259d7 659
Kojto 101:7cff1c4259d7 660 This function returns the value of the link register
Kojto 101:7cff1c4259d7 661
Kojto 101:7cff1c4259d7 662 \return Value of link register
Kojto 101:7cff1c4259d7 663 */
Kojto 101:7cff1c4259d7 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 101:7cff1c4259d7 665 {
Kojto 101:7cff1c4259d7 666 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 667 return(__reglr);
Kojto 101:7cff1c4259d7 668 }
Kojto 101:7cff1c4259d7 669
Kojto 101:7cff1c4259d7 670 #if 0
Kojto 101:7cff1c4259d7 671 /** \brief Set link register
Kojto 101:7cff1c4259d7 672
Kojto 101:7cff1c4259d7 673 This function sets the value of the link register
Kojto 101:7cff1c4259d7 674
Kojto 101:7cff1c4259d7 675 \param [in] lr LR value to set
Kojto 101:7cff1c4259d7 676 */
Kojto 101:7cff1c4259d7 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 101:7cff1c4259d7 678 {
Kojto 101:7cff1c4259d7 679 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 680 __reglr = lr;
Kojto 101:7cff1c4259d7 681 }
Kojto 101:7cff1c4259d7 682 #endif
Kojto 101:7cff1c4259d7 683
Kojto 101:7cff1c4259d7 684 /** \brief Set Process Stack Pointer
Kojto 101:7cff1c4259d7 685
Kojto 101:7cff1c4259d7 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 101:7cff1c4259d7 687
Kojto 101:7cff1c4259d7 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 689 */
Kojto 108:34e6b704fe68 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 691 {
Kojto 108:34e6b704fe68 692 __asm__ volatile (
Kojto 108:34e6b704fe68 693 ".ARM;"
Kojto 108:34e6b704fe68 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 695
Kojto 108:34e6b704fe68 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 697 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 698 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 699 "MOV SP, R0;"
Kojto 108:34e6b704fe68 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 701 "ISB;"
Kojto 108:34e6b704fe68 702 //"BX LR;"
Kojto 108:34e6b704fe68 703 :
Kojto 108:34e6b704fe68 704 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 705 : "r0", "r1");
Kojto 108:34e6b704fe68 706 return;
Kojto 108:34e6b704fe68 707 }
Kojto 101:7cff1c4259d7 708
Kojto 101:7cff1c4259d7 709 /** \brief Set User Mode
Kojto 101:7cff1c4259d7 710
Kojto 101:7cff1c4259d7 711 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 712 */
Kojto 108:34e6b704fe68 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 714 {
Kojto 108:34e6b704fe68 715 __asm__ volatile (
Kojto 108:34e6b704fe68 716 ".ARM;"
Kojto 101:7cff1c4259d7 717
Kojto 108:34e6b704fe68 718 "CPS %0;"
Kojto 108:34e6b704fe68 719 //"BX LR;"
Kojto 108:34e6b704fe68 720 :
Kojto 108:34e6b704fe68 721 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 722 : );
Kojto 108:34e6b704fe68 723 return;
Kojto 108:34e6b704fe68 724 }
Kojto 108:34e6b704fe68 725
Kojto 101:7cff1c4259d7 726
Kojto 101:7cff1c4259d7 727 /** \brief Enable FIQ
Kojto 101:7cff1c4259d7 728
Kojto 101:7cff1c4259d7 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 730 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 731 */
Kojto 108:34e6b704fe68 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 101:7cff1c4259d7 733
Kojto 101:7cff1c4259d7 734
Kojto 101:7cff1c4259d7 735 /** \brief Disable FIQ
Kojto 101:7cff1c4259d7 736
Kojto 101:7cff1c4259d7 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 738 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 739 */
Kojto 108:34e6b704fe68 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 101:7cff1c4259d7 741
Kojto 101:7cff1c4259d7 742
Kojto 101:7cff1c4259d7 743 /** \brief Get FPSCR
Kojto 101:7cff1c4259d7 744
Kojto 101:7cff1c4259d7 745 This function returns the current value of the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 746
Kojto 101:7cff1c4259d7 747 \return Floating Point Status/Control register value
Kojto 101:7cff1c4259d7 748 */
Kojto 101:7cff1c4259d7 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 101:7cff1c4259d7 750 {
Kojto 101:7cff1c4259d7 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 752 #if 1
Kojto 101:7cff1c4259d7 753 uint32_t result;
Kojto 101:7cff1c4259d7 754
Kojto 101:7cff1c4259d7 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 101:7cff1c4259d7 756 return (result);
Kojto 101:7cff1c4259d7 757 #else
Kojto 101:7cff1c4259d7 758 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 759 return(__regfpscr);
Kojto 101:7cff1c4259d7 760 #endif
Kojto 101:7cff1c4259d7 761 #else
Kojto 101:7cff1c4259d7 762 return(0);
Kojto 101:7cff1c4259d7 763 #endif
Kojto 101:7cff1c4259d7 764 }
Kojto 101:7cff1c4259d7 765
Kojto 101:7cff1c4259d7 766
Kojto 101:7cff1c4259d7 767 /** \brief Set FPSCR
Kojto 101:7cff1c4259d7 768
Kojto 101:7cff1c4259d7 769 This function assigns the given value to the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 770
Kojto 101:7cff1c4259d7 771 \param [in] fpscr Floating Point Status/Control value to set
Kojto 101:7cff1c4259d7 772 */
Kojto 101:7cff1c4259d7 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 101:7cff1c4259d7 774 {
Kojto 101:7cff1c4259d7 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 776 #if 1
Kojto 101:7cff1c4259d7 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 101:7cff1c4259d7 778 #else
Kojto 101:7cff1c4259d7 779 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 780 __regfpscr = (fpscr);
Kojto 101:7cff1c4259d7 781 #endif
Kojto 101:7cff1c4259d7 782 #endif
Kojto 101:7cff1c4259d7 783 }
Kojto 101:7cff1c4259d7 784
Kojto 101:7cff1c4259d7 785 /** \brief Get FPEXC
Kojto 101:7cff1c4259d7 786
Kojto 101:7cff1c4259d7 787 This function returns the current value of the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 788
Kojto 101:7cff1c4259d7 789 \return Floating Point Exception Control register value
Kojto 101:7cff1c4259d7 790 */
Kojto 101:7cff1c4259d7 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 101:7cff1c4259d7 792 {
Kojto 101:7cff1c4259d7 793 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 794 #if 1
Kojto 101:7cff1c4259d7 795 uint32_t result;
Kojto 101:7cff1c4259d7 796
Kojto 101:7cff1c4259d7 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 101:7cff1c4259d7 798 return (result);
Kojto 101:7cff1c4259d7 799 #else
Kojto 101:7cff1c4259d7 800 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 801 return(__regfpexc);
Kojto 101:7cff1c4259d7 802 #endif
Kojto 101:7cff1c4259d7 803 #else
Kojto 101:7cff1c4259d7 804 return(0);
Kojto 101:7cff1c4259d7 805 #endif
Kojto 101:7cff1c4259d7 806 }
Kojto 101:7cff1c4259d7 807
Kojto 101:7cff1c4259d7 808
Kojto 101:7cff1c4259d7 809 /** \brief Set FPEXC
Kojto 101:7cff1c4259d7 810
Kojto 101:7cff1c4259d7 811 This function assigns the given value to the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 812
Kojto 101:7cff1c4259d7 813 \param [in] fpscr Floating Point Exception Control value to set
Kojto 101:7cff1c4259d7 814 */
Kojto 101:7cff1c4259d7 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 101:7cff1c4259d7 816 {
Kojto 101:7cff1c4259d7 817 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 818 #if 1
Kojto 101:7cff1c4259d7 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 101:7cff1c4259d7 820 #else
Kojto 101:7cff1c4259d7 821 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 822 __regfpexc = (fpexc);
Kojto 101:7cff1c4259d7 823 #endif
Kojto 101:7cff1c4259d7 824 #endif
Kojto 101:7cff1c4259d7 825 }
Kojto 101:7cff1c4259d7 826
Kojto 101:7cff1c4259d7 827 /** \brief Get CPACR
Kojto 101:7cff1c4259d7 828
Kojto 101:7cff1c4259d7 829 This function returns the current value of the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 830
Kojto 101:7cff1c4259d7 831 \return Coprocessor Access Control register value
Kojto 101:7cff1c4259d7 832 */
Kojto 101:7cff1c4259d7 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 101:7cff1c4259d7 834 {
Kojto 101:7cff1c4259d7 835 #if 1
Kojto 101:7cff1c4259d7 836 register uint32_t __regCPACR;
Kojto 101:7cff1c4259d7 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 101:7cff1c4259d7 838 #else
Kojto 101:7cff1c4259d7 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 840 #endif
Kojto 101:7cff1c4259d7 841 return __regCPACR;
Kojto 101:7cff1c4259d7 842 }
Kojto 101:7cff1c4259d7 843
Kojto 101:7cff1c4259d7 844 /** \brief Set CPACR
Kojto 101:7cff1c4259d7 845
Kojto 101:7cff1c4259d7 846 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 847
Kojto 108:34e6b704fe68 848 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 101:7cff1c4259d7 849 */
Kojto 101:7cff1c4259d7 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 101:7cff1c4259d7 851 {
Kojto 101:7cff1c4259d7 852 #if 1
Kojto 101:7cff1c4259d7 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 101:7cff1c4259d7 854 #else
Kojto 101:7cff1c4259d7 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 856 __regCPACR = cpacr;
Kojto 101:7cff1c4259d7 857 #endif
Kojto 101:7cff1c4259d7 858 __ISB();
Kojto 101:7cff1c4259d7 859 }
Kojto 101:7cff1c4259d7 860
Kojto 101:7cff1c4259d7 861 /** \brief Get CBAR
Kojto 101:7cff1c4259d7 862
Kojto 101:7cff1c4259d7 863 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 864
Kojto 101:7cff1c4259d7 865 \return Configuration Base Address register value
Kojto 101:7cff1c4259d7 866 */
Kojto 101:7cff1c4259d7 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 101:7cff1c4259d7 868 #if 1
Kojto 101:7cff1c4259d7 869 register uint32_t __regCBAR;
Kojto 101:7cff1c4259d7 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 101:7cff1c4259d7 871 #else
Kojto 101:7cff1c4259d7 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 101:7cff1c4259d7 873 #endif
Kojto 101:7cff1c4259d7 874 return(__regCBAR);
Kojto 101:7cff1c4259d7 875 }
Kojto 101:7cff1c4259d7 876
Kojto 101:7cff1c4259d7 877 /** \brief Get TTBR0
Kojto 101:7cff1c4259d7 878
Kojto 108:34e6b704fe68 879 This function returns the value of the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 880
Kojto 101:7cff1c4259d7 881 \return Translation Table Base Register 0 value
Kojto 101:7cff1c4259d7 882 */
Kojto 101:7cff1c4259d7 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 101:7cff1c4259d7 884 #if 1
Kojto 101:7cff1c4259d7 885 register uint32_t __regTTBR0;
Kojto 101:7cff1c4259d7 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 101:7cff1c4259d7 887 #else
Kojto 101:7cff1c4259d7 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 889 #endif
Kojto 101:7cff1c4259d7 890 return(__regTTBR0);
Kojto 101:7cff1c4259d7 891 }
Kojto 101:7cff1c4259d7 892
Kojto 101:7cff1c4259d7 893 /** \brief Set TTBR0
Kojto 101:7cff1c4259d7 894
Kojto 108:34e6b704fe68 895 This function assigns the given value to the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 896
Kojto 101:7cff1c4259d7 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 101:7cff1c4259d7 898 */
Kojto 101:7cff1c4259d7 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 101:7cff1c4259d7 900 #if 1
Kojto 101:7cff1c4259d7 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 101:7cff1c4259d7 902 #else
Kojto 101:7cff1c4259d7 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 904 __regTTBR0 = ttbr0;
Kojto 101:7cff1c4259d7 905 #endif
Kojto 101:7cff1c4259d7 906 __ISB();
Kojto 101:7cff1c4259d7 907 }
Kojto 101:7cff1c4259d7 908
Kojto 101:7cff1c4259d7 909 /** \brief Get DACR
Kojto 101:7cff1c4259d7 910
Kojto 101:7cff1c4259d7 911 This function returns the value of the Domain Access Control Register.
Kojto 101:7cff1c4259d7 912
Kojto 101:7cff1c4259d7 913 \return Domain Access Control Register value
Kojto 101:7cff1c4259d7 914 */
Kojto 101:7cff1c4259d7 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 101:7cff1c4259d7 916 #if 1
Kojto 101:7cff1c4259d7 917 register uint32_t __regDACR;
Kojto 101:7cff1c4259d7 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 101:7cff1c4259d7 919 #else
Kojto 101:7cff1c4259d7 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 921 #endif
Kojto 101:7cff1c4259d7 922 return(__regDACR);
Kojto 101:7cff1c4259d7 923 }
Kojto 101:7cff1c4259d7 924
Kojto 101:7cff1c4259d7 925 /** \brief Set DACR
Kojto 101:7cff1c4259d7 926
Kojto 108:34e6b704fe68 927 This function assigns the given value to the Domain Access Control Register.
Kojto 101:7cff1c4259d7 928
Kojto 101:7cff1c4259d7 929 \param [in] dacr Domain Access Control Register value to set
Kojto 101:7cff1c4259d7 930 */
Kojto 101:7cff1c4259d7 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 101:7cff1c4259d7 932 #if 1
Kojto 101:7cff1c4259d7 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 101:7cff1c4259d7 934 #else
Kojto 101:7cff1c4259d7 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 936 __regDACR = dacr;
Kojto 101:7cff1c4259d7 937 #endif
Kojto 101:7cff1c4259d7 938 __ISB();
Kojto 101:7cff1c4259d7 939 }
Kojto 101:7cff1c4259d7 940
Kojto 101:7cff1c4259d7 941 /******************************** Cache and BTAC enable ****************************************************/
Kojto 101:7cff1c4259d7 942
Kojto 101:7cff1c4259d7 943 /** \brief Set SCTLR
Kojto 101:7cff1c4259d7 944
Kojto 101:7cff1c4259d7 945 This function assigns the given value to the System Control Register.
Kojto 101:7cff1c4259d7 946
Kojto 108:34e6b704fe68 947 \param [in] sctlr System Control Register value to set
Kojto 101:7cff1c4259d7 948 */
Kojto 101:7cff1c4259d7 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 101:7cff1c4259d7 950 {
Kojto 101:7cff1c4259d7 951 #if 1
Kojto 101:7cff1c4259d7 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 101:7cff1c4259d7 953 #else
Kojto 101:7cff1c4259d7 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 955 __regSCTLR = sctlr;
Kojto 101:7cff1c4259d7 956 #endif
Kojto 101:7cff1c4259d7 957 }
Kojto 101:7cff1c4259d7 958
Kojto 101:7cff1c4259d7 959 /** \brief Get SCTLR
Kojto 101:7cff1c4259d7 960
Kojto 101:7cff1c4259d7 961 This function returns the value of the System Control Register.
Kojto 101:7cff1c4259d7 962
Kojto 101:7cff1c4259d7 963 \return System Control Register value
Kojto 101:7cff1c4259d7 964 */
Kojto 101:7cff1c4259d7 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 101:7cff1c4259d7 966 #if 1
Kojto 101:7cff1c4259d7 967 register uint32_t __regSCTLR;
Kojto 101:7cff1c4259d7 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 101:7cff1c4259d7 969 #else
Kojto 101:7cff1c4259d7 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 971 #endif
Kojto 101:7cff1c4259d7 972 return(__regSCTLR);
Kojto 101:7cff1c4259d7 973 }
Kojto 101:7cff1c4259d7 974
Kojto 101:7cff1c4259d7 975 /** \brief Enable Caches
Kojto 101:7cff1c4259d7 976
Kojto 101:7cff1c4259d7 977 Enable Caches
Kojto 101:7cff1c4259d7 978 */
Kojto 101:7cff1c4259d7 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 101:7cff1c4259d7 980 // Set I bit 12 to enable I Cache
Kojto 101:7cff1c4259d7 981 // Set C bit 2 to enable D Cache
Kojto 101:7cff1c4259d7 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 101:7cff1c4259d7 983 }
Kojto 101:7cff1c4259d7 984
Kojto 101:7cff1c4259d7 985 /** \brief Disable Caches
Kojto 101:7cff1c4259d7 986
Kojto 101:7cff1c4259d7 987 Disable Caches
Kojto 101:7cff1c4259d7 988 */
Kojto 101:7cff1c4259d7 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 101:7cff1c4259d7 990 // Clear I bit 12 to disable I Cache
Kojto 101:7cff1c4259d7 991 // Clear C bit 2 to disable D Cache
Kojto 101:7cff1c4259d7 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 101:7cff1c4259d7 993 __ISB();
Kojto 101:7cff1c4259d7 994 }
Kojto 101:7cff1c4259d7 995
Kojto 101:7cff1c4259d7 996 /** \brief Enable BTAC
Kojto 101:7cff1c4259d7 997
Kojto 101:7cff1c4259d7 998 Enable BTAC
Kojto 101:7cff1c4259d7 999 */
Kojto 101:7cff1c4259d7 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 101:7cff1c4259d7 1001 // Set Z bit 11 to enable branch prediction
Kojto 101:7cff1c4259d7 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 101:7cff1c4259d7 1003 __ISB();
Kojto 101:7cff1c4259d7 1004 }
Kojto 101:7cff1c4259d7 1005
Kojto 101:7cff1c4259d7 1006 /** \brief Disable BTAC
Kojto 101:7cff1c4259d7 1007
Kojto 101:7cff1c4259d7 1008 Disable BTAC
Kojto 101:7cff1c4259d7 1009 */
Kojto 101:7cff1c4259d7 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 101:7cff1c4259d7 1011 // Clear Z bit 11 to disable branch prediction
Kojto 101:7cff1c4259d7 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 101:7cff1c4259d7 1013 }
Kojto 101:7cff1c4259d7 1014
Kojto 101:7cff1c4259d7 1015
Kojto 101:7cff1c4259d7 1016 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 1017
Kojto 101:7cff1c4259d7 1018 Enable MMU
Kojto 101:7cff1c4259d7 1019 */
Kojto 101:7cff1c4259d7 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 101:7cff1c4259d7 1021 // Set M bit 0 to enable the MMU
Kojto 101:7cff1c4259d7 1022 // Set AFE bit to enable simplified access permissions model
Kojto 101:7cff1c4259d7 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 101:7cff1c4259d7 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 101:7cff1c4259d7 1025 __ISB();
Kojto 101:7cff1c4259d7 1026 }
Kojto 101:7cff1c4259d7 1027
Kojto 108:34e6b704fe68 1028 /** \brief Disable MMU
Kojto 101:7cff1c4259d7 1029
Kojto 108:34e6b704fe68 1030 Disable MMU
Kojto 101:7cff1c4259d7 1031 */
Kojto 101:7cff1c4259d7 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 101:7cff1c4259d7 1033 // Clear M bit 0 to disable the MMU
Kojto 101:7cff1c4259d7 1034 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 101:7cff1c4259d7 1035 __ISB();
Kojto 101:7cff1c4259d7 1036 }
Kojto 101:7cff1c4259d7 1037
Kojto 101:7cff1c4259d7 1038 /******************************** TLB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 1039 /** \brief Invalidate the whole tlb
Kojto 101:7cff1c4259d7 1040
Kojto 101:7cff1c4259d7 1041 TLBIALL. Invalidate the whole tlb
Kojto 101:7cff1c4259d7 1042 */
Kojto 101:7cff1c4259d7 1043
Kojto 101:7cff1c4259d7 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 101:7cff1c4259d7 1045 #if 1
Kojto 101:7cff1c4259d7 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 101:7cff1c4259d7 1047 #else
Kojto 101:7cff1c4259d7 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 101:7cff1c4259d7 1049 __TLBIALL = 0;
Kojto 101:7cff1c4259d7 1050 #endif
Kojto 101:7cff1c4259d7 1051 __DSB();
Kojto 101:7cff1c4259d7 1052 __ISB();
Kojto 101:7cff1c4259d7 1053 }
Kojto 101:7cff1c4259d7 1054
Kojto 101:7cff1c4259d7 1055 /******************************** BTB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 1056 /** \brief Invalidate entire branch predictor array
Kojto 101:7cff1c4259d7 1057
Kojto 101:7cff1c4259d7 1058 BPIALL. Branch Predictor Invalidate All.
Kojto 101:7cff1c4259d7 1059 */
Kojto 101:7cff1c4259d7 1060
Kojto 101:7cff1c4259d7 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 101:7cff1c4259d7 1062 #if 1
Kojto 101:7cff1c4259d7 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 101:7cff1c4259d7 1064 #else
Kojto 101:7cff1c4259d7 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 101:7cff1c4259d7 1066 __BPIALL = 0;
Kojto 101:7cff1c4259d7 1067 #endif
Kojto 101:7cff1c4259d7 1068 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 1069 __ISB(); //ensure instruction fetch path sees new state
Kojto 101:7cff1c4259d7 1070 }
Kojto 101:7cff1c4259d7 1071
Kojto 101:7cff1c4259d7 1072
Kojto 101:7cff1c4259d7 1073 /******************************** L1 cache operations ******************************************************/
Kojto 101:7cff1c4259d7 1074
Kojto 101:7cff1c4259d7 1075 /** \brief Invalidate the whole I$
Kojto 101:7cff1c4259d7 1076
Kojto 101:7cff1c4259d7 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 101:7cff1c4259d7 1078 */
Kojto 101:7cff1c4259d7 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 101:7cff1c4259d7 1080 #if 1
Kojto 101:7cff1c4259d7 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 101:7cff1c4259d7 1082 #else
Kojto 101:7cff1c4259d7 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 101:7cff1c4259d7 1084 __ICIALLU = 0;
Kojto 101:7cff1c4259d7 1085 #endif
Kojto 101:7cff1c4259d7 1086 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 101:7cff1c4259d7 1088 }
Kojto 101:7cff1c4259d7 1089
Kojto 101:7cff1c4259d7 1090 /** \brief Clean D$ by MVA
Kojto 101:7cff1c4259d7 1091
Kojto 101:7cff1c4259d7 1092 DCCMVAC. Data cache clean by MVA to PoC
Kojto 101:7cff1c4259d7 1093 */
Kojto 101:7cff1c4259d7 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1095 #if 1
Kojto 101:7cff1c4259d7 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1097 #else
Kojto 101:7cff1c4259d7 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 101:7cff1c4259d7 1099 __DCCMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1100 #endif
Kojto 101:7cff1c4259d7 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1102 }
Kojto 101:7cff1c4259d7 1103
Kojto 101:7cff1c4259d7 1104 /** \brief Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 1105
Kojto 101:7cff1c4259d7 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 1107 */
Kojto 101:7cff1c4259d7 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1109 #if 1
Kojto 101:7cff1c4259d7 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1111 #else
Kojto 101:7cff1c4259d7 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 101:7cff1c4259d7 1113 __DCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1114 #endif
Kojto 101:7cff1c4259d7 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1116 }
Kojto 101:7cff1c4259d7 1117
Kojto 101:7cff1c4259d7 1118 /** \brief Clean and Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 1119
Kojto 101:7cff1c4259d7 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 1121 */
Kojto 101:7cff1c4259d7 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1123 #if 1
Kojto 101:7cff1c4259d7 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1125 #else
Kojto 101:7cff1c4259d7 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 101:7cff1c4259d7 1127 __DCCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1128 #endif
Kojto 101:7cff1c4259d7 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1130 }
Kojto 101:7cff1c4259d7 1131
Kojto 108:34e6b704fe68 1132 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 101:7cff1c4259d7 1133
Kojto 108:34e6b704fe68 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 101:7cff1c4259d7 1135 */
Kojto 101:7cff1c4259d7 1136 extern void __v7_all_cache(uint32_t op);
Kojto 101:7cff1c4259d7 1137
Kojto 101:7cff1c4259d7 1138
Kojto 101:7cff1c4259d7 1139 /** \brief Invalidate the whole D$
Kojto 101:7cff1c4259d7 1140
Kojto 101:7cff1c4259d7 1141 DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 1142 */
Kojto 101:7cff1c4259d7 1143
Kojto 101:7cff1c4259d7 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 1145 __v7_all_cache(0);
Kojto 101:7cff1c4259d7 1146 }
Kojto 101:7cff1c4259d7 1147
Kojto 101:7cff1c4259d7 1148 /** \brief Clean the whole D$
Kojto 101:7cff1c4259d7 1149
Kojto 101:7cff1c4259d7 1150 DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 1151 */
Kojto 101:7cff1c4259d7 1152
Kojto 101:7cff1c4259d7 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 101:7cff1c4259d7 1154 __v7_all_cache(1);
Kojto 101:7cff1c4259d7 1155 }
Kojto 101:7cff1c4259d7 1156
Kojto 101:7cff1c4259d7 1157 /** \brief Clean and invalidate the whole D$
Kojto 101:7cff1c4259d7 1158
Kojto 101:7cff1c4259d7 1159 DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 1160 */
Kojto 101:7cff1c4259d7 1161
Kojto 101:7cff1c4259d7 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 1163 __v7_all_cache(2);
Kojto 101:7cff1c4259d7 1164 }
Kojto 101:7cff1c4259d7 1165
Kojto 101:7cff1c4259d7 1166 #include "core_ca_mmu.h"
Kojto 101:7cff1c4259d7 1167
Kojto 101:7cff1c4259d7 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 101:7cff1c4259d7 1169
Kojto 101:7cff1c4259d7 1170 #error TASKING Compiler support not implemented for Cortex-A
Kojto 101:7cff1c4259d7 1171
Kojto 101:7cff1c4259d7 1172 #endif
Kojto 101:7cff1c4259d7 1173
Kojto 101:7cff1c4259d7 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 101:7cff1c4259d7 1175
Kojto 101:7cff1c4259d7 1176
Kojto 101:7cff1c4259d7 1177 #endif /* __CORE_CAFUNC_H__ */