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TARGET_ARM_MPS2_M7/core_caFunc.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Parent:
102:da0ca467f8b5
Child:
115:87f2f5183dfb
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /**************************************************************************//**
Kojto 102:da0ca467f8b5 2 * @file core_caFunc.h
Kojto 102:da0ca467f8b5 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 102:da0ca467f8b5 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 102:da0ca467f8b5 6 *
Kojto 102:da0ca467f8b5 7 * @note
Kojto 102:da0ca467f8b5 8 *
Kojto 102:da0ca467f8b5 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 102:da0ca467f8b5 11
Kojto 102:da0ca467f8b5 12 All rights reserved.
Kojto 102:da0ca467f8b5 13 Redistribution and use in source and binary forms, with or without
Kojto 102:da0ca467f8b5 14 modification, are permitted provided that the following conditions are met:
Kojto 102:da0ca467f8b5 15 - Redistributions of source code must retain the above copyright
Kojto 102:da0ca467f8b5 16 notice, this list of conditions and the following disclaimer.
Kojto 102:da0ca467f8b5 17 - Redistributions in binary form must reproduce the above copyright
Kojto 102:da0ca467f8b5 18 notice, this list of conditions and the following disclaimer in the
Kojto 102:da0ca467f8b5 19 documentation and/or other materials provided with the distribution.
Kojto 102:da0ca467f8b5 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 102:da0ca467f8b5 21 to endorse or promote products derived from this software without
Kojto 102:da0ca467f8b5 22 specific prior written permission.
Kojto 102:da0ca467f8b5 23 *
Kojto 102:da0ca467f8b5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 102:da0ca467f8b5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 102:da0ca467f8b5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 102:da0ca467f8b5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 102:da0ca467f8b5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 102:da0ca467f8b5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 102:da0ca467f8b5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 102:da0ca467f8b5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 102:da0ca467f8b5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 102:da0ca467f8b5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 102:da0ca467f8b5 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 102:da0ca467f8b5 35 ---------------------------------------------------------------------------*/
Kojto 102:da0ca467f8b5 36
Kojto 102:da0ca467f8b5 37
Kojto 102:da0ca467f8b5 38 #ifndef __CORE_CAFUNC_H__
Kojto 102:da0ca467f8b5 39 #define __CORE_CAFUNC_H__
Kojto 102:da0ca467f8b5 40
Kojto 102:da0ca467f8b5 41
Kojto 102:da0ca467f8b5 42 /* ########################### Core Function Access ########################### */
Kojto 102:da0ca467f8b5 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 102:da0ca467f8b5 45 @{
Kojto 102:da0ca467f8b5 46 */
Kojto 102:da0ca467f8b5 47
Kojto 102:da0ca467f8b5 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 102:da0ca467f8b5 49 /* ARM armcc specific functions */
Kojto 102:da0ca467f8b5 50
Kojto 102:da0ca467f8b5 51 #if (__ARMCC_VERSION < 400677)
Kojto 102:da0ca467f8b5 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 102:da0ca467f8b5 53 #endif
Kojto 102:da0ca467f8b5 54
Kojto 102:da0ca467f8b5 55 #define MODE_USR 0x10
Kojto 102:da0ca467f8b5 56 #define MODE_FIQ 0x11
Kojto 102:da0ca467f8b5 57 #define MODE_IRQ 0x12
Kojto 102:da0ca467f8b5 58 #define MODE_SVC 0x13
Kojto 102:da0ca467f8b5 59 #define MODE_MON 0x16
Kojto 102:da0ca467f8b5 60 #define MODE_ABT 0x17
Kojto 102:da0ca467f8b5 61 #define MODE_HYP 0x1A
Kojto 102:da0ca467f8b5 62 #define MODE_UND 0x1B
Kojto 102:da0ca467f8b5 63 #define MODE_SYS 0x1F
Kojto 102:da0ca467f8b5 64
Kojto 102:da0ca467f8b5 65 /** \brief Get APSR Register
Kojto 102:da0ca467f8b5 66
Kojto 102:da0ca467f8b5 67 This function returns the content of the APSR Register.
Kojto 102:da0ca467f8b5 68
Kojto 102:da0ca467f8b5 69 \return APSR Register value
Kojto 102:da0ca467f8b5 70 */
Kojto 102:da0ca467f8b5 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 102:da0ca467f8b5 72 {
Kojto 102:da0ca467f8b5 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 102:da0ca467f8b5 74 return(__regAPSR);
Kojto 102:da0ca467f8b5 75 }
Kojto 102:da0ca467f8b5 76
Kojto 102:da0ca467f8b5 77
Kojto 102:da0ca467f8b5 78 /** \brief Get CPSR Register
Kojto 102:da0ca467f8b5 79
Kojto 102:da0ca467f8b5 80 This function returns the content of the CPSR Register.
Kojto 102:da0ca467f8b5 81
Kojto 102:da0ca467f8b5 82 \return CPSR Register value
Kojto 102:da0ca467f8b5 83 */
Kojto 102:da0ca467f8b5 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 102:da0ca467f8b5 85 {
Kojto 102:da0ca467f8b5 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 102:da0ca467f8b5 87 return(__regCPSR);
Kojto 102:da0ca467f8b5 88 }
Kojto 102:da0ca467f8b5 89
Kojto 102:da0ca467f8b5 90 /** \brief Set Stack Pointer
Kojto 102:da0ca467f8b5 91
Kojto 102:da0ca467f8b5 92 This function assigns the given value to the current stack pointer.
Kojto 102:da0ca467f8b5 93
Kojto 102:da0ca467f8b5 94 \param [in] topOfStack Stack Pointer value to set
Kojto 102:da0ca467f8b5 95 */
Kojto 102:da0ca467f8b5 96 register uint32_t __regSP __ASM("sp");
Kojto 102:da0ca467f8b5 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 102:da0ca467f8b5 98 {
Kojto 102:da0ca467f8b5 99 __regSP = topOfStack;
Kojto 102:da0ca467f8b5 100 }
Kojto 102:da0ca467f8b5 101
Kojto 102:da0ca467f8b5 102
Kojto 102:da0ca467f8b5 103 /** \brief Get link register
Kojto 102:da0ca467f8b5 104
Kojto 102:da0ca467f8b5 105 This function returns the value of the link register
Kojto 102:da0ca467f8b5 106
Kojto 102:da0ca467f8b5 107 \return Value of link register
Kojto 102:da0ca467f8b5 108 */
Kojto 102:da0ca467f8b5 109 register uint32_t __reglr __ASM("lr");
Kojto 102:da0ca467f8b5 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 102:da0ca467f8b5 111 {
Kojto 102:da0ca467f8b5 112 return(__reglr);
Kojto 102:da0ca467f8b5 113 }
Kojto 102:da0ca467f8b5 114
Kojto 102:da0ca467f8b5 115 /** \brief Set link register
Kojto 102:da0ca467f8b5 116
Kojto 102:da0ca467f8b5 117 This function sets the value of the link register
Kojto 102:da0ca467f8b5 118
Kojto 102:da0ca467f8b5 119 \param [in] lr LR value to set
Kojto 102:da0ca467f8b5 120 */
Kojto 102:da0ca467f8b5 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 102:da0ca467f8b5 122 {
Kojto 102:da0ca467f8b5 123 __reglr = lr;
Kojto 102:da0ca467f8b5 124 }
Kojto 102:da0ca467f8b5 125
Kojto 102:da0ca467f8b5 126 /** \brief Set Process Stack Pointer
Kojto 102:da0ca467f8b5 127
Kojto 102:da0ca467f8b5 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 102:da0ca467f8b5 129
Kojto 102:da0ca467f8b5 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 102:da0ca467f8b5 131 */
Kojto 102:da0ca467f8b5 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 102:da0ca467f8b5 133 {
Kojto 102:da0ca467f8b5 134 ARM
Kojto 102:da0ca467f8b5 135 PRESERVE8
Kojto 102:da0ca467f8b5 136
Kojto 102:da0ca467f8b5 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 102:da0ca467f8b5 138 MRS R1, CPSR
Kojto 102:da0ca467f8b5 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 102:da0ca467f8b5 140 MOV SP, R0
Kojto 102:da0ca467f8b5 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 102:da0ca467f8b5 142 ISB
Kojto 102:da0ca467f8b5 143 BX LR
Kojto 102:da0ca467f8b5 144
Kojto 102:da0ca467f8b5 145 }
Kojto 102:da0ca467f8b5 146
Kojto 102:da0ca467f8b5 147 /** \brief Set User Mode
Kojto 102:da0ca467f8b5 148
Kojto 102:da0ca467f8b5 149 This function changes the processor state to User Mode
Kojto 102:da0ca467f8b5 150 */
Kojto 102:da0ca467f8b5 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 102:da0ca467f8b5 152 {
Kojto 102:da0ca467f8b5 153 ARM
Kojto 102:da0ca467f8b5 154
Kojto 102:da0ca467f8b5 155 CPS #MODE_USR
Kojto 102:da0ca467f8b5 156 BX LR
Kojto 102:da0ca467f8b5 157 }
Kojto 102:da0ca467f8b5 158
Kojto 102:da0ca467f8b5 159
Kojto 102:da0ca467f8b5 160 /** \brief Enable FIQ
Kojto 102:da0ca467f8b5 161
Kojto 102:da0ca467f8b5 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 102:da0ca467f8b5 163 Can only be executed in Privileged modes.
Kojto 102:da0ca467f8b5 164 */
Kojto 102:da0ca467f8b5 165 #define __enable_fault_irq __enable_fiq
Kojto 102:da0ca467f8b5 166
Kojto 102:da0ca467f8b5 167
Kojto 102:da0ca467f8b5 168 /** \brief Disable FIQ
Kojto 102:da0ca467f8b5 169
Kojto 102:da0ca467f8b5 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 102:da0ca467f8b5 171 Can only be executed in Privileged modes.
Kojto 102:da0ca467f8b5 172 */
Kojto 102:da0ca467f8b5 173 #define __disable_fault_irq __disable_fiq
Kojto 102:da0ca467f8b5 174
Kojto 102:da0ca467f8b5 175
Kojto 102:da0ca467f8b5 176 /** \brief Get FPSCR
Kojto 102:da0ca467f8b5 177
Kojto 102:da0ca467f8b5 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 102:da0ca467f8b5 179
Kojto 102:da0ca467f8b5 180 \return Floating Point Status/Control register value
Kojto 102:da0ca467f8b5 181 */
Kojto 102:da0ca467f8b5 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 102:da0ca467f8b5 183 {
Kojto 102:da0ca467f8b5 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 102:da0ca467f8b5 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 102:da0ca467f8b5 186 return(__regfpscr);
Kojto 102:da0ca467f8b5 187 #else
Kojto 102:da0ca467f8b5 188 return(0);
Kojto 102:da0ca467f8b5 189 #endif
Kojto 102:da0ca467f8b5 190 }
Kojto 102:da0ca467f8b5 191
Kojto 102:da0ca467f8b5 192
Kojto 102:da0ca467f8b5 193 /** \brief Set FPSCR
Kojto 102:da0ca467f8b5 194
Kojto 102:da0ca467f8b5 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 102:da0ca467f8b5 196
Kojto 102:da0ca467f8b5 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 102:da0ca467f8b5 198 */
Kojto 102:da0ca467f8b5 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 102:da0ca467f8b5 200 {
Kojto 102:da0ca467f8b5 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 102:da0ca467f8b5 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 102:da0ca467f8b5 203 __regfpscr = (fpscr);
Kojto 102:da0ca467f8b5 204 #endif
Kojto 102:da0ca467f8b5 205 }
Kojto 102:da0ca467f8b5 206
Kojto 102:da0ca467f8b5 207 /** \brief Get FPEXC
Kojto 102:da0ca467f8b5 208
Kojto 102:da0ca467f8b5 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 102:da0ca467f8b5 210
Kojto 102:da0ca467f8b5 211 \return Floating Point Exception Control register value
Kojto 102:da0ca467f8b5 212 */
Kojto 102:da0ca467f8b5 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 102:da0ca467f8b5 214 {
Kojto 102:da0ca467f8b5 215 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 102:da0ca467f8b5 217 return(__regfpexc);
Kojto 102:da0ca467f8b5 218 #else
Kojto 102:da0ca467f8b5 219 return(0);
Kojto 102:da0ca467f8b5 220 #endif
Kojto 102:da0ca467f8b5 221 }
Kojto 102:da0ca467f8b5 222
Kojto 102:da0ca467f8b5 223
Kojto 102:da0ca467f8b5 224 /** \brief Set FPEXC
Kojto 102:da0ca467f8b5 225
Kojto 102:da0ca467f8b5 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 102:da0ca467f8b5 227
Kojto 102:da0ca467f8b5 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 102:da0ca467f8b5 229 */
Kojto 102:da0ca467f8b5 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 102:da0ca467f8b5 231 {
Kojto 102:da0ca467f8b5 232 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 102:da0ca467f8b5 234 __regfpexc = (fpexc);
Kojto 102:da0ca467f8b5 235 #endif
Kojto 102:da0ca467f8b5 236 }
Kojto 102:da0ca467f8b5 237
Kojto 102:da0ca467f8b5 238 /** \brief Get CPACR
Kojto 102:da0ca467f8b5 239
Kojto 102:da0ca467f8b5 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 102:da0ca467f8b5 241
Kojto 102:da0ca467f8b5 242 \return Coprocessor Access Control register value
Kojto 102:da0ca467f8b5 243 */
Kojto 102:da0ca467f8b5 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 102:da0ca467f8b5 245 {
Kojto 102:da0ca467f8b5 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 102:da0ca467f8b5 247 return __regCPACR;
Kojto 102:da0ca467f8b5 248 }
Kojto 102:da0ca467f8b5 249
Kojto 102:da0ca467f8b5 250 /** \brief Set CPACR
Kojto 102:da0ca467f8b5 251
Kojto 102:da0ca467f8b5 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 102:da0ca467f8b5 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 102:da0ca467f8b5 255 */
Kojto 102:da0ca467f8b5 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 102:da0ca467f8b5 257 {
Kojto 102:da0ca467f8b5 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 102:da0ca467f8b5 259 __regCPACR = cpacr;
Kojto 102:da0ca467f8b5 260 __ISB();
Kojto 102:da0ca467f8b5 261 }
Kojto 102:da0ca467f8b5 262
Kojto 102:da0ca467f8b5 263 /** \brief Get CBAR
Kojto 102:da0ca467f8b5 264
Kojto 102:da0ca467f8b5 265 This function returns the value of the Configuration Base Address register.
Kojto 102:da0ca467f8b5 266
Kojto 102:da0ca467f8b5 267 \return Configuration Base Address register value
Kojto 102:da0ca467f8b5 268 */
Kojto 102:da0ca467f8b5 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 102:da0ca467f8b5 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 102:da0ca467f8b5 271 return(__regCBAR);
Kojto 102:da0ca467f8b5 272 }
Kojto 102:da0ca467f8b5 273
Kojto 102:da0ca467f8b5 274 /** \brief Get TTBR0
Kojto 102:da0ca467f8b5 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 102:da0ca467f8b5 277
Kojto 102:da0ca467f8b5 278 \return Translation Table Base Register 0 value
Kojto 102:da0ca467f8b5 279 */
Kojto 102:da0ca467f8b5 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 102:da0ca467f8b5 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 102:da0ca467f8b5 282 return(__regTTBR0);
Kojto 102:da0ca467f8b5 283 }
Kojto 102:da0ca467f8b5 284
Kojto 102:da0ca467f8b5 285 /** \brief Set TTBR0
Kojto 102:da0ca467f8b5 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 102:da0ca467f8b5 288
Kojto 102:da0ca467f8b5 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 102:da0ca467f8b5 290 */
Kojto 102:da0ca467f8b5 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 102:da0ca467f8b5 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 102:da0ca467f8b5 293 __regTTBR0 = ttbr0;
Kojto 102:da0ca467f8b5 294 __ISB();
Kojto 102:da0ca467f8b5 295 }
Kojto 102:da0ca467f8b5 296
Kojto 102:da0ca467f8b5 297 /** \brief Get DACR
Kojto 102:da0ca467f8b5 298
Kojto 102:da0ca467f8b5 299 This function returns the value of the Domain Access Control Register.
Kojto 102:da0ca467f8b5 300
Kojto 102:da0ca467f8b5 301 \return Domain Access Control Register value
Kojto 102:da0ca467f8b5 302 */
Kojto 102:da0ca467f8b5 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 102:da0ca467f8b5 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 102:da0ca467f8b5 305 return(__regDACR);
Kojto 102:da0ca467f8b5 306 }
Kojto 102:da0ca467f8b5 307
Kojto 102:da0ca467f8b5 308 /** \brief Set DACR
Kojto 102:da0ca467f8b5 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 102:da0ca467f8b5 311
Kojto 102:da0ca467f8b5 312 \param [in] dacr Domain Access Control Register value to set
Kojto 102:da0ca467f8b5 313 */
Kojto 102:da0ca467f8b5 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 102:da0ca467f8b5 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 102:da0ca467f8b5 316 __regDACR = dacr;
Kojto 102:da0ca467f8b5 317 __ISB();
Kojto 102:da0ca467f8b5 318 }
Kojto 102:da0ca467f8b5 319
Kojto 102:da0ca467f8b5 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 102:da0ca467f8b5 321
Kojto 102:da0ca467f8b5 322 /** \brief Set SCTLR
Kojto 102:da0ca467f8b5 323
Kojto 102:da0ca467f8b5 324 This function assigns the given value to the System Control Register.
Kojto 102:da0ca467f8b5 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 102:da0ca467f8b5 327 */
Kojto 102:da0ca467f8b5 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 102:da0ca467f8b5 329 {
Kojto 102:da0ca467f8b5 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 102:da0ca467f8b5 331 __regSCTLR = sctlr;
Kojto 102:da0ca467f8b5 332 }
Kojto 102:da0ca467f8b5 333
Kojto 102:da0ca467f8b5 334 /** \brief Get SCTLR
Kojto 102:da0ca467f8b5 335
Kojto 102:da0ca467f8b5 336 This function returns the value of the System Control Register.
Kojto 102:da0ca467f8b5 337
Kojto 102:da0ca467f8b5 338 \return System Control Register value
Kojto 102:da0ca467f8b5 339 */
Kojto 102:da0ca467f8b5 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 102:da0ca467f8b5 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 102:da0ca467f8b5 342 return(__regSCTLR);
Kojto 102:da0ca467f8b5 343 }
Kojto 102:da0ca467f8b5 344
Kojto 102:da0ca467f8b5 345 /** \brief Enable Caches
Kojto 102:da0ca467f8b5 346
Kojto 102:da0ca467f8b5 347 Enable Caches
Kojto 102:da0ca467f8b5 348 */
Kojto 102:da0ca467f8b5 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 102:da0ca467f8b5 350 // Set I bit 12 to enable I Cache
Kojto 102:da0ca467f8b5 351 // Set C bit 2 to enable D Cache
Kojto 102:da0ca467f8b5 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 102:da0ca467f8b5 353 }
Kojto 102:da0ca467f8b5 354
Kojto 102:da0ca467f8b5 355 /** \brief Disable Caches
Kojto 102:da0ca467f8b5 356
Kojto 102:da0ca467f8b5 357 Disable Caches
Kojto 102:da0ca467f8b5 358 */
Kojto 102:da0ca467f8b5 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 102:da0ca467f8b5 360 // Clear I bit 12 to disable I Cache
Kojto 102:da0ca467f8b5 361 // Clear C bit 2 to disable D Cache
Kojto 102:da0ca467f8b5 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 102:da0ca467f8b5 363 __ISB();
Kojto 102:da0ca467f8b5 364 }
Kojto 102:da0ca467f8b5 365
Kojto 102:da0ca467f8b5 366 /** \brief Enable BTAC
Kojto 102:da0ca467f8b5 367
Kojto 102:da0ca467f8b5 368 Enable BTAC
Kojto 102:da0ca467f8b5 369 */
Kojto 102:da0ca467f8b5 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 102:da0ca467f8b5 371 // Set Z bit 11 to enable branch prediction
Kojto 102:da0ca467f8b5 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 102:da0ca467f8b5 373 __ISB();
Kojto 102:da0ca467f8b5 374 }
Kojto 102:da0ca467f8b5 375
Kojto 102:da0ca467f8b5 376 /** \brief Disable BTAC
Kojto 102:da0ca467f8b5 377
Kojto 102:da0ca467f8b5 378 Disable BTAC
Kojto 102:da0ca467f8b5 379 */
Kojto 102:da0ca467f8b5 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 102:da0ca467f8b5 381 // Clear Z bit 11 to disable branch prediction
Kojto 102:da0ca467f8b5 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 102:da0ca467f8b5 383 }
Kojto 102:da0ca467f8b5 384
Kojto 102:da0ca467f8b5 385
Kojto 102:da0ca467f8b5 386 /** \brief Enable MMU
Kojto 102:da0ca467f8b5 387
Kojto 102:da0ca467f8b5 388 Enable MMU
Kojto 102:da0ca467f8b5 389 */
Kojto 102:da0ca467f8b5 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 102:da0ca467f8b5 391 // Set M bit 0 to enable the MMU
Kojto 102:da0ca467f8b5 392 // Set AFE bit to enable simplified access permissions model
Kojto 102:da0ca467f8b5 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 102:da0ca467f8b5 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 102:da0ca467f8b5 395 __ISB();
Kojto 102:da0ca467f8b5 396 }
Kojto 102:da0ca467f8b5 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 102:da0ca467f8b5 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 102:da0ca467f8b5 401 */
Kojto 102:da0ca467f8b5 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 102:da0ca467f8b5 403 // Clear M bit 0 to disable the MMU
Kojto 102:da0ca467f8b5 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 102:da0ca467f8b5 405 __ISB();
Kojto 102:da0ca467f8b5 406 }
Kojto 102:da0ca467f8b5 407
Kojto 102:da0ca467f8b5 408 /******************************** TLB maintenance operations ************************************************/
Kojto 102:da0ca467f8b5 409 /** \brief Invalidate the whole tlb
Kojto 102:da0ca467f8b5 410
Kojto 102:da0ca467f8b5 411 TLBIALL. Invalidate the whole tlb
Kojto 102:da0ca467f8b5 412 */
Kojto 102:da0ca467f8b5 413
Kojto 102:da0ca467f8b5 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 102:da0ca467f8b5 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 102:da0ca467f8b5 416 __TLBIALL = 0;
Kojto 102:da0ca467f8b5 417 __DSB();
Kojto 102:da0ca467f8b5 418 __ISB();
Kojto 102:da0ca467f8b5 419 }
Kojto 102:da0ca467f8b5 420
Kojto 102:da0ca467f8b5 421 /******************************** BTB maintenance operations ************************************************/
Kojto 102:da0ca467f8b5 422 /** \brief Invalidate entire branch predictor array
Kojto 102:da0ca467f8b5 423
Kojto 102:da0ca467f8b5 424 BPIALL. Branch Predictor Invalidate All.
Kojto 102:da0ca467f8b5 425 */
Kojto 102:da0ca467f8b5 426
Kojto 102:da0ca467f8b5 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 102:da0ca467f8b5 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 102:da0ca467f8b5 429 __BPIALL = 0;
Kojto 102:da0ca467f8b5 430 __DSB(); //ensure completion of the invalidation
Kojto 102:da0ca467f8b5 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 102:da0ca467f8b5 432 }
Kojto 102:da0ca467f8b5 433
Kojto 102:da0ca467f8b5 434
Kojto 102:da0ca467f8b5 435 /******************************** L1 cache operations ******************************************************/
Kojto 102:da0ca467f8b5 436
Kojto 102:da0ca467f8b5 437 /** \brief Invalidate the whole I$
Kojto 102:da0ca467f8b5 438
Kojto 102:da0ca467f8b5 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 102:da0ca467f8b5 440 */
Kojto 102:da0ca467f8b5 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 102:da0ca467f8b5 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 102:da0ca467f8b5 443 __ICIALLU = 0;
Kojto 102:da0ca467f8b5 444 __DSB(); //ensure completion of the invalidation
Kojto 102:da0ca467f8b5 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 102:da0ca467f8b5 446 }
Kojto 102:da0ca467f8b5 447
Kojto 102:da0ca467f8b5 448 /** \brief Clean D$ by MVA
Kojto 102:da0ca467f8b5 449
Kojto 102:da0ca467f8b5 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 102:da0ca467f8b5 451 */
Kojto 102:da0ca467f8b5 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 102:da0ca467f8b5 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 102:da0ca467f8b5 454 __DCCMVAC = (uint32_t)va;
Kojto 102:da0ca467f8b5 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 102:da0ca467f8b5 456 }
Kojto 102:da0ca467f8b5 457
Kojto 102:da0ca467f8b5 458 /** \brief Invalidate D$ by MVA
Kojto 102:da0ca467f8b5 459
Kojto 102:da0ca467f8b5 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 102:da0ca467f8b5 461 */
Kojto 102:da0ca467f8b5 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 102:da0ca467f8b5 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 102:da0ca467f8b5 464 __DCIMVAC = (uint32_t)va;
Kojto 102:da0ca467f8b5 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 102:da0ca467f8b5 466 }
Kojto 102:da0ca467f8b5 467
Kojto 102:da0ca467f8b5 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 102:da0ca467f8b5 469
Kojto 102:da0ca467f8b5 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 102:da0ca467f8b5 471 */
Kojto 102:da0ca467f8b5 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 102:da0ca467f8b5 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 102:da0ca467f8b5 474 __DCCIMVAC = (uint32_t)va;
Kojto 102:da0ca467f8b5 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 102:da0ca467f8b5 476 }
Kojto 102:da0ca467f8b5 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 102:da0ca467f8b5 481 */
Kojto 102:da0ca467f8b5 482 #pragma push
Kojto 102:da0ca467f8b5 483 #pragma arm
Kojto 102:da0ca467f8b5 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 102:da0ca467f8b5 485 ARM
Kojto 102:da0ca467f8b5 486
Kojto 102:da0ca467f8b5 487 PUSH {R4-R11}
Kojto 102:da0ca467f8b5 488
Kojto 102:da0ca467f8b5 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 102:da0ca467f8b5 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 102:da0ca467f8b5 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 102:da0ca467f8b5 492 BEQ Finished // If 0, no need to clean
Kojto 102:da0ca467f8b5 493
Kojto 102:da0ca467f8b5 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 102:da0ca467f8b5 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 102:da0ca467f8b5 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 102:da0ca467f8b5 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 102:da0ca467f8b5 498 CMP R1, #2
Kojto 102:da0ca467f8b5 499 BLT Skip // No cache or only instruction cache at this level
Kojto 102:da0ca467f8b5 500
Kojto 102:da0ca467f8b5 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 102:da0ca467f8b5 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 102:da0ca467f8b5 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 102:da0ca467f8b5 504 AND R2, R1, #7 // Extract the line length field
Kojto 102:da0ca467f8b5 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 102:da0ca467f8b5 506 LDR R4, =0x3FF
Kojto 102:da0ca467f8b5 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 102:da0ca467f8b5 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 102:da0ca467f8b5 509 LDR R7, =0x7FFF
Kojto 102:da0ca467f8b5 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 102:da0ca467f8b5 511
Kojto 102:da0ca467f8b5 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 102:da0ca467f8b5 513
Kojto 102:da0ca467f8b5 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 102:da0ca467f8b5 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 102:da0ca467f8b5 516 CMP R0, #0
Kojto 102:da0ca467f8b5 517 BNE Dccsw
Kojto 102:da0ca467f8b5 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 102:da0ca467f8b5 519 B cont
Kojto 102:da0ca467f8b5 520 Dccsw CMP R0, #1
Kojto 102:da0ca467f8b5 521 BNE Dccisw
Kojto 102:da0ca467f8b5 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 102:da0ca467f8b5 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 102:da0ca467f8b5 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 102:da0ca467f8b5 526 BGE Loop3
Kojto 102:da0ca467f8b5 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 102:da0ca467f8b5 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 102:da0ca467f8b5 530 CMP R3, R10
Kojto 102:da0ca467f8b5 531 BGT Loop1
Kojto 102:da0ca467f8b5 532
Kojto 102:da0ca467f8b5 533 Finished
Kojto 102:da0ca467f8b5 534 DSB
Kojto 102:da0ca467f8b5 535 POP {R4-R11}
Kojto 102:da0ca467f8b5 536 BX lr
Kojto 102:da0ca467f8b5 537
Kojto 102:da0ca467f8b5 538 }
Kojto 102:da0ca467f8b5 539 #pragma pop
Kojto 102:da0ca467f8b5 540
Kojto 102:da0ca467f8b5 541
Kojto 102:da0ca467f8b5 542 /** \brief Invalidate the whole D$
Kojto 102:da0ca467f8b5 543
Kojto 102:da0ca467f8b5 544 DCISW. Invalidate by Set/Way
Kojto 102:da0ca467f8b5 545 */
Kojto 102:da0ca467f8b5 546
Kojto 102:da0ca467f8b5 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 102:da0ca467f8b5 548 __v7_all_cache(0);
Kojto 102:da0ca467f8b5 549 }
Kojto 102:da0ca467f8b5 550
Kojto 102:da0ca467f8b5 551 /** \brief Clean the whole D$
Kojto 102:da0ca467f8b5 552
Kojto 102:da0ca467f8b5 553 DCCSW. Clean by Set/Way
Kojto 102:da0ca467f8b5 554 */
Kojto 102:da0ca467f8b5 555
Kojto 102:da0ca467f8b5 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 102:da0ca467f8b5 557 __v7_all_cache(1);
Kojto 102:da0ca467f8b5 558 }
Kojto 102:da0ca467f8b5 559
Kojto 102:da0ca467f8b5 560 /** \brief Clean and invalidate the whole D$
Kojto 102:da0ca467f8b5 561
Kojto 102:da0ca467f8b5 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 102:da0ca467f8b5 563 */
Kojto 102:da0ca467f8b5 564
Kojto 102:da0ca467f8b5 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 102:da0ca467f8b5 566 __v7_all_cache(2);
Kojto 102:da0ca467f8b5 567 }
Kojto 102:da0ca467f8b5 568
Kojto 102:da0ca467f8b5 569 #include "core_ca_mmu.h"
Kojto 102:da0ca467f8b5 570
Kojto 102:da0ca467f8b5 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 102:da0ca467f8b5 572
Kojto 102:da0ca467f8b5 573 #error IAR Compiler support not implemented for Cortex-A
Kojto 102:da0ca467f8b5 574
Kojto 102:da0ca467f8b5 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 102:da0ca467f8b5 576 /* GNU gcc specific functions */
Kojto 102:da0ca467f8b5 577
Kojto 102:da0ca467f8b5 578 #define MODE_USR 0x10
Kojto 102:da0ca467f8b5 579 #define MODE_FIQ 0x11
Kojto 102:da0ca467f8b5 580 #define MODE_IRQ 0x12
Kojto 102:da0ca467f8b5 581 #define MODE_SVC 0x13
Kojto 102:da0ca467f8b5 582 #define MODE_MON 0x16
Kojto 102:da0ca467f8b5 583 #define MODE_ABT 0x17
Kojto 102:da0ca467f8b5 584 #define MODE_HYP 0x1A
Kojto 102:da0ca467f8b5 585 #define MODE_UND 0x1B
Kojto 102:da0ca467f8b5 586 #define MODE_SYS 0x1F
Kojto 102:da0ca467f8b5 587
Kojto 102:da0ca467f8b5 588
Kojto 102:da0ca467f8b5 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 102:da0ca467f8b5 590 {
Kojto 102:da0ca467f8b5 591 __ASM volatile ("cpsie i");
Kojto 102:da0ca467f8b5 592 }
Kojto 102:da0ca467f8b5 593
Kojto 102:da0ca467f8b5 594 /** \brief Disable IRQ Interrupts
Kojto 102:da0ca467f8b5 595
Kojto 102:da0ca467f8b5 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 102:da0ca467f8b5 597 Can only be executed in Privileged modes.
Kojto 102:da0ca467f8b5 598 */
Kojto 102:da0ca467f8b5 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 102:da0ca467f8b5 600 {
Kojto 102:da0ca467f8b5 601 uint32_t result;
Kojto 102:da0ca467f8b5 602
Kojto 102:da0ca467f8b5 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 102:da0ca467f8b5 604 __ASM volatile ("cpsid i");
Kojto 102:da0ca467f8b5 605 return(result & 0x80);
Kojto 102:da0ca467f8b5 606 }
Kojto 102:da0ca467f8b5 607
Kojto 102:da0ca467f8b5 608
Kojto 102:da0ca467f8b5 609 /** \brief Get APSR Register
Kojto 102:da0ca467f8b5 610
Kojto 102:da0ca467f8b5 611 This function returns the content of the APSR Register.
Kojto 102:da0ca467f8b5 612
Kojto 102:da0ca467f8b5 613 \return APSR Register value
Kojto 102:da0ca467f8b5 614 */
Kojto 102:da0ca467f8b5 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 102:da0ca467f8b5 616 {
Kojto 102:da0ca467f8b5 617 #if 1
Kojto 108:34e6b704fe68 618 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 102:da0ca467f8b5 620 #else
Kojto 102:da0ca467f8b5 621 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 622 #endif
Kojto 102:da0ca467f8b5 623 return(__regAPSR);
Kojto 102:da0ca467f8b5 624 }
Kojto 102:da0ca467f8b5 625
Kojto 102:da0ca467f8b5 626
Kojto 102:da0ca467f8b5 627 /** \brief Get CPSR Register
Kojto 102:da0ca467f8b5 628
Kojto 102:da0ca467f8b5 629 This function returns the content of the CPSR Register.
Kojto 102:da0ca467f8b5 630
Kojto 102:da0ca467f8b5 631 \return CPSR Register value
Kojto 102:da0ca467f8b5 632 */
Kojto 102:da0ca467f8b5 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 102:da0ca467f8b5 634 {
Kojto 102:da0ca467f8b5 635 #if 1
Kojto 102:da0ca467f8b5 636 register uint32_t __regCPSR;
Kojto 102:da0ca467f8b5 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 102:da0ca467f8b5 638 #else
Kojto 102:da0ca467f8b5 639 register uint32_t __regCPSR __ASM("cpsr");
Kojto 102:da0ca467f8b5 640 #endif
Kojto 102:da0ca467f8b5 641 return(__regCPSR);
Kojto 102:da0ca467f8b5 642 }
Kojto 102:da0ca467f8b5 643
Kojto 102:da0ca467f8b5 644 #if 0
Kojto 102:da0ca467f8b5 645 /** \brief Set Stack Pointer
Kojto 102:da0ca467f8b5 646
Kojto 102:da0ca467f8b5 647 This function assigns the given value to the current stack pointer.
Kojto 102:da0ca467f8b5 648
Kojto 102:da0ca467f8b5 649 \param [in] topOfStack Stack Pointer value to set
Kojto 102:da0ca467f8b5 650 */
Kojto 102:da0ca467f8b5 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 102:da0ca467f8b5 652 {
Kojto 102:da0ca467f8b5 653 register uint32_t __regSP __ASM("sp");
Kojto 102:da0ca467f8b5 654 __regSP = topOfStack;
Kojto 102:da0ca467f8b5 655 }
Kojto 102:da0ca467f8b5 656 #endif
Kojto 102:da0ca467f8b5 657
Kojto 102:da0ca467f8b5 658 /** \brief Get link register
Kojto 102:da0ca467f8b5 659
Kojto 102:da0ca467f8b5 660 This function returns the value of the link register
Kojto 102:da0ca467f8b5 661
Kojto 102:da0ca467f8b5 662 \return Value of link register
Kojto 102:da0ca467f8b5 663 */
Kojto 102:da0ca467f8b5 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 102:da0ca467f8b5 665 {
Kojto 102:da0ca467f8b5 666 register uint32_t __reglr __ASM("lr");
Kojto 102:da0ca467f8b5 667 return(__reglr);
Kojto 102:da0ca467f8b5 668 }
Kojto 102:da0ca467f8b5 669
Kojto 102:da0ca467f8b5 670 #if 0
Kojto 102:da0ca467f8b5 671 /** \brief Set link register
Kojto 102:da0ca467f8b5 672
Kojto 102:da0ca467f8b5 673 This function sets the value of the link register
Kojto 102:da0ca467f8b5 674
Kojto 102:da0ca467f8b5 675 \param [in] lr LR value to set
Kojto 102:da0ca467f8b5 676 */
Kojto 102:da0ca467f8b5 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 102:da0ca467f8b5 678 {
Kojto 102:da0ca467f8b5 679 register uint32_t __reglr __ASM("lr");
Kojto 102:da0ca467f8b5 680 __reglr = lr;
Kojto 102:da0ca467f8b5 681 }
Kojto 102:da0ca467f8b5 682 #endif
Kojto 102:da0ca467f8b5 683
Kojto 102:da0ca467f8b5 684 /** \brief Set Process Stack Pointer
Kojto 102:da0ca467f8b5 685
Kojto 102:da0ca467f8b5 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 102:da0ca467f8b5 687
Kojto 102:da0ca467f8b5 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 102:da0ca467f8b5 689 */
Kojto 108:34e6b704fe68 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 691 {
Kojto 108:34e6b704fe68 692 __asm__ volatile (
Kojto 108:34e6b704fe68 693 ".ARM;"
Kojto 108:34e6b704fe68 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 695
Kojto 108:34e6b704fe68 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 697 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 698 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 699 "MOV SP, R0;"
Kojto 108:34e6b704fe68 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 701 "ISB;"
Kojto 108:34e6b704fe68 702 //"BX LR;"
Kojto 108:34e6b704fe68 703 :
Kojto 108:34e6b704fe68 704 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 705 : "r0", "r1");
Kojto 108:34e6b704fe68 706 return;
Kojto 108:34e6b704fe68 707 }
Kojto 102:da0ca467f8b5 708
Kojto 102:da0ca467f8b5 709 /** \brief Set User Mode
Kojto 102:da0ca467f8b5 710
Kojto 102:da0ca467f8b5 711 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 712 */
Kojto 108:34e6b704fe68 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 714 {
Kojto 108:34e6b704fe68 715 __asm__ volatile (
Kojto 108:34e6b704fe68 716 ".ARM;"
Kojto 102:da0ca467f8b5 717
Kojto 108:34e6b704fe68 718 "CPS %0;"
Kojto 108:34e6b704fe68 719 //"BX LR;"
Kojto 108:34e6b704fe68 720 :
Kojto 108:34e6b704fe68 721 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 722 : );
Kojto 108:34e6b704fe68 723 return;
Kojto 108:34e6b704fe68 724 }
Kojto 108:34e6b704fe68 725
Kojto 102:da0ca467f8b5 726
Kojto 102:da0ca467f8b5 727 /** \brief Enable FIQ
Kojto 102:da0ca467f8b5 728
Kojto 102:da0ca467f8b5 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 102:da0ca467f8b5 730 Can only be executed in Privileged modes.
Kojto 102:da0ca467f8b5 731 */
Kojto 108:34e6b704fe68 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 102:da0ca467f8b5 733
Kojto 102:da0ca467f8b5 734
Kojto 102:da0ca467f8b5 735 /** \brief Disable FIQ
Kojto 102:da0ca467f8b5 736
Kojto 102:da0ca467f8b5 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 102:da0ca467f8b5 738 Can only be executed in Privileged modes.
Kojto 102:da0ca467f8b5 739 */
Kojto 108:34e6b704fe68 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 102:da0ca467f8b5 741
Kojto 102:da0ca467f8b5 742
Kojto 102:da0ca467f8b5 743 /** \brief Get FPSCR
Kojto 102:da0ca467f8b5 744
Kojto 102:da0ca467f8b5 745 This function returns the current value of the Floating Point Status/Control register.
Kojto 102:da0ca467f8b5 746
Kojto 102:da0ca467f8b5 747 \return Floating Point Status/Control register value
Kojto 102:da0ca467f8b5 748 */
Kojto 102:da0ca467f8b5 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 102:da0ca467f8b5 750 {
Kojto 102:da0ca467f8b5 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 102:da0ca467f8b5 752 #if 1
Kojto 102:da0ca467f8b5 753 uint32_t result;
Kojto 102:da0ca467f8b5 754
Kojto 102:da0ca467f8b5 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 102:da0ca467f8b5 756 return (result);
Kojto 102:da0ca467f8b5 757 #else
Kojto 102:da0ca467f8b5 758 register uint32_t __regfpscr __ASM("fpscr");
Kojto 102:da0ca467f8b5 759 return(__regfpscr);
Kojto 102:da0ca467f8b5 760 #endif
Kojto 102:da0ca467f8b5 761 #else
Kojto 102:da0ca467f8b5 762 return(0);
Kojto 102:da0ca467f8b5 763 #endif
Kojto 102:da0ca467f8b5 764 }
Kojto 102:da0ca467f8b5 765
Kojto 102:da0ca467f8b5 766
Kojto 102:da0ca467f8b5 767 /** \brief Set FPSCR
Kojto 102:da0ca467f8b5 768
Kojto 102:da0ca467f8b5 769 This function assigns the given value to the Floating Point Status/Control register.
Kojto 102:da0ca467f8b5 770
Kojto 102:da0ca467f8b5 771 \param [in] fpscr Floating Point Status/Control value to set
Kojto 102:da0ca467f8b5 772 */
Kojto 102:da0ca467f8b5 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 102:da0ca467f8b5 774 {
Kojto 102:da0ca467f8b5 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 102:da0ca467f8b5 776 #if 1
Kojto 102:da0ca467f8b5 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 102:da0ca467f8b5 778 #else
Kojto 102:da0ca467f8b5 779 register uint32_t __regfpscr __ASM("fpscr");
Kojto 102:da0ca467f8b5 780 __regfpscr = (fpscr);
Kojto 102:da0ca467f8b5 781 #endif
Kojto 102:da0ca467f8b5 782 #endif
Kojto 102:da0ca467f8b5 783 }
Kojto 102:da0ca467f8b5 784
Kojto 102:da0ca467f8b5 785 /** \brief Get FPEXC
Kojto 102:da0ca467f8b5 786
Kojto 102:da0ca467f8b5 787 This function returns the current value of the Floating Point Exception Control register.
Kojto 102:da0ca467f8b5 788
Kojto 102:da0ca467f8b5 789 \return Floating Point Exception Control register value
Kojto 102:da0ca467f8b5 790 */
Kojto 102:da0ca467f8b5 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 102:da0ca467f8b5 792 {
Kojto 102:da0ca467f8b5 793 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 794 #if 1
Kojto 102:da0ca467f8b5 795 uint32_t result;
Kojto 102:da0ca467f8b5 796
Kojto 102:da0ca467f8b5 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 102:da0ca467f8b5 798 return (result);
Kojto 102:da0ca467f8b5 799 #else
Kojto 102:da0ca467f8b5 800 register uint32_t __regfpexc __ASM("fpexc");
Kojto 102:da0ca467f8b5 801 return(__regfpexc);
Kojto 102:da0ca467f8b5 802 #endif
Kojto 102:da0ca467f8b5 803 #else
Kojto 102:da0ca467f8b5 804 return(0);
Kojto 102:da0ca467f8b5 805 #endif
Kojto 102:da0ca467f8b5 806 }
Kojto 102:da0ca467f8b5 807
Kojto 102:da0ca467f8b5 808
Kojto 102:da0ca467f8b5 809 /** \brief Set FPEXC
Kojto 102:da0ca467f8b5 810
Kojto 102:da0ca467f8b5 811 This function assigns the given value to the Floating Point Exception Control register.
Kojto 102:da0ca467f8b5 812
Kojto 102:da0ca467f8b5 813 \param [in] fpscr Floating Point Exception Control value to set
Kojto 102:da0ca467f8b5 814 */
Kojto 102:da0ca467f8b5 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 102:da0ca467f8b5 816 {
Kojto 102:da0ca467f8b5 817 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 818 #if 1
Kojto 102:da0ca467f8b5 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 102:da0ca467f8b5 820 #else
Kojto 102:da0ca467f8b5 821 register uint32_t __regfpexc __ASM("fpexc");
Kojto 102:da0ca467f8b5 822 __regfpexc = (fpexc);
Kojto 102:da0ca467f8b5 823 #endif
Kojto 102:da0ca467f8b5 824 #endif
Kojto 102:da0ca467f8b5 825 }
Kojto 102:da0ca467f8b5 826
Kojto 102:da0ca467f8b5 827 /** \brief Get CPACR
Kojto 102:da0ca467f8b5 828
Kojto 102:da0ca467f8b5 829 This function returns the current value of the Coprocessor Access Control register.
Kojto 102:da0ca467f8b5 830
Kojto 102:da0ca467f8b5 831 \return Coprocessor Access Control register value
Kojto 102:da0ca467f8b5 832 */
Kojto 102:da0ca467f8b5 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 102:da0ca467f8b5 834 {
Kojto 102:da0ca467f8b5 835 #if 1
Kojto 102:da0ca467f8b5 836 register uint32_t __regCPACR;
Kojto 102:da0ca467f8b5 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 102:da0ca467f8b5 838 #else
Kojto 102:da0ca467f8b5 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 102:da0ca467f8b5 840 #endif
Kojto 102:da0ca467f8b5 841 return __regCPACR;
Kojto 102:da0ca467f8b5 842 }
Kojto 102:da0ca467f8b5 843
Kojto 102:da0ca467f8b5 844 /** \brief Set CPACR
Kojto 102:da0ca467f8b5 845
Kojto 102:da0ca467f8b5 846 This function assigns the given value to the Coprocessor Access Control register.
Kojto 102:da0ca467f8b5 847
Kojto 108:34e6b704fe68 848 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 102:da0ca467f8b5 849 */
Kojto 102:da0ca467f8b5 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 102:da0ca467f8b5 851 {
Kojto 102:da0ca467f8b5 852 #if 1
Kojto 102:da0ca467f8b5 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 102:da0ca467f8b5 854 #else
Kojto 102:da0ca467f8b5 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 102:da0ca467f8b5 856 __regCPACR = cpacr;
Kojto 102:da0ca467f8b5 857 #endif
Kojto 102:da0ca467f8b5 858 __ISB();
Kojto 102:da0ca467f8b5 859 }
Kojto 102:da0ca467f8b5 860
Kojto 102:da0ca467f8b5 861 /** \brief Get CBAR
Kojto 102:da0ca467f8b5 862
Kojto 102:da0ca467f8b5 863 This function returns the value of the Configuration Base Address register.
Kojto 102:da0ca467f8b5 864
Kojto 102:da0ca467f8b5 865 \return Configuration Base Address register value
Kojto 102:da0ca467f8b5 866 */
Kojto 102:da0ca467f8b5 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 102:da0ca467f8b5 868 #if 1
Kojto 102:da0ca467f8b5 869 register uint32_t __regCBAR;
Kojto 102:da0ca467f8b5 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 102:da0ca467f8b5 871 #else
Kojto 102:da0ca467f8b5 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 102:da0ca467f8b5 873 #endif
Kojto 102:da0ca467f8b5 874 return(__regCBAR);
Kojto 102:da0ca467f8b5 875 }
Kojto 102:da0ca467f8b5 876
Kojto 102:da0ca467f8b5 877 /** \brief Get TTBR0
Kojto 102:da0ca467f8b5 878
Kojto 108:34e6b704fe68 879 This function returns the value of the Translation Table Base Register 0.
Kojto 102:da0ca467f8b5 880
Kojto 102:da0ca467f8b5 881 \return Translation Table Base Register 0 value
Kojto 102:da0ca467f8b5 882 */
Kojto 102:da0ca467f8b5 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 102:da0ca467f8b5 884 #if 1
Kojto 102:da0ca467f8b5 885 register uint32_t __regTTBR0;
Kojto 102:da0ca467f8b5 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 102:da0ca467f8b5 887 #else
Kojto 102:da0ca467f8b5 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 102:da0ca467f8b5 889 #endif
Kojto 102:da0ca467f8b5 890 return(__regTTBR0);
Kojto 102:da0ca467f8b5 891 }
Kojto 102:da0ca467f8b5 892
Kojto 102:da0ca467f8b5 893 /** \brief Set TTBR0
Kojto 102:da0ca467f8b5 894
Kojto 108:34e6b704fe68 895 This function assigns the given value to the Translation Table Base Register 0.
Kojto 102:da0ca467f8b5 896
Kojto 102:da0ca467f8b5 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 102:da0ca467f8b5 898 */
Kojto 102:da0ca467f8b5 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 102:da0ca467f8b5 900 #if 1
Kojto 102:da0ca467f8b5 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 102:da0ca467f8b5 902 #else
Kojto 102:da0ca467f8b5 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 102:da0ca467f8b5 904 __regTTBR0 = ttbr0;
Kojto 102:da0ca467f8b5 905 #endif
Kojto 102:da0ca467f8b5 906 __ISB();
Kojto 102:da0ca467f8b5 907 }
Kojto 102:da0ca467f8b5 908
Kojto 102:da0ca467f8b5 909 /** \brief Get DACR
Kojto 102:da0ca467f8b5 910
Kojto 102:da0ca467f8b5 911 This function returns the value of the Domain Access Control Register.
Kojto 102:da0ca467f8b5 912
Kojto 102:da0ca467f8b5 913 \return Domain Access Control Register value
Kojto 102:da0ca467f8b5 914 */
Kojto 102:da0ca467f8b5 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 102:da0ca467f8b5 916 #if 1
Kojto 102:da0ca467f8b5 917 register uint32_t __regDACR;
Kojto 102:da0ca467f8b5 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 102:da0ca467f8b5 919 #else
Kojto 102:da0ca467f8b5 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 102:da0ca467f8b5 921 #endif
Kojto 102:da0ca467f8b5 922 return(__regDACR);
Kojto 102:da0ca467f8b5 923 }
Kojto 102:da0ca467f8b5 924
Kojto 102:da0ca467f8b5 925 /** \brief Set DACR
Kojto 102:da0ca467f8b5 926
Kojto 108:34e6b704fe68 927 This function assigns the given value to the Domain Access Control Register.
Kojto 102:da0ca467f8b5 928
Kojto 102:da0ca467f8b5 929 \param [in] dacr Domain Access Control Register value to set
Kojto 102:da0ca467f8b5 930 */
Kojto 102:da0ca467f8b5 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 102:da0ca467f8b5 932 #if 1
Kojto 102:da0ca467f8b5 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 102:da0ca467f8b5 934 #else
Kojto 102:da0ca467f8b5 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 102:da0ca467f8b5 936 __regDACR = dacr;
Kojto 102:da0ca467f8b5 937 #endif
Kojto 102:da0ca467f8b5 938 __ISB();
Kojto 102:da0ca467f8b5 939 }
Kojto 102:da0ca467f8b5 940
Kojto 102:da0ca467f8b5 941 /******************************** Cache and BTAC enable ****************************************************/
Kojto 102:da0ca467f8b5 942
Kojto 102:da0ca467f8b5 943 /** \brief Set SCTLR
Kojto 102:da0ca467f8b5 944
Kojto 102:da0ca467f8b5 945 This function assigns the given value to the System Control Register.
Kojto 102:da0ca467f8b5 946
Kojto 108:34e6b704fe68 947 \param [in] sctlr System Control Register value to set
Kojto 102:da0ca467f8b5 948 */
Kojto 102:da0ca467f8b5 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 102:da0ca467f8b5 950 {
Kojto 102:da0ca467f8b5 951 #if 1
Kojto 102:da0ca467f8b5 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 102:da0ca467f8b5 953 #else
Kojto 102:da0ca467f8b5 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 102:da0ca467f8b5 955 __regSCTLR = sctlr;
Kojto 102:da0ca467f8b5 956 #endif
Kojto 102:da0ca467f8b5 957 }
Kojto 102:da0ca467f8b5 958
Kojto 102:da0ca467f8b5 959 /** \brief Get SCTLR
Kojto 102:da0ca467f8b5 960
Kojto 102:da0ca467f8b5 961 This function returns the value of the System Control Register.
Kojto 102:da0ca467f8b5 962
Kojto 102:da0ca467f8b5 963 \return System Control Register value
Kojto 102:da0ca467f8b5 964 */
Kojto 102:da0ca467f8b5 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 102:da0ca467f8b5 966 #if 1
Kojto 102:da0ca467f8b5 967 register uint32_t __regSCTLR;
Kojto 102:da0ca467f8b5 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 102:da0ca467f8b5 969 #else
Kojto 102:da0ca467f8b5 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 102:da0ca467f8b5 971 #endif
Kojto 102:da0ca467f8b5 972 return(__regSCTLR);
Kojto 102:da0ca467f8b5 973 }
Kojto 102:da0ca467f8b5 974
Kojto 102:da0ca467f8b5 975 /** \brief Enable Caches
Kojto 102:da0ca467f8b5 976
Kojto 102:da0ca467f8b5 977 Enable Caches
Kojto 102:da0ca467f8b5 978 */
Kojto 102:da0ca467f8b5 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 102:da0ca467f8b5 980 // Set I bit 12 to enable I Cache
Kojto 102:da0ca467f8b5 981 // Set C bit 2 to enable D Cache
Kojto 102:da0ca467f8b5 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 102:da0ca467f8b5 983 }
Kojto 102:da0ca467f8b5 984
Kojto 102:da0ca467f8b5 985 /** \brief Disable Caches
Kojto 102:da0ca467f8b5 986
Kojto 102:da0ca467f8b5 987 Disable Caches
Kojto 102:da0ca467f8b5 988 */
Kojto 102:da0ca467f8b5 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 102:da0ca467f8b5 990 // Clear I bit 12 to disable I Cache
Kojto 102:da0ca467f8b5 991 // Clear C bit 2 to disable D Cache
Kojto 102:da0ca467f8b5 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 102:da0ca467f8b5 993 __ISB();
Kojto 102:da0ca467f8b5 994 }
Kojto 102:da0ca467f8b5 995
Kojto 102:da0ca467f8b5 996 /** \brief Enable BTAC
Kojto 102:da0ca467f8b5 997
Kojto 102:da0ca467f8b5 998 Enable BTAC
Kojto 102:da0ca467f8b5 999 */
Kojto 102:da0ca467f8b5 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 102:da0ca467f8b5 1001 // Set Z bit 11 to enable branch prediction
Kojto 102:da0ca467f8b5 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 102:da0ca467f8b5 1003 __ISB();
Kojto 102:da0ca467f8b5 1004 }
Kojto 102:da0ca467f8b5 1005
Kojto 102:da0ca467f8b5 1006 /** \brief Disable BTAC
Kojto 102:da0ca467f8b5 1007
Kojto 102:da0ca467f8b5 1008 Disable BTAC
Kojto 102:da0ca467f8b5 1009 */
Kojto 102:da0ca467f8b5 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 102:da0ca467f8b5 1011 // Clear Z bit 11 to disable branch prediction
Kojto 102:da0ca467f8b5 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 102:da0ca467f8b5 1013 }
Kojto 102:da0ca467f8b5 1014
Kojto 102:da0ca467f8b5 1015
Kojto 102:da0ca467f8b5 1016 /** \brief Enable MMU
Kojto 102:da0ca467f8b5 1017
Kojto 102:da0ca467f8b5 1018 Enable MMU
Kojto 102:da0ca467f8b5 1019 */
Kojto 102:da0ca467f8b5 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 102:da0ca467f8b5 1021 // Set M bit 0 to enable the MMU
Kojto 102:da0ca467f8b5 1022 // Set AFE bit to enable simplified access permissions model
Kojto 102:da0ca467f8b5 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 102:da0ca467f8b5 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 102:da0ca467f8b5 1025 __ISB();
Kojto 102:da0ca467f8b5 1026 }
Kojto 102:da0ca467f8b5 1027
Kojto 108:34e6b704fe68 1028 /** \brief Disable MMU
Kojto 102:da0ca467f8b5 1029
Kojto 108:34e6b704fe68 1030 Disable MMU
Kojto 102:da0ca467f8b5 1031 */
Kojto 102:da0ca467f8b5 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 102:da0ca467f8b5 1033 // Clear M bit 0 to disable the MMU
Kojto 102:da0ca467f8b5 1034 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 102:da0ca467f8b5 1035 __ISB();
Kojto 102:da0ca467f8b5 1036 }
Kojto 102:da0ca467f8b5 1037
Kojto 102:da0ca467f8b5 1038 /******************************** TLB maintenance operations ************************************************/
Kojto 102:da0ca467f8b5 1039 /** \brief Invalidate the whole tlb
Kojto 102:da0ca467f8b5 1040
Kojto 102:da0ca467f8b5 1041 TLBIALL. Invalidate the whole tlb
Kojto 102:da0ca467f8b5 1042 */
Kojto 102:da0ca467f8b5 1043
Kojto 102:da0ca467f8b5 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 102:da0ca467f8b5 1045 #if 1
Kojto 102:da0ca467f8b5 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 102:da0ca467f8b5 1047 #else
Kojto 102:da0ca467f8b5 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 102:da0ca467f8b5 1049 __TLBIALL = 0;
Kojto 102:da0ca467f8b5 1050 #endif
Kojto 102:da0ca467f8b5 1051 __DSB();
Kojto 102:da0ca467f8b5 1052 __ISB();
Kojto 102:da0ca467f8b5 1053 }
Kojto 102:da0ca467f8b5 1054
Kojto 102:da0ca467f8b5 1055 /******************************** BTB maintenance operations ************************************************/
Kojto 102:da0ca467f8b5 1056 /** \brief Invalidate entire branch predictor array
Kojto 102:da0ca467f8b5 1057
Kojto 102:da0ca467f8b5 1058 BPIALL. Branch Predictor Invalidate All.
Kojto 102:da0ca467f8b5 1059 */
Kojto 102:da0ca467f8b5 1060
Kojto 102:da0ca467f8b5 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 102:da0ca467f8b5 1062 #if 1
Kojto 102:da0ca467f8b5 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 102:da0ca467f8b5 1064 #else
Kojto 102:da0ca467f8b5 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 102:da0ca467f8b5 1066 __BPIALL = 0;
Kojto 102:da0ca467f8b5 1067 #endif
Kojto 102:da0ca467f8b5 1068 __DSB(); //ensure completion of the invalidation
Kojto 102:da0ca467f8b5 1069 __ISB(); //ensure instruction fetch path sees new state
Kojto 102:da0ca467f8b5 1070 }
Kojto 102:da0ca467f8b5 1071
Kojto 102:da0ca467f8b5 1072
Kojto 102:da0ca467f8b5 1073 /******************************** L1 cache operations ******************************************************/
Kojto 102:da0ca467f8b5 1074
Kojto 102:da0ca467f8b5 1075 /** \brief Invalidate the whole I$
Kojto 102:da0ca467f8b5 1076
Kojto 102:da0ca467f8b5 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 102:da0ca467f8b5 1078 */
Kojto 102:da0ca467f8b5 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 102:da0ca467f8b5 1080 #if 1
Kojto 102:da0ca467f8b5 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 102:da0ca467f8b5 1082 #else
Kojto 102:da0ca467f8b5 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 102:da0ca467f8b5 1084 __ICIALLU = 0;
Kojto 102:da0ca467f8b5 1085 #endif
Kojto 102:da0ca467f8b5 1086 __DSB(); //ensure completion of the invalidation
Kojto 102:da0ca467f8b5 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 102:da0ca467f8b5 1088 }
Kojto 102:da0ca467f8b5 1089
Kojto 102:da0ca467f8b5 1090 /** \brief Clean D$ by MVA
Kojto 102:da0ca467f8b5 1091
Kojto 102:da0ca467f8b5 1092 DCCMVAC. Data cache clean by MVA to PoC
Kojto 102:da0ca467f8b5 1093 */
Kojto 102:da0ca467f8b5 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 102:da0ca467f8b5 1095 #if 1
Kojto 102:da0ca467f8b5 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 102:da0ca467f8b5 1097 #else
Kojto 102:da0ca467f8b5 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 102:da0ca467f8b5 1099 __DCCMVAC = (uint32_t)va;
Kojto 102:da0ca467f8b5 1100 #endif
Kojto 102:da0ca467f8b5 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 102:da0ca467f8b5 1102 }
Kojto 102:da0ca467f8b5 1103
Kojto 102:da0ca467f8b5 1104 /** \brief Invalidate D$ by MVA
Kojto 102:da0ca467f8b5 1105
Kojto 102:da0ca467f8b5 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 102:da0ca467f8b5 1107 */
Kojto 102:da0ca467f8b5 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 102:da0ca467f8b5 1109 #if 1
Kojto 102:da0ca467f8b5 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 102:da0ca467f8b5 1111 #else
Kojto 102:da0ca467f8b5 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 102:da0ca467f8b5 1113 __DCIMVAC = (uint32_t)va;
Kojto 102:da0ca467f8b5 1114 #endif
Kojto 102:da0ca467f8b5 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 102:da0ca467f8b5 1116 }
Kojto 102:da0ca467f8b5 1117
Kojto 102:da0ca467f8b5 1118 /** \brief Clean and Invalidate D$ by MVA
Kojto 102:da0ca467f8b5 1119
Kojto 102:da0ca467f8b5 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 102:da0ca467f8b5 1121 */
Kojto 102:da0ca467f8b5 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 102:da0ca467f8b5 1123 #if 1
Kojto 102:da0ca467f8b5 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 102:da0ca467f8b5 1125 #else
Kojto 102:da0ca467f8b5 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 102:da0ca467f8b5 1127 __DCCIMVAC = (uint32_t)va;
Kojto 102:da0ca467f8b5 1128 #endif
Kojto 102:da0ca467f8b5 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 102:da0ca467f8b5 1130 }
Kojto 102:da0ca467f8b5 1131
Kojto 108:34e6b704fe68 1132 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 102:da0ca467f8b5 1133
Kojto 108:34e6b704fe68 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 102:da0ca467f8b5 1135 */
Kojto 102:da0ca467f8b5 1136 extern void __v7_all_cache(uint32_t op);
Kojto 102:da0ca467f8b5 1137
Kojto 102:da0ca467f8b5 1138
Kojto 102:da0ca467f8b5 1139 /** \brief Invalidate the whole D$
Kojto 102:da0ca467f8b5 1140
Kojto 102:da0ca467f8b5 1141 DCISW. Invalidate by Set/Way
Kojto 102:da0ca467f8b5 1142 */
Kojto 102:da0ca467f8b5 1143
Kojto 102:da0ca467f8b5 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 102:da0ca467f8b5 1145 __v7_all_cache(0);
Kojto 102:da0ca467f8b5 1146 }
Kojto 102:da0ca467f8b5 1147
Kojto 102:da0ca467f8b5 1148 /** \brief Clean the whole D$
Kojto 102:da0ca467f8b5 1149
Kojto 102:da0ca467f8b5 1150 DCCSW. Clean by Set/Way
Kojto 102:da0ca467f8b5 1151 */
Kojto 102:da0ca467f8b5 1152
Kojto 102:da0ca467f8b5 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 102:da0ca467f8b5 1154 __v7_all_cache(1);
Kojto 102:da0ca467f8b5 1155 }
Kojto 102:da0ca467f8b5 1156
Kojto 102:da0ca467f8b5 1157 /** \brief Clean and invalidate the whole D$
Kojto 102:da0ca467f8b5 1158
Kojto 102:da0ca467f8b5 1159 DCCISW. Clean and Invalidate by Set/Way
Kojto 102:da0ca467f8b5 1160 */
Kojto 102:da0ca467f8b5 1161
Kojto 102:da0ca467f8b5 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 102:da0ca467f8b5 1163 __v7_all_cache(2);
Kojto 102:da0ca467f8b5 1164 }
Kojto 102:da0ca467f8b5 1165
Kojto 102:da0ca467f8b5 1166 #include "core_ca_mmu.h"
Kojto 102:da0ca467f8b5 1167
Kojto 102:da0ca467f8b5 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 102:da0ca467f8b5 1169
Kojto 102:da0ca467f8b5 1170 #error TASKING Compiler support not implemented for Cortex-A
Kojto 102:da0ca467f8b5 1171
Kojto 102:da0ca467f8b5 1172 #endif
Kojto 102:da0ca467f8b5 1173
Kojto 102:da0ca467f8b5 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 102:da0ca467f8b5 1175
Kojto 102:da0ca467f8b5 1176
Kojto 102:da0ca467f8b5 1177 #endif /* __CORE_CAFUNC_H__ */