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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_MPS2_BEID/core_cm0.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Child:
110:165afa46840b
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**************************************************************************//**
Kojto 108:34e6b704fe68 2 * @file core_cm0.h
Kojto 108:34e6b704fe68 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 108:34e6b704fe68 4 * @version V3.20
Kojto 108:34e6b704fe68 5 * @date 25. February 2013
Kojto 108:34e6b704fe68 6 *
Kojto 108:34e6b704fe68 7 * @note
Kojto 108:34e6b704fe68 8 *
Kojto 108:34e6b704fe68 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 108:34e6b704fe68 11
Kojto 108:34e6b704fe68 12 All rights reserved.
Kojto 108:34e6b704fe68 13 Redistribution and use in source and binary forms, with or without
Kojto 108:34e6b704fe68 14 modification, are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 15 - Redistributions of source code must retain the above copyright
Kojto 108:34e6b704fe68 16 notice, this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 17 - Redistributions in binary form must reproduce the above copyright
Kojto 108:34e6b704fe68 18 notice, this list of conditions and the following disclaimer in the
Kojto 108:34e6b704fe68 19 documentation and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 108:34e6b704fe68 21 to endorse or promote products derived from this software without
Kojto 108:34e6b704fe68 22 specific prior written permission.
Kojto 108:34e6b704fe68 23 *
Kojto 108:34e6b704fe68 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 108:34e6b704fe68 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 108:34e6b704fe68 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 108:34e6b704fe68 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 108:34e6b704fe68 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 108:34e6b704fe68 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 108:34e6b704fe68 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 108:34e6b704fe68 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 108:34e6b704fe68 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 35 ---------------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 36
Kojto 108:34e6b704fe68 37
Kojto 108:34e6b704fe68 38 #if defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 108:34e6b704fe68 40 #endif
Kojto 108:34e6b704fe68 41
Kojto 108:34e6b704fe68 42 #ifdef __cplusplus
Kojto 108:34e6b704fe68 43 extern "C" {
Kojto 108:34e6b704fe68 44 #endif
Kojto 108:34e6b704fe68 45
Kojto 108:34e6b704fe68 46 #ifndef __CORE_CM0_H_GENERIC
Kojto 108:34e6b704fe68 47 #define __CORE_CM0_H_GENERIC
Kojto 108:34e6b704fe68 48
Kojto 108:34e6b704fe68 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 108:34e6b704fe68 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 108:34e6b704fe68 51
Kojto 108:34e6b704fe68 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 108:34e6b704fe68 53 Function definitions in header files are used to allow 'inlining'.
Kojto 108:34e6b704fe68 54
Kojto 108:34e6b704fe68 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 108:34e6b704fe68 56 Unions are used for effective representation of core registers.
Kojto 108:34e6b704fe68 57
Kojto 108:34e6b704fe68 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 108:34e6b704fe68 59 Function-like macros are used to allow more efficient code.
Kojto 108:34e6b704fe68 60 */
Kojto 108:34e6b704fe68 61
Kojto 108:34e6b704fe68 62
Kojto 108:34e6b704fe68 63 /*******************************************************************************
Kojto 108:34e6b704fe68 64 * CMSIS definitions
Kojto 108:34e6b704fe68 65 ******************************************************************************/
Kojto 108:34e6b704fe68 66 /** \ingroup Cortex_M0
Kojto 108:34e6b704fe68 67 @{
Kojto 108:34e6b704fe68 68 */
Kojto 108:34e6b704fe68 69
Kojto 108:34e6b704fe68 70 /* CMSIS CM0 definitions */
Kojto 108:34e6b704fe68 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 108:34e6b704fe68 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 108:34e6b704fe68 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 108:34e6b704fe68 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 108:34e6b704fe68 75
Kojto 108:34e6b704fe68 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 108:34e6b704fe68 77
Kojto 108:34e6b704fe68 78
Kojto 108:34e6b704fe68 79 #if defined ( __CC_ARM )
Kojto 108:34e6b704fe68 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 108:34e6b704fe68 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 108:34e6b704fe68 82 #define __STATIC_INLINE static __inline
Kojto 108:34e6b704fe68 83
Kojto 108:34e6b704fe68 84 #elif defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 108:34e6b704fe68 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 108:34e6b704fe68 87 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 88
Kojto 108:34e6b704fe68 89 #elif defined ( __GNUC__ )
Kojto 108:34e6b704fe68 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 108:34e6b704fe68 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 108:34e6b704fe68 92 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 93
Kojto 108:34e6b704fe68 94 #elif defined ( __TASKING__ )
Kojto 108:34e6b704fe68 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 108:34e6b704fe68 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 108:34e6b704fe68 97 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 98
Kojto 108:34e6b704fe68 99 #endif
Kojto 108:34e6b704fe68 100
Kojto 108:34e6b704fe68 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 108:34e6b704fe68 102 */
Kojto 108:34e6b704fe68 103 #define __FPU_USED 0
Kojto 108:34e6b704fe68 104
Kojto 108:34e6b704fe68 105 #if defined ( __CC_ARM )
Kojto 108:34e6b704fe68 106 #if defined __TARGET_FPU_VFP
Kojto 108:34e6b704fe68 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 108 #endif
Kojto 108:34e6b704fe68 109
Kojto 108:34e6b704fe68 110 #elif defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 111 #if defined __ARMVFP__
Kojto 108:34e6b704fe68 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 113 #endif
Kojto 108:34e6b704fe68 114
Kojto 108:34e6b704fe68 115 #elif defined ( __GNUC__ )
Kojto 108:34e6b704fe68 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 108:34e6b704fe68 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 118 #endif
Kojto 108:34e6b704fe68 119
Kojto 108:34e6b704fe68 120 #elif defined ( __TASKING__ )
Kojto 108:34e6b704fe68 121 #if defined __FPU_VFP__
Kojto 108:34e6b704fe68 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 123 #endif
Kojto 108:34e6b704fe68 124 #endif
Kojto 108:34e6b704fe68 125
Kojto 108:34e6b704fe68 126 #include <stdint.h> /* standard types definitions */
Kojto 108:34e6b704fe68 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 108:34e6b704fe68 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 108:34e6b704fe68 129
Kojto 108:34e6b704fe68 130 #endif /* __CORE_CM0_H_GENERIC */
Kojto 108:34e6b704fe68 131
Kojto 108:34e6b704fe68 132 #ifndef __CMSIS_GENERIC
Kojto 108:34e6b704fe68 133
Kojto 108:34e6b704fe68 134 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 108:34e6b704fe68 135 #define __CORE_CM0_H_DEPENDANT
Kojto 108:34e6b704fe68 136
Kojto 108:34e6b704fe68 137 /* check device defines and use defaults */
Kojto 108:34e6b704fe68 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 108:34e6b704fe68 139 #ifndef __CM0_REV
Kojto 108:34e6b704fe68 140 #define __CM0_REV 0x0000
Kojto 108:34e6b704fe68 141 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 108:34e6b704fe68 142 #endif
Kojto 108:34e6b704fe68 143
Kojto 108:34e6b704fe68 144 #ifndef __NVIC_PRIO_BITS
Kojto 108:34e6b704fe68 145 #define __NVIC_PRIO_BITS 2
Kojto 108:34e6b704fe68 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 108:34e6b704fe68 147 #endif
Kojto 108:34e6b704fe68 148
Kojto 108:34e6b704fe68 149 #ifndef __Vendor_SysTickConfig
Kojto 108:34e6b704fe68 150 #define __Vendor_SysTickConfig 0
Kojto 108:34e6b704fe68 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 108:34e6b704fe68 152 #endif
Kojto 108:34e6b704fe68 153 #endif
Kojto 108:34e6b704fe68 154
Kojto 108:34e6b704fe68 155 /* IO definitions (access restrictions to peripheral registers) */
Kojto 108:34e6b704fe68 156 /**
Kojto 108:34e6b704fe68 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 108:34e6b704fe68 158
Kojto 108:34e6b704fe68 159 <strong>IO Type Qualifiers</strong> are used
Kojto 108:34e6b704fe68 160 \li to specify the access to peripheral variables.
Kojto 108:34e6b704fe68 161 \li for automatic generation of peripheral register debug information.
Kojto 108:34e6b704fe68 162 */
Kojto 108:34e6b704fe68 163 #ifdef __cplusplus
Kojto 108:34e6b704fe68 164 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 108:34e6b704fe68 165 #else
Kojto 108:34e6b704fe68 166 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 108:34e6b704fe68 167 #endif
Kojto 108:34e6b704fe68 168 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 108:34e6b704fe68 169 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 108:34e6b704fe68 170
Kojto 108:34e6b704fe68 171 /*@} end of group Cortex_M0 */
Kojto 108:34e6b704fe68 172
Kojto 108:34e6b704fe68 173
Kojto 108:34e6b704fe68 174
Kojto 108:34e6b704fe68 175 /*******************************************************************************
Kojto 108:34e6b704fe68 176 * Register Abstraction
Kojto 108:34e6b704fe68 177 Core Register contain:
Kojto 108:34e6b704fe68 178 - Core Register
Kojto 108:34e6b704fe68 179 - Core NVIC Register
Kojto 108:34e6b704fe68 180 - Core SCB Register
Kojto 108:34e6b704fe68 181 - Core SysTick Register
Kojto 108:34e6b704fe68 182 ******************************************************************************/
Kojto 108:34e6b704fe68 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 108:34e6b704fe68 184 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 108:34e6b704fe68 185 */
Kojto 108:34e6b704fe68 186
Kojto 108:34e6b704fe68 187 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 188 \defgroup CMSIS_CORE Status and Control Registers
Kojto 108:34e6b704fe68 189 \brief Core Register type definitions.
Kojto 108:34e6b704fe68 190 @{
Kojto 108:34e6b704fe68 191 */
Kojto 108:34e6b704fe68 192
Kojto 108:34e6b704fe68 193 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 108:34e6b704fe68 194 */
Kojto 108:34e6b704fe68 195 typedef union
Kojto 108:34e6b704fe68 196 {
Kojto 108:34e6b704fe68 197 struct
Kojto 108:34e6b704fe68 198 {
Kojto 108:34e6b704fe68 199 #if (__CORTEX_M != 0x04)
Kojto 108:34e6b704fe68 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 108:34e6b704fe68 201 #else
Kojto 108:34e6b704fe68 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 108:34e6b704fe68 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 108:34e6b704fe68 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 108:34e6b704fe68 205 #endif
Kojto 108:34e6b704fe68 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 108:34e6b704fe68 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 108:34e6b704fe68 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 108:34e6b704fe68 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 108:34e6b704fe68 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 108:34e6b704fe68 211 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 212 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 213 } APSR_Type;
Kojto 108:34e6b704fe68 214
Kojto 108:34e6b704fe68 215
Kojto 108:34e6b704fe68 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 108:34e6b704fe68 217 */
Kojto 108:34e6b704fe68 218 typedef union
Kojto 108:34e6b704fe68 219 {
Kojto 108:34e6b704fe68 220 struct
Kojto 108:34e6b704fe68 221 {
Kojto 108:34e6b704fe68 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 108:34e6b704fe68 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 108:34e6b704fe68 224 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 225 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 226 } IPSR_Type;
Kojto 108:34e6b704fe68 227
Kojto 108:34e6b704fe68 228
Kojto 108:34e6b704fe68 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 108:34e6b704fe68 230 */
Kojto 108:34e6b704fe68 231 typedef union
Kojto 108:34e6b704fe68 232 {
Kojto 108:34e6b704fe68 233 struct
Kojto 108:34e6b704fe68 234 {
Kojto 108:34e6b704fe68 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 108:34e6b704fe68 236 #if (__CORTEX_M != 0x04)
Kojto 108:34e6b704fe68 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 108:34e6b704fe68 238 #else
Kojto 108:34e6b704fe68 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 108:34e6b704fe68 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 108:34e6b704fe68 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 108:34e6b704fe68 242 #endif
Kojto 108:34e6b704fe68 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 108:34e6b704fe68 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 108:34e6b704fe68 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 108:34e6b704fe68 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 108:34e6b704fe68 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 108:34e6b704fe68 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 108:34e6b704fe68 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 108:34e6b704fe68 250 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 251 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 252 } xPSR_Type;
Kojto 108:34e6b704fe68 253
Kojto 108:34e6b704fe68 254
Kojto 108:34e6b704fe68 255 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 108:34e6b704fe68 256 */
Kojto 108:34e6b704fe68 257 typedef union
Kojto 108:34e6b704fe68 258 {
Kojto 108:34e6b704fe68 259 struct
Kojto 108:34e6b704fe68 260 {
Kojto 108:34e6b704fe68 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 108:34e6b704fe68 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 108:34e6b704fe68 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 108:34e6b704fe68 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 108:34e6b704fe68 265 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 266 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 267 } CONTROL_Type;
Kojto 108:34e6b704fe68 268
Kojto 108:34e6b704fe68 269 /*@} end of group CMSIS_CORE */
Kojto 108:34e6b704fe68 270
Kojto 108:34e6b704fe68 271
Kojto 108:34e6b704fe68 272 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 108:34e6b704fe68 274 \brief Type definitions for the NVIC Registers
Kojto 108:34e6b704fe68 275 @{
Kojto 108:34e6b704fe68 276 */
Kojto 108:34e6b704fe68 277
Kojto 108:34e6b704fe68 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 108:34e6b704fe68 279 */
Kojto 108:34e6b704fe68 280 typedef struct
Kojto 108:34e6b704fe68 281 {
Kojto 108:34e6b704fe68 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 108:34e6b704fe68 283 uint32_t RESERVED0[31];
Kojto 108:34e6b704fe68 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 108:34e6b704fe68 285 uint32_t RSERVED1[31];
Kojto 108:34e6b704fe68 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 108:34e6b704fe68 287 uint32_t RESERVED2[31];
Kojto 108:34e6b704fe68 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 108:34e6b704fe68 289 uint32_t RESERVED3[31];
Kojto 108:34e6b704fe68 290 uint32_t RESERVED4[64];
Kojto 108:34e6b704fe68 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 108:34e6b704fe68 292 } NVIC_Type;
Kojto 108:34e6b704fe68 293
Kojto 108:34e6b704fe68 294 /*@} end of group CMSIS_NVIC */
Kojto 108:34e6b704fe68 295
Kojto 108:34e6b704fe68 296
Kojto 108:34e6b704fe68 297 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 298 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 108:34e6b704fe68 299 \brief Type definitions for the System Control Block Registers
Kojto 108:34e6b704fe68 300 @{
Kojto 108:34e6b704fe68 301 */
Kojto 108:34e6b704fe68 302
Kojto 108:34e6b704fe68 303 /** \brief Structure type to access the System Control Block (SCB).
Kojto 108:34e6b704fe68 304 */
Kojto 108:34e6b704fe68 305 typedef struct
Kojto 108:34e6b704fe68 306 {
Kojto 108:34e6b704fe68 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 108:34e6b704fe68 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 108:34e6b704fe68 309 uint32_t RESERVED0;
Kojto 108:34e6b704fe68 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 108:34e6b704fe68 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 108:34e6b704fe68 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 108:34e6b704fe68 313 uint32_t RESERVED1;
Kojto 108:34e6b704fe68 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 108:34e6b704fe68 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 108:34e6b704fe68 316 } SCB_Type;
Kojto 108:34e6b704fe68 317
Kojto 108:34e6b704fe68 318 /* SCB CPUID Register Definitions */
Kojto 108:34e6b704fe68 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 108:34e6b704fe68 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 108:34e6b704fe68 321
Kojto 108:34e6b704fe68 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 108:34e6b704fe68 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 108:34e6b704fe68 324
Kojto 108:34e6b704fe68 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 108:34e6b704fe68 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 108:34e6b704fe68 327
Kojto 108:34e6b704fe68 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 108:34e6b704fe68 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 108:34e6b704fe68 330
Kojto 108:34e6b704fe68 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 108:34e6b704fe68 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 108:34e6b704fe68 333
Kojto 108:34e6b704fe68 334 /* SCB Interrupt Control State Register Definitions */
Kojto 108:34e6b704fe68 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 108:34e6b704fe68 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 108:34e6b704fe68 337
Kojto 108:34e6b704fe68 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 108:34e6b704fe68 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 108:34e6b704fe68 340
Kojto 108:34e6b704fe68 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 108:34e6b704fe68 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 108:34e6b704fe68 343
Kojto 108:34e6b704fe68 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 108:34e6b704fe68 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 108:34e6b704fe68 346
Kojto 108:34e6b704fe68 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 108:34e6b704fe68 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 108:34e6b704fe68 349
Kojto 108:34e6b704fe68 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 108:34e6b704fe68 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 108:34e6b704fe68 352
Kojto 108:34e6b704fe68 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 108:34e6b704fe68 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 108:34e6b704fe68 355
Kojto 108:34e6b704fe68 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 108:34e6b704fe68 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 108:34e6b704fe68 358
Kojto 108:34e6b704fe68 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 108:34e6b704fe68 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 108:34e6b704fe68 361
Kojto 108:34e6b704fe68 362 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 108:34e6b704fe68 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 108:34e6b704fe68 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 108:34e6b704fe68 365
Kojto 108:34e6b704fe68 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 108:34e6b704fe68 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 108:34e6b704fe68 368
Kojto 108:34e6b704fe68 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 108:34e6b704fe68 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 108:34e6b704fe68 371
Kojto 108:34e6b704fe68 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 108:34e6b704fe68 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 108:34e6b704fe68 374
Kojto 108:34e6b704fe68 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 108:34e6b704fe68 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 108:34e6b704fe68 377
Kojto 108:34e6b704fe68 378 /* SCB System Control Register Definitions */
Kojto 108:34e6b704fe68 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 108:34e6b704fe68 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 108:34e6b704fe68 381
Kojto 108:34e6b704fe68 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 108:34e6b704fe68 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 108:34e6b704fe68 384
Kojto 108:34e6b704fe68 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 108:34e6b704fe68 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 108:34e6b704fe68 387
Kojto 108:34e6b704fe68 388 /* SCB Configuration Control Register Definitions */
Kojto 108:34e6b704fe68 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 108:34e6b704fe68 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 108:34e6b704fe68 391
Kojto 108:34e6b704fe68 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 108:34e6b704fe68 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 108:34e6b704fe68 394
Kojto 108:34e6b704fe68 395 /* SCB System Handler Control and State Register Definitions */
Kojto 108:34e6b704fe68 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 108:34e6b704fe68 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 108:34e6b704fe68 398
Kojto 108:34e6b704fe68 399 /*@} end of group CMSIS_SCB */
Kojto 108:34e6b704fe68 400
Kojto 108:34e6b704fe68 401
Kojto 108:34e6b704fe68 402 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 108:34e6b704fe68 404 \brief Type definitions for the System Timer Registers.
Kojto 108:34e6b704fe68 405 @{
Kojto 108:34e6b704fe68 406 */
Kojto 108:34e6b704fe68 407
Kojto 108:34e6b704fe68 408 /** \brief Structure type to access the System Timer (SysTick).
Kojto 108:34e6b704fe68 409 */
Kojto 108:34e6b704fe68 410 typedef struct
Kojto 108:34e6b704fe68 411 {
Kojto 108:34e6b704fe68 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 108:34e6b704fe68 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 108:34e6b704fe68 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 108:34e6b704fe68 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 108:34e6b704fe68 416 } SysTick_Type;
Kojto 108:34e6b704fe68 417
Kojto 108:34e6b704fe68 418 /* SysTick Control / Status Register Definitions */
Kojto 108:34e6b704fe68 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 108:34e6b704fe68 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 108:34e6b704fe68 421
Kojto 108:34e6b704fe68 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 108:34e6b704fe68 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 108:34e6b704fe68 424
Kojto 108:34e6b704fe68 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 108:34e6b704fe68 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 108:34e6b704fe68 427
Kojto 108:34e6b704fe68 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 108:34e6b704fe68 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 108:34e6b704fe68 430
Kojto 108:34e6b704fe68 431 /* SysTick Reload Register Definitions */
Kojto 108:34e6b704fe68 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 108:34e6b704fe68 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 108:34e6b704fe68 434
Kojto 108:34e6b704fe68 435 /* SysTick Current Register Definitions */
Kojto 108:34e6b704fe68 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 108:34e6b704fe68 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 108:34e6b704fe68 438
Kojto 108:34e6b704fe68 439 /* SysTick Calibration Register Definitions */
Kojto 108:34e6b704fe68 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 108:34e6b704fe68 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 108:34e6b704fe68 442
Kojto 108:34e6b704fe68 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 108:34e6b704fe68 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 108:34e6b704fe68 445
Kojto 108:34e6b704fe68 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 108:34e6b704fe68 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 108:34e6b704fe68 448
Kojto 108:34e6b704fe68 449 /*@} end of group CMSIS_SysTick */
Kojto 108:34e6b704fe68 450
Kojto 108:34e6b704fe68 451
Kojto 108:34e6b704fe68 452 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 108:34e6b704fe68 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 108:34e6b704fe68 455 are only accessible over DAP and not via processor. Therefore
Kojto 108:34e6b704fe68 456 they are not covered by the Cortex-M0 header file.
Kojto 108:34e6b704fe68 457 @{
Kojto 108:34e6b704fe68 458 */
Kojto 108:34e6b704fe68 459 /*@} end of group CMSIS_CoreDebug */
Kojto 108:34e6b704fe68 460
Kojto 108:34e6b704fe68 461
Kojto 108:34e6b704fe68 462 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 463 \defgroup CMSIS_core_base Core Definitions
Kojto 108:34e6b704fe68 464 \brief Definitions for base addresses, unions, and structures.
Kojto 108:34e6b704fe68 465 @{
Kojto 108:34e6b704fe68 466 */
Kojto 108:34e6b704fe68 467
Kojto 108:34e6b704fe68 468 /* Memory mapping of Cortex-M0 Hardware */
Kojto 108:34e6b704fe68 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 108:34e6b704fe68 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 108:34e6b704fe68 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 108:34e6b704fe68 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 108:34e6b704fe68 473
Kojto 108:34e6b704fe68 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 108:34e6b704fe68 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 108:34e6b704fe68 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 108:34e6b704fe68 477
Kojto 108:34e6b704fe68 478
Kojto 108:34e6b704fe68 479 /*@} */
Kojto 108:34e6b704fe68 480
Kojto 108:34e6b704fe68 481
Kojto 108:34e6b704fe68 482
Kojto 108:34e6b704fe68 483 /*******************************************************************************
Kojto 108:34e6b704fe68 484 * Hardware Abstraction Layer
Kojto 108:34e6b704fe68 485 Core Function Interface contains:
Kojto 108:34e6b704fe68 486 - Core NVIC Functions
Kojto 108:34e6b704fe68 487 - Core SysTick Functions
Kojto 108:34e6b704fe68 488 - Core Register Access Functions
Kojto 108:34e6b704fe68 489 ******************************************************************************/
Kojto 108:34e6b704fe68 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 108:34e6b704fe68 491 */
Kojto 108:34e6b704fe68 492
Kojto 108:34e6b704fe68 493
Kojto 108:34e6b704fe68 494
Kojto 108:34e6b704fe68 495 /* ########################## NVIC functions #################################### */
Kojto 108:34e6b704fe68 496 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 108:34e6b704fe68 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 108:34e6b704fe68 498 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 108:34e6b704fe68 499 @{
Kojto 108:34e6b704fe68 500 */
Kojto 108:34e6b704fe68 501
Kojto 108:34e6b704fe68 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 108:34e6b704fe68 503 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 108:34e6b704fe68 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 108:34e6b704fe68 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 108:34e6b704fe68 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 108:34e6b704fe68 507
Kojto 108:34e6b704fe68 508
Kojto 108:34e6b704fe68 509 /** \brief Enable External Interrupt
Kojto 108:34e6b704fe68 510
Kojto 108:34e6b704fe68 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 108:34e6b704fe68 512
Kojto 108:34e6b704fe68 513 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 514 */
Kojto 108:34e6b704fe68 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 516 {
Kojto 108:34e6b704fe68 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 108:34e6b704fe68 518 }
Kojto 108:34e6b704fe68 519
Kojto 108:34e6b704fe68 520
Kojto 108:34e6b704fe68 521 /** \brief Disable External Interrupt
Kojto 108:34e6b704fe68 522
Kojto 108:34e6b704fe68 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 108:34e6b704fe68 524
Kojto 108:34e6b704fe68 525 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 526 */
Kojto 108:34e6b704fe68 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 528 {
Kojto 108:34e6b704fe68 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 108:34e6b704fe68 530 }
Kojto 108:34e6b704fe68 531
Kojto 108:34e6b704fe68 532
Kojto 108:34e6b704fe68 533 /** \brief Get Pending Interrupt
Kojto 108:34e6b704fe68 534
Kojto 108:34e6b704fe68 535 The function reads the pending register in the NVIC and returns the pending bit
Kojto 108:34e6b704fe68 536 for the specified interrupt.
Kojto 108:34e6b704fe68 537
Kojto 108:34e6b704fe68 538 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 539
Kojto 108:34e6b704fe68 540 \return 0 Interrupt status is not pending.
Kojto 108:34e6b704fe68 541 \return 1 Interrupt status is pending.
Kojto 108:34e6b704fe68 542 */
Kojto 108:34e6b704fe68 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 544 {
Kojto 108:34e6b704fe68 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 108:34e6b704fe68 546 }
Kojto 108:34e6b704fe68 547
Kojto 108:34e6b704fe68 548
Kojto 108:34e6b704fe68 549 /** \brief Set Pending Interrupt
Kojto 108:34e6b704fe68 550
Kojto 108:34e6b704fe68 551 The function sets the pending bit of an external interrupt.
Kojto 108:34e6b704fe68 552
Kojto 108:34e6b704fe68 553 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 554 */
Kojto 108:34e6b704fe68 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 556 {
Kojto 108:34e6b704fe68 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 108:34e6b704fe68 558 }
Kojto 108:34e6b704fe68 559
Kojto 108:34e6b704fe68 560
Kojto 108:34e6b704fe68 561 /** \brief Clear Pending Interrupt
Kojto 108:34e6b704fe68 562
Kojto 108:34e6b704fe68 563 The function clears the pending bit of an external interrupt.
Kojto 108:34e6b704fe68 564
Kojto 108:34e6b704fe68 565 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 566 */
Kojto 108:34e6b704fe68 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 568 {
Kojto 108:34e6b704fe68 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 108:34e6b704fe68 570 }
Kojto 108:34e6b704fe68 571
Kojto 108:34e6b704fe68 572
Kojto 108:34e6b704fe68 573 /** \brief Set Interrupt Priority
Kojto 108:34e6b704fe68 574
Kojto 108:34e6b704fe68 575 The function sets the priority of an interrupt.
Kojto 108:34e6b704fe68 576
Kojto 108:34e6b704fe68 577 \note The priority cannot be set for every core interrupt.
Kojto 108:34e6b704fe68 578
Kojto 108:34e6b704fe68 579 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 580 \param [in] priority Priority to set.
Kojto 108:34e6b704fe68 581 */
Kojto 108:34e6b704fe68 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 108:34e6b704fe68 583 {
Kojto 108:34e6b704fe68 584 if(IRQn < 0) {
Kojto 108:34e6b704fe68 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 108:34e6b704fe68 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 108:34e6b704fe68 587 else {
Kojto 108:34e6b704fe68 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 108:34e6b704fe68 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 108:34e6b704fe68 590 }
Kojto 108:34e6b704fe68 591
Kojto 108:34e6b704fe68 592
Kojto 108:34e6b704fe68 593 /** \brief Get Interrupt Priority
Kojto 108:34e6b704fe68 594
Kojto 108:34e6b704fe68 595 The function reads the priority of an interrupt. The interrupt
Kojto 108:34e6b704fe68 596 number can be positive to specify an external (device specific)
Kojto 108:34e6b704fe68 597 interrupt, or negative to specify an internal (core) interrupt.
Kojto 108:34e6b704fe68 598
Kojto 108:34e6b704fe68 599
Kojto 108:34e6b704fe68 600 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 601 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 108:34e6b704fe68 602 priority bits of the microcontroller.
Kojto 108:34e6b704fe68 603 */
Kojto 108:34e6b704fe68 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 605 {
Kojto 108:34e6b704fe68 606
Kojto 108:34e6b704fe68 607 if(IRQn < 0) {
Kojto 108:34e6b704fe68 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 108:34e6b704fe68 609 else {
Kojto 108:34e6b704fe68 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 108:34e6b704fe68 611 }
Kojto 108:34e6b704fe68 612
Kojto 108:34e6b704fe68 613
Kojto 108:34e6b704fe68 614 /** \brief System Reset
Kojto 108:34e6b704fe68 615
Kojto 108:34e6b704fe68 616 The function initiates a system reset request to reset the MCU.
Kojto 108:34e6b704fe68 617 */
Kojto 108:34e6b704fe68 618 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 108:34e6b704fe68 619 {
Kojto 108:34e6b704fe68 620 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 108:34e6b704fe68 621 buffered write are completed before reset */
Kojto 108:34e6b704fe68 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 108:34e6b704fe68 623 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 108:34e6b704fe68 624 __DSB(); /* Ensure completion of memory access */
Kojto 108:34e6b704fe68 625 while(1); /* wait until reset */
Kojto 108:34e6b704fe68 626 }
Kojto 108:34e6b704fe68 627
Kojto 108:34e6b704fe68 628 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 108:34e6b704fe68 629
Kojto 108:34e6b704fe68 630
Kojto 108:34e6b704fe68 631
Kojto 108:34e6b704fe68 632 /* ################################## SysTick function ############################################ */
Kojto 108:34e6b704fe68 633 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 108:34e6b704fe68 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 108:34e6b704fe68 635 \brief Functions that configure the System.
Kojto 108:34e6b704fe68 636 @{
Kojto 108:34e6b704fe68 637 */
Kojto 108:34e6b704fe68 638
Kojto 108:34e6b704fe68 639 #if (__Vendor_SysTickConfig == 0)
Kojto 108:34e6b704fe68 640
Kojto 108:34e6b704fe68 641 /** \brief System Tick Configuration
Kojto 108:34e6b704fe68 642
Kojto 108:34e6b704fe68 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 108:34e6b704fe68 644 Counter is in free running mode to generate periodic interrupts.
Kojto 108:34e6b704fe68 645
Kojto 108:34e6b704fe68 646 \param [in] ticks Number of ticks between two interrupts.
Kojto 108:34e6b704fe68 647
Kojto 108:34e6b704fe68 648 \return 0 Function succeeded.
Kojto 108:34e6b704fe68 649 \return 1 Function failed.
Kojto 108:34e6b704fe68 650
Kojto 108:34e6b704fe68 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 108:34e6b704fe68 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 108:34e6b704fe68 653 must contain a vendor-specific implementation of this function.
Kojto 108:34e6b704fe68 654
Kojto 108:34e6b704fe68 655 */
Kojto 108:34e6b704fe68 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 108:34e6b704fe68 657 {
Kojto 108:34e6b704fe68 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 108:34e6b704fe68 659
Kojto 108:34e6b704fe68 660 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 108:34e6b704fe68 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 108:34e6b704fe68 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 108:34e6b704fe68 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 108:34e6b704fe68 664 SysTick_CTRL_TICKINT_Msk |
Kojto 108:34e6b704fe68 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 108:34e6b704fe68 666 return (0); /* Function successful */
Kojto 108:34e6b704fe68 667 }
Kojto 108:34e6b704fe68 668
Kojto 108:34e6b704fe68 669 #endif
Kojto 108:34e6b704fe68 670
Kojto 108:34e6b704fe68 671 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 108:34e6b704fe68 672
Kojto 108:34e6b704fe68 673
Kojto 108:34e6b704fe68 674
Kojto 108:34e6b704fe68 675
Kojto 108:34e6b704fe68 676 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 108:34e6b704fe68 677
Kojto 108:34e6b704fe68 678 #endif /* __CMSIS_GENERIC */
Kojto 108:34e6b704fe68 679
Kojto 108:34e6b704fe68 680 #ifdef __cplusplus
Kojto 108:34e6b704fe68 681 }
Kojto 108:34e6b704fe68 682 #endif