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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_MPS2_BEID/core_caFunc.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Child:
115:87f2f5183dfb
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**************************************************************************//**
Kojto 108:34e6b704fe68 2 * @file core_caFunc.h
Kojto 108:34e6b704fe68 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 108:34e6b704fe68 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 108:34e6b704fe68 6 *
Kojto 108:34e6b704fe68 7 * @note
Kojto 108:34e6b704fe68 8 *
Kojto 108:34e6b704fe68 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 108:34e6b704fe68 11
Kojto 108:34e6b704fe68 12 All rights reserved.
Kojto 108:34e6b704fe68 13 Redistribution and use in source and binary forms, with or without
Kojto 108:34e6b704fe68 14 modification, are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 15 - Redistributions of source code must retain the above copyright
Kojto 108:34e6b704fe68 16 notice, this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 17 - Redistributions in binary form must reproduce the above copyright
Kojto 108:34e6b704fe68 18 notice, this list of conditions and the following disclaimer in the
Kojto 108:34e6b704fe68 19 documentation and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 108:34e6b704fe68 21 to endorse or promote products derived from this software without
Kojto 108:34e6b704fe68 22 specific prior written permission.
Kojto 108:34e6b704fe68 23 *
Kojto 108:34e6b704fe68 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 108:34e6b704fe68 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 108:34e6b704fe68 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 108:34e6b704fe68 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 108:34e6b704fe68 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 108:34e6b704fe68 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 108:34e6b704fe68 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 108:34e6b704fe68 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 108:34e6b704fe68 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 35 ---------------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 36
Kojto 108:34e6b704fe68 37
Kojto 108:34e6b704fe68 38 #ifndef __CORE_CAFUNC_H__
Kojto 108:34e6b704fe68 39 #define __CORE_CAFUNC_H__
Kojto 108:34e6b704fe68 40
Kojto 108:34e6b704fe68 41
Kojto 108:34e6b704fe68 42 /* ########################### Core Function Access ########################### */
Kojto 108:34e6b704fe68 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 108:34e6b704fe68 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 108:34e6b704fe68 45 @{
Kojto 108:34e6b704fe68 46 */
Kojto 108:34e6b704fe68 47
Kojto 108:34e6b704fe68 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 108:34e6b704fe68 49 /* ARM armcc specific functions */
Kojto 108:34e6b704fe68 50
Kojto 108:34e6b704fe68 51 #if (__ARMCC_VERSION < 400677)
Kojto 108:34e6b704fe68 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 108:34e6b704fe68 53 #endif
Kojto 108:34e6b704fe68 54
Kojto 108:34e6b704fe68 55 #define MODE_USR 0x10
Kojto 108:34e6b704fe68 56 #define MODE_FIQ 0x11
Kojto 108:34e6b704fe68 57 #define MODE_IRQ 0x12
Kojto 108:34e6b704fe68 58 #define MODE_SVC 0x13
Kojto 108:34e6b704fe68 59 #define MODE_MON 0x16
Kojto 108:34e6b704fe68 60 #define MODE_ABT 0x17
Kojto 108:34e6b704fe68 61 #define MODE_HYP 0x1A
Kojto 108:34e6b704fe68 62 #define MODE_UND 0x1B
Kojto 108:34e6b704fe68 63 #define MODE_SYS 0x1F
Kojto 108:34e6b704fe68 64
Kojto 108:34e6b704fe68 65 /** \brief Get APSR Register
Kojto 108:34e6b704fe68 66
Kojto 108:34e6b704fe68 67 This function returns the content of the APSR Register.
Kojto 108:34e6b704fe68 68
Kojto 108:34e6b704fe68 69 \return APSR Register value
Kojto 108:34e6b704fe68 70 */
Kojto 108:34e6b704fe68 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 108:34e6b704fe68 72 {
Kojto 108:34e6b704fe68 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 74 return(__regAPSR);
Kojto 108:34e6b704fe68 75 }
Kojto 108:34e6b704fe68 76
Kojto 108:34e6b704fe68 77
Kojto 108:34e6b704fe68 78 /** \brief Get CPSR Register
Kojto 108:34e6b704fe68 79
Kojto 108:34e6b704fe68 80 This function returns the content of the CPSR Register.
Kojto 108:34e6b704fe68 81
Kojto 108:34e6b704fe68 82 \return CPSR Register value
Kojto 108:34e6b704fe68 83 */
Kojto 108:34e6b704fe68 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 108:34e6b704fe68 85 {
Kojto 108:34e6b704fe68 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 108:34e6b704fe68 87 return(__regCPSR);
Kojto 108:34e6b704fe68 88 }
Kojto 108:34e6b704fe68 89
Kojto 108:34e6b704fe68 90 /** \brief Set Stack Pointer
Kojto 108:34e6b704fe68 91
Kojto 108:34e6b704fe68 92 This function assigns the given value to the current stack pointer.
Kojto 108:34e6b704fe68 93
Kojto 108:34e6b704fe68 94 \param [in] topOfStack Stack Pointer value to set
Kojto 108:34e6b704fe68 95 */
Kojto 108:34e6b704fe68 96 register uint32_t __regSP __ASM("sp");
Kojto 108:34e6b704fe68 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 108:34e6b704fe68 98 {
Kojto 108:34e6b704fe68 99 __regSP = topOfStack;
Kojto 108:34e6b704fe68 100 }
Kojto 108:34e6b704fe68 101
Kojto 108:34e6b704fe68 102
Kojto 108:34e6b704fe68 103 /** \brief Get link register
Kojto 108:34e6b704fe68 104
Kojto 108:34e6b704fe68 105 This function returns the value of the link register
Kojto 108:34e6b704fe68 106
Kojto 108:34e6b704fe68 107 \return Value of link register
Kojto 108:34e6b704fe68 108 */
Kojto 108:34e6b704fe68 109 register uint32_t __reglr __ASM("lr");
Kojto 108:34e6b704fe68 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 108:34e6b704fe68 111 {
Kojto 108:34e6b704fe68 112 return(__reglr);
Kojto 108:34e6b704fe68 113 }
Kojto 108:34e6b704fe68 114
Kojto 108:34e6b704fe68 115 /** \brief Set link register
Kojto 108:34e6b704fe68 116
Kojto 108:34e6b704fe68 117 This function sets the value of the link register
Kojto 108:34e6b704fe68 118
Kojto 108:34e6b704fe68 119 \param [in] lr LR value to set
Kojto 108:34e6b704fe68 120 */
Kojto 108:34e6b704fe68 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 108:34e6b704fe68 122 {
Kojto 108:34e6b704fe68 123 __reglr = lr;
Kojto 108:34e6b704fe68 124 }
Kojto 108:34e6b704fe68 125
Kojto 108:34e6b704fe68 126 /** \brief Set Process Stack Pointer
Kojto 108:34e6b704fe68 127
Kojto 108:34e6b704fe68 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 108:34e6b704fe68 129
Kojto 108:34e6b704fe68 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 108:34e6b704fe68 131 */
Kojto 108:34e6b704fe68 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 133 {
Kojto 108:34e6b704fe68 134 ARM
Kojto 108:34e6b704fe68 135 PRESERVE8
Kojto 108:34e6b704fe68 136
Kojto 108:34e6b704fe68 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 108:34e6b704fe68 138 MRS R1, CPSR
Kojto 108:34e6b704fe68 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 108:34e6b704fe68 140 MOV SP, R0
Kojto 108:34e6b704fe68 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 108:34e6b704fe68 142 ISB
Kojto 108:34e6b704fe68 143 BX LR
Kojto 108:34e6b704fe68 144
Kojto 108:34e6b704fe68 145 }
Kojto 108:34e6b704fe68 146
Kojto 108:34e6b704fe68 147 /** \brief Set User Mode
Kojto 108:34e6b704fe68 148
Kojto 108:34e6b704fe68 149 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 150 */
Kojto 108:34e6b704fe68 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 152 {
Kojto 108:34e6b704fe68 153 ARM
Kojto 108:34e6b704fe68 154
Kojto 108:34e6b704fe68 155 CPS #MODE_USR
Kojto 108:34e6b704fe68 156 BX LR
Kojto 108:34e6b704fe68 157 }
Kojto 108:34e6b704fe68 158
Kojto 108:34e6b704fe68 159
Kojto 108:34e6b704fe68 160 /** \brief Enable FIQ
Kojto 108:34e6b704fe68 161
Kojto 108:34e6b704fe68 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 108:34e6b704fe68 163 Can only be executed in Privileged modes.
Kojto 108:34e6b704fe68 164 */
Kojto 108:34e6b704fe68 165 #define __enable_fault_irq __enable_fiq
Kojto 108:34e6b704fe68 166
Kojto 108:34e6b704fe68 167
Kojto 108:34e6b704fe68 168 /** \brief Disable FIQ
Kojto 108:34e6b704fe68 169
Kojto 108:34e6b704fe68 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 108:34e6b704fe68 171 Can only be executed in Privileged modes.
Kojto 108:34e6b704fe68 172 */
Kojto 108:34e6b704fe68 173 #define __disable_fault_irq __disable_fiq
Kojto 108:34e6b704fe68 174
Kojto 108:34e6b704fe68 175
Kojto 108:34e6b704fe68 176 /** \brief Get FPSCR
Kojto 108:34e6b704fe68 177
Kojto 108:34e6b704fe68 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 108:34e6b704fe68 179
Kojto 108:34e6b704fe68 180 \return Floating Point Status/Control register value
Kojto 108:34e6b704fe68 181 */
Kojto 108:34e6b704fe68 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 108:34e6b704fe68 183 {
Kojto 108:34e6b704fe68 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 108:34e6b704fe68 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 108:34e6b704fe68 186 return(__regfpscr);
Kojto 108:34e6b704fe68 187 #else
Kojto 108:34e6b704fe68 188 return(0);
Kojto 108:34e6b704fe68 189 #endif
Kojto 108:34e6b704fe68 190 }
Kojto 108:34e6b704fe68 191
Kojto 108:34e6b704fe68 192
Kojto 108:34e6b704fe68 193 /** \brief Set FPSCR
Kojto 108:34e6b704fe68 194
Kojto 108:34e6b704fe68 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 108:34e6b704fe68 196
Kojto 108:34e6b704fe68 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 108:34e6b704fe68 198 */
Kojto 108:34e6b704fe68 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 108:34e6b704fe68 200 {
Kojto 108:34e6b704fe68 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 108:34e6b704fe68 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 108:34e6b704fe68 203 __regfpscr = (fpscr);
Kojto 108:34e6b704fe68 204 #endif
Kojto 108:34e6b704fe68 205 }
Kojto 108:34e6b704fe68 206
Kojto 108:34e6b704fe68 207 /** \brief Get FPEXC
Kojto 108:34e6b704fe68 208
Kojto 108:34e6b704fe68 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 108:34e6b704fe68 210
Kojto 108:34e6b704fe68 211 \return Floating Point Exception Control register value
Kojto 108:34e6b704fe68 212 */
Kojto 108:34e6b704fe68 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 108:34e6b704fe68 214 {
Kojto 108:34e6b704fe68 215 #if (__FPU_PRESENT == 1)
Kojto 108:34e6b704fe68 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 108:34e6b704fe68 217 return(__regfpexc);
Kojto 108:34e6b704fe68 218 #else
Kojto 108:34e6b704fe68 219 return(0);
Kojto 108:34e6b704fe68 220 #endif
Kojto 108:34e6b704fe68 221 }
Kojto 108:34e6b704fe68 222
Kojto 108:34e6b704fe68 223
Kojto 108:34e6b704fe68 224 /** \brief Set FPEXC
Kojto 108:34e6b704fe68 225
Kojto 108:34e6b704fe68 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 108:34e6b704fe68 227
Kojto 108:34e6b704fe68 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 108:34e6b704fe68 229 */
Kojto 108:34e6b704fe68 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 108:34e6b704fe68 231 {
Kojto 108:34e6b704fe68 232 #if (__FPU_PRESENT == 1)
Kojto 108:34e6b704fe68 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 108:34e6b704fe68 234 __regfpexc = (fpexc);
Kojto 108:34e6b704fe68 235 #endif
Kojto 108:34e6b704fe68 236 }
Kojto 108:34e6b704fe68 237
Kojto 108:34e6b704fe68 238 /** \brief Get CPACR
Kojto 108:34e6b704fe68 239
Kojto 108:34e6b704fe68 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 108:34e6b704fe68 241
Kojto 108:34e6b704fe68 242 \return Coprocessor Access Control register value
Kojto 108:34e6b704fe68 243 */
Kojto 108:34e6b704fe68 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 108:34e6b704fe68 245 {
Kojto 108:34e6b704fe68 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 108:34e6b704fe68 247 return __regCPACR;
Kojto 108:34e6b704fe68 248 }
Kojto 108:34e6b704fe68 249
Kojto 108:34e6b704fe68 250 /** \brief Set CPACR
Kojto 108:34e6b704fe68 251
Kojto 108:34e6b704fe68 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 108:34e6b704fe68 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 108:34e6b704fe68 255 */
Kojto 108:34e6b704fe68 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 108:34e6b704fe68 257 {
Kojto 108:34e6b704fe68 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 108:34e6b704fe68 259 __regCPACR = cpacr;
Kojto 108:34e6b704fe68 260 __ISB();
Kojto 108:34e6b704fe68 261 }
Kojto 108:34e6b704fe68 262
Kojto 108:34e6b704fe68 263 /** \brief Get CBAR
Kojto 108:34e6b704fe68 264
Kojto 108:34e6b704fe68 265 This function returns the value of the Configuration Base Address register.
Kojto 108:34e6b704fe68 266
Kojto 108:34e6b704fe68 267 \return Configuration Base Address register value
Kojto 108:34e6b704fe68 268 */
Kojto 108:34e6b704fe68 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 108:34e6b704fe68 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 108:34e6b704fe68 271 return(__regCBAR);
Kojto 108:34e6b704fe68 272 }
Kojto 108:34e6b704fe68 273
Kojto 108:34e6b704fe68 274 /** \brief Get TTBR0
Kojto 108:34e6b704fe68 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 108:34e6b704fe68 277
Kojto 108:34e6b704fe68 278 \return Translation Table Base Register 0 value
Kojto 108:34e6b704fe68 279 */
Kojto 108:34e6b704fe68 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 108:34e6b704fe68 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 108:34e6b704fe68 282 return(__regTTBR0);
Kojto 108:34e6b704fe68 283 }
Kojto 108:34e6b704fe68 284
Kojto 108:34e6b704fe68 285 /** \brief Set TTBR0
Kojto 108:34e6b704fe68 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 108:34e6b704fe68 288
Kojto 108:34e6b704fe68 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 108:34e6b704fe68 290 */
Kojto 108:34e6b704fe68 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 108:34e6b704fe68 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 108:34e6b704fe68 293 __regTTBR0 = ttbr0;
Kojto 108:34e6b704fe68 294 __ISB();
Kojto 108:34e6b704fe68 295 }
Kojto 108:34e6b704fe68 296
Kojto 108:34e6b704fe68 297 /** \brief Get DACR
Kojto 108:34e6b704fe68 298
Kojto 108:34e6b704fe68 299 This function returns the value of the Domain Access Control Register.
Kojto 108:34e6b704fe68 300
Kojto 108:34e6b704fe68 301 \return Domain Access Control Register value
Kojto 108:34e6b704fe68 302 */
Kojto 108:34e6b704fe68 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 108:34e6b704fe68 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 108:34e6b704fe68 305 return(__regDACR);
Kojto 108:34e6b704fe68 306 }
Kojto 108:34e6b704fe68 307
Kojto 108:34e6b704fe68 308 /** \brief Set DACR
Kojto 108:34e6b704fe68 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 108:34e6b704fe68 311
Kojto 108:34e6b704fe68 312 \param [in] dacr Domain Access Control Register value to set
Kojto 108:34e6b704fe68 313 */
Kojto 108:34e6b704fe68 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 108:34e6b704fe68 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 108:34e6b704fe68 316 __regDACR = dacr;
Kojto 108:34e6b704fe68 317 __ISB();
Kojto 108:34e6b704fe68 318 }
Kojto 108:34e6b704fe68 319
Kojto 108:34e6b704fe68 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 108:34e6b704fe68 321
Kojto 108:34e6b704fe68 322 /** \brief Set SCTLR
Kojto 108:34e6b704fe68 323
Kojto 108:34e6b704fe68 324 This function assigns the given value to the System Control Register.
Kojto 108:34e6b704fe68 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 108:34e6b704fe68 327 */
Kojto 108:34e6b704fe68 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 108:34e6b704fe68 329 {
Kojto 108:34e6b704fe68 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 108:34e6b704fe68 331 __regSCTLR = sctlr;
Kojto 108:34e6b704fe68 332 }
Kojto 108:34e6b704fe68 333
Kojto 108:34e6b704fe68 334 /** \brief Get SCTLR
Kojto 108:34e6b704fe68 335
Kojto 108:34e6b704fe68 336 This function returns the value of the System Control Register.
Kojto 108:34e6b704fe68 337
Kojto 108:34e6b704fe68 338 \return System Control Register value
Kojto 108:34e6b704fe68 339 */
Kojto 108:34e6b704fe68 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 108:34e6b704fe68 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 108:34e6b704fe68 342 return(__regSCTLR);
Kojto 108:34e6b704fe68 343 }
Kojto 108:34e6b704fe68 344
Kojto 108:34e6b704fe68 345 /** \brief Enable Caches
Kojto 108:34e6b704fe68 346
Kojto 108:34e6b704fe68 347 Enable Caches
Kojto 108:34e6b704fe68 348 */
Kojto 108:34e6b704fe68 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 108:34e6b704fe68 350 // Set I bit 12 to enable I Cache
Kojto 108:34e6b704fe68 351 // Set C bit 2 to enable D Cache
Kojto 108:34e6b704fe68 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 108:34e6b704fe68 353 }
Kojto 108:34e6b704fe68 354
Kojto 108:34e6b704fe68 355 /** \brief Disable Caches
Kojto 108:34e6b704fe68 356
Kojto 108:34e6b704fe68 357 Disable Caches
Kojto 108:34e6b704fe68 358 */
Kojto 108:34e6b704fe68 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 108:34e6b704fe68 360 // Clear I bit 12 to disable I Cache
Kojto 108:34e6b704fe68 361 // Clear C bit 2 to disable D Cache
Kojto 108:34e6b704fe68 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 108:34e6b704fe68 363 __ISB();
Kojto 108:34e6b704fe68 364 }
Kojto 108:34e6b704fe68 365
Kojto 108:34e6b704fe68 366 /** \brief Enable BTAC
Kojto 108:34e6b704fe68 367
Kojto 108:34e6b704fe68 368 Enable BTAC
Kojto 108:34e6b704fe68 369 */
Kojto 108:34e6b704fe68 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 108:34e6b704fe68 371 // Set Z bit 11 to enable branch prediction
Kojto 108:34e6b704fe68 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 108:34e6b704fe68 373 __ISB();
Kojto 108:34e6b704fe68 374 }
Kojto 108:34e6b704fe68 375
Kojto 108:34e6b704fe68 376 /** \brief Disable BTAC
Kojto 108:34e6b704fe68 377
Kojto 108:34e6b704fe68 378 Disable BTAC
Kojto 108:34e6b704fe68 379 */
Kojto 108:34e6b704fe68 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 108:34e6b704fe68 381 // Clear Z bit 11 to disable branch prediction
Kojto 108:34e6b704fe68 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 108:34e6b704fe68 383 }
Kojto 108:34e6b704fe68 384
Kojto 108:34e6b704fe68 385
Kojto 108:34e6b704fe68 386 /** \brief Enable MMU
Kojto 108:34e6b704fe68 387
Kojto 108:34e6b704fe68 388 Enable MMU
Kojto 108:34e6b704fe68 389 */
Kojto 108:34e6b704fe68 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 108:34e6b704fe68 391 // Set M bit 0 to enable the MMU
Kojto 108:34e6b704fe68 392 // Set AFE bit to enable simplified access permissions model
Kojto 108:34e6b704fe68 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 108:34e6b704fe68 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 108:34e6b704fe68 395 __ISB();
Kojto 108:34e6b704fe68 396 }
Kojto 108:34e6b704fe68 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 108:34e6b704fe68 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 108:34e6b704fe68 401 */
Kojto 108:34e6b704fe68 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 108:34e6b704fe68 403 // Clear M bit 0 to disable the MMU
Kojto 108:34e6b704fe68 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 108:34e6b704fe68 405 __ISB();
Kojto 108:34e6b704fe68 406 }
Kojto 108:34e6b704fe68 407
Kojto 108:34e6b704fe68 408 /******************************** TLB maintenance operations ************************************************/
Kojto 108:34e6b704fe68 409 /** \brief Invalidate the whole tlb
Kojto 108:34e6b704fe68 410
Kojto 108:34e6b704fe68 411 TLBIALL. Invalidate the whole tlb
Kojto 108:34e6b704fe68 412 */
Kojto 108:34e6b704fe68 413
Kojto 108:34e6b704fe68 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 108:34e6b704fe68 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 108:34e6b704fe68 416 __TLBIALL = 0;
Kojto 108:34e6b704fe68 417 __DSB();
Kojto 108:34e6b704fe68 418 __ISB();
Kojto 108:34e6b704fe68 419 }
Kojto 108:34e6b704fe68 420
Kojto 108:34e6b704fe68 421 /******************************** BTB maintenance operations ************************************************/
Kojto 108:34e6b704fe68 422 /** \brief Invalidate entire branch predictor array
Kojto 108:34e6b704fe68 423
Kojto 108:34e6b704fe68 424 BPIALL. Branch Predictor Invalidate All.
Kojto 108:34e6b704fe68 425 */
Kojto 108:34e6b704fe68 426
Kojto 108:34e6b704fe68 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 108:34e6b704fe68 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 108:34e6b704fe68 429 __BPIALL = 0;
Kojto 108:34e6b704fe68 430 __DSB(); //ensure completion of the invalidation
Kojto 108:34e6b704fe68 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 108:34e6b704fe68 432 }
Kojto 108:34e6b704fe68 433
Kojto 108:34e6b704fe68 434
Kojto 108:34e6b704fe68 435 /******************************** L1 cache operations ******************************************************/
Kojto 108:34e6b704fe68 436
Kojto 108:34e6b704fe68 437 /** \brief Invalidate the whole I$
Kojto 108:34e6b704fe68 438
Kojto 108:34e6b704fe68 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 108:34e6b704fe68 440 */
Kojto 108:34e6b704fe68 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 108:34e6b704fe68 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 108:34e6b704fe68 443 __ICIALLU = 0;
Kojto 108:34e6b704fe68 444 __DSB(); //ensure completion of the invalidation
Kojto 108:34e6b704fe68 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 108:34e6b704fe68 446 }
Kojto 108:34e6b704fe68 447
Kojto 108:34e6b704fe68 448 /** \brief Clean D$ by MVA
Kojto 108:34e6b704fe68 449
Kojto 108:34e6b704fe68 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 108:34e6b704fe68 451 */
Kojto 108:34e6b704fe68 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 108:34e6b704fe68 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 108:34e6b704fe68 454 __DCCMVAC = (uint32_t)va;
Kojto 108:34e6b704fe68 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 108:34e6b704fe68 456 }
Kojto 108:34e6b704fe68 457
Kojto 108:34e6b704fe68 458 /** \brief Invalidate D$ by MVA
Kojto 108:34e6b704fe68 459
Kojto 108:34e6b704fe68 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 108:34e6b704fe68 461 */
Kojto 108:34e6b704fe68 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 108:34e6b704fe68 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 108:34e6b704fe68 464 __DCIMVAC = (uint32_t)va;
Kojto 108:34e6b704fe68 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 108:34e6b704fe68 466 }
Kojto 108:34e6b704fe68 467
Kojto 108:34e6b704fe68 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 108:34e6b704fe68 469
Kojto 108:34e6b704fe68 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 108:34e6b704fe68 471 */
Kojto 108:34e6b704fe68 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 108:34e6b704fe68 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 108:34e6b704fe68 474 __DCCIMVAC = (uint32_t)va;
Kojto 108:34e6b704fe68 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 108:34e6b704fe68 476 }
Kojto 108:34e6b704fe68 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 108:34e6b704fe68 481 */
Kojto 108:34e6b704fe68 482 #pragma push
Kojto 108:34e6b704fe68 483 #pragma arm
Kojto 108:34e6b704fe68 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 108:34e6b704fe68 485 ARM
Kojto 108:34e6b704fe68 486
Kojto 108:34e6b704fe68 487 PUSH {R4-R11}
Kojto 108:34e6b704fe68 488
Kojto 108:34e6b704fe68 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 108:34e6b704fe68 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 108:34e6b704fe68 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 108:34e6b704fe68 492 BEQ Finished // If 0, no need to clean
Kojto 108:34e6b704fe68 493
Kojto 108:34e6b704fe68 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 108:34e6b704fe68 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 108:34e6b704fe68 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 108:34e6b704fe68 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 108:34e6b704fe68 498 CMP R1, #2
Kojto 108:34e6b704fe68 499 BLT Skip // No cache or only instruction cache at this level
Kojto 108:34e6b704fe68 500
Kojto 108:34e6b704fe68 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 108:34e6b704fe68 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 108:34e6b704fe68 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 108:34e6b704fe68 504 AND R2, R1, #7 // Extract the line length field
Kojto 108:34e6b704fe68 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 108:34e6b704fe68 506 LDR R4, =0x3FF
Kojto 108:34e6b704fe68 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 108:34e6b704fe68 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 108:34e6b704fe68 509 LDR R7, =0x7FFF
Kojto 108:34e6b704fe68 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 108:34e6b704fe68 511
Kojto 108:34e6b704fe68 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 108:34e6b704fe68 513
Kojto 108:34e6b704fe68 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 108:34e6b704fe68 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 108:34e6b704fe68 516 CMP R0, #0
Kojto 108:34e6b704fe68 517 BNE Dccsw
Kojto 108:34e6b704fe68 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 108:34e6b704fe68 519 B cont
Kojto 108:34e6b704fe68 520 Dccsw CMP R0, #1
Kojto 108:34e6b704fe68 521 BNE Dccisw
Kojto 108:34e6b704fe68 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 108:34e6b704fe68 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 108:34e6b704fe68 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 108:34e6b704fe68 526 BGE Loop3
Kojto 108:34e6b704fe68 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 108:34e6b704fe68 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 108:34e6b704fe68 530 CMP R3, R10
Kojto 108:34e6b704fe68 531 BGT Loop1
Kojto 108:34e6b704fe68 532
Kojto 108:34e6b704fe68 533 Finished
Kojto 108:34e6b704fe68 534 DSB
Kojto 108:34e6b704fe68 535 POP {R4-R11}
Kojto 108:34e6b704fe68 536 BX lr
Kojto 108:34e6b704fe68 537
Kojto 108:34e6b704fe68 538 }
Kojto 108:34e6b704fe68 539 #pragma pop
Kojto 108:34e6b704fe68 540
Kojto 108:34e6b704fe68 541
Kojto 108:34e6b704fe68 542 /** \brief Invalidate the whole D$
Kojto 108:34e6b704fe68 543
Kojto 108:34e6b704fe68 544 DCISW. Invalidate by Set/Way
Kojto 108:34e6b704fe68 545 */
Kojto 108:34e6b704fe68 546
Kojto 108:34e6b704fe68 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 108:34e6b704fe68 548 __v7_all_cache(0);
Kojto 108:34e6b704fe68 549 }
Kojto 108:34e6b704fe68 550
Kojto 108:34e6b704fe68 551 /** \brief Clean the whole D$
Kojto 108:34e6b704fe68 552
Kojto 108:34e6b704fe68 553 DCCSW. Clean by Set/Way
Kojto 108:34e6b704fe68 554 */
Kojto 108:34e6b704fe68 555
Kojto 108:34e6b704fe68 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 108:34e6b704fe68 557 __v7_all_cache(1);
Kojto 108:34e6b704fe68 558 }
Kojto 108:34e6b704fe68 559
Kojto 108:34e6b704fe68 560 /** \brief Clean and invalidate the whole D$
Kojto 108:34e6b704fe68 561
Kojto 108:34e6b704fe68 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 108:34e6b704fe68 563 */
Kojto 108:34e6b704fe68 564
Kojto 108:34e6b704fe68 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 108:34e6b704fe68 566 __v7_all_cache(2);
Kojto 108:34e6b704fe68 567 }
Kojto 108:34e6b704fe68 568
Kojto 108:34e6b704fe68 569 #include "core_ca_mmu.h"
Kojto 108:34e6b704fe68 570
Kojto 108:34e6b704fe68 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 108:34e6b704fe68 572
Kojto 108:34e6b704fe68 573 #error IAR Compiler support not implemented for Cortex-A
Kojto 108:34e6b704fe68 574
Kojto 108:34e6b704fe68 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 108:34e6b704fe68 576 /* GNU gcc specific functions */
Kojto 108:34e6b704fe68 577
Kojto 108:34e6b704fe68 578 #define MODE_USR 0x10
Kojto 108:34e6b704fe68 579 #define MODE_FIQ 0x11
Kojto 108:34e6b704fe68 580 #define MODE_IRQ 0x12
Kojto 108:34e6b704fe68 581 #define MODE_SVC 0x13
Kojto 108:34e6b704fe68 582 #define MODE_MON 0x16
Kojto 108:34e6b704fe68 583 #define MODE_ABT 0x17
Kojto 108:34e6b704fe68 584 #define MODE_HYP 0x1A
Kojto 108:34e6b704fe68 585 #define MODE_UND 0x1B
Kojto 108:34e6b704fe68 586 #define MODE_SYS 0x1F
Kojto 108:34e6b704fe68 587
Kojto 108:34e6b704fe68 588
Kojto 108:34e6b704fe68 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 108:34e6b704fe68 590 {
Kojto 108:34e6b704fe68 591 __ASM volatile ("cpsie i");
Kojto 108:34e6b704fe68 592 }
Kojto 108:34e6b704fe68 593
Kojto 108:34e6b704fe68 594 /** \brief Disable IRQ Interrupts
Kojto 108:34e6b704fe68 595
Kojto 108:34e6b704fe68 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 108:34e6b704fe68 597 Can only be executed in Privileged modes.
Kojto 108:34e6b704fe68 598 */
Kojto 108:34e6b704fe68 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 108:34e6b704fe68 600 {
Kojto 108:34e6b704fe68 601 uint32_t result;
Kojto 108:34e6b704fe68 602
Kojto 108:34e6b704fe68 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 108:34e6b704fe68 604 __ASM volatile ("cpsid i");
Kojto 108:34e6b704fe68 605 return(result & 0x80);
Kojto 108:34e6b704fe68 606 }
Kojto 108:34e6b704fe68 607
Kojto 108:34e6b704fe68 608
Kojto 108:34e6b704fe68 609 /** \brief Get APSR Register
Kojto 108:34e6b704fe68 610
Kojto 108:34e6b704fe68 611 This function returns the content of the APSR Register.
Kojto 108:34e6b704fe68 612
Kojto 108:34e6b704fe68 613 \return APSR Register value
Kojto 108:34e6b704fe68 614 */
Kojto 108:34e6b704fe68 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 108:34e6b704fe68 616 {
Kojto 108:34e6b704fe68 617 #if 1
Kojto 108:34e6b704fe68 618 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 108:34e6b704fe68 620 #else
Kojto 108:34e6b704fe68 621 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 622 #endif
Kojto 108:34e6b704fe68 623 return(__regAPSR);
Kojto 108:34e6b704fe68 624 }
Kojto 108:34e6b704fe68 625
Kojto 108:34e6b704fe68 626
Kojto 108:34e6b704fe68 627 /** \brief Get CPSR Register
Kojto 108:34e6b704fe68 628
Kojto 108:34e6b704fe68 629 This function returns the content of the CPSR Register.
Kojto 108:34e6b704fe68 630
Kojto 108:34e6b704fe68 631 \return CPSR Register value
Kojto 108:34e6b704fe68 632 */
Kojto 108:34e6b704fe68 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 108:34e6b704fe68 634 {
Kojto 108:34e6b704fe68 635 #if 1
Kojto 108:34e6b704fe68 636 register uint32_t __regCPSR;
Kojto 108:34e6b704fe68 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 108:34e6b704fe68 638 #else
Kojto 108:34e6b704fe68 639 register uint32_t __regCPSR __ASM("cpsr");
Kojto 108:34e6b704fe68 640 #endif
Kojto 108:34e6b704fe68 641 return(__regCPSR);
Kojto 108:34e6b704fe68 642 }
Kojto 108:34e6b704fe68 643
Kojto 108:34e6b704fe68 644 #if 0
Kojto 108:34e6b704fe68 645 /** \brief Set Stack Pointer
Kojto 108:34e6b704fe68 646
Kojto 108:34e6b704fe68 647 This function assigns the given value to the current stack pointer.
Kojto 108:34e6b704fe68 648
Kojto 108:34e6b704fe68 649 \param [in] topOfStack Stack Pointer value to set
Kojto 108:34e6b704fe68 650 */
Kojto 108:34e6b704fe68 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 108:34e6b704fe68 652 {
Kojto 108:34e6b704fe68 653 register uint32_t __regSP __ASM("sp");
Kojto 108:34e6b704fe68 654 __regSP = topOfStack;
Kojto 108:34e6b704fe68 655 }
Kojto 108:34e6b704fe68 656 #endif
Kojto 108:34e6b704fe68 657
Kojto 108:34e6b704fe68 658 /** \brief Get link register
Kojto 108:34e6b704fe68 659
Kojto 108:34e6b704fe68 660 This function returns the value of the link register
Kojto 108:34e6b704fe68 661
Kojto 108:34e6b704fe68 662 \return Value of link register
Kojto 108:34e6b704fe68 663 */
Kojto 108:34e6b704fe68 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 108:34e6b704fe68 665 {
Kojto 108:34e6b704fe68 666 register uint32_t __reglr __ASM("lr");
Kojto 108:34e6b704fe68 667 return(__reglr);
Kojto 108:34e6b704fe68 668 }
Kojto 108:34e6b704fe68 669
Kojto 108:34e6b704fe68 670 #if 0
Kojto 108:34e6b704fe68 671 /** \brief Set link register
Kojto 108:34e6b704fe68 672
Kojto 108:34e6b704fe68 673 This function sets the value of the link register
Kojto 108:34e6b704fe68 674
Kojto 108:34e6b704fe68 675 \param [in] lr LR value to set
Kojto 108:34e6b704fe68 676 */
Kojto 108:34e6b704fe68 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 108:34e6b704fe68 678 {
Kojto 108:34e6b704fe68 679 register uint32_t __reglr __ASM("lr");
Kojto 108:34e6b704fe68 680 __reglr = lr;
Kojto 108:34e6b704fe68 681 }
Kojto 108:34e6b704fe68 682 #endif
Kojto 108:34e6b704fe68 683
Kojto 108:34e6b704fe68 684 /** \brief Set Process Stack Pointer
Kojto 108:34e6b704fe68 685
Kojto 108:34e6b704fe68 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 108:34e6b704fe68 687
Kojto 108:34e6b704fe68 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 108:34e6b704fe68 689 */
Kojto 108:34e6b704fe68 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 691 {
Kojto 108:34e6b704fe68 692 __asm__ volatile (
Kojto 108:34e6b704fe68 693 ".ARM;"
Kojto 108:34e6b704fe68 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 695
Kojto 108:34e6b704fe68 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 697 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 698 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 699 "MOV SP, R0;"
Kojto 108:34e6b704fe68 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 701 "ISB;"
Kojto 108:34e6b704fe68 702 //"BX LR;"
Kojto 108:34e6b704fe68 703 :
Kojto 108:34e6b704fe68 704 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 705 : "r0", "r1");
Kojto 108:34e6b704fe68 706 return;
Kojto 108:34e6b704fe68 707 }
Kojto 108:34e6b704fe68 708
Kojto 108:34e6b704fe68 709 /** \brief Set User Mode
Kojto 108:34e6b704fe68 710
Kojto 108:34e6b704fe68 711 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 712 */
Kojto 108:34e6b704fe68 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 714 {
Kojto 108:34e6b704fe68 715 __asm__ volatile (
Kojto 108:34e6b704fe68 716 ".ARM;"
Kojto 108:34e6b704fe68 717
Kojto 108:34e6b704fe68 718 "CPS %0;"
Kojto 108:34e6b704fe68 719 //"BX LR;"
Kojto 108:34e6b704fe68 720 :
Kojto 108:34e6b704fe68 721 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 722 : );
Kojto 108:34e6b704fe68 723 return;
Kojto 108:34e6b704fe68 724 }
Kojto 108:34e6b704fe68 725
Kojto 108:34e6b704fe68 726
Kojto 108:34e6b704fe68 727 /** \brief Enable FIQ
Kojto 108:34e6b704fe68 728
Kojto 108:34e6b704fe68 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 108:34e6b704fe68 730 Can only be executed in Privileged modes.
Kojto 108:34e6b704fe68 731 */
Kojto 108:34e6b704fe68 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 108:34e6b704fe68 733
Kojto 108:34e6b704fe68 734
Kojto 108:34e6b704fe68 735 /** \brief Disable FIQ
Kojto 108:34e6b704fe68 736
Kojto 108:34e6b704fe68 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 108:34e6b704fe68 738 Can only be executed in Privileged modes.
Kojto 108:34e6b704fe68 739 */
Kojto 108:34e6b704fe68 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 108:34e6b704fe68 741
Kojto 108:34e6b704fe68 742
Kojto 108:34e6b704fe68 743 /** \brief Get FPSCR
Kojto 108:34e6b704fe68 744
Kojto 108:34e6b704fe68 745 This function returns the current value of the Floating Point Status/Control register.
Kojto 108:34e6b704fe68 746
Kojto 108:34e6b704fe68 747 \return Floating Point Status/Control register value
Kojto 108:34e6b704fe68 748 */
Kojto 108:34e6b704fe68 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 108:34e6b704fe68 750 {
Kojto 108:34e6b704fe68 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 108:34e6b704fe68 752 #if 1
Kojto 108:34e6b704fe68 753 uint32_t result;
Kojto 108:34e6b704fe68 754
Kojto 108:34e6b704fe68 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 108:34e6b704fe68 756 return (result);
Kojto 108:34e6b704fe68 757 #else
Kojto 108:34e6b704fe68 758 register uint32_t __regfpscr __ASM("fpscr");
Kojto 108:34e6b704fe68 759 return(__regfpscr);
Kojto 108:34e6b704fe68 760 #endif
Kojto 108:34e6b704fe68 761 #else
Kojto 108:34e6b704fe68 762 return(0);
Kojto 108:34e6b704fe68 763 #endif
Kojto 108:34e6b704fe68 764 }
Kojto 108:34e6b704fe68 765
Kojto 108:34e6b704fe68 766
Kojto 108:34e6b704fe68 767 /** \brief Set FPSCR
Kojto 108:34e6b704fe68 768
Kojto 108:34e6b704fe68 769 This function assigns the given value to the Floating Point Status/Control register.
Kojto 108:34e6b704fe68 770
Kojto 108:34e6b704fe68 771 \param [in] fpscr Floating Point Status/Control value to set
Kojto 108:34e6b704fe68 772 */
Kojto 108:34e6b704fe68 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 108:34e6b704fe68 774 {
Kojto 108:34e6b704fe68 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 108:34e6b704fe68 776 #if 1
Kojto 108:34e6b704fe68 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 108:34e6b704fe68 778 #else
Kojto 108:34e6b704fe68 779 register uint32_t __regfpscr __ASM("fpscr");
Kojto 108:34e6b704fe68 780 __regfpscr = (fpscr);
Kojto 108:34e6b704fe68 781 #endif
Kojto 108:34e6b704fe68 782 #endif
Kojto 108:34e6b704fe68 783 }
Kojto 108:34e6b704fe68 784
Kojto 108:34e6b704fe68 785 /** \brief Get FPEXC
Kojto 108:34e6b704fe68 786
Kojto 108:34e6b704fe68 787 This function returns the current value of the Floating Point Exception Control register.
Kojto 108:34e6b704fe68 788
Kojto 108:34e6b704fe68 789 \return Floating Point Exception Control register value
Kojto 108:34e6b704fe68 790 */
Kojto 108:34e6b704fe68 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 108:34e6b704fe68 792 {
Kojto 108:34e6b704fe68 793 #if (__FPU_PRESENT == 1)
Kojto 108:34e6b704fe68 794 #if 1
Kojto 108:34e6b704fe68 795 uint32_t result;
Kojto 108:34e6b704fe68 796
Kojto 108:34e6b704fe68 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 108:34e6b704fe68 798 return (result);
Kojto 108:34e6b704fe68 799 #else
Kojto 108:34e6b704fe68 800 register uint32_t __regfpexc __ASM("fpexc");
Kojto 108:34e6b704fe68 801 return(__regfpexc);
Kojto 108:34e6b704fe68 802 #endif
Kojto 108:34e6b704fe68 803 #else
Kojto 108:34e6b704fe68 804 return(0);
Kojto 108:34e6b704fe68 805 #endif
Kojto 108:34e6b704fe68 806 }
Kojto 108:34e6b704fe68 807
Kojto 108:34e6b704fe68 808
Kojto 108:34e6b704fe68 809 /** \brief Set FPEXC
Kojto 108:34e6b704fe68 810
Kojto 108:34e6b704fe68 811 This function assigns the given value to the Floating Point Exception Control register.
Kojto 108:34e6b704fe68 812
Kojto 108:34e6b704fe68 813 \param [in] fpscr Floating Point Exception Control value to set
Kojto 108:34e6b704fe68 814 */
Kojto 108:34e6b704fe68 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 108:34e6b704fe68 816 {
Kojto 108:34e6b704fe68 817 #if (__FPU_PRESENT == 1)
Kojto 108:34e6b704fe68 818 #if 1
Kojto 108:34e6b704fe68 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 108:34e6b704fe68 820 #else
Kojto 108:34e6b704fe68 821 register uint32_t __regfpexc __ASM("fpexc");
Kojto 108:34e6b704fe68 822 __regfpexc = (fpexc);
Kojto 108:34e6b704fe68 823 #endif
Kojto 108:34e6b704fe68 824 #endif
Kojto 108:34e6b704fe68 825 }
Kojto 108:34e6b704fe68 826
Kojto 108:34e6b704fe68 827 /** \brief Get CPACR
Kojto 108:34e6b704fe68 828
Kojto 108:34e6b704fe68 829 This function returns the current value of the Coprocessor Access Control register.
Kojto 108:34e6b704fe68 830
Kojto 108:34e6b704fe68 831 \return Coprocessor Access Control register value
Kojto 108:34e6b704fe68 832 */
Kojto 108:34e6b704fe68 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 108:34e6b704fe68 834 {
Kojto 108:34e6b704fe68 835 #if 1
Kojto 108:34e6b704fe68 836 register uint32_t __regCPACR;
Kojto 108:34e6b704fe68 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 108:34e6b704fe68 838 #else
Kojto 108:34e6b704fe68 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 108:34e6b704fe68 840 #endif
Kojto 108:34e6b704fe68 841 return __regCPACR;
Kojto 108:34e6b704fe68 842 }
Kojto 108:34e6b704fe68 843
Kojto 108:34e6b704fe68 844 /** \brief Set CPACR
Kojto 108:34e6b704fe68 845
Kojto 108:34e6b704fe68 846 This function assigns the given value to the Coprocessor Access Control register.
Kojto 108:34e6b704fe68 847
Kojto 108:34e6b704fe68 848 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 108:34e6b704fe68 849 */
Kojto 108:34e6b704fe68 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 108:34e6b704fe68 851 {
Kojto 108:34e6b704fe68 852 #if 1
Kojto 108:34e6b704fe68 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 108:34e6b704fe68 854 #else
Kojto 108:34e6b704fe68 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 108:34e6b704fe68 856 __regCPACR = cpacr;
Kojto 108:34e6b704fe68 857 #endif
Kojto 108:34e6b704fe68 858 __ISB();
Kojto 108:34e6b704fe68 859 }
Kojto 108:34e6b704fe68 860
Kojto 108:34e6b704fe68 861 /** \brief Get CBAR
Kojto 108:34e6b704fe68 862
Kojto 108:34e6b704fe68 863 This function returns the value of the Configuration Base Address register.
Kojto 108:34e6b704fe68 864
Kojto 108:34e6b704fe68 865 \return Configuration Base Address register value
Kojto 108:34e6b704fe68 866 */
Kojto 108:34e6b704fe68 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 108:34e6b704fe68 868 #if 1
Kojto 108:34e6b704fe68 869 register uint32_t __regCBAR;
Kojto 108:34e6b704fe68 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 108:34e6b704fe68 871 #else
Kojto 108:34e6b704fe68 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 108:34e6b704fe68 873 #endif
Kojto 108:34e6b704fe68 874 return(__regCBAR);
Kojto 108:34e6b704fe68 875 }
Kojto 108:34e6b704fe68 876
Kojto 108:34e6b704fe68 877 /** \brief Get TTBR0
Kojto 108:34e6b704fe68 878
Kojto 108:34e6b704fe68 879 This function returns the value of the Translation Table Base Register 0.
Kojto 108:34e6b704fe68 880
Kojto 108:34e6b704fe68 881 \return Translation Table Base Register 0 value
Kojto 108:34e6b704fe68 882 */
Kojto 108:34e6b704fe68 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 108:34e6b704fe68 884 #if 1
Kojto 108:34e6b704fe68 885 register uint32_t __regTTBR0;
Kojto 108:34e6b704fe68 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 108:34e6b704fe68 887 #else
Kojto 108:34e6b704fe68 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 108:34e6b704fe68 889 #endif
Kojto 108:34e6b704fe68 890 return(__regTTBR0);
Kojto 108:34e6b704fe68 891 }
Kojto 108:34e6b704fe68 892
Kojto 108:34e6b704fe68 893 /** \brief Set TTBR0
Kojto 108:34e6b704fe68 894
Kojto 108:34e6b704fe68 895 This function assigns the given value to the Translation Table Base Register 0.
Kojto 108:34e6b704fe68 896
Kojto 108:34e6b704fe68 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 108:34e6b704fe68 898 */
Kojto 108:34e6b704fe68 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 108:34e6b704fe68 900 #if 1
Kojto 108:34e6b704fe68 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 108:34e6b704fe68 902 #else
Kojto 108:34e6b704fe68 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 108:34e6b704fe68 904 __regTTBR0 = ttbr0;
Kojto 108:34e6b704fe68 905 #endif
Kojto 108:34e6b704fe68 906 __ISB();
Kojto 108:34e6b704fe68 907 }
Kojto 108:34e6b704fe68 908
Kojto 108:34e6b704fe68 909 /** \brief Get DACR
Kojto 108:34e6b704fe68 910
Kojto 108:34e6b704fe68 911 This function returns the value of the Domain Access Control Register.
Kojto 108:34e6b704fe68 912
Kojto 108:34e6b704fe68 913 \return Domain Access Control Register value
Kojto 108:34e6b704fe68 914 */
Kojto 108:34e6b704fe68 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 108:34e6b704fe68 916 #if 1
Kojto 108:34e6b704fe68 917 register uint32_t __regDACR;
Kojto 108:34e6b704fe68 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 108:34e6b704fe68 919 #else
Kojto 108:34e6b704fe68 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 108:34e6b704fe68 921 #endif
Kojto 108:34e6b704fe68 922 return(__regDACR);
Kojto 108:34e6b704fe68 923 }
Kojto 108:34e6b704fe68 924
Kojto 108:34e6b704fe68 925 /** \brief Set DACR
Kojto 108:34e6b704fe68 926
Kojto 108:34e6b704fe68 927 This function assigns the given value to the Domain Access Control Register.
Kojto 108:34e6b704fe68 928
Kojto 108:34e6b704fe68 929 \param [in] dacr Domain Access Control Register value to set
Kojto 108:34e6b704fe68 930 */
Kojto 108:34e6b704fe68 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 108:34e6b704fe68 932 #if 1
Kojto 108:34e6b704fe68 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 108:34e6b704fe68 934 #else
Kojto 108:34e6b704fe68 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 108:34e6b704fe68 936 __regDACR = dacr;
Kojto 108:34e6b704fe68 937 #endif
Kojto 108:34e6b704fe68 938 __ISB();
Kojto 108:34e6b704fe68 939 }
Kojto 108:34e6b704fe68 940
Kojto 108:34e6b704fe68 941 /******************************** Cache and BTAC enable ****************************************************/
Kojto 108:34e6b704fe68 942
Kojto 108:34e6b704fe68 943 /** \brief Set SCTLR
Kojto 108:34e6b704fe68 944
Kojto 108:34e6b704fe68 945 This function assigns the given value to the System Control Register.
Kojto 108:34e6b704fe68 946
Kojto 108:34e6b704fe68 947 \param [in] sctlr System Control Register value to set
Kojto 108:34e6b704fe68 948 */
Kojto 108:34e6b704fe68 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 108:34e6b704fe68 950 {
Kojto 108:34e6b704fe68 951 #if 1
Kojto 108:34e6b704fe68 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 108:34e6b704fe68 953 #else
Kojto 108:34e6b704fe68 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 108:34e6b704fe68 955 __regSCTLR = sctlr;
Kojto 108:34e6b704fe68 956 #endif
Kojto 108:34e6b704fe68 957 }
Kojto 108:34e6b704fe68 958
Kojto 108:34e6b704fe68 959 /** \brief Get SCTLR
Kojto 108:34e6b704fe68 960
Kojto 108:34e6b704fe68 961 This function returns the value of the System Control Register.
Kojto 108:34e6b704fe68 962
Kojto 108:34e6b704fe68 963 \return System Control Register value
Kojto 108:34e6b704fe68 964 */
Kojto 108:34e6b704fe68 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 108:34e6b704fe68 966 #if 1
Kojto 108:34e6b704fe68 967 register uint32_t __regSCTLR;
Kojto 108:34e6b704fe68 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 108:34e6b704fe68 969 #else
Kojto 108:34e6b704fe68 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 108:34e6b704fe68 971 #endif
Kojto 108:34e6b704fe68 972 return(__regSCTLR);
Kojto 108:34e6b704fe68 973 }
Kojto 108:34e6b704fe68 974
Kojto 108:34e6b704fe68 975 /** \brief Enable Caches
Kojto 108:34e6b704fe68 976
Kojto 108:34e6b704fe68 977 Enable Caches
Kojto 108:34e6b704fe68 978 */
Kojto 108:34e6b704fe68 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 108:34e6b704fe68 980 // Set I bit 12 to enable I Cache
Kojto 108:34e6b704fe68 981 // Set C bit 2 to enable D Cache
Kojto 108:34e6b704fe68 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 108:34e6b704fe68 983 }
Kojto 108:34e6b704fe68 984
Kojto 108:34e6b704fe68 985 /** \brief Disable Caches
Kojto 108:34e6b704fe68 986
Kojto 108:34e6b704fe68 987 Disable Caches
Kojto 108:34e6b704fe68 988 */
Kojto 108:34e6b704fe68 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 108:34e6b704fe68 990 // Clear I bit 12 to disable I Cache
Kojto 108:34e6b704fe68 991 // Clear C bit 2 to disable D Cache
Kojto 108:34e6b704fe68 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 108:34e6b704fe68 993 __ISB();
Kojto 108:34e6b704fe68 994 }
Kojto 108:34e6b704fe68 995
Kojto 108:34e6b704fe68 996 /** \brief Enable BTAC
Kojto 108:34e6b704fe68 997
Kojto 108:34e6b704fe68 998 Enable BTAC
Kojto 108:34e6b704fe68 999 */
Kojto 108:34e6b704fe68 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 108:34e6b704fe68 1001 // Set Z bit 11 to enable branch prediction
Kojto 108:34e6b704fe68 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 108:34e6b704fe68 1003 __ISB();
Kojto 108:34e6b704fe68 1004 }
Kojto 108:34e6b704fe68 1005
Kojto 108:34e6b704fe68 1006 /** \brief Disable BTAC
Kojto 108:34e6b704fe68 1007
Kojto 108:34e6b704fe68 1008 Disable BTAC
Kojto 108:34e6b704fe68 1009 */
Kojto 108:34e6b704fe68 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 108:34e6b704fe68 1011 // Clear Z bit 11 to disable branch prediction
Kojto 108:34e6b704fe68 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 108:34e6b704fe68 1013 }
Kojto 108:34e6b704fe68 1014
Kojto 108:34e6b704fe68 1015
Kojto 108:34e6b704fe68 1016 /** \brief Enable MMU
Kojto 108:34e6b704fe68 1017
Kojto 108:34e6b704fe68 1018 Enable MMU
Kojto 108:34e6b704fe68 1019 */
Kojto 108:34e6b704fe68 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 108:34e6b704fe68 1021 // Set M bit 0 to enable the MMU
Kojto 108:34e6b704fe68 1022 // Set AFE bit to enable simplified access permissions model
Kojto 108:34e6b704fe68 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 108:34e6b704fe68 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 108:34e6b704fe68 1025 __ISB();
Kojto 108:34e6b704fe68 1026 }
Kojto 108:34e6b704fe68 1027
Kojto 108:34e6b704fe68 1028 /** \brief Disable MMU
Kojto 108:34e6b704fe68 1029
Kojto 108:34e6b704fe68 1030 Disable MMU
Kojto 108:34e6b704fe68 1031 */
Kojto 108:34e6b704fe68 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 108:34e6b704fe68 1033 // Clear M bit 0 to disable the MMU
Kojto 108:34e6b704fe68 1034 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 108:34e6b704fe68 1035 __ISB();
Kojto 108:34e6b704fe68 1036 }
Kojto 108:34e6b704fe68 1037
Kojto 108:34e6b704fe68 1038 /******************************** TLB maintenance operations ************************************************/
Kojto 108:34e6b704fe68 1039 /** \brief Invalidate the whole tlb
Kojto 108:34e6b704fe68 1040
Kojto 108:34e6b704fe68 1041 TLBIALL. Invalidate the whole tlb
Kojto 108:34e6b704fe68 1042 */
Kojto 108:34e6b704fe68 1043
Kojto 108:34e6b704fe68 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 108:34e6b704fe68 1045 #if 1
Kojto 108:34e6b704fe68 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 108:34e6b704fe68 1047 #else
Kojto 108:34e6b704fe68 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 108:34e6b704fe68 1049 __TLBIALL = 0;
Kojto 108:34e6b704fe68 1050 #endif
Kojto 108:34e6b704fe68 1051 __DSB();
Kojto 108:34e6b704fe68 1052 __ISB();
Kojto 108:34e6b704fe68 1053 }
Kojto 108:34e6b704fe68 1054
Kojto 108:34e6b704fe68 1055 /******************************** BTB maintenance operations ************************************************/
Kojto 108:34e6b704fe68 1056 /** \brief Invalidate entire branch predictor array
Kojto 108:34e6b704fe68 1057
Kojto 108:34e6b704fe68 1058 BPIALL. Branch Predictor Invalidate All.
Kojto 108:34e6b704fe68 1059 */
Kojto 108:34e6b704fe68 1060
Kojto 108:34e6b704fe68 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 108:34e6b704fe68 1062 #if 1
Kojto 108:34e6b704fe68 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 108:34e6b704fe68 1064 #else
Kojto 108:34e6b704fe68 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 108:34e6b704fe68 1066 __BPIALL = 0;
Kojto 108:34e6b704fe68 1067 #endif
Kojto 108:34e6b704fe68 1068 __DSB(); //ensure completion of the invalidation
Kojto 108:34e6b704fe68 1069 __ISB(); //ensure instruction fetch path sees new state
Kojto 108:34e6b704fe68 1070 }
Kojto 108:34e6b704fe68 1071
Kojto 108:34e6b704fe68 1072
Kojto 108:34e6b704fe68 1073 /******************************** L1 cache operations ******************************************************/
Kojto 108:34e6b704fe68 1074
Kojto 108:34e6b704fe68 1075 /** \brief Invalidate the whole I$
Kojto 108:34e6b704fe68 1076
Kojto 108:34e6b704fe68 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 108:34e6b704fe68 1078 */
Kojto 108:34e6b704fe68 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 108:34e6b704fe68 1080 #if 1
Kojto 108:34e6b704fe68 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 108:34e6b704fe68 1082 #else
Kojto 108:34e6b704fe68 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 108:34e6b704fe68 1084 __ICIALLU = 0;
Kojto 108:34e6b704fe68 1085 #endif
Kojto 108:34e6b704fe68 1086 __DSB(); //ensure completion of the invalidation
Kojto 108:34e6b704fe68 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 108:34e6b704fe68 1088 }
Kojto 108:34e6b704fe68 1089
Kojto 108:34e6b704fe68 1090 /** \brief Clean D$ by MVA
Kojto 108:34e6b704fe68 1091
Kojto 108:34e6b704fe68 1092 DCCMVAC. Data cache clean by MVA to PoC
Kojto 108:34e6b704fe68 1093 */
Kojto 108:34e6b704fe68 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 108:34e6b704fe68 1095 #if 1
Kojto 108:34e6b704fe68 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 108:34e6b704fe68 1097 #else
Kojto 108:34e6b704fe68 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 108:34e6b704fe68 1099 __DCCMVAC = (uint32_t)va;
Kojto 108:34e6b704fe68 1100 #endif
Kojto 108:34e6b704fe68 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 108:34e6b704fe68 1102 }
Kojto 108:34e6b704fe68 1103
Kojto 108:34e6b704fe68 1104 /** \brief Invalidate D$ by MVA
Kojto 108:34e6b704fe68 1105
Kojto 108:34e6b704fe68 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 108:34e6b704fe68 1107 */
Kojto 108:34e6b704fe68 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 108:34e6b704fe68 1109 #if 1
Kojto 108:34e6b704fe68 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 108:34e6b704fe68 1111 #else
Kojto 108:34e6b704fe68 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 108:34e6b704fe68 1113 __DCIMVAC = (uint32_t)va;
Kojto 108:34e6b704fe68 1114 #endif
Kojto 108:34e6b704fe68 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 108:34e6b704fe68 1116 }
Kojto 108:34e6b704fe68 1117
Kojto 108:34e6b704fe68 1118 /** \brief Clean and Invalidate D$ by MVA
Kojto 108:34e6b704fe68 1119
Kojto 108:34e6b704fe68 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 108:34e6b704fe68 1121 */
Kojto 108:34e6b704fe68 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 108:34e6b704fe68 1123 #if 1
Kojto 108:34e6b704fe68 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 108:34e6b704fe68 1125 #else
Kojto 108:34e6b704fe68 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 108:34e6b704fe68 1127 __DCCIMVAC = (uint32_t)va;
Kojto 108:34e6b704fe68 1128 #endif
Kojto 108:34e6b704fe68 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 108:34e6b704fe68 1130 }
Kojto 108:34e6b704fe68 1131
Kojto 108:34e6b704fe68 1132 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 1133
Kojto 108:34e6b704fe68 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 108:34e6b704fe68 1135 */
Kojto 108:34e6b704fe68 1136 extern void __v7_all_cache(uint32_t op);
Kojto 108:34e6b704fe68 1137
Kojto 108:34e6b704fe68 1138
Kojto 108:34e6b704fe68 1139 /** \brief Invalidate the whole D$
Kojto 108:34e6b704fe68 1140
Kojto 108:34e6b704fe68 1141 DCISW. Invalidate by Set/Way
Kojto 108:34e6b704fe68 1142 */
Kojto 108:34e6b704fe68 1143
Kojto 108:34e6b704fe68 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 108:34e6b704fe68 1145 __v7_all_cache(0);
Kojto 108:34e6b704fe68 1146 }
Kojto 108:34e6b704fe68 1147
Kojto 108:34e6b704fe68 1148 /** \brief Clean the whole D$
Kojto 108:34e6b704fe68 1149
Kojto 108:34e6b704fe68 1150 DCCSW. Clean by Set/Way
Kojto 108:34e6b704fe68 1151 */
Kojto 108:34e6b704fe68 1152
Kojto 108:34e6b704fe68 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 108:34e6b704fe68 1154 __v7_all_cache(1);
Kojto 108:34e6b704fe68 1155 }
Kojto 108:34e6b704fe68 1156
Kojto 108:34e6b704fe68 1157 /** \brief Clean and invalidate the whole D$
Kojto 108:34e6b704fe68 1158
Kojto 108:34e6b704fe68 1159 DCCISW. Clean and Invalidate by Set/Way
Kojto 108:34e6b704fe68 1160 */
Kojto 108:34e6b704fe68 1161
Kojto 108:34e6b704fe68 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 108:34e6b704fe68 1163 __v7_all_cache(2);
Kojto 108:34e6b704fe68 1164 }
Kojto 108:34e6b704fe68 1165
Kojto 108:34e6b704fe68 1166 #include "core_ca_mmu.h"
Kojto 108:34e6b704fe68 1167
Kojto 108:34e6b704fe68 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 108:34e6b704fe68 1169
Kojto 108:34e6b704fe68 1170 #error TASKING Compiler support not implemented for Cortex-A
Kojto 108:34e6b704fe68 1171
Kojto 108:34e6b704fe68 1172 #endif
Kojto 108:34e6b704fe68 1173
Kojto 108:34e6b704fe68 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 108:34e6b704fe68 1175
Kojto 108:34e6b704fe68 1176
Kojto 108:34e6b704fe68 1177 #endif /* __CORE_CAFUNC_H__ */