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TARGET_NCS36510/core_cm7.h@125:2e9cc70d1897, 2016-08-31 (annotated)

Committer:: AnnaBridge
Date:: Wed Aug 31 18:09:46 2016 +0100
Revision:: 125:2e9cc70d1897
Child:: 128:9bcdf88f62b0

Release 125 of the mbed library

Changes:

New target - KL27Z_IAR

New target - MAX32620HSP_ARM_STD

New target - MAX32620HSP_GCC_ARM

New target - MAX32620HSP_IAR

New target - NCS36510_ARM_STD

New target - NCS36510_GCC_ARM

New target - NCS36510_IAR

Added support for NSAPI_REUSEADDR to the lwip interface.

STM32F3 family : Add and enable asynchronous serial, plus tests.

STM32L4 family : Add and enable asynchronous serial, plus tests.

Fixing issue where GCC fails to report compile errors when non-verbose.

Add ethernet and IPV4 support for: NUCLEO_F207ZG, NUCLEO_F429ZI, NUCLEO_F767ZI, DISCO_F746NG.

RZ_A1H - Enable SPI1 on pins P6_4 to P6_7.

KL27Z : SPI driver bug fixes and Improvements, ARM linker file update.

STM32F4, STM32F7 families : Add entropy functions, documentation, code improvements, fix build issues.

HEXIWEAR: Update I2C pin mapping, Add support to create KDS projects.

LWIP - fix recv blocking send on accepted sockets.

SingletonPtr bugfixes.

Beetle: Implement sleep API.

uVisor: Update to v0.20.1-alpha, minor documentation update.

STM32F3 : fix RTOS IAR test, RTOS GCC_ARM test.

nrf5x : Introduce uart hardware flow control configuration.

K64F/K22F: Implement HAL lp_timer API.

Ticker: Move ticker initialisation to object creation time.

STM32F4 : remove printf from pwmout

NXP : Fix multiple definition errors in GCC_CR build, fix linker errors.

Add TOOLCHAIN_GCC_CR support.

STM32L1 family : Add and enable asynchronous serial, plus tests.

mbed-client : Fix Bootstrap and Connector functionality.

NUC472 : Fix Ethernet wrong INT status in RX_Action.

RTX_CM_lib.h : fix compiler warning.

NUCLEO : Use GCC small build for 64K flash STM32.

STM32F2 family : Add and enable asynchronous serial, plus tests.

uvisor : Move page heap after uVisor private data, update page allocator.

K64F: Revert to hardcoded stack pointer in RTX .

dns-query : Internal API change , documentation, Added support for multiple results and ipv6.

Add support for implementation-provided DNS servers.

Adopted netconn_gethostbyname in the lwip interface.

Restructured nsapi_dns.h to have clear separation between C/C++ .

Tool fixes.

Tests : New ones added and some updates to existing.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	125:2e9cc70d1897	1	/************************************************************************//
AnnaBridge	125:2e9cc70d1897	2	* @file core_cm7.h
AnnaBridge	125:2e9cc70d1897	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
AnnaBridge	125:2e9cc70d1897	4	* @version V4.10
AnnaBridge	125:2e9cc70d1897	5	* @date 18. March 2015
AnnaBridge	125:2e9cc70d1897	6	*
AnnaBridge	125:2e9cc70d1897	7	* @note
AnnaBridge	125:2e9cc70d1897	8	*
AnnaBridge	125:2e9cc70d1897	9	******************************************************************************/
AnnaBridge	125:2e9cc70d1897	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge	125:2e9cc70d1897	11
AnnaBridge	125:2e9cc70d1897	12	All rights reserved.
AnnaBridge	125:2e9cc70d1897	13	Redistribution and use in source and binary forms, with or without
AnnaBridge	125:2e9cc70d1897	14	modification, are permitted provided that the following conditions are met:
AnnaBridge	125:2e9cc70d1897	15	- Redistributions of source code must retain the above copyright
AnnaBridge	125:2e9cc70d1897	16	notice, this list of conditions and the following disclaimer.
AnnaBridge	125:2e9cc70d1897	17	- Redistributions in binary form must reproduce the above copyright
AnnaBridge	125:2e9cc70d1897	18	notice, this list of conditions and the following disclaimer in the
AnnaBridge	125:2e9cc70d1897	19	documentation and/or other materials provided with the distribution.
AnnaBridge	125:2e9cc70d1897	20	- Neither the name of ARM nor the names of its contributors may be used
AnnaBridge	125:2e9cc70d1897	21	to endorse or promote products derived from this software without
AnnaBridge	125:2e9cc70d1897	22	specific prior written permission.
AnnaBridge	125:2e9cc70d1897	23	*
AnnaBridge	125:2e9cc70d1897	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	125:2e9cc70d1897	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	125:2e9cc70d1897	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge	125:2e9cc70d1897	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge	125:2e9cc70d1897	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge	125:2e9cc70d1897	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge	125:2e9cc70d1897	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge	125:2e9cc70d1897	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge	125:2e9cc70d1897	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge	125:2e9cc70d1897	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge	125:2e9cc70d1897	34	POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	125:2e9cc70d1897	35	---------------------------------------------------------------------------*/
AnnaBridge	125:2e9cc70d1897	36
AnnaBridge	125:2e9cc70d1897	37
AnnaBridge	125:2e9cc70d1897	38	#if defined ( __ICCARM__ )
AnnaBridge	125:2e9cc70d1897	39	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	125:2e9cc70d1897	40	#endif
AnnaBridge	125:2e9cc70d1897	41
AnnaBridge	125:2e9cc70d1897	42	#ifndef __CORE_CM7_H_GENERIC
AnnaBridge	125:2e9cc70d1897	43	#define __CORE_CM7_H_GENERIC
AnnaBridge	125:2e9cc70d1897	44
AnnaBridge	125:2e9cc70d1897	45	#ifdef __cplusplus
AnnaBridge	125:2e9cc70d1897	46	extern "C" {
AnnaBridge	125:2e9cc70d1897	47	#endif
AnnaBridge	125:2e9cc70d1897	48
AnnaBridge	125:2e9cc70d1897	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	125:2e9cc70d1897	50	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	125:2e9cc70d1897	51
AnnaBridge	125:2e9cc70d1897	52	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	125:2e9cc70d1897	53	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	125:2e9cc70d1897	54
AnnaBridge	125:2e9cc70d1897	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	125:2e9cc70d1897	56	Unions are used for effective representation of core registers.
AnnaBridge	125:2e9cc70d1897	57
AnnaBridge	125:2e9cc70d1897	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	125:2e9cc70d1897	59	Function-like macros are used to allow more efficient code.
AnnaBridge	125:2e9cc70d1897	60	*/
AnnaBridge	125:2e9cc70d1897	61
AnnaBridge	125:2e9cc70d1897	62
AnnaBridge	125:2e9cc70d1897	63	/*******************************************************************************
AnnaBridge	125:2e9cc70d1897	64	* CMSIS definitions
AnnaBridge	125:2e9cc70d1897	65	******************************************************************************/
AnnaBridge	125:2e9cc70d1897	66	/** \ingroup Cortex_M7
AnnaBridge	125:2e9cc70d1897	67	@{
AnnaBridge	125:2e9cc70d1897	68	*/
AnnaBridge	125:2e9cc70d1897	69
AnnaBridge	125:2e9cc70d1897	70	/* CMSIS CM7 definitions */
AnnaBridge	125:2e9cc70d1897	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
AnnaBridge	125:2e9cc70d1897	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
AnnaBridge	125:2e9cc70d1897	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
AnnaBridge	125:2e9cc70d1897	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
AnnaBridge	125:2e9cc70d1897	75
AnnaBridge	125:2e9cc70d1897	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
AnnaBridge	125:2e9cc70d1897	77
AnnaBridge	125:2e9cc70d1897	78
AnnaBridge	125:2e9cc70d1897	79	#if defined ( __CC_ARM )
AnnaBridge	125:2e9cc70d1897	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
AnnaBridge	125:2e9cc70d1897	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
AnnaBridge	125:2e9cc70d1897	82	#define __STATIC_INLINE static __inline
AnnaBridge	125:2e9cc70d1897	83
AnnaBridge	125:2e9cc70d1897	84	#elif defined ( __GNUC__ )
AnnaBridge	125:2e9cc70d1897	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
AnnaBridge	125:2e9cc70d1897	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
AnnaBridge	125:2e9cc70d1897	87	#define __STATIC_INLINE static inline
AnnaBridge	125:2e9cc70d1897	88
AnnaBridge	125:2e9cc70d1897	89	#elif defined ( __ICCARM__ )
AnnaBridge	125:2e9cc70d1897	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
AnnaBridge	125:2e9cc70d1897	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
AnnaBridge	125:2e9cc70d1897	92	#define __STATIC_INLINE static inline
AnnaBridge	125:2e9cc70d1897	93
AnnaBridge	125:2e9cc70d1897	94	#elif defined ( __TMS470__ )
AnnaBridge	125:2e9cc70d1897	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
AnnaBridge	125:2e9cc70d1897	96	#define __STATIC_INLINE static inline
AnnaBridge	125:2e9cc70d1897	97
AnnaBridge	125:2e9cc70d1897	98	#elif defined ( __TASKING__ )
AnnaBridge	125:2e9cc70d1897	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
AnnaBridge	125:2e9cc70d1897	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
AnnaBridge	125:2e9cc70d1897	101	#define __STATIC_INLINE static inline
AnnaBridge	125:2e9cc70d1897	102
AnnaBridge	125:2e9cc70d1897	103	#elif defined ( __CSMC__ )
AnnaBridge	125:2e9cc70d1897	104	#define __packed
AnnaBridge	125:2e9cc70d1897	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
AnnaBridge	125:2e9cc70d1897	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
AnnaBridge	125:2e9cc70d1897	107	#define __STATIC_INLINE static inline
AnnaBridge	125:2e9cc70d1897	108
AnnaBridge	125:2e9cc70d1897	109	#endif
AnnaBridge	125:2e9cc70d1897	110
AnnaBridge	125:2e9cc70d1897	111	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	125:2e9cc70d1897	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	125:2e9cc70d1897	113	*/
AnnaBridge	125:2e9cc70d1897	114	#if defined ( __CC_ARM )
AnnaBridge	125:2e9cc70d1897	115	#if defined __TARGET_FPU_VFP
AnnaBridge	125:2e9cc70d1897	116	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	117	#define __FPU_USED 1
AnnaBridge	125:2e9cc70d1897	118	#else
AnnaBridge	125:2e9cc70d1897	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	125:2e9cc70d1897	120	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	121	#endif
AnnaBridge	125:2e9cc70d1897	122	#else
AnnaBridge	125:2e9cc70d1897	123	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	124	#endif
AnnaBridge	125:2e9cc70d1897	125
AnnaBridge	125:2e9cc70d1897	126	#elif defined ( __GNUC__ )
AnnaBridge	125:2e9cc70d1897	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	125:2e9cc70d1897	128	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	129	#define __FPU_USED 1
AnnaBridge	125:2e9cc70d1897	130	#else
AnnaBridge	125:2e9cc70d1897	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	125:2e9cc70d1897	132	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	133	#endif
AnnaBridge	125:2e9cc70d1897	134	#else
AnnaBridge	125:2e9cc70d1897	135	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	136	#endif
AnnaBridge	125:2e9cc70d1897	137
AnnaBridge	125:2e9cc70d1897	138	#elif defined ( __ICCARM__ )
AnnaBridge	125:2e9cc70d1897	139	#if defined __ARMVFP__
AnnaBridge	125:2e9cc70d1897	140	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	141	#define __FPU_USED 1
AnnaBridge	125:2e9cc70d1897	142	#else
AnnaBridge	125:2e9cc70d1897	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	125:2e9cc70d1897	144	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	145	#endif
AnnaBridge	125:2e9cc70d1897	146	#else
AnnaBridge	125:2e9cc70d1897	147	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	148	#endif
AnnaBridge	125:2e9cc70d1897	149
AnnaBridge	125:2e9cc70d1897	150	#elif defined ( __TMS470__ )
AnnaBridge	125:2e9cc70d1897	151	#if defined __TI_VFP_SUPPORT__
AnnaBridge	125:2e9cc70d1897	152	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	153	#define __FPU_USED 1
AnnaBridge	125:2e9cc70d1897	154	#else
AnnaBridge	125:2e9cc70d1897	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	125:2e9cc70d1897	156	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	157	#endif
AnnaBridge	125:2e9cc70d1897	158	#else
AnnaBridge	125:2e9cc70d1897	159	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	160	#endif
AnnaBridge	125:2e9cc70d1897	161
AnnaBridge	125:2e9cc70d1897	162	#elif defined ( __TASKING__ )
AnnaBridge	125:2e9cc70d1897	163	#if defined __FPU_VFP__
AnnaBridge	125:2e9cc70d1897	164	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	165	#define __FPU_USED 1
AnnaBridge	125:2e9cc70d1897	166	#else
AnnaBridge	125:2e9cc70d1897	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	125:2e9cc70d1897	168	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	169	#endif
AnnaBridge	125:2e9cc70d1897	170	#else
AnnaBridge	125:2e9cc70d1897	171	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	172	#endif
AnnaBridge	125:2e9cc70d1897	173
AnnaBridge	125:2e9cc70d1897	174	#elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge	125:2e9cc70d1897	175	#if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge	125:2e9cc70d1897	176	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	177	#define __FPU_USED 1
AnnaBridge	125:2e9cc70d1897	178	#else
AnnaBridge	125:2e9cc70d1897	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	125:2e9cc70d1897	180	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	181	#endif
AnnaBridge	125:2e9cc70d1897	182	#else
AnnaBridge	125:2e9cc70d1897	183	#define __FPU_USED 0
AnnaBridge	125:2e9cc70d1897	184	#endif
AnnaBridge	125:2e9cc70d1897	185	#endif
AnnaBridge	125:2e9cc70d1897	186
AnnaBridge	125:2e9cc70d1897	187	#include <stdint.h> /* standard types definitions */
AnnaBridge	125:2e9cc70d1897	188	#include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge	125:2e9cc70d1897	189	#include <core_cmFunc.h> /* Core Function Access */
AnnaBridge	125:2e9cc70d1897	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
AnnaBridge	125:2e9cc70d1897	191
AnnaBridge	125:2e9cc70d1897	192	#ifdef __cplusplus
AnnaBridge	125:2e9cc70d1897	193	}
AnnaBridge	125:2e9cc70d1897	194	#endif
AnnaBridge	125:2e9cc70d1897	195
AnnaBridge	125:2e9cc70d1897	196	#endif /* __CORE_CM7_H_GENERIC */
AnnaBridge	125:2e9cc70d1897	197
AnnaBridge	125:2e9cc70d1897	198	#ifndef __CMSIS_GENERIC
AnnaBridge	125:2e9cc70d1897	199
AnnaBridge	125:2e9cc70d1897	200	#ifndef __CORE_CM7_H_DEPENDANT
AnnaBridge	125:2e9cc70d1897	201	#define __CORE_CM7_H_DEPENDANT
AnnaBridge	125:2e9cc70d1897	202
AnnaBridge	125:2e9cc70d1897	203	#ifdef __cplusplus
AnnaBridge	125:2e9cc70d1897	204	extern "C" {
AnnaBridge	125:2e9cc70d1897	205	#endif
AnnaBridge	125:2e9cc70d1897	206
AnnaBridge	125:2e9cc70d1897	207	/* check device defines and use defaults */
AnnaBridge	125:2e9cc70d1897	208	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	125:2e9cc70d1897	209	#ifndef __CM7_REV
AnnaBridge	125:2e9cc70d1897	210	#define __CM7_REV 0x0000
AnnaBridge	125:2e9cc70d1897	211	#warning "__CM7_REV not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	212	#endif
AnnaBridge	125:2e9cc70d1897	213
AnnaBridge	125:2e9cc70d1897	214	#ifndef __FPU_PRESENT
AnnaBridge	125:2e9cc70d1897	215	#define __FPU_PRESENT 0
AnnaBridge	125:2e9cc70d1897	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	217	#endif
AnnaBridge	125:2e9cc70d1897	218
AnnaBridge	125:2e9cc70d1897	219	#ifndef __MPU_PRESENT
AnnaBridge	125:2e9cc70d1897	220	#define __MPU_PRESENT 0
AnnaBridge	125:2e9cc70d1897	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	222	#endif
AnnaBridge	125:2e9cc70d1897	223
AnnaBridge	125:2e9cc70d1897	224	#ifndef __ICACHE_PRESENT
AnnaBridge	125:2e9cc70d1897	225	#define __ICACHE_PRESENT 0
AnnaBridge	125:2e9cc70d1897	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	227	#endif
AnnaBridge	125:2e9cc70d1897	228
AnnaBridge	125:2e9cc70d1897	229	#ifndef __DCACHE_PRESENT
AnnaBridge	125:2e9cc70d1897	230	#define __DCACHE_PRESENT 0
AnnaBridge	125:2e9cc70d1897	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	232	#endif
AnnaBridge	125:2e9cc70d1897	233
AnnaBridge	125:2e9cc70d1897	234	#ifndef __DTCM_PRESENT
AnnaBridge	125:2e9cc70d1897	235	#define __DTCM_PRESENT 0
AnnaBridge	125:2e9cc70d1897	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	237	#endif
AnnaBridge	125:2e9cc70d1897	238
AnnaBridge	125:2e9cc70d1897	239	#ifndef __NVIC_PRIO_BITS
AnnaBridge	125:2e9cc70d1897	240	#define __NVIC_PRIO_BITS 3
AnnaBridge	125:2e9cc70d1897	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	242	#endif
AnnaBridge	125:2e9cc70d1897	243
AnnaBridge	125:2e9cc70d1897	244	#ifndef __Vendor_SysTickConfig
AnnaBridge	125:2e9cc70d1897	245	#define __Vendor_SysTickConfig 0
AnnaBridge	125:2e9cc70d1897	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	125:2e9cc70d1897	247	#endif
AnnaBridge	125:2e9cc70d1897	248	#endif
AnnaBridge	125:2e9cc70d1897	249
AnnaBridge	125:2e9cc70d1897	250	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	125:2e9cc70d1897	251	/**
AnnaBridge	125:2e9cc70d1897	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	125:2e9cc70d1897	253
AnnaBridge	125:2e9cc70d1897	254	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	125:2e9cc70d1897	255	\li to specify the access to peripheral variables.
AnnaBridge	125:2e9cc70d1897	256	\li for automatic generation of peripheral register debug information.
AnnaBridge	125:2e9cc70d1897	257	*/
AnnaBridge	125:2e9cc70d1897	258	#ifdef __cplusplus
AnnaBridge	125:2e9cc70d1897	259	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	125:2e9cc70d1897	260	#else
AnnaBridge	125:2e9cc70d1897	261	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	125:2e9cc70d1897	262	#endif
AnnaBridge	125:2e9cc70d1897	263	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	125:2e9cc70d1897	264	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	125:2e9cc70d1897	265
AnnaBridge	125:2e9cc70d1897	266	/@} end of group Cortex_M7 /
AnnaBridge	125:2e9cc70d1897	267
AnnaBridge	125:2e9cc70d1897	268
AnnaBridge	125:2e9cc70d1897	269
AnnaBridge	125:2e9cc70d1897	270	/*******************************************************************************
AnnaBridge	125:2e9cc70d1897	271	* Register Abstraction
AnnaBridge	125:2e9cc70d1897	272	Core Register contain:
AnnaBridge	125:2e9cc70d1897	273	- Core Register
AnnaBridge	125:2e9cc70d1897	274	- Core NVIC Register
AnnaBridge	125:2e9cc70d1897	275	- Core SCB Register
AnnaBridge	125:2e9cc70d1897	276	- Core SysTick Register
AnnaBridge	125:2e9cc70d1897	277	- Core Debug Register
AnnaBridge	125:2e9cc70d1897	278	- Core MPU Register
AnnaBridge	125:2e9cc70d1897	279	- Core FPU Register
AnnaBridge	125:2e9cc70d1897	280	******************************************************************************/
AnnaBridge	125:2e9cc70d1897	281	/** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	125:2e9cc70d1897	282	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	125:2e9cc70d1897	283	*/
AnnaBridge	125:2e9cc70d1897	284
AnnaBridge	125:2e9cc70d1897	285	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	286	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	125:2e9cc70d1897	287	\brief Core Register type definitions.
AnnaBridge	125:2e9cc70d1897	288	@{
AnnaBridge	125:2e9cc70d1897	289	*/
AnnaBridge	125:2e9cc70d1897	290
AnnaBridge	125:2e9cc70d1897	291	/** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	125:2e9cc70d1897	292	*/
AnnaBridge	125:2e9cc70d1897	293	typedef union
AnnaBridge	125:2e9cc70d1897	294	{
AnnaBridge	125:2e9cc70d1897	295	struct
AnnaBridge	125:2e9cc70d1897	296	{
AnnaBridge	125:2e9cc70d1897	297	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	125:2e9cc70d1897	298	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	125:2e9cc70d1897	299	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	125:2e9cc70d1897	300	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	125:2e9cc70d1897	301	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	125:2e9cc70d1897	302	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	125:2e9cc70d1897	303	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	125:2e9cc70d1897	304	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	125:2e9cc70d1897	305	} b; /!< Structure used for bit access /
AnnaBridge	125:2e9cc70d1897	306	uint32_t w; /!< Type used for word access /
AnnaBridge	125:2e9cc70d1897	307	} APSR_Type;
AnnaBridge	125:2e9cc70d1897	308
AnnaBridge	125:2e9cc70d1897	309	/* APSR Register Definitions */
AnnaBridge	125:2e9cc70d1897	310	#define APSR_N_Pos 31 /!< APSR: N Position /
AnnaBridge	125:2e9cc70d1897	311	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	125:2e9cc70d1897	312
AnnaBridge	125:2e9cc70d1897	313	#define APSR_Z_Pos 30 /!< APSR: Z Position /
AnnaBridge	125:2e9cc70d1897	314	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	125:2e9cc70d1897	315
AnnaBridge	125:2e9cc70d1897	316	#define APSR_C_Pos 29 /!< APSR: C Position /
AnnaBridge	125:2e9cc70d1897	317	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	125:2e9cc70d1897	318
AnnaBridge	125:2e9cc70d1897	319	#define APSR_V_Pos 28 /!< APSR: V Position /
AnnaBridge	125:2e9cc70d1897	320	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	125:2e9cc70d1897	321
AnnaBridge	125:2e9cc70d1897	322	#define APSR_Q_Pos 27 /!< APSR: Q Position /
AnnaBridge	125:2e9cc70d1897	323	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	125:2e9cc70d1897	324
AnnaBridge	125:2e9cc70d1897	325	#define APSR_GE_Pos 16 /!< APSR: GE Position /
AnnaBridge	125:2e9cc70d1897	326	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	125:2e9cc70d1897	327
AnnaBridge	125:2e9cc70d1897	328
AnnaBridge	125:2e9cc70d1897	329	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	125:2e9cc70d1897	330	*/
AnnaBridge	125:2e9cc70d1897	331	typedef union
AnnaBridge	125:2e9cc70d1897	332	{
AnnaBridge	125:2e9cc70d1897	333	struct
AnnaBridge	125:2e9cc70d1897	334	{
AnnaBridge	125:2e9cc70d1897	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	125:2e9cc70d1897	336	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	125:2e9cc70d1897	337	} b; /!< Structure used for bit access /
AnnaBridge	125:2e9cc70d1897	338	uint32_t w; /!< Type used for word access /
AnnaBridge	125:2e9cc70d1897	339	} IPSR_Type;
AnnaBridge	125:2e9cc70d1897	340
AnnaBridge	125:2e9cc70d1897	341	/* IPSR Register Definitions */
AnnaBridge	125:2e9cc70d1897	342	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
AnnaBridge	125:2e9cc70d1897	343	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	125:2e9cc70d1897	344
AnnaBridge	125:2e9cc70d1897	345
AnnaBridge	125:2e9cc70d1897	346	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	125:2e9cc70d1897	347	*/
AnnaBridge	125:2e9cc70d1897	348	typedef union
AnnaBridge	125:2e9cc70d1897	349	{
AnnaBridge	125:2e9cc70d1897	350	struct
AnnaBridge	125:2e9cc70d1897	351	{
AnnaBridge	125:2e9cc70d1897	352	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	125:2e9cc70d1897	353	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
AnnaBridge	125:2e9cc70d1897	354	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	125:2e9cc70d1897	355	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	125:2e9cc70d1897	356	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	125:2e9cc70d1897	357	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
AnnaBridge	125:2e9cc70d1897	358	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	125:2e9cc70d1897	359	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	125:2e9cc70d1897	360	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	125:2e9cc70d1897	361	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	125:2e9cc70d1897	362	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	125:2e9cc70d1897	363	} b; /!< Structure used for bit access /
AnnaBridge	125:2e9cc70d1897	364	uint32_t w; /!< Type used for word access /
AnnaBridge	125:2e9cc70d1897	365	} xPSR_Type;
AnnaBridge	125:2e9cc70d1897	366
AnnaBridge	125:2e9cc70d1897	367	/* xPSR Register Definitions */
AnnaBridge	125:2e9cc70d1897	368	#define xPSR_N_Pos 31 /!< xPSR: N Position /
AnnaBridge	125:2e9cc70d1897	369	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	125:2e9cc70d1897	370
AnnaBridge	125:2e9cc70d1897	371	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
AnnaBridge	125:2e9cc70d1897	372	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	125:2e9cc70d1897	373
AnnaBridge	125:2e9cc70d1897	374	#define xPSR_C_Pos 29 /!< xPSR: C Position /
AnnaBridge	125:2e9cc70d1897	375	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	125:2e9cc70d1897	376
AnnaBridge	125:2e9cc70d1897	377	#define xPSR_V_Pos 28 /!< xPSR: V Position /
AnnaBridge	125:2e9cc70d1897	378	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	125:2e9cc70d1897	379
AnnaBridge	125:2e9cc70d1897	380	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
AnnaBridge	125:2e9cc70d1897	381	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	125:2e9cc70d1897	382
AnnaBridge	125:2e9cc70d1897	383	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
AnnaBridge	125:2e9cc70d1897	384	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
AnnaBridge	125:2e9cc70d1897	385
AnnaBridge	125:2e9cc70d1897	386	#define xPSR_T_Pos 24 /!< xPSR: T Position /
AnnaBridge	125:2e9cc70d1897	387	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	125:2e9cc70d1897	388
AnnaBridge	125:2e9cc70d1897	389	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
AnnaBridge	125:2e9cc70d1897	390	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	125:2e9cc70d1897	391
AnnaBridge	125:2e9cc70d1897	392	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
AnnaBridge	125:2e9cc70d1897	393	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	125:2e9cc70d1897	394
AnnaBridge	125:2e9cc70d1897	395
AnnaBridge	125:2e9cc70d1897	396	/** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge	125:2e9cc70d1897	397	*/
AnnaBridge	125:2e9cc70d1897	398	typedef union
AnnaBridge	125:2e9cc70d1897	399	{
AnnaBridge	125:2e9cc70d1897	400	struct
AnnaBridge	125:2e9cc70d1897	401	{
AnnaBridge	125:2e9cc70d1897	402	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	125:2e9cc70d1897	403	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	125:2e9cc70d1897	404	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	125:2e9cc70d1897	405	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	125:2e9cc70d1897	406	} b; /!< Structure used for bit access /
AnnaBridge	125:2e9cc70d1897	407	uint32_t w; /!< Type used for word access /
AnnaBridge	125:2e9cc70d1897	408	} CONTROL_Type;
AnnaBridge	125:2e9cc70d1897	409
AnnaBridge	125:2e9cc70d1897	410	/* CONTROL Register Definitions */
AnnaBridge	125:2e9cc70d1897	411	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
AnnaBridge	125:2e9cc70d1897	412	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	125:2e9cc70d1897	413
AnnaBridge	125:2e9cc70d1897	414	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
AnnaBridge	125:2e9cc70d1897	415	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	125:2e9cc70d1897	416
AnnaBridge	125:2e9cc70d1897	417	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
AnnaBridge	125:2e9cc70d1897	418	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	125:2e9cc70d1897	419
AnnaBridge	125:2e9cc70d1897	420	/@} end of group CMSIS_CORE /
AnnaBridge	125:2e9cc70d1897	421
AnnaBridge	125:2e9cc70d1897	422
AnnaBridge	125:2e9cc70d1897	423	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	424	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	125:2e9cc70d1897	425	\brief Type definitions for the NVIC Registers
AnnaBridge	125:2e9cc70d1897	426	@{
AnnaBridge	125:2e9cc70d1897	427	*/
AnnaBridge	125:2e9cc70d1897	428
AnnaBridge	125:2e9cc70d1897	429	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	125:2e9cc70d1897	430	*/
AnnaBridge	125:2e9cc70d1897	431	typedef struct
AnnaBridge	125:2e9cc70d1897	432	{
AnnaBridge	125:2e9cc70d1897	433	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	125:2e9cc70d1897	434	uint32_t RESERVED0[24];
AnnaBridge	125:2e9cc70d1897	435	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	125:2e9cc70d1897	436	uint32_t RSERVED1[24];
AnnaBridge	125:2e9cc70d1897	437	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	125:2e9cc70d1897	438	uint32_t RESERVED2[24];
AnnaBridge	125:2e9cc70d1897	439	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	125:2e9cc70d1897	440	uint32_t RESERVED3[24];
AnnaBridge	125:2e9cc70d1897	441	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	125:2e9cc70d1897	442	uint32_t RESERVED4[56];
AnnaBridge	125:2e9cc70d1897	443	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	125:2e9cc70d1897	444	uint32_t RESERVED5[644];
AnnaBridge	125:2e9cc70d1897	445	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	125:2e9cc70d1897	446	} NVIC_Type;
AnnaBridge	125:2e9cc70d1897	447
AnnaBridge	125:2e9cc70d1897	448	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	125:2e9cc70d1897	449	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
AnnaBridge	125:2e9cc70d1897	450	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	125:2e9cc70d1897	451
AnnaBridge	125:2e9cc70d1897	452	/@} end of group CMSIS_NVIC /
AnnaBridge	125:2e9cc70d1897	453
AnnaBridge	125:2e9cc70d1897	454
AnnaBridge	125:2e9cc70d1897	455	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	456	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	125:2e9cc70d1897	457	\brief Type definitions for the System Control Block Registers
AnnaBridge	125:2e9cc70d1897	458	@{
AnnaBridge	125:2e9cc70d1897	459	*/
AnnaBridge	125:2e9cc70d1897	460
AnnaBridge	125:2e9cc70d1897	461	/** \brief Structure type to access the System Control Block (SCB).
AnnaBridge	125:2e9cc70d1897	462	*/
AnnaBridge	125:2e9cc70d1897	463	typedef struct
AnnaBridge	125:2e9cc70d1897	464	{
AnnaBridge	125:2e9cc70d1897	465	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	125:2e9cc70d1897	466	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	125:2e9cc70d1897	467	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	125:2e9cc70d1897	468	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	125:2e9cc70d1897	469	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	125:2e9cc70d1897	470	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	125:2e9cc70d1897	471	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	125:2e9cc70d1897	472	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	125:2e9cc70d1897	473	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	125:2e9cc70d1897	474	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	125:2e9cc70d1897	475	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	125:2e9cc70d1897	476	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	125:2e9cc70d1897	477	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	125:2e9cc70d1897	478	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	125:2e9cc70d1897	479	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	125:2e9cc70d1897	480	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	125:2e9cc70d1897	481	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	125:2e9cc70d1897	482	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	125:2e9cc70d1897	483	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	125:2e9cc70d1897	484	uint32_t RESERVED0[1];
AnnaBridge	125:2e9cc70d1897	485	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	125:2e9cc70d1897	486	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	125:2e9cc70d1897	487	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	125:2e9cc70d1897	488	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	125:2e9cc70d1897	489	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	125:2e9cc70d1897	490	uint32_t RESERVED3[93];
AnnaBridge	125:2e9cc70d1897	491	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	125:2e9cc70d1897	492	uint32_t RESERVED4[15];
AnnaBridge	125:2e9cc70d1897	493	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	125:2e9cc70d1897	494	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	125:2e9cc70d1897	495	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	125:2e9cc70d1897	496	uint32_t RESERVED5[1];
AnnaBridge	125:2e9cc70d1897	497	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	125:2e9cc70d1897	498	uint32_t RESERVED6[1];
AnnaBridge	125:2e9cc70d1897	499	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	125:2e9cc70d1897	500	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	125:2e9cc70d1897	501	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	125:2e9cc70d1897	502	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	125:2e9cc70d1897	503	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	125:2e9cc70d1897	504	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	125:2e9cc70d1897	505	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	125:2e9cc70d1897	506	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	125:2e9cc70d1897	507	uint32_t RESERVED7[6];
AnnaBridge	125:2e9cc70d1897	508	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	125:2e9cc70d1897	509	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	125:2e9cc70d1897	510	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	125:2e9cc70d1897	511	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	125:2e9cc70d1897	512	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	125:2e9cc70d1897	513	uint32_t RESERVED8[1];
AnnaBridge	125:2e9cc70d1897	514	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
AnnaBridge	125:2e9cc70d1897	515	} SCB_Type;
AnnaBridge	125:2e9cc70d1897	516
AnnaBridge	125:2e9cc70d1897	517	/* SCB CPUID Register Definitions */
AnnaBridge	125:2e9cc70d1897	518	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	125:2e9cc70d1897	519	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	125:2e9cc70d1897	520
AnnaBridge	125:2e9cc70d1897	521	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
AnnaBridge	125:2e9cc70d1897	522	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	125:2e9cc70d1897	523
AnnaBridge	125:2e9cc70d1897	524	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	125:2e9cc70d1897	525	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	125:2e9cc70d1897	526
AnnaBridge	125:2e9cc70d1897	527	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
AnnaBridge	125:2e9cc70d1897	528	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	125:2e9cc70d1897	529
AnnaBridge	125:2e9cc70d1897	530	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
AnnaBridge	125:2e9cc70d1897	531	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	125:2e9cc70d1897	532
AnnaBridge	125:2e9cc70d1897	533	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	125:2e9cc70d1897	534	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	125:2e9cc70d1897	535	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	125:2e9cc70d1897	536
AnnaBridge	125:2e9cc70d1897	537	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	125:2e9cc70d1897	538	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	125:2e9cc70d1897	539
AnnaBridge	125:2e9cc70d1897	540	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	125:2e9cc70d1897	541	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	125:2e9cc70d1897	542
AnnaBridge	125:2e9cc70d1897	543	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	125:2e9cc70d1897	544	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	125:2e9cc70d1897	545
AnnaBridge	125:2e9cc70d1897	546	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	125:2e9cc70d1897	547	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	125:2e9cc70d1897	548
AnnaBridge	125:2e9cc70d1897	549	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	125:2e9cc70d1897	550	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	125:2e9cc70d1897	551
AnnaBridge	125:2e9cc70d1897	552	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	125:2e9cc70d1897	553	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	125:2e9cc70d1897	554
AnnaBridge	125:2e9cc70d1897	555	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	125:2e9cc70d1897	556	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	125:2e9cc70d1897	557
AnnaBridge	125:2e9cc70d1897	558	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	125:2e9cc70d1897	559	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	125:2e9cc70d1897	560
AnnaBridge	125:2e9cc70d1897	561	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	125:2e9cc70d1897	562	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	125:2e9cc70d1897	563
AnnaBridge	125:2e9cc70d1897	564	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	125:2e9cc70d1897	565	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
AnnaBridge	125:2e9cc70d1897	566	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	125:2e9cc70d1897	567
AnnaBridge	125:2e9cc70d1897	568	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	569	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	125:2e9cc70d1897	570	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	125:2e9cc70d1897	571
AnnaBridge	125:2e9cc70d1897	572	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	125:2e9cc70d1897	573	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	125:2e9cc70d1897	574
AnnaBridge	125:2e9cc70d1897	575	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	125:2e9cc70d1897	576	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	125:2e9cc70d1897	577
AnnaBridge	125:2e9cc70d1897	578	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	125:2e9cc70d1897	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	125:2e9cc70d1897	580
AnnaBridge	125:2e9cc70d1897	581	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	125:2e9cc70d1897	582	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	125:2e9cc70d1897	583
AnnaBridge	125:2e9cc70d1897	584	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	125:2e9cc70d1897	585	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	125:2e9cc70d1897	586
AnnaBridge	125:2e9cc70d1897	587	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	125:2e9cc70d1897	588	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	125:2e9cc70d1897	589
AnnaBridge	125:2e9cc70d1897	590	/* SCB System Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	591	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
AnnaBridge	125:2e9cc70d1897	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	125:2e9cc70d1897	593
AnnaBridge	125:2e9cc70d1897	594	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	125:2e9cc70d1897	595	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	125:2e9cc70d1897	596
AnnaBridge	125:2e9cc70d1897	597	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	125:2e9cc70d1897	598	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	125:2e9cc70d1897	599
AnnaBridge	125:2e9cc70d1897	600	/* SCB Configuration Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	601	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
AnnaBridge	125:2e9cc70d1897	602	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
AnnaBridge	125:2e9cc70d1897	603
AnnaBridge	125:2e9cc70d1897	604	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
AnnaBridge	125:2e9cc70d1897	605	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
AnnaBridge	125:2e9cc70d1897	606
AnnaBridge	125:2e9cc70d1897	607	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
AnnaBridge	125:2e9cc70d1897	608	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
AnnaBridge	125:2e9cc70d1897	609
AnnaBridge	125:2e9cc70d1897	610	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
AnnaBridge	125:2e9cc70d1897	611	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	125:2e9cc70d1897	612
AnnaBridge	125:2e9cc70d1897	613	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	125:2e9cc70d1897	614	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	125:2e9cc70d1897	615
AnnaBridge	125:2e9cc70d1897	616	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	125:2e9cc70d1897	617	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	125:2e9cc70d1897	618
AnnaBridge	125:2e9cc70d1897	619	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	125:2e9cc70d1897	620	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	125:2e9cc70d1897	621
AnnaBridge	125:2e9cc70d1897	622	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	125:2e9cc70d1897	623	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	125:2e9cc70d1897	624
AnnaBridge	125:2e9cc70d1897	625	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	125:2e9cc70d1897	626	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	125:2e9cc70d1897	627
AnnaBridge	125:2e9cc70d1897	628	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	125:2e9cc70d1897	629	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	125:2e9cc70d1897	630	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	125:2e9cc70d1897	631
AnnaBridge	125:2e9cc70d1897	632	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	125:2e9cc70d1897	633	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	125:2e9cc70d1897	634
AnnaBridge	125:2e9cc70d1897	635	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	125:2e9cc70d1897	636	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	125:2e9cc70d1897	637
AnnaBridge	125:2e9cc70d1897	638	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	125:2e9cc70d1897	639	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	125:2e9cc70d1897	640
AnnaBridge	125:2e9cc70d1897	641	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	125:2e9cc70d1897	642	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	125:2e9cc70d1897	643
AnnaBridge	125:2e9cc70d1897	644	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	125:2e9cc70d1897	645	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	125:2e9cc70d1897	646
AnnaBridge	125:2e9cc70d1897	647	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	125:2e9cc70d1897	648	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	125:2e9cc70d1897	649
AnnaBridge	125:2e9cc70d1897	650	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	125:2e9cc70d1897	651	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	125:2e9cc70d1897	652
AnnaBridge	125:2e9cc70d1897	653	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	125:2e9cc70d1897	654	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	125:2e9cc70d1897	655
AnnaBridge	125:2e9cc70d1897	656	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	125:2e9cc70d1897	657	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	125:2e9cc70d1897	658
AnnaBridge	125:2e9cc70d1897	659	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	125:2e9cc70d1897	660	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	125:2e9cc70d1897	661
AnnaBridge	125:2e9cc70d1897	662	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	125:2e9cc70d1897	663	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	125:2e9cc70d1897	664
AnnaBridge	125:2e9cc70d1897	665	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	125:2e9cc70d1897	666	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	125:2e9cc70d1897	667
AnnaBridge	125:2e9cc70d1897	668	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	125:2e9cc70d1897	669	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	125:2e9cc70d1897	670
AnnaBridge	125:2e9cc70d1897	671	/* SCB Configurable Fault Status Registers Definitions */
AnnaBridge	125:2e9cc70d1897	672	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	125:2e9cc70d1897	673	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	125:2e9cc70d1897	674
AnnaBridge	125:2e9cc70d1897	675	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	125:2e9cc70d1897	676	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	125:2e9cc70d1897	677
AnnaBridge	125:2e9cc70d1897	678	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	125:2e9cc70d1897	679	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	125:2e9cc70d1897	680
AnnaBridge	125:2e9cc70d1897	681	/* SCB Hard Fault Status Registers Definitions */
AnnaBridge	125:2e9cc70d1897	682	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	125:2e9cc70d1897	683	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	125:2e9cc70d1897	684
AnnaBridge	125:2e9cc70d1897	685	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
AnnaBridge	125:2e9cc70d1897	686	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	125:2e9cc70d1897	687
AnnaBridge	125:2e9cc70d1897	688	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
AnnaBridge	125:2e9cc70d1897	689	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	125:2e9cc70d1897	690
AnnaBridge	125:2e9cc70d1897	691	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	125:2e9cc70d1897	692	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	125:2e9cc70d1897	693	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	125:2e9cc70d1897	694
AnnaBridge	125:2e9cc70d1897	695	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
AnnaBridge	125:2e9cc70d1897	696	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	125:2e9cc70d1897	697
AnnaBridge	125:2e9cc70d1897	698	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	125:2e9cc70d1897	699	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	125:2e9cc70d1897	700
AnnaBridge	125:2e9cc70d1897	701	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
AnnaBridge	125:2e9cc70d1897	702	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	125:2e9cc70d1897	703
AnnaBridge	125:2e9cc70d1897	704	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
AnnaBridge	125:2e9cc70d1897	705	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	125:2e9cc70d1897	706
AnnaBridge	125:2e9cc70d1897	707	/* Cache Level ID register */
AnnaBridge	125:2e9cc70d1897	708	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
AnnaBridge	125:2e9cc70d1897	709	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
AnnaBridge	125:2e9cc70d1897	710
AnnaBridge	125:2e9cc70d1897	711	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
AnnaBridge	125:2e9cc70d1897	712	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	125:2e9cc70d1897	713
AnnaBridge	125:2e9cc70d1897	714	/* Cache Type register */
AnnaBridge	125:2e9cc70d1897	715	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
AnnaBridge	125:2e9cc70d1897	716	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
AnnaBridge	125:2e9cc70d1897	717
AnnaBridge	125:2e9cc70d1897	718	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
AnnaBridge	125:2e9cc70d1897	719	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
AnnaBridge	125:2e9cc70d1897	720
AnnaBridge	125:2e9cc70d1897	721	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
AnnaBridge	125:2e9cc70d1897	722	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
AnnaBridge	125:2e9cc70d1897	723
AnnaBridge	125:2e9cc70d1897	724	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
AnnaBridge	125:2e9cc70d1897	725	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
AnnaBridge	125:2e9cc70d1897	726
AnnaBridge	125:2e9cc70d1897	727	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
AnnaBridge	125:2e9cc70d1897	728	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
AnnaBridge	125:2e9cc70d1897	729
AnnaBridge	125:2e9cc70d1897	730	/* Cache Size ID Register */
AnnaBridge	125:2e9cc70d1897	731	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
AnnaBridge	125:2e9cc70d1897	732	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	125:2e9cc70d1897	733
AnnaBridge	125:2e9cc70d1897	734	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
AnnaBridge	125:2e9cc70d1897	735	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	125:2e9cc70d1897	736
AnnaBridge	125:2e9cc70d1897	737	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
AnnaBridge	125:2e9cc70d1897	738	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	125:2e9cc70d1897	739
AnnaBridge	125:2e9cc70d1897	740	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
AnnaBridge	125:2e9cc70d1897	741	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	125:2e9cc70d1897	742
AnnaBridge	125:2e9cc70d1897	743	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
AnnaBridge	125:2e9cc70d1897	744	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
AnnaBridge	125:2e9cc70d1897	745
AnnaBridge	125:2e9cc70d1897	746	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
AnnaBridge	125:2e9cc70d1897	747	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
AnnaBridge	125:2e9cc70d1897	748
AnnaBridge	125:2e9cc70d1897	749	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
AnnaBridge	125:2e9cc70d1897	750	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
AnnaBridge	125:2e9cc70d1897	751
AnnaBridge	125:2e9cc70d1897	752	/* Cache Size Selection Register */
AnnaBridge	125:2e9cc70d1897	753	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
AnnaBridge	125:2e9cc70d1897	754	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
AnnaBridge	125:2e9cc70d1897	755
AnnaBridge	125:2e9cc70d1897	756	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
AnnaBridge	125:2e9cc70d1897	757	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
AnnaBridge	125:2e9cc70d1897	758
AnnaBridge	125:2e9cc70d1897	759	/* SCB Software Triggered Interrupt Register */
AnnaBridge	125:2e9cc70d1897	760	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
AnnaBridge	125:2e9cc70d1897	761	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
AnnaBridge	125:2e9cc70d1897	762
AnnaBridge	125:2e9cc70d1897	763	/* Instruction Tightly-Coupled Memory Control Register*/
AnnaBridge	125:2e9cc70d1897	764	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
AnnaBridge	125:2e9cc70d1897	765	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
AnnaBridge	125:2e9cc70d1897	766
AnnaBridge	125:2e9cc70d1897	767	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
AnnaBridge	125:2e9cc70d1897	768	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
AnnaBridge	125:2e9cc70d1897	769
AnnaBridge	125:2e9cc70d1897	770	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
AnnaBridge	125:2e9cc70d1897	771	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
AnnaBridge	125:2e9cc70d1897	772
AnnaBridge	125:2e9cc70d1897	773	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
AnnaBridge	125:2e9cc70d1897	774	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
AnnaBridge	125:2e9cc70d1897	775
AnnaBridge	125:2e9cc70d1897	776	/* Data Tightly-Coupled Memory Control Registers */
AnnaBridge	125:2e9cc70d1897	777	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
AnnaBridge	125:2e9cc70d1897	778	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
AnnaBridge	125:2e9cc70d1897	779
AnnaBridge	125:2e9cc70d1897	780	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
AnnaBridge	125:2e9cc70d1897	781	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
AnnaBridge	125:2e9cc70d1897	782
AnnaBridge	125:2e9cc70d1897	783	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
AnnaBridge	125:2e9cc70d1897	784	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
AnnaBridge	125:2e9cc70d1897	785
AnnaBridge	125:2e9cc70d1897	786	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
AnnaBridge	125:2e9cc70d1897	787	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
AnnaBridge	125:2e9cc70d1897	788
AnnaBridge	125:2e9cc70d1897	789	/* AHBP Control Register */
AnnaBridge	125:2e9cc70d1897	790	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
AnnaBridge	125:2e9cc70d1897	791	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
AnnaBridge	125:2e9cc70d1897	792
AnnaBridge	125:2e9cc70d1897	793	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
AnnaBridge	125:2e9cc70d1897	794	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
AnnaBridge	125:2e9cc70d1897	795
AnnaBridge	125:2e9cc70d1897	796	/* L1 Cache Control Register */
AnnaBridge	125:2e9cc70d1897	797	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
AnnaBridge	125:2e9cc70d1897	798	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
AnnaBridge	125:2e9cc70d1897	799
AnnaBridge	125:2e9cc70d1897	800	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
AnnaBridge	125:2e9cc70d1897	801	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
AnnaBridge	125:2e9cc70d1897	802
AnnaBridge	125:2e9cc70d1897	803	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
AnnaBridge	125:2e9cc70d1897	804	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
AnnaBridge	125:2e9cc70d1897	805
AnnaBridge	125:2e9cc70d1897	806	/* AHBS control register */
AnnaBridge	125:2e9cc70d1897	807	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
AnnaBridge	125:2e9cc70d1897	808	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
AnnaBridge	125:2e9cc70d1897	809
AnnaBridge	125:2e9cc70d1897	810	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
AnnaBridge	125:2e9cc70d1897	811	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
AnnaBridge	125:2e9cc70d1897	812
AnnaBridge	125:2e9cc70d1897	813	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
AnnaBridge	125:2e9cc70d1897	814	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
AnnaBridge	125:2e9cc70d1897	815
AnnaBridge	125:2e9cc70d1897	816	/* Auxiliary Bus Fault Status Register */
AnnaBridge	125:2e9cc70d1897	817	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
AnnaBridge	125:2e9cc70d1897	818	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
AnnaBridge	125:2e9cc70d1897	819
AnnaBridge	125:2e9cc70d1897	820	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
AnnaBridge	125:2e9cc70d1897	821	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
AnnaBridge	125:2e9cc70d1897	822
AnnaBridge	125:2e9cc70d1897	823	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
AnnaBridge	125:2e9cc70d1897	824	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
AnnaBridge	125:2e9cc70d1897	825
AnnaBridge	125:2e9cc70d1897	826	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
AnnaBridge	125:2e9cc70d1897	827	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
AnnaBridge	125:2e9cc70d1897	828
AnnaBridge	125:2e9cc70d1897	829	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
AnnaBridge	125:2e9cc70d1897	830	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
AnnaBridge	125:2e9cc70d1897	831
AnnaBridge	125:2e9cc70d1897	832	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
AnnaBridge	125:2e9cc70d1897	833	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
AnnaBridge	125:2e9cc70d1897	834
AnnaBridge	125:2e9cc70d1897	835	/@} end of group CMSIS_SCB /
AnnaBridge	125:2e9cc70d1897	836
AnnaBridge	125:2e9cc70d1897	837
AnnaBridge	125:2e9cc70d1897	838	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	839	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	125:2e9cc70d1897	840	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	125:2e9cc70d1897	841	@{
AnnaBridge	125:2e9cc70d1897	842	*/
AnnaBridge	125:2e9cc70d1897	843
AnnaBridge	125:2e9cc70d1897	844	/** \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	125:2e9cc70d1897	845	*/
AnnaBridge	125:2e9cc70d1897	846	typedef struct
AnnaBridge	125:2e9cc70d1897	847	{
AnnaBridge	125:2e9cc70d1897	848	uint32_t RESERVED0[1];
AnnaBridge	125:2e9cc70d1897	849	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	125:2e9cc70d1897	850	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	125:2e9cc70d1897	851	} SCnSCB_Type;
AnnaBridge	125:2e9cc70d1897	852
AnnaBridge	125:2e9cc70d1897	853	/* Interrupt Controller Type Register Definitions */
AnnaBridge	125:2e9cc70d1897	854	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
AnnaBridge	125:2e9cc70d1897	855	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	125:2e9cc70d1897	856
AnnaBridge	125:2e9cc70d1897	857	/* Auxiliary Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	858	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
AnnaBridge	125:2e9cc70d1897	859	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
AnnaBridge	125:2e9cc70d1897	860
AnnaBridge	125:2e9cc70d1897	861	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
AnnaBridge	125:2e9cc70d1897	862	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
AnnaBridge	125:2e9cc70d1897	863
AnnaBridge	125:2e9cc70d1897	864	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
AnnaBridge	125:2e9cc70d1897	865	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
AnnaBridge	125:2e9cc70d1897	866
AnnaBridge	125:2e9cc70d1897	867	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
AnnaBridge	125:2e9cc70d1897	868	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	125:2e9cc70d1897	869
AnnaBridge	125:2e9cc70d1897	870	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
AnnaBridge	125:2e9cc70d1897	871	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	125:2e9cc70d1897	872
AnnaBridge	125:2e9cc70d1897	873	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	125:2e9cc70d1897	874
AnnaBridge	125:2e9cc70d1897	875
AnnaBridge	125:2e9cc70d1897	876	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	877	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	125:2e9cc70d1897	878	\brief Type definitions for the System Timer Registers.
AnnaBridge	125:2e9cc70d1897	879	@{
AnnaBridge	125:2e9cc70d1897	880	*/
AnnaBridge	125:2e9cc70d1897	881
AnnaBridge	125:2e9cc70d1897	882	/** \brief Structure type to access the System Timer (SysTick).
AnnaBridge	125:2e9cc70d1897	883	*/
AnnaBridge	125:2e9cc70d1897	884	typedef struct
AnnaBridge	125:2e9cc70d1897	885	{
AnnaBridge	125:2e9cc70d1897	886	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	125:2e9cc70d1897	887	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	125:2e9cc70d1897	888	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	125:2e9cc70d1897	889	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	125:2e9cc70d1897	890	} SysTick_Type;
AnnaBridge	125:2e9cc70d1897	891
AnnaBridge	125:2e9cc70d1897	892	/* SysTick Control / Status Register Definitions */
AnnaBridge	125:2e9cc70d1897	893	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	125:2e9cc70d1897	894	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	125:2e9cc70d1897	895
AnnaBridge	125:2e9cc70d1897	896	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	125:2e9cc70d1897	897	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	125:2e9cc70d1897	898
AnnaBridge	125:2e9cc70d1897	899	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
AnnaBridge	125:2e9cc70d1897	900	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	125:2e9cc70d1897	901
AnnaBridge	125:2e9cc70d1897	902	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
AnnaBridge	125:2e9cc70d1897	903	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	125:2e9cc70d1897	904
AnnaBridge	125:2e9cc70d1897	905	/* SysTick Reload Register Definitions */
AnnaBridge	125:2e9cc70d1897	906	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
AnnaBridge	125:2e9cc70d1897	907	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	125:2e9cc70d1897	908
AnnaBridge	125:2e9cc70d1897	909	/* SysTick Current Register Definitions */
AnnaBridge	125:2e9cc70d1897	910	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
AnnaBridge	125:2e9cc70d1897	911	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	125:2e9cc70d1897	912
AnnaBridge	125:2e9cc70d1897	913	/* SysTick Calibration Register Definitions */
AnnaBridge	125:2e9cc70d1897	914	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
AnnaBridge	125:2e9cc70d1897	915	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	125:2e9cc70d1897	916
AnnaBridge	125:2e9cc70d1897	917	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
AnnaBridge	125:2e9cc70d1897	918	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	125:2e9cc70d1897	919
AnnaBridge	125:2e9cc70d1897	920	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
AnnaBridge	125:2e9cc70d1897	921	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	125:2e9cc70d1897	922
AnnaBridge	125:2e9cc70d1897	923	/@} end of group CMSIS_SysTick /
AnnaBridge	125:2e9cc70d1897	924
AnnaBridge	125:2e9cc70d1897	925
AnnaBridge	125:2e9cc70d1897	926	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	927	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	125:2e9cc70d1897	928	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	125:2e9cc70d1897	929	@{
AnnaBridge	125:2e9cc70d1897	930	*/
AnnaBridge	125:2e9cc70d1897	931
AnnaBridge	125:2e9cc70d1897	932	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	125:2e9cc70d1897	933	*/
AnnaBridge	125:2e9cc70d1897	934	typedef struct
AnnaBridge	125:2e9cc70d1897	935	{
AnnaBridge	125:2e9cc70d1897	936	__O union
AnnaBridge	125:2e9cc70d1897	937	{
AnnaBridge	125:2e9cc70d1897	938	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	125:2e9cc70d1897	939	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	125:2e9cc70d1897	940	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	125:2e9cc70d1897	941	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	125:2e9cc70d1897	942	uint32_t RESERVED0[864];
AnnaBridge	125:2e9cc70d1897	943	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	125:2e9cc70d1897	944	uint32_t RESERVED1[15];
AnnaBridge	125:2e9cc70d1897	945	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	125:2e9cc70d1897	946	uint32_t RESERVED2[15];
AnnaBridge	125:2e9cc70d1897	947	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	125:2e9cc70d1897	948	uint32_t RESERVED3[29];
AnnaBridge	125:2e9cc70d1897	949	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	125:2e9cc70d1897	950	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	125:2e9cc70d1897	951	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	125:2e9cc70d1897	952	uint32_t RESERVED4[43];
AnnaBridge	125:2e9cc70d1897	953	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	125:2e9cc70d1897	954	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	125:2e9cc70d1897	955	uint32_t RESERVED5[6];
AnnaBridge	125:2e9cc70d1897	956	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	125:2e9cc70d1897	957	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	125:2e9cc70d1897	958	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	125:2e9cc70d1897	959	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	125:2e9cc70d1897	960	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	125:2e9cc70d1897	961	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	125:2e9cc70d1897	962	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	125:2e9cc70d1897	963	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	125:2e9cc70d1897	964	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	125:2e9cc70d1897	965	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	125:2e9cc70d1897	966	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	125:2e9cc70d1897	967	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	125:2e9cc70d1897	968	} ITM_Type;
AnnaBridge	125:2e9cc70d1897	969
AnnaBridge	125:2e9cc70d1897	970	/* ITM Trace Privilege Register Definitions */
AnnaBridge	125:2e9cc70d1897	971	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
AnnaBridge	125:2e9cc70d1897	972	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	125:2e9cc70d1897	973
AnnaBridge	125:2e9cc70d1897	974	/* ITM Trace Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	975	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
AnnaBridge	125:2e9cc70d1897	976	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	125:2e9cc70d1897	977
AnnaBridge	125:2e9cc70d1897	978	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
AnnaBridge	125:2e9cc70d1897	979	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	125:2e9cc70d1897	980
AnnaBridge	125:2e9cc70d1897	981	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	125:2e9cc70d1897	982	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	125:2e9cc70d1897	983
AnnaBridge	125:2e9cc70d1897	984	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
AnnaBridge	125:2e9cc70d1897	985	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	125:2e9cc70d1897	986
AnnaBridge	125:2e9cc70d1897	987	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
AnnaBridge	125:2e9cc70d1897	988	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	125:2e9cc70d1897	989
AnnaBridge	125:2e9cc70d1897	990	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
AnnaBridge	125:2e9cc70d1897	991	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	125:2e9cc70d1897	992
AnnaBridge	125:2e9cc70d1897	993	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
AnnaBridge	125:2e9cc70d1897	994	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	125:2e9cc70d1897	995
AnnaBridge	125:2e9cc70d1897	996	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
AnnaBridge	125:2e9cc70d1897	997	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	125:2e9cc70d1897	998
AnnaBridge	125:2e9cc70d1897	999	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	125:2e9cc70d1897	1000	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	125:2e9cc70d1897	1001
AnnaBridge	125:2e9cc70d1897	1002	/* ITM Integration Write Register Definitions */
AnnaBridge	125:2e9cc70d1897	1003	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
AnnaBridge	125:2e9cc70d1897	1004	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	125:2e9cc70d1897	1005
AnnaBridge	125:2e9cc70d1897	1006	/* ITM Integration Read Register Definitions */
AnnaBridge	125:2e9cc70d1897	1007	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
AnnaBridge	125:2e9cc70d1897	1008	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	125:2e9cc70d1897	1009
AnnaBridge	125:2e9cc70d1897	1010	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	1011	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	125:2e9cc70d1897	1012	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	125:2e9cc70d1897	1013
AnnaBridge	125:2e9cc70d1897	1014	/* ITM Lock Status Register Definitions */
AnnaBridge	125:2e9cc70d1897	1015	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
AnnaBridge	125:2e9cc70d1897	1016	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	125:2e9cc70d1897	1017
AnnaBridge	125:2e9cc70d1897	1018	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
AnnaBridge	125:2e9cc70d1897	1019	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	125:2e9cc70d1897	1020
AnnaBridge	125:2e9cc70d1897	1021	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
AnnaBridge	125:2e9cc70d1897	1022	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	125:2e9cc70d1897	1023
AnnaBridge	125:2e9cc70d1897	1024	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	125:2e9cc70d1897	1025
AnnaBridge	125:2e9cc70d1897	1026
AnnaBridge	125:2e9cc70d1897	1027	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	1028	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	125:2e9cc70d1897	1029	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	125:2e9cc70d1897	1030	@{
AnnaBridge	125:2e9cc70d1897	1031	*/
AnnaBridge	125:2e9cc70d1897	1032
AnnaBridge	125:2e9cc70d1897	1033	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	125:2e9cc70d1897	1034	*/
AnnaBridge	125:2e9cc70d1897	1035	typedef struct
AnnaBridge	125:2e9cc70d1897	1036	{
AnnaBridge	125:2e9cc70d1897	1037	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	125:2e9cc70d1897	1038	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	125:2e9cc70d1897	1039	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	125:2e9cc70d1897	1040	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	125:2e9cc70d1897	1041	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	125:2e9cc70d1897	1042	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	125:2e9cc70d1897	1043	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	125:2e9cc70d1897	1044	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	125:2e9cc70d1897	1045	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	125:2e9cc70d1897	1046	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	125:2e9cc70d1897	1047	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	125:2e9cc70d1897	1048	uint32_t RESERVED0[1];
AnnaBridge	125:2e9cc70d1897	1049	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	125:2e9cc70d1897	1050	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	125:2e9cc70d1897	1051	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	125:2e9cc70d1897	1052	uint32_t RESERVED1[1];
AnnaBridge	125:2e9cc70d1897	1053	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	125:2e9cc70d1897	1054	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	125:2e9cc70d1897	1055	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	125:2e9cc70d1897	1056	uint32_t RESERVED2[1];
AnnaBridge	125:2e9cc70d1897	1057	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	125:2e9cc70d1897	1058	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	125:2e9cc70d1897	1059	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	125:2e9cc70d1897	1060	uint32_t RESERVED3[981];
AnnaBridge	125:2e9cc70d1897	1061	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
AnnaBridge	125:2e9cc70d1897	1062	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
AnnaBridge	125:2e9cc70d1897	1063	} DWT_Type;
AnnaBridge	125:2e9cc70d1897	1064
AnnaBridge	125:2e9cc70d1897	1065	/* DWT Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	1066	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	125:2e9cc70d1897	1067	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	125:2e9cc70d1897	1068
AnnaBridge	125:2e9cc70d1897	1069	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	125:2e9cc70d1897	1070	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	125:2e9cc70d1897	1071
AnnaBridge	125:2e9cc70d1897	1072	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	125:2e9cc70d1897	1073	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	125:2e9cc70d1897	1074
AnnaBridge	125:2e9cc70d1897	1075	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	125:2e9cc70d1897	1076	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	125:2e9cc70d1897	1077
AnnaBridge	125:2e9cc70d1897	1078	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	125:2e9cc70d1897	1079	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	125:2e9cc70d1897	1080
AnnaBridge	125:2e9cc70d1897	1081	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	125:2e9cc70d1897	1082	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	125:2e9cc70d1897	1083
AnnaBridge	125:2e9cc70d1897	1084	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	125:2e9cc70d1897	1085	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	125:2e9cc70d1897	1086
AnnaBridge	125:2e9cc70d1897	1087	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	125:2e9cc70d1897	1088	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	125:2e9cc70d1897	1089
AnnaBridge	125:2e9cc70d1897	1090	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	125:2e9cc70d1897	1091	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	125:2e9cc70d1897	1092
AnnaBridge	125:2e9cc70d1897	1093	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	125:2e9cc70d1897	1094	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	125:2e9cc70d1897	1095
AnnaBridge	125:2e9cc70d1897	1096	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	125:2e9cc70d1897	1097	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	125:2e9cc70d1897	1098
AnnaBridge	125:2e9cc70d1897	1099	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	125:2e9cc70d1897	1100	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	125:2e9cc70d1897	1101
AnnaBridge	125:2e9cc70d1897	1102	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	125:2e9cc70d1897	1103	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	125:2e9cc70d1897	1104
AnnaBridge	125:2e9cc70d1897	1105	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	125:2e9cc70d1897	1106	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	125:2e9cc70d1897	1107
AnnaBridge	125:2e9cc70d1897	1108	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
AnnaBridge	125:2e9cc70d1897	1109	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	125:2e9cc70d1897	1110
AnnaBridge	125:2e9cc70d1897	1111	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
AnnaBridge	125:2e9cc70d1897	1112	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	125:2e9cc70d1897	1113
AnnaBridge	125:2e9cc70d1897	1114	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	125:2e9cc70d1897	1115	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	125:2e9cc70d1897	1116
AnnaBridge	125:2e9cc70d1897	1117	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	125:2e9cc70d1897	1118	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	125:2e9cc70d1897	1119
AnnaBridge	125:2e9cc70d1897	1120	/* DWT CPI Count Register Definitions */
AnnaBridge	125:2e9cc70d1897	1121	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
AnnaBridge	125:2e9cc70d1897	1122	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	125:2e9cc70d1897	1123
AnnaBridge	125:2e9cc70d1897	1124	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	125:2e9cc70d1897	1125	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	125:2e9cc70d1897	1126	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	125:2e9cc70d1897	1127
AnnaBridge	125:2e9cc70d1897	1128	/* DWT Sleep Count Register Definitions */
AnnaBridge	125:2e9cc70d1897	1129	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	125:2e9cc70d1897	1130	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	125:2e9cc70d1897	1131
AnnaBridge	125:2e9cc70d1897	1132	/* DWT LSU Count Register Definitions */
AnnaBridge	125:2e9cc70d1897	1133	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	125:2e9cc70d1897	1134	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	125:2e9cc70d1897	1135
AnnaBridge	125:2e9cc70d1897	1136	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	125:2e9cc70d1897	1137	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	125:2e9cc70d1897	1138	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	125:2e9cc70d1897	1139
AnnaBridge	125:2e9cc70d1897	1140	/* DWT Comparator Mask Register Definitions */
AnnaBridge	125:2e9cc70d1897	1141	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
AnnaBridge	125:2e9cc70d1897	1142	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	125:2e9cc70d1897	1143
AnnaBridge	125:2e9cc70d1897	1144	/* DWT Comparator Function Register Definitions */
AnnaBridge	125:2e9cc70d1897	1145	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	125:2e9cc70d1897	1146	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	125:2e9cc70d1897	1147
AnnaBridge	125:2e9cc70d1897	1148	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	125:2e9cc70d1897	1149	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	125:2e9cc70d1897	1150
AnnaBridge	125:2e9cc70d1897	1151	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	125:2e9cc70d1897	1152	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	125:2e9cc70d1897	1153
AnnaBridge	125:2e9cc70d1897	1154	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	125:2e9cc70d1897	1155	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	125:2e9cc70d1897	1156
AnnaBridge	125:2e9cc70d1897	1157	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	125:2e9cc70d1897	1158	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	125:2e9cc70d1897	1159
AnnaBridge	125:2e9cc70d1897	1160	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	125:2e9cc70d1897	1161	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	125:2e9cc70d1897	1162
AnnaBridge	125:2e9cc70d1897	1163	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	125:2e9cc70d1897	1164	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	125:2e9cc70d1897	1165
AnnaBridge	125:2e9cc70d1897	1166	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	125:2e9cc70d1897	1167	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	125:2e9cc70d1897	1168
AnnaBridge	125:2e9cc70d1897	1169	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	125:2e9cc70d1897	1170	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	125:2e9cc70d1897	1171
AnnaBridge	125:2e9cc70d1897	1172	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	125:2e9cc70d1897	1173
AnnaBridge	125:2e9cc70d1897	1174
AnnaBridge	125:2e9cc70d1897	1175	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	1176	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	125:2e9cc70d1897	1177	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	125:2e9cc70d1897	1178	@{
AnnaBridge	125:2e9cc70d1897	1179	*/
AnnaBridge	125:2e9cc70d1897	1180
AnnaBridge	125:2e9cc70d1897	1181	/** \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	125:2e9cc70d1897	1182	*/
AnnaBridge	125:2e9cc70d1897	1183	typedef struct
AnnaBridge	125:2e9cc70d1897	1184	{
AnnaBridge	125:2e9cc70d1897	1185	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	125:2e9cc70d1897	1186	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	125:2e9cc70d1897	1187	uint32_t RESERVED0[2];
AnnaBridge	125:2e9cc70d1897	1188	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	125:2e9cc70d1897	1189	uint32_t RESERVED1[55];
AnnaBridge	125:2e9cc70d1897	1190	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	125:2e9cc70d1897	1191	uint32_t RESERVED2[131];
AnnaBridge	125:2e9cc70d1897	1192	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	125:2e9cc70d1897	1193	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	125:2e9cc70d1897	1194	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	125:2e9cc70d1897	1195	uint32_t RESERVED3[759];
AnnaBridge	125:2e9cc70d1897	1196	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	125:2e9cc70d1897	1197	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	125:2e9cc70d1897	1198	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	125:2e9cc70d1897	1199	uint32_t RESERVED4[1];
AnnaBridge	125:2e9cc70d1897	1200	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	125:2e9cc70d1897	1201	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	125:2e9cc70d1897	1202	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	125:2e9cc70d1897	1203	uint32_t RESERVED5[39];
AnnaBridge	125:2e9cc70d1897	1204	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	125:2e9cc70d1897	1205	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	125:2e9cc70d1897	1206	uint32_t RESERVED7[8];
AnnaBridge	125:2e9cc70d1897	1207	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	125:2e9cc70d1897	1208	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	125:2e9cc70d1897	1209	} TPI_Type;
AnnaBridge	125:2e9cc70d1897	1210
AnnaBridge	125:2e9cc70d1897	1211	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	125:2e9cc70d1897	1212	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
AnnaBridge	125:2e9cc70d1897	1213	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	125:2e9cc70d1897	1214
AnnaBridge	125:2e9cc70d1897	1215	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	125:2e9cc70d1897	1216	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
AnnaBridge	125:2e9cc70d1897	1217	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	125:2e9cc70d1897	1218
AnnaBridge	125:2e9cc70d1897	1219	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	125:2e9cc70d1897	1220	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
AnnaBridge	125:2e9cc70d1897	1221	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	125:2e9cc70d1897	1222
AnnaBridge	125:2e9cc70d1897	1223	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
AnnaBridge	125:2e9cc70d1897	1224	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	125:2e9cc70d1897	1225
AnnaBridge	125:2e9cc70d1897	1226	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
AnnaBridge	125:2e9cc70d1897	1227	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	125:2e9cc70d1897	1228
AnnaBridge	125:2e9cc70d1897	1229	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
AnnaBridge	125:2e9cc70d1897	1230	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	125:2e9cc70d1897	1231
AnnaBridge	125:2e9cc70d1897	1232	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	1233	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
AnnaBridge	125:2e9cc70d1897	1234	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	125:2e9cc70d1897	1235
AnnaBridge	125:2e9cc70d1897	1236	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
AnnaBridge	125:2e9cc70d1897	1237	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	125:2e9cc70d1897	1238
AnnaBridge	125:2e9cc70d1897	1239	/* TPI TRIGGER Register Definitions */
AnnaBridge	125:2e9cc70d1897	1240	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	125:2e9cc70d1897	1241	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	125:2e9cc70d1897	1242
AnnaBridge	125:2e9cc70d1897	1243	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	125:2e9cc70d1897	1244	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	125:2e9cc70d1897	1245	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	125:2e9cc70d1897	1246
AnnaBridge	125:2e9cc70d1897	1247	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	125:2e9cc70d1897	1248	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	125:2e9cc70d1897	1249
AnnaBridge	125:2e9cc70d1897	1250	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	125:2e9cc70d1897	1251	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	125:2e9cc70d1897	1252
AnnaBridge	125:2e9cc70d1897	1253	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	125:2e9cc70d1897	1254	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	125:2e9cc70d1897	1255
AnnaBridge	125:2e9cc70d1897	1256	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
AnnaBridge	125:2e9cc70d1897	1257	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	125:2e9cc70d1897	1258
AnnaBridge	125:2e9cc70d1897	1259	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
AnnaBridge	125:2e9cc70d1897	1260	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	125:2e9cc70d1897	1261
AnnaBridge	125:2e9cc70d1897	1262	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
AnnaBridge	125:2e9cc70d1897	1263	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	125:2e9cc70d1897	1264
AnnaBridge	125:2e9cc70d1897	1265	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	125:2e9cc70d1897	1266	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	125:2e9cc70d1897	1267	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	125:2e9cc70d1897	1268
AnnaBridge	125:2e9cc70d1897	1269	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	125:2e9cc70d1897	1270	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	125:2e9cc70d1897	1271	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	125:2e9cc70d1897	1272
AnnaBridge	125:2e9cc70d1897	1273	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	125:2e9cc70d1897	1274	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	125:2e9cc70d1897	1275
AnnaBridge	125:2e9cc70d1897	1276	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	125:2e9cc70d1897	1277	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	125:2e9cc70d1897	1278
AnnaBridge	125:2e9cc70d1897	1279	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	125:2e9cc70d1897	1280	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	125:2e9cc70d1897	1281
AnnaBridge	125:2e9cc70d1897	1282	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
AnnaBridge	125:2e9cc70d1897	1283	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	125:2e9cc70d1897	1284
AnnaBridge	125:2e9cc70d1897	1285	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
AnnaBridge	125:2e9cc70d1897	1286	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	125:2e9cc70d1897	1287
AnnaBridge	125:2e9cc70d1897	1288	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
AnnaBridge	125:2e9cc70d1897	1289	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	125:2e9cc70d1897	1290
AnnaBridge	125:2e9cc70d1897	1291	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	125:2e9cc70d1897	1292	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	125:2e9cc70d1897	1293	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	125:2e9cc70d1897	1294
AnnaBridge	125:2e9cc70d1897	1295	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	125:2e9cc70d1897	1296	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
AnnaBridge	125:2e9cc70d1897	1297	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	125:2e9cc70d1897	1298
AnnaBridge	125:2e9cc70d1897	1299	/* TPI DEVID Register Definitions */
AnnaBridge	125:2e9cc70d1897	1300	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
AnnaBridge	125:2e9cc70d1897	1301	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	125:2e9cc70d1897	1302
AnnaBridge	125:2e9cc70d1897	1303	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
AnnaBridge	125:2e9cc70d1897	1304	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	125:2e9cc70d1897	1305
AnnaBridge	125:2e9cc70d1897	1306	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
AnnaBridge	125:2e9cc70d1897	1307	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	125:2e9cc70d1897	1308
AnnaBridge	125:2e9cc70d1897	1309	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
AnnaBridge	125:2e9cc70d1897	1310	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	125:2e9cc70d1897	1311
AnnaBridge	125:2e9cc70d1897	1312	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	125:2e9cc70d1897	1313	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	125:2e9cc70d1897	1314
AnnaBridge	125:2e9cc70d1897	1315	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	125:2e9cc70d1897	1316	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	125:2e9cc70d1897	1317
AnnaBridge	125:2e9cc70d1897	1318	/* TPI DEVTYPE Register Definitions */
AnnaBridge	125:2e9cc70d1897	1319	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	125:2e9cc70d1897	1320	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	125:2e9cc70d1897	1321
AnnaBridge	125:2e9cc70d1897	1322	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
AnnaBridge	125:2e9cc70d1897	1323	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	125:2e9cc70d1897	1324
AnnaBridge	125:2e9cc70d1897	1325	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	125:2e9cc70d1897	1326
AnnaBridge	125:2e9cc70d1897	1327
AnnaBridge	125:2e9cc70d1897	1328	#if (__MPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	1329	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	1330	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	125:2e9cc70d1897	1331	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	125:2e9cc70d1897	1332	@{
AnnaBridge	125:2e9cc70d1897	1333	*/
AnnaBridge	125:2e9cc70d1897	1334
AnnaBridge	125:2e9cc70d1897	1335	/** \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	125:2e9cc70d1897	1336	*/
AnnaBridge	125:2e9cc70d1897	1337	typedef struct
AnnaBridge	125:2e9cc70d1897	1338	{
AnnaBridge	125:2e9cc70d1897	1339	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	125:2e9cc70d1897	1340	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	125:2e9cc70d1897	1341	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	125:2e9cc70d1897	1342	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	125:2e9cc70d1897	1343	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	125:2e9cc70d1897	1344	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	125:2e9cc70d1897	1345	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	125:2e9cc70d1897	1346	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	125:2e9cc70d1897	1347	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	125:2e9cc70d1897	1348	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	125:2e9cc70d1897	1349	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	125:2e9cc70d1897	1350	} MPU_Type;
AnnaBridge	125:2e9cc70d1897	1351
AnnaBridge	125:2e9cc70d1897	1352	/* MPU Type Register */
AnnaBridge	125:2e9cc70d1897	1353	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
AnnaBridge	125:2e9cc70d1897	1354	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	125:2e9cc70d1897	1355
AnnaBridge	125:2e9cc70d1897	1356	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
AnnaBridge	125:2e9cc70d1897	1357	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	125:2e9cc70d1897	1358
AnnaBridge	125:2e9cc70d1897	1359	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
AnnaBridge	125:2e9cc70d1897	1360	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	125:2e9cc70d1897	1361
AnnaBridge	125:2e9cc70d1897	1362	/* MPU Control Register */
AnnaBridge	125:2e9cc70d1897	1363	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	125:2e9cc70d1897	1364	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	125:2e9cc70d1897	1365
AnnaBridge	125:2e9cc70d1897	1366	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	125:2e9cc70d1897	1367	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	125:2e9cc70d1897	1368
AnnaBridge	125:2e9cc70d1897	1369	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
AnnaBridge	125:2e9cc70d1897	1370	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	125:2e9cc70d1897	1371
AnnaBridge	125:2e9cc70d1897	1372	/* MPU Region Number Register */
AnnaBridge	125:2e9cc70d1897	1373	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
AnnaBridge	125:2e9cc70d1897	1374	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	125:2e9cc70d1897	1375
AnnaBridge	125:2e9cc70d1897	1376	/* MPU Region Base Address Register */
AnnaBridge	125:2e9cc70d1897	1377	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
AnnaBridge	125:2e9cc70d1897	1378	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	125:2e9cc70d1897	1379
AnnaBridge	125:2e9cc70d1897	1380	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
AnnaBridge	125:2e9cc70d1897	1381	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	125:2e9cc70d1897	1382
AnnaBridge	125:2e9cc70d1897	1383	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
AnnaBridge	125:2e9cc70d1897	1384	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	125:2e9cc70d1897	1385
AnnaBridge	125:2e9cc70d1897	1386	/* MPU Region Attribute and Size Register */
AnnaBridge	125:2e9cc70d1897	1387	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	125:2e9cc70d1897	1388	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	125:2e9cc70d1897	1389
AnnaBridge	125:2e9cc70d1897	1390	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	125:2e9cc70d1897	1391	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	125:2e9cc70d1897	1392
AnnaBridge	125:2e9cc70d1897	1393	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	125:2e9cc70d1897	1394	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	125:2e9cc70d1897	1395
AnnaBridge	125:2e9cc70d1897	1396	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	125:2e9cc70d1897	1397	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	125:2e9cc70d1897	1398
AnnaBridge	125:2e9cc70d1897	1399	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
AnnaBridge	125:2e9cc70d1897	1400	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	125:2e9cc70d1897	1401
AnnaBridge	125:2e9cc70d1897	1402	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
AnnaBridge	125:2e9cc70d1897	1403	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	125:2e9cc70d1897	1404
AnnaBridge	125:2e9cc70d1897	1405	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
AnnaBridge	125:2e9cc70d1897	1406	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	125:2e9cc70d1897	1407
AnnaBridge	125:2e9cc70d1897	1408	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	125:2e9cc70d1897	1409	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	125:2e9cc70d1897	1410
AnnaBridge	125:2e9cc70d1897	1411	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
AnnaBridge	125:2e9cc70d1897	1412	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	125:2e9cc70d1897	1413
AnnaBridge	125:2e9cc70d1897	1414	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
AnnaBridge	125:2e9cc70d1897	1415	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	125:2e9cc70d1897	1416
AnnaBridge	125:2e9cc70d1897	1417	/@} end of group CMSIS_MPU /
AnnaBridge	125:2e9cc70d1897	1418	#endif
AnnaBridge	125:2e9cc70d1897	1419
AnnaBridge	125:2e9cc70d1897	1420
AnnaBridge	125:2e9cc70d1897	1421	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	1422	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	1423	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	125:2e9cc70d1897	1424	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	125:2e9cc70d1897	1425	@{
AnnaBridge	125:2e9cc70d1897	1426	*/
AnnaBridge	125:2e9cc70d1897	1427
AnnaBridge	125:2e9cc70d1897	1428	/** \brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	125:2e9cc70d1897	1429	*/
AnnaBridge	125:2e9cc70d1897	1430	typedef struct
AnnaBridge	125:2e9cc70d1897	1431	{
AnnaBridge	125:2e9cc70d1897	1432	uint32_t RESERVED0[1];
AnnaBridge	125:2e9cc70d1897	1433	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	125:2e9cc70d1897	1434	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	125:2e9cc70d1897	1435	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	125:2e9cc70d1897	1436	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	125:2e9cc70d1897	1437	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	125:2e9cc70d1897	1438	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
AnnaBridge	125:2e9cc70d1897	1439	} FPU_Type;
AnnaBridge	125:2e9cc70d1897	1440
AnnaBridge	125:2e9cc70d1897	1441	/* Floating-Point Context Control Register */
AnnaBridge	125:2e9cc70d1897	1442	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
AnnaBridge	125:2e9cc70d1897	1443	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	125:2e9cc70d1897	1444
AnnaBridge	125:2e9cc70d1897	1445	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
AnnaBridge	125:2e9cc70d1897	1446	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	125:2e9cc70d1897	1447
AnnaBridge	125:2e9cc70d1897	1448	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
AnnaBridge	125:2e9cc70d1897	1449	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	125:2e9cc70d1897	1450
AnnaBridge	125:2e9cc70d1897	1451	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
AnnaBridge	125:2e9cc70d1897	1452	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	125:2e9cc70d1897	1453
AnnaBridge	125:2e9cc70d1897	1454	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
AnnaBridge	125:2e9cc70d1897	1455	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	125:2e9cc70d1897	1456
AnnaBridge	125:2e9cc70d1897	1457	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
AnnaBridge	125:2e9cc70d1897	1458	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	125:2e9cc70d1897	1459
AnnaBridge	125:2e9cc70d1897	1460	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
AnnaBridge	125:2e9cc70d1897	1461	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	125:2e9cc70d1897	1462
AnnaBridge	125:2e9cc70d1897	1463	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
AnnaBridge	125:2e9cc70d1897	1464	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	125:2e9cc70d1897	1465
AnnaBridge	125:2e9cc70d1897	1466	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	125:2e9cc70d1897	1467	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	125:2e9cc70d1897	1468
AnnaBridge	125:2e9cc70d1897	1469	/* Floating-Point Context Address Register */
AnnaBridge	125:2e9cc70d1897	1470	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
AnnaBridge	125:2e9cc70d1897	1471	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	125:2e9cc70d1897	1472
AnnaBridge	125:2e9cc70d1897	1473	/* Floating-Point Default Status Control Register */
AnnaBridge	125:2e9cc70d1897	1474	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
AnnaBridge	125:2e9cc70d1897	1475	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	125:2e9cc70d1897	1476
AnnaBridge	125:2e9cc70d1897	1477	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
AnnaBridge	125:2e9cc70d1897	1478	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	125:2e9cc70d1897	1479
AnnaBridge	125:2e9cc70d1897	1480	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
AnnaBridge	125:2e9cc70d1897	1481	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	125:2e9cc70d1897	1482
AnnaBridge	125:2e9cc70d1897	1483	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
AnnaBridge	125:2e9cc70d1897	1484	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	125:2e9cc70d1897	1485
AnnaBridge	125:2e9cc70d1897	1486	/* Media and FP Feature Register 0 */
AnnaBridge	125:2e9cc70d1897	1487	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	125:2e9cc70d1897	1488	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	125:2e9cc70d1897	1489
AnnaBridge	125:2e9cc70d1897	1490	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
AnnaBridge	125:2e9cc70d1897	1491	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	125:2e9cc70d1897	1492
AnnaBridge	125:2e9cc70d1897	1493	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
AnnaBridge	125:2e9cc70d1897	1494	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	125:2e9cc70d1897	1495
AnnaBridge	125:2e9cc70d1897	1496	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
AnnaBridge	125:2e9cc70d1897	1497	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	125:2e9cc70d1897	1498
AnnaBridge	125:2e9cc70d1897	1499	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	125:2e9cc70d1897	1500	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	125:2e9cc70d1897	1501
AnnaBridge	125:2e9cc70d1897	1502	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
AnnaBridge	125:2e9cc70d1897	1503	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	125:2e9cc70d1897	1504
AnnaBridge	125:2e9cc70d1897	1505	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
AnnaBridge	125:2e9cc70d1897	1506	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	125:2e9cc70d1897	1507
AnnaBridge	125:2e9cc70d1897	1508	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	125:2e9cc70d1897	1509	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	125:2e9cc70d1897	1510
AnnaBridge	125:2e9cc70d1897	1511	/* Media and FP Feature Register 1 */
AnnaBridge	125:2e9cc70d1897	1512	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	125:2e9cc70d1897	1513	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	125:2e9cc70d1897	1514
AnnaBridge	125:2e9cc70d1897	1515	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
AnnaBridge	125:2e9cc70d1897	1516	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	125:2e9cc70d1897	1517
AnnaBridge	125:2e9cc70d1897	1518	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	125:2e9cc70d1897	1519	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	125:2e9cc70d1897	1520
AnnaBridge	125:2e9cc70d1897	1521	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
AnnaBridge	125:2e9cc70d1897	1522	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	125:2e9cc70d1897	1523
AnnaBridge	125:2e9cc70d1897	1524	/* Media and FP Feature Register 2 */
AnnaBridge	125:2e9cc70d1897	1525
AnnaBridge	125:2e9cc70d1897	1526	/@} end of group CMSIS_FPU /
AnnaBridge	125:2e9cc70d1897	1527	#endif
AnnaBridge	125:2e9cc70d1897	1528
AnnaBridge	125:2e9cc70d1897	1529
AnnaBridge	125:2e9cc70d1897	1530	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	1531	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	125:2e9cc70d1897	1532	\brief Type definitions for the Core Debug Registers
AnnaBridge	125:2e9cc70d1897	1533	@{
AnnaBridge	125:2e9cc70d1897	1534	*/
AnnaBridge	125:2e9cc70d1897	1535
AnnaBridge	125:2e9cc70d1897	1536	/** \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	125:2e9cc70d1897	1537	*/
AnnaBridge	125:2e9cc70d1897	1538	typedef struct
AnnaBridge	125:2e9cc70d1897	1539	{
AnnaBridge	125:2e9cc70d1897	1540	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	125:2e9cc70d1897	1541	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	125:2e9cc70d1897	1542	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	125:2e9cc70d1897	1543	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	125:2e9cc70d1897	1544	} CoreDebug_Type;
AnnaBridge	125:2e9cc70d1897	1545
AnnaBridge	125:2e9cc70d1897	1546	/* Debug Halting Control and Status Register */
AnnaBridge	125:2e9cc70d1897	1547	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	125:2e9cc70d1897	1548	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	125:2e9cc70d1897	1549
AnnaBridge	125:2e9cc70d1897	1550	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	125:2e9cc70d1897	1551	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	125:2e9cc70d1897	1552
AnnaBridge	125:2e9cc70d1897	1553	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	125:2e9cc70d1897	1554	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	125:2e9cc70d1897	1555
AnnaBridge	125:2e9cc70d1897	1556	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	125:2e9cc70d1897	1557	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	125:2e9cc70d1897	1558
AnnaBridge	125:2e9cc70d1897	1559	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	125:2e9cc70d1897	1560	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	125:2e9cc70d1897	1561
AnnaBridge	125:2e9cc70d1897	1562	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	125:2e9cc70d1897	1563	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	125:2e9cc70d1897	1564
AnnaBridge	125:2e9cc70d1897	1565	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	125:2e9cc70d1897	1566	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	125:2e9cc70d1897	1567
AnnaBridge	125:2e9cc70d1897	1568	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	125:2e9cc70d1897	1569	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	125:2e9cc70d1897	1570
AnnaBridge	125:2e9cc70d1897	1571	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	125:2e9cc70d1897	1572	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	125:2e9cc70d1897	1573
AnnaBridge	125:2e9cc70d1897	1574	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	125:2e9cc70d1897	1575	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	125:2e9cc70d1897	1576
AnnaBridge	125:2e9cc70d1897	1577	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	125:2e9cc70d1897	1578	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	125:2e9cc70d1897	1579
AnnaBridge	125:2e9cc70d1897	1580	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	125:2e9cc70d1897	1581	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	125:2e9cc70d1897	1582
AnnaBridge	125:2e9cc70d1897	1583	/* Debug Core Register Selector Register */
AnnaBridge	125:2e9cc70d1897	1584	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	125:2e9cc70d1897	1585	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	125:2e9cc70d1897	1586
AnnaBridge	125:2e9cc70d1897	1587	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	125:2e9cc70d1897	1588	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	125:2e9cc70d1897	1589
AnnaBridge	125:2e9cc70d1897	1590	/* Debug Exception and Monitor Control Register */
AnnaBridge	125:2e9cc70d1897	1591	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	125:2e9cc70d1897	1592	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	125:2e9cc70d1897	1593
AnnaBridge	125:2e9cc70d1897	1594	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	125:2e9cc70d1897	1595	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	125:2e9cc70d1897	1596
AnnaBridge	125:2e9cc70d1897	1597	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	125:2e9cc70d1897	1598	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	125:2e9cc70d1897	1599
AnnaBridge	125:2e9cc70d1897	1600	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	125:2e9cc70d1897	1601	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	125:2e9cc70d1897	1602
AnnaBridge	125:2e9cc70d1897	1603	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	125:2e9cc70d1897	1604	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	125:2e9cc70d1897	1605
AnnaBridge	125:2e9cc70d1897	1606	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	125:2e9cc70d1897	1607	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	125:2e9cc70d1897	1608
AnnaBridge	125:2e9cc70d1897	1609	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	125:2e9cc70d1897	1610	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	125:2e9cc70d1897	1611
AnnaBridge	125:2e9cc70d1897	1612	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	125:2e9cc70d1897	1613	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	125:2e9cc70d1897	1614
AnnaBridge	125:2e9cc70d1897	1615	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	125:2e9cc70d1897	1616	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	125:2e9cc70d1897	1617
AnnaBridge	125:2e9cc70d1897	1618	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	125:2e9cc70d1897	1619	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	125:2e9cc70d1897	1620
AnnaBridge	125:2e9cc70d1897	1621	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	125:2e9cc70d1897	1622	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	125:2e9cc70d1897	1623
AnnaBridge	125:2e9cc70d1897	1624	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	125:2e9cc70d1897	1625	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	125:2e9cc70d1897	1626
AnnaBridge	125:2e9cc70d1897	1627	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	125:2e9cc70d1897	1628	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	125:2e9cc70d1897	1629
AnnaBridge	125:2e9cc70d1897	1630	/@} end of group CMSIS_CoreDebug /
AnnaBridge	125:2e9cc70d1897	1631
AnnaBridge	125:2e9cc70d1897	1632
AnnaBridge	125:2e9cc70d1897	1633	/** \ingroup CMSIS_core_register
AnnaBridge	125:2e9cc70d1897	1634	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	125:2e9cc70d1897	1635	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	125:2e9cc70d1897	1636	@{
AnnaBridge	125:2e9cc70d1897	1637	*/
AnnaBridge	125:2e9cc70d1897	1638
AnnaBridge	125:2e9cc70d1897	1639	/* Memory mapping of Cortex-M4 Hardware */
AnnaBridge	125:2e9cc70d1897	1640	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	125:2e9cc70d1897	1641	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	125:2e9cc70d1897	1642	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	125:2e9cc70d1897	1643	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	125:2e9cc70d1897	1644	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	125:2e9cc70d1897	1645	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	125:2e9cc70d1897	1646	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	125:2e9cc70d1897	1647	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	125:2e9cc70d1897	1648
AnnaBridge	125:2e9cc70d1897	1649	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	125:2e9cc70d1897	1650	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	125:2e9cc70d1897	1651	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	125:2e9cc70d1897	1652	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	125:2e9cc70d1897	1653	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	125:2e9cc70d1897	1654	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	125:2e9cc70d1897	1655	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	125:2e9cc70d1897	1656	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	125:2e9cc70d1897	1657
AnnaBridge	125:2e9cc70d1897	1658	#if (__MPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	1659	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	125:2e9cc70d1897	1660	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	125:2e9cc70d1897	1661	#endif
AnnaBridge	125:2e9cc70d1897	1662
AnnaBridge	125:2e9cc70d1897	1663	#if (__FPU_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	1664	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	125:2e9cc70d1897	1665	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	125:2e9cc70d1897	1666	#endif
AnnaBridge	125:2e9cc70d1897	1667
AnnaBridge	125:2e9cc70d1897	1668	/@} /
AnnaBridge	125:2e9cc70d1897	1669
AnnaBridge	125:2e9cc70d1897	1670
AnnaBridge	125:2e9cc70d1897	1671
AnnaBridge	125:2e9cc70d1897	1672	/*******************************************************************************
AnnaBridge	125:2e9cc70d1897	1673	* Hardware Abstraction Layer
AnnaBridge	125:2e9cc70d1897	1674	Core Function Interface contains:
AnnaBridge	125:2e9cc70d1897	1675	- Core NVIC Functions
AnnaBridge	125:2e9cc70d1897	1676	- Core SysTick Functions
AnnaBridge	125:2e9cc70d1897	1677	- Core Debug Functions
AnnaBridge	125:2e9cc70d1897	1678	- Core Register Access Functions
AnnaBridge	125:2e9cc70d1897	1679	******************************************************************************/
AnnaBridge	125:2e9cc70d1897	1680	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	125:2e9cc70d1897	1681	*/
AnnaBridge	125:2e9cc70d1897	1682
AnnaBridge	125:2e9cc70d1897	1683
AnnaBridge	125:2e9cc70d1897	1684
AnnaBridge	125:2e9cc70d1897	1685	/* ########################## NVIC functions #################################### */
AnnaBridge	125:2e9cc70d1897	1686	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	125:2e9cc70d1897	1687	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	125:2e9cc70d1897	1688	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	125:2e9cc70d1897	1689	@{
AnnaBridge	125:2e9cc70d1897	1690	*/
AnnaBridge	125:2e9cc70d1897	1691
AnnaBridge	125:2e9cc70d1897	1692	/** \brief Set Priority Grouping
AnnaBridge	125:2e9cc70d1897	1693
AnnaBridge	125:2e9cc70d1897	1694	The function sets the priority grouping field using the required unlock sequence.
AnnaBridge	125:2e9cc70d1897	1695	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	125:2e9cc70d1897	1696	Only values from 0..7 are used.
AnnaBridge	125:2e9cc70d1897	1697	In case of a conflict between priority grouping and available
AnnaBridge	125:2e9cc70d1897	1698	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	125:2e9cc70d1897	1699
AnnaBridge	125:2e9cc70d1897	1700	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	125:2e9cc70d1897	1701	*/
AnnaBridge	125:2e9cc70d1897	1702	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	125:2e9cc70d1897	1703	{
AnnaBridge	125:2e9cc70d1897	1704	uint32_t reg_value;
AnnaBridge	125:2e9cc70d1897	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	125:2e9cc70d1897	1706
AnnaBridge	125:2e9cc70d1897	1707	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	125:2e9cc70d1897	1708	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	125:2e9cc70d1897	1709	reg_value = (reg_value \|
AnnaBridge	125:2e9cc70d1897	1710	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	125:2e9cc70d1897	1711	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
AnnaBridge	125:2e9cc70d1897	1712	SCB->AIRCR = reg_value;
AnnaBridge	125:2e9cc70d1897	1713	}
AnnaBridge	125:2e9cc70d1897	1714
AnnaBridge	125:2e9cc70d1897	1715
AnnaBridge	125:2e9cc70d1897	1716	/** \brief Get Priority Grouping
AnnaBridge	125:2e9cc70d1897	1717
AnnaBridge	125:2e9cc70d1897	1718	The function reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	125:2e9cc70d1897	1719
AnnaBridge	125:2e9cc70d1897	1720	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	125:2e9cc70d1897	1721	*/
AnnaBridge	125:2e9cc70d1897	1722	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
AnnaBridge	125:2e9cc70d1897	1723	{
AnnaBridge	125:2e9cc70d1897	1724	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	125:2e9cc70d1897	1725	}
AnnaBridge	125:2e9cc70d1897	1726
AnnaBridge	125:2e9cc70d1897	1727
AnnaBridge	125:2e9cc70d1897	1728	/** \brief Enable External Interrupt
AnnaBridge	125:2e9cc70d1897	1729
AnnaBridge	125:2e9cc70d1897	1730	The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge	125:2e9cc70d1897	1731
AnnaBridge	125:2e9cc70d1897	1732	\param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge	125:2e9cc70d1897	1733	*/
AnnaBridge	125:2e9cc70d1897	1734	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	125:2e9cc70d1897	1735	{
AnnaBridge	125:2e9cc70d1897	1736	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	125:2e9cc70d1897	1737	}
AnnaBridge	125:2e9cc70d1897	1738
AnnaBridge	125:2e9cc70d1897	1739
AnnaBridge	125:2e9cc70d1897	1740	/** \brief Disable External Interrupt
AnnaBridge	125:2e9cc70d1897	1741
AnnaBridge	125:2e9cc70d1897	1742	The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge	125:2e9cc70d1897	1743
AnnaBridge	125:2e9cc70d1897	1744	\param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge	125:2e9cc70d1897	1745	*/
AnnaBridge	125:2e9cc70d1897	1746	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	125:2e9cc70d1897	1747	{
AnnaBridge	125:2e9cc70d1897	1748	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	125:2e9cc70d1897	1749	}
AnnaBridge	125:2e9cc70d1897	1750
AnnaBridge	125:2e9cc70d1897	1751
AnnaBridge	125:2e9cc70d1897	1752	/** \brief Get Pending Interrupt
AnnaBridge	125:2e9cc70d1897	1753
AnnaBridge	125:2e9cc70d1897	1754	The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge	125:2e9cc70d1897	1755	for the specified interrupt.
AnnaBridge	125:2e9cc70d1897	1756
AnnaBridge	125:2e9cc70d1897	1757	\param [in] IRQn Interrupt number.
AnnaBridge	125:2e9cc70d1897	1758
AnnaBridge	125:2e9cc70d1897	1759	\return 0 Interrupt status is not pending.
AnnaBridge	125:2e9cc70d1897	1760	\return 1 Interrupt status is pending.
AnnaBridge	125:2e9cc70d1897	1761	*/
AnnaBridge	125:2e9cc70d1897	1762	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	125:2e9cc70d1897	1763	{
AnnaBridge	125:2e9cc70d1897	1764	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	125:2e9cc70d1897	1765	}
AnnaBridge	125:2e9cc70d1897	1766
AnnaBridge	125:2e9cc70d1897	1767
AnnaBridge	125:2e9cc70d1897	1768	/** \brief Set Pending Interrupt
AnnaBridge	125:2e9cc70d1897	1769
AnnaBridge	125:2e9cc70d1897	1770	The function sets the pending bit of an external interrupt.
AnnaBridge	125:2e9cc70d1897	1771
AnnaBridge	125:2e9cc70d1897	1772	\param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge	125:2e9cc70d1897	1773	*/
AnnaBridge	125:2e9cc70d1897	1774	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	125:2e9cc70d1897	1775	{
AnnaBridge	125:2e9cc70d1897	1776	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	125:2e9cc70d1897	1777	}
AnnaBridge	125:2e9cc70d1897	1778
AnnaBridge	125:2e9cc70d1897	1779
AnnaBridge	125:2e9cc70d1897	1780	/** \brief Clear Pending Interrupt
AnnaBridge	125:2e9cc70d1897	1781
AnnaBridge	125:2e9cc70d1897	1782	The function clears the pending bit of an external interrupt.
AnnaBridge	125:2e9cc70d1897	1783
AnnaBridge	125:2e9cc70d1897	1784	\param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge	125:2e9cc70d1897	1785	*/
AnnaBridge	125:2e9cc70d1897	1786	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	125:2e9cc70d1897	1787	{
AnnaBridge	125:2e9cc70d1897	1788	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	125:2e9cc70d1897	1789	}
AnnaBridge	125:2e9cc70d1897	1790
AnnaBridge	125:2e9cc70d1897	1791
AnnaBridge	125:2e9cc70d1897	1792	/** \brief Get Active Interrupt
AnnaBridge	125:2e9cc70d1897	1793
AnnaBridge	125:2e9cc70d1897	1794	The function reads the active register in NVIC and returns the active bit.
AnnaBridge	125:2e9cc70d1897	1795
AnnaBridge	125:2e9cc70d1897	1796	\param [in] IRQn Interrupt number.
AnnaBridge	125:2e9cc70d1897	1797
AnnaBridge	125:2e9cc70d1897	1798	\return 0 Interrupt status is not active.
AnnaBridge	125:2e9cc70d1897	1799	\return 1 Interrupt status is active.
AnnaBridge	125:2e9cc70d1897	1800	*/
AnnaBridge	125:2e9cc70d1897	1801	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	125:2e9cc70d1897	1802	{
AnnaBridge	125:2e9cc70d1897	1803	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	125:2e9cc70d1897	1804	}
AnnaBridge	125:2e9cc70d1897	1805
AnnaBridge	125:2e9cc70d1897	1806
AnnaBridge	125:2e9cc70d1897	1807	/** \brief Set Interrupt Priority
AnnaBridge	125:2e9cc70d1897	1808
AnnaBridge	125:2e9cc70d1897	1809	The function sets the priority of an interrupt.
AnnaBridge	125:2e9cc70d1897	1810
AnnaBridge	125:2e9cc70d1897	1811	\note The priority cannot be set for every core interrupt.
AnnaBridge	125:2e9cc70d1897	1812
AnnaBridge	125:2e9cc70d1897	1813	\param [in] IRQn Interrupt number.
AnnaBridge	125:2e9cc70d1897	1814	\param [in] priority Priority to set.
AnnaBridge	125:2e9cc70d1897	1815	*/
AnnaBridge	125:2e9cc70d1897	1816	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	125:2e9cc70d1897	1817	{
AnnaBridge	125:2e9cc70d1897	1818	if((int32_t)IRQn < 0) {
AnnaBridge	125:2e9cc70d1897	1819	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	125:2e9cc70d1897	1820	}
AnnaBridge	125:2e9cc70d1897	1821	else {
AnnaBridge	125:2e9cc70d1897	1822	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	125:2e9cc70d1897	1823	}
AnnaBridge	125:2e9cc70d1897	1824	}
AnnaBridge	125:2e9cc70d1897	1825
AnnaBridge	125:2e9cc70d1897	1826
AnnaBridge	125:2e9cc70d1897	1827	/** \brief Get Interrupt Priority
AnnaBridge	125:2e9cc70d1897	1828
AnnaBridge	125:2e9cc70d1897	1829	The function reads the priority of an interrupt. The interrupt
AnnaBridge	125:2e9cc70d1897	1830	number can be positive to specify an external (device specific)
AnnaBridge	125:2e9cc70d1897	1831	interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge	125:2e9cc70d1897	1832
AnnaBridge	125:2e9cc70d1897	1833
AnnaBridge	125:2e9cc70d1897	1834	\param [in] IRQn Interrupt number.
AnnaBridge	125:2e9cc70d1897	1835	\return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge	125:2e9cc70d1897	1836	priority bits of the microcontroller.
AnnaBridge	125:2e9cc70d1897	1837	*/
AnnaBridge	125:2e9cc70d1897	1838	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	125:2e9cc70d1897	1839	{
AnnaBridge	125:2e9cc70d1897	1840
AnnaBridge	125:2e9cc70d1897	1841	if((int32_t)IRQn < 0) {
AnnaBridge	125:2e9cc70d1897	1842	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge	125:2e9cc70d1897	1843	}
AnnaBridge	125:2e9cc70d1897	1844	else {
AnnaBridge	125:2e9cc70d1897	1845	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge	125:2e9cc70d1897	1846	}
AnnaBridge	125:2e9cc70d1897	1847	}
AnnaBridge	125:2e9cc70d1897	1848
AnnaBridge	125:2e9cc70d1897	1849
AnnaBridge	125:2e9cc70d1897	1850	/** \brief Encode Priority
AnnaBridge	125:2e9cc70d1897	1851
AnnaBridge	125:2e9cc70d1897	1852	The function encodes the priority for an interrupt with the given priority group,
AnnaBridge	125:2e9cc70d1897	1853	preemptive priority value, and subpriority value.
AnnaBridge	125:2e9cc70d1897	1854	In case of a conflict between priority grouping and available
AnnaBridge	125:2e9cc70d1897	1855	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	125:2e9cc70d1897	1856
AnnaBridge	125:2e9cc70d1897	1857	\param [in] PriorityGroup Used priority group.
AnnaBridge	125:2e9cc70d1897	1858	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	125:2e9cc70d1897	1859	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	125:2e9cc70d1897	1860	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	125:2e9cc70d1897	1861	*/
AnnaBridge	125:2e9cc70d1897	1862	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	125:2e9cc70d1897	1863	{
AnnaBridge	125:2e9cc70d1897	1864	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	125:2e9cc70d1897	1865	uint32_t PreemptPriorityBits;
AnnaBridge	125:2e9cc70d1897	1866	uint32_t SubPriorityBits;
AnnaBridge	125:2e9cc70d1897	1867
AnnaBridge	125:2e9cc70d1897	1868	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	125:2e9cc70d1897	1869	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	125:2e9cc70d1897	1870
AnnaBridge	125:2e9cc70d1897	1871	return (
AnnaBridge	125:2e9cc70d1897	1872	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	125:2e9cc70d1897	1873	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	125:2e9cc70d1897	1874	);
AnnaBridge	125:2e9cc70d1897	1875	}
AnnaBridge	125:2e9cc70d1897	1876
AnnaBridge	125:2e9cc70d1897	1877
AnnaBridge	125:2e9cc70d1897	1878	/** \brief Decode Priority
AnnaBridge	125:2e9cc70d1897	1879
AnnaBridge	125:2e9cc70d1897	1880	The function decodes an interrupt priority value with a given priority group to
AnnaBridge	125:2e9cc70d1897	1881	preemptive priority value and subpriority value.
AnnaBridge	125:2e9cc70d1897	1882	In case of a conflict between priority grouping and available
AnnaBridge	125:2e9cc70d1897	1883	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	125:2e9cc70d1897	1884
AnnaBridge	125:2e9cc70d1897	1885	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	125:2e9cc70d1897	1886	\param [in] PriorityGroup Used priority group.
AnnaBridge	125:2e9cc70d1897	1887	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	125:2e9cc70d1897	1888	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	125:2e9cc70d1897	1889	*/
AnnaBridge	125:2e9cc70d1897	1890	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
AnnaBridge	125:2e9cc70d1897	1891	{
AnnaBridge	125:2e9cc70d1897	1892	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	125:2e9cc70d1897	1893	uint32_t PreemptPriorityBits;
AnnaBridge	125:2e9cc70d1897	1894	uint32_t SubPriorityBits;
AnnaBridge	125:2e9cc70d1897	1895
AnnaBridge	125:2e9cc70d1897	1896	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	125:2e9cc70d1897	1897	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	125:2e9cc70d1897	1898
AnnaBridge	125:2e9cc70d1897	1899	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	125:2e9cc70d1897	1900	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	125:2e9cc70d1897	1901	}
AnnaBridge	125:2e9cc70d1897	1902
AnnaBridge	125:2e9cc70d1897	1903
AnnaBridge	125:2e9cc70d1897	1904	/** \brief System Reset
AnnaBridge	125:2e9cc70d1897	1905
AnnaBridge	125:2e9cc70d1897	1906	The function initiates a system reset request to reset the MCU.
AnnaBridge	125:2e9cc70d1897	1907	*/
AnnaBridge	125:2e9cc70d1897	1908	__STATIC_INLINE void NVIC_SystemReset(void)
AnnaBridge	125:2e9cc70d1897	1909	{
AnnaBridge	125:2e9cc70d1897	1910	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	125:2e9cc70d1897	1911	buffered write are completed before reset */
AnnaBridge	125:2e9cc70d1897	1912	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	125:2e9cc70d1897	1913	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	125:2e9cc70d1897	1914	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	125:2e9cc70d1897	1915	__DSB(); /* Ensure completion of memory access */
AnnaBridge	125:2e9cc70d1897	1916	while(1) { __NOP(); } /* wait until reset */
AnnaBridge	125:2e9cc70d1897	1917	}
AnnaBridge	125:2e9cc70d1897	1918
AnnaBridge	125:2e9cc70d1897	1919	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	125:2e9cc70d1897	1920
AnnaBridge	125:2e9cc70d1897	1921
AnnaBridge	125:2e9cc70d1897	1922	/* ########################## FPU functions #################################### */
AnnaBridge	125:2e9cc70d1897	1923	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	125:2e9cc70d1897	1924	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	125:2e9cc70d1897	1925	\brief Function that provides FPU type.
AnnaBridge	125:2e9cc70d1897	1926	@{
AnnaBridge	125:2e9cc70d1897	1927	*/
AnnaBridge	125:2e9cc70d1897	1928
AnnaBridge	125:2e9cc70d1897	1929	/**
AnnaBridge	125:2e9cc70d1897	1930	\fn uint32_t SCB_GetFPUType(void)
AnnaBridge	125:2e9cc70d1897	1931	\brief get FPU type
AnnaBridge	125:2e9cc70d1897	1932	\returns
AnnaBridge	125:2e9cc70d1897	1933	- \b 0: No FPU
AnnaBridge	125:2e9cc70d1897	1934	- \b 1: Single precision FPU
AnnaBridge	125:2e9cc70d1897	1935	- \b 2: Double + Single precision FPU
AnnaBridge	125:2e9cc70d1897	1936	*/
AnnaBridge	125:2e9cc70d1897	1937	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	125:2e9cc70d1897	1938	{
AnnaBridge	125:2e9cc70d1897	1939	uint32_t mvfr0;
AnnaBridge	125:2e9cc70d1897	1940
AnnaBridge	125:2e9cc70d1897	1941	mvfr0 = SCB->MVFR0;
AnnaBridge	125:2e9cc70d1897	1942	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
AnnaBridge	125:2e9cc70d1897	1943	return 2UL; // Double + Single precision FPU
AnnaBridge	125:2e9cc70d1897	1944	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
AnnaBridge	125:2e9cc70d1897	1945	return 1UL; // Single precision FPU
AnnaBridge	125:2e9cc70d1897	1946	} else {
AnnaBridge	125:2e9cc70d1897	1947	return 0UL; // No FPU
AnnaBridge	125:2e9cc70d1897	1948	}
AnnaBridge	125:2e9cc70d1897	1949	}
AnnaBridge	125:2e9cc70d1897	1950
AnnaBridge	125:2e9cc70d1897	1951
AnnaBridge	125:2e9cc70d1897	1952	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	125:2e9cc70d1897	1953
AnnaBridge	125:2e9cc70d1897	1954
AnnaBridge	125:2e9cc70d1897	1955
AnnaBridge	125:2e9cc70d1897	1956	/* ########################## Cache functions #################################### */
AnnaBridge	125:2e9cc70d1897	1957	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	125:2e9cc70d1897	1958	\defgroup CMSIS_Core_CacheFunctions Cache Functions
AnnaBridge	125:2e9cc70d1897	1959	\brief Functions that configure Instruction and Data cache.
AnnaBridge	125:2e9cc70d1897	1960	@{
AnnaBridge	125:2e9cc70d1897	1961	*/
AnnaBridge	125:2e9cc70d1897	1962
AnnaBridge	125:2e9cc70d1897	1963	/* Cache Size ID Register Macros */
AnnaBridge	125:2e9cc70d1897	1964	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
AnnaBridge	125:2e9cc70d1897	1965	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
AnnaBridge	125:2e9cc70d1897	1966	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
AnnaBridge	125:2e9cc70d1897	1967
AnnaBridge	125:2e9cc70d1897	1968
AnnaBridge	125:2e9cc70d1897	1969	/** \brief Enable I-Cache
AnnaBridge	125:2e9cc70d1897	1970
AnnaBridge	125:2e9cc70d1897	1971	The function turns on I-Cache
AnnaBridge	125:2e9cc70d1897	1972	*/
AnnaBridge	125:2e9cc70d1897	1973	__STATIC_INLINE void SCB_EnableICache (void)
AnnaBridge	125:2e9cc70d1897	1974	{
AnnaBridge	125:2e9cc70d1897	1975	#if (__ICACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	1976	__DSB();
AnnaBridge	125:2e9cc70d1897	1977	__ISB();
AnnaBridge	125:2e9cc70d1897	1978	SCB->ICIALLU = 0UL; // invalidate I-Cache
AnnaBridge	125:2e9cc70d1897	1979	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
AnnaBridge	125:2e9cc70d1897	1980	__DSB();
AnnaBridge	125:2e9cc70d1897	1981	__ISB();
AnnaBridge	125:2e9cc70d1897	1982	#endif
AnnaBridge	125:2e9cc70d1897	1983	}
AnnaBridge	125:2e9cc70d1897	1984
AnnaBridge	125:2e9cc70d1897	1985
AnnaBridge	125:2e9cc70d1897	1986	/** \brief Disable I-Cache
AnnaBridge	125:2e9cc70d1897	1987
AnnaBridge	125:2e9cc70d1897	1988	The function turns off I-Cache
AnnaBridge	125:2e9cc70d1897	1989	*/
AnnaBridge	125:2e9cc70d1897	1990	__STATIC_INLINE void SCB_DisableICache (void)
AnnaBridge	125:2e9cc70d1897	1991	{
AnnaBridge	125:2e9cc70d1897	1992	#if (__ICACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	1993	__DSB();
AnnaBridge	125:2e9cc70d1897	1994	__ISB();
AnnaBridge	125:2e9cc70d1897	1995	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
AnnaBridge	125:2e9cc70d1897	1996	SCB->ICIALLU = 0UL; // invalidate I-Cache
AnnaBridge	125:2e9cc70d1897	1997	__DSB();
AnnaBridge	125:2e9cc70d1897	1998	__ISB();
AnnaBridge	125:2e9cc70d1897	1999	#endif
AnnaBridge	125:2e9cc70d1897	2000	}
AnnaBridge	125:2e9cc70d1897	2001
AnnaBridge	125:2e9cc70d1897	2002
AnnaBridge	125:2e9cc70d1897	2003	/** \brief Invalidate I-Cache
AnnaBridge	125:2e9cc70d1897	2004
AnnaBridge	125:2e9cc70d1897	2005	The function invalidates I-Cache
AnnaBridge	125:2e9cc70d1897	2006	*/
AnnaBridge	125:2e9cc70d1897	2007	__STATIC_INLINE void SCB_InvalidateICache (void)
AnnaBridge	125:2e9cc70d1897	2008	{
AnnaBridge	125:2e9cc70d1897	2009	#if (__ICACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2010	__DSB();
AnnaBridge	125:2e9cc70d1897	2011	__ISB();
AnnaBridge	125:2e9cc70d1897	2012	SCB->ICIALLU = 0UL;
AnnaBridge	125:2e9cc70d1897	2013	__DSB();
AnnaBridge	125:2e9cc70d1897	2014	__ISB();
AnnaBridge	125:2e9cc70d1897	2015	#endif
AnnaBridge	125:2e9cc70d1897	2016	}
AnnaBridge	125:2e9cc70d1897	2017
AnnaBridge	125:2e9cc70d1897	2018
AnnaBridge	125:2e9cc70d1897	2019	/** \brief Enable D-Cache
AnnaBridge	125:2e9cc70d1897	2020
AnnaBridge	125:2e9cc70d1897	2021	The function turns on D-Cache
AnnaBridge	125:2e9cc70d1897	2022	*/
AnnaBridge	125:2e9cc70d1897	2023	__STATIC_INLINE void SCB_EnableDCache (void)
AnnaBridge	125:2e9cc70d1897	2024	{
AnnaBridge	125:2e9cc70d1897	2025	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2026	uint32_t ccsidr, sshift, wshift, sw;
AnnaBridge	125:2e9cc70d1897	2027	uint32_t sets, ways;
AnnaBridge	125:2e9cc70d1897	2028
AnnaBridge	125:2e9cc70d1897	2029	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
AnnaBridge	125:2e9cc70d1897	2030	ccsidr = SCB->CCSIDR;
AnnaBridge	125:2e9cc70d1897	2031	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2032	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
AnnaBridge	125:2e9cc70d1897	2033	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2034	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
AnnaBridge	125:2e9cc70d1897	2035
AnnaBridge	125:2e9cc70d1897	2036	__DSB();
AnnaBridge	125:2e9cc70d1897	2037
AnnaBridge	125:2e9cc70d1897	2038	do { // invalidate D-Cache
AnnaBridge	125:2e9cc70d1897	2039	uint32_t tmpways = ways;
AnnaBridge	125:2e9cc70d1897	2040	do {
AnnaBridge	125:2e9cc70d1897	2041	sw = ((tmpways << wshift) \| (sets << sshift));
AnnaBridge	125:2e9cc70d1897	2042	SCB->DCISW = sw;
AnnaBridge	125:2e9cc70d1897	2043	} while(tmpways--);
AnnaBridge	125:2e9cc70d1897	2044	} while(sets--);
AnnaBridge	125:2e9cc70d1897	2045	__DSB();
AnnaBridge	125:2e9cc70d1897	2046
AnnaBridge	125:2e9cc70d1897	2047	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
AnnaBridge	125:2e9cc70d1897	2048
AnnaBridge	125:2e9cc70d1897	2049	__DSB();
AnnaBridge	125:2e9cc70d1897	2050	__ISB();
AnnaBridge	125:2e9cc70d1897	2051	#endif
AnnaBridge	125:2e9cc70d1897	2052	}
AnnaBridge	125:2e9cc70d1897	2053
AnnaBridge	125:2e9cc70d1897	2054
AnnaBridge	125:2e9cc70d1897	2055	/** \brief Disable D-Cache
AnnaBridge	125:2e9cc70d1897	2056
AnnaBridge	125:2e9cc70d1897	2057	The function turns off D-Cache
AnnaBridge	125:2e9cc70d1897	2058	*/
AnnaBridge	125:2e9cc70d1897	2059	__STATIC_INLINE void SCB_DisableDCache (void)
AnnaBridge	125:2e9cc70d1897	2060	{
AnnaBridge	125:2e9cc70d1897	2061	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2062	uint32_t ccsidr, sshift, wshift, sw;
AnnaBridge	125:2e9cc70d1897	2063	uint32_t sets, ways;
AnnaBridge	125:2e9cc70d1897	2064
AnnaBridge	125:2e9cc70d1897	2065	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
AnnaBridge	125:2e9cc70d1897	2066	ccsidr = SCB->CCSIDR;
AnnaBridge	125:2e9cc70d1897	2067	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2068	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
AnnaBridge	125:2e9cc70d1897	2069	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2070	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
AnnaBridge	125:2e9cc70d1897	2071
AnnaBridge	125:2e9cc70d1897	2072	__DSB();
AnnaBridge	125:2e9cc70d1897	2073
AnnaBridge	125:2e9cc70d1897	2074	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
AnnaBridge	125:2e9cc70d1897	2075
AnnaBridge	125:2e9cc70d1897	2076	do { // clean & invalidate D-Cache
AnnaBridge	125:2e9cc70d1897	2077	uint32_t tmpways = ways;
AnnaBridge	125:2e9cc70d1897	2078	do {
AnnaBridge	125:2e9cc70d1897	2079	sw = ((tmpways << wshift) \| (sets << sshift));
AnnaBridge	125:2e9cc70d1897	2080	SCB->DCCISW = sw;
AnnaBridge	125:2e9cc70d1897	2081	} while(tmpways--);
AnnaBridge	125:2e9cc70d1897	2082	} while(sets--);
AnnaBridge	125:2e9cc70d1897	2083
AnnaBridge	125:2e9cc70d1897	2084
AnnaBridge	125:2e9cc70d1897	2085	__DSB();
AnnaBridge	125:2e9cc70d1897	2086	__ISB();
AnnaBridge	125:2e9cc70d1897	2087	#endif
AnnaBridge	125:2e9cc70d1897	2088	}
AnnaBridge	125:2e9cc70d1897	2089
AnnaBridge	125:2e9cc70d1897	2090
AnnaBridge	125:2e9cc70d1897	2091	/** \brief Invalidate D-Cache
AnnaBridge	125:2e9cc70d1897	2092
AnnaBridge	125:2e9cc70d1897	2093	The function invalidates D-Cache
AnnaBridge	125:2e9cc70d1897	2094	*/
AnnaBridge	125:2e9cc70d1897	2095	__STATIC_INLINE void SCB_InvalidateDCache (void)
AnnaBridge	125:2e9cc70d1897	2096	{
AnnaBridge	125:2e9cc70d1897	2097	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2098	uint32_t ccsidr, sshift, wshift, sw;
AnnaBridge	125:2e9cc70d1897	2099	uint32_t sets, ways;
AnnaBridge	125:2e9cc70d1897	2100
AnnaBridge	125:2e9cc70d1897	2101	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
AnnaBridge	125:2e9cc70d1897	2102	ccsidr = SCB->CCSIDR;
AnnaBridge	125:2e9cc70d1897	2103	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2104	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
AnnaBridge	125:2e9cc70d1897	2105	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2106	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
AnnaBridge	125:2e9cc70d1897	2107
AnnaBridge	125:2e9cc70d1897	2108	__DSB();
AnnaBridge	125:2e9cc70d1897	2109
AnnaBridge	125:2e9cc70d1897	2110	do { // invalidate D-Cache
AnnaBridge	125:2e9cc70d1897	2111	uint32_t tmpways = ways;
AnnaBridge	125:2e9cc70d1897	2112	do {
AnnaBridge	125:2e9cc70d1897	2113	sw = ((tmpways << wshift) \| (sets << sshift));
AnnaBridge	125:2e9cc70d1897	2114	SCB->DCISW = sw;
AnnaBridge	125:2e9cc70d1897	2115	} while(tmpways--);
AnnaBridge	125:2e9cc70d1897	2116	} while(sets--);
AnnaBridge	125:2e9cc70d1897	2117
AnnaBridge	125:2e9cc70d1897	2118	__DSB();
AnnaBridge	125:2e9cc70d1897	2119	__ISB();
AnnaBridge	125:2e9cc70d1897	2120	#endif
AnnaBridge	125:2e9cc70d1897	2121	}
AnnaBridge	125:2e9cc70d1897	2122
AnnaBridge	125:2e9cc70d1897	2123
AnnaBridge	125:2e9cc70d1897	2124	/** \brief Clean D-Cache
AnnaBridge	125:2e9cc70d1897	2125
AnnaBridge	125:2e9cc70d1897	2126	The function cleans D-Cache
AnnaBridge	125:2e9cc70d1897	2127	*/
AnnaBridge	125:2e9cc70d1897	2128	__STATIC_INLINE void SCB_CleanDCache (void)
AnnaBridge	125:2e9cc70d1897	2129	{
AnnaBridge	125:2e9cc70d1897	2130	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2131	uint32_t ccsidr, sshift, wshift, sw;
AnnaBridge	125:2e9cc70d1897	2132	uint32_t sets, ways;
AnnaBridge	125:2e9cc70d1897	2133
AnnaBridge	125:2e9cc70d1897	2134	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
AnnaBridge	125:2e9cc70d1897	2135	ccsidr = SCB->CCSIDR;
AnnaBridge	125:2e9cc70d1897	2136	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2137	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
AnnaBridge	125:2e9cc70d1897	2138	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2139	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
AnnaBridge	125:2e9cc70d1897	2140
AnnaBridge	125:2e9cc70d1897	2141	__DSB();
AnnaBridge	125:2e9cc70d1897	2142
AnnaBridge	125:2e9cc70d1897	2143	do { // clean D-Cache
AnnaBridge	125:2e9cc70d1897	2144	uint32_t tmpways = ways;
AnnaBridge	125:2e9cc70d1897	2145	do {
AnnaBridge	125:2e9cc70d1897	2146	sw = ((tmpways << wshift) \| (sets << sshift));
AnnaBridge	125:2e9cc70d1897	2147	SCB->DCCSW = sw;
AnnaBridge	125:2e9cc70d1897	2148	} while(tmpways--);
AnnaBridge	125:2e9cc70d1897	2149	} while(sets--);
AnnaBridge	125:2e9cc70d1897	2150
AnnaBridge	125:2e9cc70d1897	2151	__DSB();
AnnaBridge	125:2e9cc70d1897	2152	__ISB();
AnnaBridge	125:2e9cc70d1897	2153	#endif
AnnaBridge	125:2e9cc70d1897	2154	}
AnnaBridge	125:2e9cc70d1897	2155
AnnaBridge	125:2e9cc70d1897	2156
AnnaBridge	125:2e9cc70d1897	2157	/** \brief Clean & Invalidate D-Cache
AnnaBridge	125:2e9cc70d1897	2158
AnnaBridge	125:2e9cc70d1897	2159	The function cleans and Invalidates D-Cache
AnnaBridge	125:2e9cc70d1897	2160	*/
AnnaBridge	125:2e9cc70d1897	2161	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
AnnaBridge	125:2e9cc70d1897	2162	{
AnnaBridge	125:2e9cc70d1897	2163	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2164	uint32_t ccsidr, sshift, wshift, sw;
AnnaBridge	125:2e9cc70d1897	2165	uint32_t sets, ways;
AnnaBridge	125:2e9cc70d1897	2166
AnnaBridge	125:2e9cc70d1897	2167	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
AnnaBridge	125:2e9cc70d1897	2168	ccsidr = SCB->CCSIDR;
AnnaBridge	125:2e9cc70d1897	2169	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2170	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
AnnaBridge	125:2e9cc70d1897	2171	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	125:2e9cc70d1897	2172	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
AnnaBridge	125:2e9cc70d1897	2173
AnnaBridge	125:2e9cc70d1897	2174	__DSB();
AnnaBridge	125:2e9cc70d1897	2175
AnnaBridge	125:2e9cc70d1897	2176	do { // clean & invalidate D-Cache
AnnaBridge	125:2e9cc70d1897	2177	uint32_t tmpways = ways;
AnnaBridge	125:2e9cc70d1897	2178	do {
AnnaBridge	125:2e9cc70d1897	2179	sw = ((tmpways << wshift) \| (sets << sshift));
AnnaBridge	125:2e9cc70d1897	2180	SCB->DCCISW = sw;
AnnaBridge	125:2e9cc70d1897	2181	} while(tmpways--);
AnnaBridge	125:2e9cc70d1897	2182	} while(sets--);
AnnaBridge	125:2e9cc70d1897	2183
AnnaBridge	125:2e9cc70d1897	2184	__DSB();
AnnaBridge	125:2e9cc70d1897	2185	__ISB();
AnnaBridge	125:2e9cc70d1897	2186	#endif
AnnaBridge	125:2e9cc70d1897	2187	}
AnnaBridge	125:2e9cc70d1897	2188
AnnaBridge	125:2e9cc70d1897	2189
AnnaBridge	125:2e9cc70d1897	2190	/**
AnnaBridge	125:2e9cc70d1897	2191	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
AnnaBridge	125:2e9cc70d1897	2192	\brief D-Cache Invalidate by address
AnnaBridge	125:2e9cc70d1897	2193	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	125:2e9cc70d1897	2194	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	125:2e9cc70d1897	2195	*/
AnnaBridge	125:2e9cc70d1897	2196	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	125:2e9cc70d1897	2197	{
AnnaBridge	125:2e9cc70d1897	2198	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2199	int32_t op_size = dsize;
AnnaBridge	125:2e9cc70d1897	2200	uint32_t op_addr = (uint32_t)addr;
AnnaBridge	125:2e9cc70d1897	2201	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
AnnaBridge	125:2e9cc70d1897	2202
AnnaBridge	125:2e9cc70d1897	2203	__DSB();
AnnaBridge	125:2e9cc70d1897	2204
AnnaBridge	125:2e9cc70d1897	2205	while (op_size > 0) {
AnnaBridge	125:2e9cc70d1897	2206	SCB->DCIMVAC = op_addr;
AnnaBridge	125:2e9cc70d1897	2207	op_addr += linesize;
AnnaBridge	125:2e9cc70d1897	2208	op_size -= (int32_t)linesize;
AnnaBridge	125:2e9cc70d1897	2209	}
AnnaBridge	125:2e9cc70d1897	2210
AnnaBridge	125:2e9cc70d1897	2211	__DSB();
AnnaBridge	125:2e9cc70d1897	2212	__ISB();
AnnaBridge	125:2e9cc70d1897	2213	#endif
AnnaBridge	125:2e9cc70d1897	2214	}
AnnaBridge	125:2e9cc70d1897	2215
AnnaBridge	125:2e9cc70d1897	2216
AnnaBridge	125:2e9cc70d1897	2217	/**
AnnaBridge	125:2e9cc70d1897	2218	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
AnnaBridge	125:2e9cc70d1897	2219	\brief D-Cache Clean by address
AnnaBridge	125:2e9cc70d1897	2220	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	125:2e9cc70d1897	2221	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	125:2e9cc70d1897	2222	*/
AnnaBridge	125:2e9cc70d1897	2223	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	125:2e9cc70d1897	2224	{
AnnaBridge	125:2e9cc70d1897	2225	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2226	int32_t op_size = dsize;
AnnaBridge	125:2e9cc70d1897	2227	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	125:2e9cc70d1897	2228	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
AnnaBridge	125:2e9cc70d1897	2229
AnnaBridge	125:2e9cc70d1897	2230	__DSB();
AnnaBridge	125:2e9cc70d1897	2231
AnnaBridge	125:2e9cc70d1897	2232	while (op_size > 0) {
AnnaBridge	125:2e9cc70d1897	2233	SCB->DCCMVAC = op_addr;
AnnaBridge	125:2e9cc70d1897	2234	op_addr += linesize;
AnnaBridge	125:2e9cc70d1897	2235	op_size -= (int32_t)linesize;
AnnaBridge	125:2e9cc70d1897	2236	}
AnnaBridge	125:2e9cc70d1897	2237
AnnaBridge	125:2e9cc70d1897	2238	__DSB();
AnnaBridge	125:2e9cc70d1897	2239	__ISB();
AnnaBridge	125:2e9cc70d1897	2240	#endif
AnnaBridge	125:2e9cc70d1897	2241	}
AnnaBridge	125:2e9cc70d1897	2242
AnnaBridge	125:2e9cc70d1897	2243
AnnaBridge	125:2e9cc70d1897	2244	/**
AnnaBridge	125:2e9cc70d1897	2245	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
AnnaBridge	125:2e9cc70d1897	2246	\brief D-Cache Clean and Invalidate by address
AnnaBridge	125:2e9cc70d1897	2247	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	125:2e9cc70d1897	2248	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	125:2e9cc70d1897	2249	*/
AnnaBridge	125:2e9cc70d1897	2250	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	125:2e9cc70d1897	2251	{
AnnaBridge	125:2e9cc70d1897	2252	#if (__DCACHE_PRESENT == 1)
AnnaBridge	125:2e9cc70d1897	2253	int32_t op_size = dsize;
AnnaBridge	125:2e9cc70d1897	2254	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	125:2e9cc70d1897	2255	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
AnnaBridge	125:2e9cc70d1897	2256
AnnaBridge	125:2e9cc70d1897	2257	__DSB();
AnnaBridge	125:2e9cc70d1897	2258
AnnaBridge	125:2e9cc70d1897	2259	while (op_size > 0) {
AnnaBridge	125:2e9cc70d1897	2260	SCB->DCCIMVAC = op_addr;
AnnaBridge	125:2e9cc70d1897	2261	op_addr += linesize;
AnnaBridge	125:2e9cc70d1897	2262	op_size -= (int32_t)linesize;
AnnaBridge	125:2e9cc70d1897	2263	}
AnnaBridge	125:2e9cc70d1897	2264
AnnaBridge	125:2e9cc70d1897	2265	__DSB();
AnnaBridge	125:2e9cc70d1897	2266	__ISB();
AnnaBridge	125:2e9cc70d1897	2267	#endif
AnnaBridge	125:2e9cc70d1897	2268	}
AnnaBridge	125:2e9cc70d1897	2269
AnnaBridge	125:2e9cc70d1897	2270
AnnaBridge	125:2e9cc70d1897	2271	/@} end of CMSIS_Core_CacheFunctions /
AnnaBridge	125:2e9cc70d1897	2272
AnnaBridge	125:2e9cc70d1897	2273
AnnaBridge	125:2e9cc70d1897	2274
AnnaBridge	125:2e9cc70d1897	2275	/* ################################## SysTick function ############################################ */
AnnaBridge	125:2e9cc70d1897	2276	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	125:2e9cc70d1897	2277	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	125:2e9cc70d1897	2278	\brief Functions that configure the System.
AnnaBridge	125:2e9cc70d1897	2279	@{
AnnaBridge	125:2e9cc70d1897	2280	*/
AnnaBridge	125:2e9cc70d1897	2281
AnnaBridge	125:2e9cc70d1897	2282	#if (__Vendor_SysTickConfig == 0)
AnnaBridge	125:2e9cc70d1897	2283
AnnaBridge	125:2e9cc70d1897	2284	/** \brief System Tick Configuration
AnnaBridge	125:2e9cc70d1897	2285
AnnaBridge	125:2e9cc70d1897	2286	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	125:2e9cc70d1897	2287	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	125:2e9cc70d1897	2288
AnnaBridge	125:2e9cc70d1897	2289	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	125:2e9cc70d1897	2290
AnnaBridge	125:2e9cc70d1897	2291	\return 0 Function succeeded.
AnnaBridge	125:2e9cc70d1897	2292	\return 1 Function failed.
AnnaBridge	125:2e9cc70d1897	2293
AnnaBridge	125:2e9cc70d1897	2294	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	125:2e9cc70d1897	2295	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	125:2e9cc70d1897	2296	must contain a vendor-specific implementation of this function.
AnnaBridge	125:2e9cc70d1897	2297
AnnaBridge	125:2e9cc70d1897	2298	*/
AnnaBridge	125:2e9cc70d1897	2299	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	125:2e9cc70d1897	2300	{
AnnaBridge	125:2e9cc70d1897	2301	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
AnnaBridge	125:2e9cc70d1897	2302
AnnaBridge	125:2e9cc70d1897	2303	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	125:2e9cc70d1897	2304	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	125:2e9cc70d1897	2305	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	125:2e9cc70d1897	2306	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	125:2e9cc70d1897	2307	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	125:2e9cc70d1897	2308	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	125:2e9cc70d1897	2309	return (0UL); /* Function successful */
AnnaBridge	125:2e9cc70d1897	2310	}
AnnaBridge	125:2e9cc70d1897	2311
AnnaBridge	125:2e9cc70d1897	2312	#endif
AnnaBridge	125:2e9cc70d1897	2313
AnnaBridge	125:2e9cc70d1897	2314	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	125:2e9cc70d1897	2315
AnnaBridge	125:2e9cc70d1897	2316
AnnaBridge	125:2e9cc70d1897	2317
AnnaBridge	125:2e9cc70d1897	2318	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	125:2e9cc70d1897	2319	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	125:2e9cc70d1897	2320	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	125:2e9cc70d1897	2321	\brief Functions that access the ITM debug interface.
AnnaBridge	125:2e9cc70d1897	2322	@{
AnnaBridge	125:2e9cc70d1897	2323	*/
AnnaBridge	125:2e9cc70d1897	2324
AnnaBridge	125:2e9cc70d1897	2325	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	125:2e9cc70d1897	2326	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	125:2e9cc70d1897	2327
AnnaBridge	125:2e9cc70d1897	2328
AnnaBridge	125:2e9cc70d1897	2329	/** \brief ITM Send Character
AnnaBridge	125:2e9cc70d1897	2330
AnnaBridge	125:2e9cc70d1897	2331	The function transmits a character via the ITM channel 0, and
AnnaBridge	125:2e9cc70d1897	2332	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	125:2e9cc70d1897	2333	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	125:2e9cc70d1897	2334
AnnaBridge	125:2e9cc70d1897	2335	\param [in] ch Character to transmit.
AnnaBridge	125:2e9cc70d1897	2336
AnnaBridge	125:2e9cc70d1897	2337	\returns Character to transmit.
AnnaBridge	125:2e9cc70d1897	2338	*/
AnnaBridge	125:2e9cc70d1897	2339	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	125:2e9cc70d1897	2340	{
AnnaBridge	125:2e9cc70d1897	2341	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	125:2e9cc70d1897	2342	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	125:2e9cc70d1897	2343	{
AnnaBridge	125:2e9cc70d1897	2344	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
AnnaBridge	125:2e9cc70d1897	2345	ITM->PORT[0].u8 = (uint8_t)ch;
AnnaBridge	125:2e9cc70d1897	2346	}
AnnaBridge	125:2e9cc70d1897	2347	return (ch);
AnnaBridge	125:2e9cc70d1897	2348	}
AnnaBridge	125:2e9cc70d1897	2349
AnnaBridge	125:2e9cc70d1897	2350
AnnaBridge	125:2e9cc70d1897	2351	/** \brief ITM Receive Character
AnnaBridge	125:2e9cc70d1897	2352
AnnaBridge	125:2e9cc70d1897	2353	The function inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	125:2e9cc70d1897	2354
AnnaBridge	125:2e9cc70d1897	2355	\return Received character.
AnnaBridge	125:2e9cc70d1897	2356	\return -1 No character pending.
AnnaBridge	125:2e9cc70d1897	2357	*/
AnnaBridge	125:2e9cc70d1897	2358	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
AnnaBridge	125:2e9cc70d1897	2359	int32_t ch = -1; /* no character available */
AnnaBridge	125:2e9cc70d1897	2360
AnnaBridge	125:2e9cc70d1897	2361	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
AnnaBridge	125:2e9cc70d1897	2362	ch = ITM_RxBuffer;
AnnaBridge	125:2e9cc70d1897	2363	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	125:2e9cc70d1897	2364	}
AnnaBridge	125:2e9cc70d1897	2365
AnnaBridge	125:2e9cc70d1897	2366	return (ch);
AnnaBridge	125:2e9cc70d1897	2367	}
AnnaBridge	125:2e9cc70d1897	2368
AnnaBridge	125:2e9cc70d1897	2369
AnnaBridge	125:2e9cc70d1897	2370	/** \brief ITM Check Character
AnnaBridge	125:2e9cc70d1897	2371
AnnaBridge	125:2e9cc70d1897	2372	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	125:2e9cc70d1897	2373
AnnaBridge	125:2e9cc70d1897	2374	\return 0 No character available.
AnnaBridge	125:2e9cc70d1897	2375	\return 1 Character available.
AnnaBridge	125:2e9cc70d1897	2376	*/
AnnaBridge	125:2e9cc70d1897	2377	__STATIC_INLINE int32_t ITM_CheckChar (void) {
AnnaBridge	125:2e9cc70d1897	2378
AnnaBridge	125:2e9cc70d1897	2379	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
AnnaBridge	125:2e9cc70d1897	2380	return (0); /* no character available */
AnnaBridge	125:2e9cc70d1897	2381	} else {
AnnaBridge	125:2e9cc70d1897	2382	return (1); /* character available */
AnnaBridge	125:2e9cc70d1897	2383	}
AnnaBridge	125:2e9cc70d1897	2384	}
AnnaBridge	125:2e9cc70d1897	2385
AnnaBridge	125:2e9cc70d1897	2386	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	125:2e9cc70d1897	2387
AnnaBridge	125:2e9cc70d1897	2388
AnnaBridge	125:2e9cc70d1897	2389
AnnaBridge	125:2e9cc70d1897	2390
AnnaBridge	125:2e9cc70d1897	2391	#ifdef __cplusplus
AnnaBridge	125:2e9cc70d1897	2392	}
AnnaBridge	125:2e9cc70d1897	2393	#endif
AnnaBridge	125:2e9cc70d1897	2394
AnnaBridge	125:2e9cc70d1897	2395	#endif /* __CORE_CM7_H_DEPENDANT */
AnnaBridge	125:2e9cc70d1897	2396
AnnaBridge	125:2e9cc70d1897	2397	#endif /* __CMSIS_GENERIC */