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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32620HSP/core_caFunc.h@125:2e9cc70d1897, 2016-08-31 (annotated)

Committer:
AnnaBridge
Date:
Wed Aug 31 18:09:46 2016 +0100
Revision:
125:2e9cc70d1897
Child:
130:d75b3fe1f5cb
Release 125 of the mbed library



Changes:



New target - KL27Z_IAR

New target - MAX32620HSP_ARM_STD

New target - MAX32620HSP_GCC_ARM

New target - MAX32620HSP_IAR

New target - NCS36510_ARM_STD

New target - NCS36510_GCC_ARM

New target - NCS36510_IAR



Added support for NSAPI_REUSEADDR to the lwip interface.

STM32F3 family : Add and enable asynchronous serial, plus tests.

STM32L4 family : Add and enable asynchronous serial, plus tests.

Fixing issue where GCC fails to report compile errors when non-verbose.

Add ethernet and IPV4 support for: NUCLEO_F207ZG, NUCLEO_F429ZI, NUCLEO_F767ZI, DISCO_F746NG.

RZ_A1H - Enable SPI1 on pins P6_4 to P6_7.

KL27Z : SPI driver bug fixes and Improvements, ARM linker file update.

STM32F4, STM32F7 families : Add entropy functions, documentation, code improvements, fix build issues.

HEXIWEAR: Update I2C pin mapping, Add support to create KDS projects.

LWIP - fix recv blocking send on accepted sockets.

SingletonPtr bugfixes.

Beetle: Implement sleep API.

uVisor: Update to v0.20.1-alpha, minor documentation update.

STM32F3 : fix RTOS IAR test, RTOS GCC_ARM test.

nrf5x : Introduce uart hardware flow control configuration.

K64F/K22F: Implement HAL lp_timer API.

Ticker: Move ticker initialisation to object creation time.

STM32F4 : remove printf from pwmout

NXP : Fix multiple definition errors in GCC_CR build,  fix linker errors.

Add TOOLCHAIN_GCC_CR support.

STM32L1 family : Add and enable asynchronous serial, plus tests.

mbed-client : Fix Bootstrap and Connector functionality.

NUC472 : Fix Ethernet wrong INT status in RX_Action.

RTX_CM_lib.h : fix compiler warning.

NUCLEO : Use GCC small build for 64K flash STM32.

STM32F2 family : Add and enable asynchronous serial, plus tests.

uvisor : Move page heap after uVisor private data, update page allocator.

K64F: Revert to hardcoded stack pointer in RTX .

dns-query : Internal API change , documentation, Added support for multiple results and ipv6.

Add support for implementation-provided DNS servers.

Adopted netconn_gethostbyname in the lwip interface.

Restructured nsapi_dns.h to have clear separation between C/C++ .

Tool fixes.

Tests : New ones added and some updates to existing.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 125:2e9cc70d1897 1 /**************************************************************************//**
AnnaBridge 125:2e9cc70d1897 2 * @file core_caFunc.h
AnnaBridge 125:2e9cc70d1897 3 * @brief CMSIS Cortex-A Core Function Access Header File
AnnaBridge 125:2e9cc70d1897 4 * @version V3.10
AnnaBridge 125:2e9cc70d1897 5 * @date 30 Oct 2013
AnnaBridge 125:2e9cc70d1897 6 *
AnnaBridge 125:2e9cc70d1897 7 * @note
AnnaBridge 125:2e9cc70d1897 8 *
AnnaBridge 125:2e9cc70d1897 9 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
AnnaBridge 125:2e9cc70d1897 11
AnnaBridge 125:2e9cc70d1897 12 All rights reserved.
AnnaBridge 125:2e9cc70d1897 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 125:2e9cc70d1897 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 125:2e9cc70d1897 15 - Redistributions of source code must retain the above copyright
AnnaBridge 125:2e9cc70d1897 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 125:2e9cc70d1897 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 125:2e9cc70d1897 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 125:2e9cc70d1897 19 documentation and/or other materials provided with the distribution.
AnnaBridge 125:2e9cc70d1897 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 125:2e9cc70d1897 21 to endorse or promote products derived from this software without
AnnaBridge 125:2e9cc70d1897 22 specific prior written permission.
AnnaBridge 125:2e9cc70d1897 23 *
AnnaBridge 125:2e9cc70d1897 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 125:2e9cc70d1897 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 125:2e9cc70d1897 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 125:2e9cc70d1897 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 125:2e9cc70d1897 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 125:2e9cc70d1897 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 125:2e9cc70d1897 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 125:2e9cc70d1897 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 125:2e9cc70d1897 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 125:2e9cc70d1897 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 125:2e9cc70d1897 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 125:2e9cc70d1897 35 ---------------------------------------------------------------------------*/
AnnaBridge 125:2e9cc70d1897 36
AnnaBridge 125:2e9cc70d1897 37
AnnaBridge 125:2e9cc70d1897 38 #ifndef __CORE_CAFUNC_H__
AnnaBridge 125:2e9cc70d1897 39 #define __CORE_CAFUNC_H__
AnnaBridge 125:2e9cc70d1897 40
AnnaBridge 125:2e9cc70d1897 41
AnnaBridge 125:2e9cc70d1897 42 /* ########################### Core Function Access ########################### */
AnnaBridge 125:2e9cc70d1897 43 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 125:2e9cc70d1897 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 125:2e9cc70d1897 45 @{
AnnaBridge 125:2e9cc70d1897 46 */
AnnaBridge 125:2e9cc70d1897 47
AnnaBridge 125:2e9cc70d1897 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
AnnaBridge 125:2e9cc70d1897 49 /* ARM armcc specific functions */
AnnaBridge 125:2e9cc70d1897 50
AnnaBridge 125:2e9cc70d1897 51 #if (__ARMCC_VERSION < 400677)
AnnaBridge 125:2e9cc70d1897 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
AnnaBridge 125:2e9cc70d1897 53 #endif
AnnaBridge 125:2e9cc70d1897 54
AnnaBridge 125:2e9cc70d1897 55 #define MODE_USR 0x10
AnnaBridge 125:2e9cc70d1897 56 #define MODE_FIQ 0x11
AnnaBridge 125:2e9cc70d1897 57 #define MODE_IRQ 0x12
AnnaBridge 125:2e9cc70d1897 58 #define MODE_SVC 0x13
AnnaBridge 125:2e9cc70d1897 59 #define MODE_MON 0x16
AnnaBridge 125:2e9cc70d1897 60 #define MODE_ABT 0x17
AnnaBridge 125:2e9cc70d1897 61 #define MODE_HYP 0x1A
AnnaBridge 125:2e9cc70d1897 62 #define MODE_UND 0x1B
AnnaBridge 125:2e9cc70d1897 63 #define MODE_SYS 0x1F
AnnaBridge 125:2e9cc70d1897 64
AnnaBridge 125:2e9cc70d1897 65 /** \brief Get APSR Register
AnnaBridge 125:2e9cc70d1897 66
AnnaBridge 125:2e9cc70d1897 67 This function returns the content of the APSR Register.
AnnaBridge 125:2e9cc70d1897 68
AnnaBridge 125:2e9cc70d1897 69 \return APSR Register value
AnnaBridge 125:2e9cc70d1897 70 */
AnnaBridge 125:2e9cc70d1897 71 __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 125:2e9cc70d1897 72 {
AnnaBridge 125:2e9cc70d1897 73 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 125:2e9cc70d1897 74 return(__regAPSR);
AnnaBridge 125:2e9cc70d1897 75 }
AnnaBridge 125:2e9cc70d1897 76
AnnaBridge 125:2e9cc70d1897 77
AnnaBridge 125:2e9cc70d1897 78 /** \brief Get CPSR Register
AnnaBridge 125:2e9cc70d1897 79
AnnaBridge 125:2e9cc70d1897 80 This function returns the content of the CPSR Register.
AnnaBridge 125:2e9cc70d1897 81
AnnaBridge 125:2e9cc70d1897 82 \return CPSR Register value
AnnaBridge 125:2e9cc70d1897 83 */
AnnaBridge 125:2e9cc70d1897 84 __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 125:2e9cc70d1897 85 {
AnnaBridge 125:2e9cc70d1897 86 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 125:2e9cc70d1897 87 return(__regCPSR);
AnnaBridge 125:2e9cc70d1897 88 }
AnnaBridge 125:2e9cc70d1897 89
AnnaBridge 125:2e9cc70d1897 90 /** \brief Set Stack Pointer
AnnaBridge 125:2e9cc70d1897 91
AnnaBridge 125:2e9cc70d1897 92 This function assigns the given value to the current stack pointer.
AnnaBridge 125:2e9cc70d1897 93
AnnaBridge 125:2e9cc70d1897 94 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 125:2e9cc70d1897 95 */
AnnaBridge 125:2e9cc70d1897 96 register uint32_t __regSP __ASM("sp");
AnnaBridge 125:2e9cc70d1897 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 125:2e9cc70d1897 98 {
AnnaBridge 125:2e9cc70d1897 99 __regSP = topOfStack;
AnnaBridge 125:2e9cc70d1897 100 }
AnnaBridge 125:2e9cc70d1897 101
AnnaBridge 125:2e9cc70d1897 102
AnnaBridge 125:2e9cc70d1897 103 /** \brief Get link register
AnnaBridge 125:2e9cc70d1897 104
AnnaBridge 125:2e9cc70d1897 105 This function returns the value of the link register
AnnaBridge 125:2e9cc70d1897 106
AnnaBridge 125:2e9cc70d1897 107 \return Value of link register
AnnaBridge 125:2e9cc70d1897 108 */
AnnaBridge 125:2e9cc70d1897 109 register uint32_t __reglr __ASM("lr");
AnnaBridge 125:2e9cc70d1897 110 __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 125:2e9cc70d1897 111 {
AnnaBridge 125:2e9cc70d1897 112 return(__reglr);
AnnaBridge 125:2e9cc70d1897 113 }
AnnaBridge 125:2e9cc70d1897 114
AnnaBridge 125:2e9cc70d1897 115 /** \brief Set link register
AnnaBridge 125:2e9cc70d1897 116
AnnaBridge 125:2e9cc70d1897 117 This function sets the value of the link register
AnnaBridge 125:2e9cc70d1897 118
AnnaBridge 125:2e9cc70d1897 119 \param [in] lr LR value to set
AnnaBridge 125:2e9cc70d1897 120 */
AnnaBridge 125:2e9cc70d1897 121 __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 125:2e9cc70d1897 122 {
AnnaBridge 125:2e9cc70d1897 123 __reglr = lr;
AnnaBridge 125:2e9cc70d1897 124 }
AnnaBridge 125:2e9cc70d1897 125
AnnaBridge 125:2e9cc70d1897 126 /** \brief Set Process Stack Pointer
AnnaBridge 125:2e9cc70d1897 127
AnnaBridge 125:2e9cc70d1897 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 125:2e9cc70d1897 129
AnnaBridge 125:2e9cc70d1897 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 125:2e9cc70d1897 131 */
AnnaBridge 125:2e9cc70d1897 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 125:2e9cc70d1897 133 {
AnnaBridge 125:2e9cc70d1897 134 ARM
AnnaBridge 125:2e9cc70d1897 135 PRESERVE8
AnnaBridge 125:2e9cc70d1897 136
AnnaBridge 125:2e9cc70d1897 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
AnnaBridge 125:2e9cc70d1897 138 MRS R1, CPSR
AnnaBridge 125:2e9cc70d1897 139 CPS #MODE_SYS ;no effect in USR mode
AnnaBridge 125:2e9cc70d1897 140 MOV SP, R0
AnnaBridge 125:2e9cc70d1897 141 MSR CPSR_c, R1 ;no effect in USR mode
AnnaBridge 125:2e9cc70d1897 142 ISB
AnnaBridge 125:2e9cc70d1897 143 BX LR
AnnaBridge 125:2e9cc70d1897 144
AnnaBridge 125:2e9cc70d1897 145 }
AnnaBridge 125:2e9cc70d1897 146
AnnaBridge 125:2e9cc70d1897 147 /** \brief Set User Mode
AnnaBridge 125:2e9cc70d1897 148
AnnaBridge 125:2e9cc70d1897 149 This function changes the processor state to User Mode
AnnaBridge 125:2e9cc70d1897 150 */
AnnaBridge 125:2e9cc70d1897 151 __STATIC_ASM void __set_CPS_USR(void)
AnnaBridge 125:2e9cc70d1897 152 {
AnnaBridge 125:2e9cc70d1897 153 ARM
AnnaBridge 125:2e9cc70d1897 154
AnnaBridge 125:2e9cc70d1897 155 CPS #MODE_USR
AnnaBridge 125:2e9cc70d1897 156 BX LR
AnnaBridge 125:2e9cc70d1897 157 }
AnnaBridge 125:2e9cc70d1897 158
AnnaBridge 125:2e9cc70d1897 159
AnnaBridge 125:2e9cc70d1897 160 /** \brief Enable FIQ
AnnaBridge 125:2e9cc70d1897 161
AnnaBridge 125:2e9cc70d1897 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 125:2e9cc70d1897 163 Can only be executed in Privileged modes.
AnnaBridge 125:2e9cc70d1897 164 */
AnnaBridge 125:2e9cc70d1897 165 #define __enable_fault_irq __enable_fiq
AnnaBridge 125:2e9cc70d1897 166
AnnaBridge 125:2e9cc70d1897 167
AnnaBridge 125:2e9cc70d1897 168 /** \brief Disable FIQ
AnnaBridge 125:2e9cc70d1897 169
AnnaBridge 125:2e9cc70d1897 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 125:2e9cc70d1897 171 Can only be executed in Privileged modes.
AnnaBridge 125:2e9cc70d1897 172 */
AnnaBridge 125:2e9cc70d1897 173 #define __disable_fault_irq __disable_fiq
AnnaBridge 125:2e9cc70d1897 174
AnnaBridge 125:2e9cc70d1897 175
AnnaBridge 125:2e9cc70d1897 176 /** \brief Get FPSCR
AnnaBridge 125:2e9cc70d1897 177
AnnaBridge 125:2e9cc70d1897 178 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 125:2e9cc70d1897 179
AnnaBridge 125:2e9cc70d1897 180 \return Floating Point Status/Control register value
AnnaBridge 125:2e9cc70d1897 181 */
AnnaBridge 125:2e9cc70d1897 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 125:2e9cc70d1897 183 {
AnnaBridge 125:2e9cc70d1897 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 125:2e9cc70d1897 185 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 125:2e9cc70d1897 186 return(__regfpscr);
AnnaBridge 125:2e9cc70d1897 187 #else
AnnaBridge 125:2e9cc70d1897 188 return(0);
AnnaBridge 125:2e9cc70d1897 189 #endif
AnnaBridge 125:2e9cc70d1897 190 }
AnnaBridge 125:2e9cc70d1897 191
AnnaBridge 125:2e9cc70d1897 192
AnnaBridge 125:2e9cc70d1897 193 /** \brief Set FPSCR
AnnaBridge 125:2e9cc70d1897 194
AnnaBridge 125:2e9cc70d1897 195 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 125:2e9cc70d1897 196
AnnaBridge 125:2e9cc70d1897 197 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 125:2e9cc70d1897 198 */
AnnaBridge 125:2e9cc70d1897 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 125:2e9cc70d1897 200 {
AnnaBridge 125:2e9cc70d1897 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 125:2e9cc70d1897 202 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 125:2e9cc70d1897 203 __regfpscr = (fpscr);
AnnaBridge 125:2e9cc70d1897 204 #endif
AnnaBridge 125:2e9cc70d1897 205 }
AnnaBridge 125:2e9cc70d1897 206
AnnaBridge 125:2e9cc70d1897 207 /** \brief Get FPEXC
AnnaBridge 125:2e9cc70d1897 208
AnnaBridge 125:2e9cc70d1897 209 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 125:2e9cc70d1897 210
AnnaBridge 125:2e9cc70d1897 211 \return Floating Point Exception Control register value
AnnaBridge 125:2e9cc70d1897 212 */
AnnaBridge 125:2e9cc70d1897 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 125:2e9cc70d1897 214 {
AnnaBridge 125:2e9cc70d1897 215 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 216 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 125:2e9cc70d1897 217 return(__regfpexc);
AnnaBridge 125:2e9cc70d1897 218 #else
AnnaBridge 125:2e9cc70d1897 219 return(0);
AnnaBridge 125:2e9cc70d1897 220 #endif
AnnaBridge 125:2e9cc70d1897 221 }
AnnaBridge 125:2e9cc70d1897 222
AnnaBridge 125:2e9cc70d1897 223
AnnaBridge 125:2e9cc70d1897 224 /** \brief Set FPEXC
AnnaBridge 125:2e9cc70d1897 225
AnnaBridge 125:2e9cc70d1897 226 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 125:2e9cc70d1897 227
AnnaBridge 125:2e9cc70d1897 228 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 125:2e9cc70d1897 229 */
AnnaBridge 125:2e9cc70d1897 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 125:2e9cc70d1897 231 {
AnnaBridge 125:2e9cc70d1897 232 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 233 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 125:2e9cc70d1897 234 __regfpexc = (fpexc);
AnnaBridge 125:2e9cc70d1897 235 #endif
AnnaBridge 125:2e9cc70d1897 236 }
AnnaBridge 125:2e9cc70d1897 237
AnnaBridge 125:2e9cc70d1897 238 /** \brief Get CPACR
AnnaBridge 125:2e9cc70d1897 239
AnnaBridge 125:2e9cc70d1897 240 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 125:2e9cc70d1897 241
AnnaBridge 125:2e9cc70d1897 242 \return Coprocessor Access Control register value
AnnaBridge 125:2e9cc70d1897 243 */
AnnaBridge 125:2e9cc70d1897 244 __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 125:2e9cc70d1897 245 {
AnnaBridge 125:2e9cc70d1897 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 125:2e9cc70d1897 247 return __regCPACR;
AnnaBridge 125:2e9cc70d1897 248 }
AnnaBridge 125:2e9cc70d1897 249
AnnaBridge 125:2e9cc70d1897 250 /** \brief Set CPACR
AnnaBridge 125:2e9cc70d1897 251
AnnaBridge 125:2e9cc70d1897 252 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 125:2e9cc70d1897 253
AnnaBridge 125:2e9cc70d1897 254 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 125:2e9cc70d1897 255 */
AnnaBridge 125:2e9cc70d1897 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 125:2e9cc70d1897 257 {
AnnaBridge 125:2e9cc70d1897 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 125:2e9cc70d1897 259 __regCPACR = cpacr;
AnnaBridge 125:2e9cc70d1897 260 __ISB();
AnnaBridge 125:2e9cc70d1897 261 }
AnnaBridge 125:2e9cc70d1897 262
AnnaBridge 125:2e9cc70d1897 263 /** \brief Get CBAR
AnnaBridge 125:2e9cc70d1897 264
AnnaBridge 125:2e9cc70d1897 265 This function returns the value of the Configuration Base Address register.
AnnaBridge 125:2e9cc70d1897 266
AnnaBridge 125:2e9cc70d1897 267 \return Configuration Base Address register value
AnnaBridge 125:2e9cc70d1897 268 */
AnnaBridge 125:2e9cc70d1897 269 __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 125:2e9cc70d1897 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 125:2e9cc70d1897 271 return(__regCBAR);
AnnaBridge 125:2e9cc70d1897 272 }
AnnaBridge 125:2e9cc70d1897 273
AnnaBridge 125:2e9cc70d1897 274 /** \brief Get TTBR0
AnnaBridge 125:2e9cc70d1897 275
AnnaBridge 125:2e9cc70d1897 276 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 125:2e9cc70d1897 277
AnnaBridge 125:2e9cc70d1897 278 \return Translation Table Base Register 0 value
AnnaBridge 125:2e9cc70d1897 279 */
AnnaBridge 125:2e9cc70d1897 280 __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 125:2e9cc70d1897 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 125:2e9cc70d1897 282 return(__regTTBR0);
AnnaBridge 125:2e9cc70d1897 283 }
AnnaBridge 125:2e9cc70d1897 284
AnnaBridge 125:2e9cc70d1897 285 /** \brief Set TTBR0
AnnaBridge 125:2e9cc70d1897 286
AnnaBridge 125:2e9cc70d1897 287 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 125:2e9cc70d1897 288
AnnaBridge 125:2e9cc70d1897 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 125:2e9cc70d1897 290 */
AnnaBridge 125:2e9cc70d1897 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 125:2e9cc70d1897 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 125:2e9cc70d1897 293 __regTTBR0 = ttbr0;
AnnaBridge 125:2e9cc70d1897 294 __ISB();
AnnaBridge 125:2e9cc70d1897 295 }
AnnaBridge 125:2e9cc70d1897 296
AnnaBridge 125:2e9cc70d1897 297 /** \brief Get DACR
AnnaBridge 125:2e9cc70d1897 298
AnnaBridge 125:2e9cc70d1897 299 This function returns the value of the Domain Access Control Register.
AnnaBridge 125:2e9cc70d1897 300
AnnaBridge 125:2e9cc70d1897 301 \return Domain Access Control Register value
AnnaBridge 125:2e9cc70d1897 302 */
AnnaBridge 125:2e9cc70d1897 303 __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 125:2e9cc70d1897 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 125:2e9cc70d1897 305 return(__regDACR);
AnnaBridge 125:2e9cc70d1897 306 }
AnnaBridge 125:2e9cc70d1897 307
AnnaBridge 125:2e9cc70d1897 308 /** \brief Set DACR
AnnaBridge 125:2e9cc70d1897 309
AnnaBridge 125:2e9cc70d1897 310 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 125:2e9cc70d1897 311
AnnaBridge 125:2e9cc70d1897 312 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 125:2e9cc70d1897 313 */
AnnaBridge 125:2e9cc70d1897 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 125:2e9cc70d1897 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 125:2e9cc70d1897 316 __regDACR = dacr;
AnnaBridge 125:2e9cc70d1897 317 __ISB();
AnnaBridge 125:2e9cc70d1897 318 }
AnnaBridge 125:2e9cc70d1897 319
AnnaBridge 125:2e9cc70d1897 320 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 125:2e9cc70d1897 321
AnnaBridge 125:2e9cc70d1897 322 /** \brief Set SCTLR
AnnaBridge 125:2e9cc70d1897 323
AnnaBridge 125:2e9cc70d1897 324 This function assigns the given value to the System Control Register.
AnnaBridge 125:2e9cc70d1897 325
AnnaBridge 125:2e9cc70d1897 326 \param [in] sctlr System Control Register value to set
AnnaBridge 125:2e9cc70d1897 327 */
AnnaBridge 125:2e9cc70d1897 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 125:2e9cc70d1897 329 {
AnnaBridge 125:2e9cc70d1897 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 125:2e9cc70d1897 331 __regSCTLR = sctlr;
AnnaBridge 125:2e9cc70d1897 332 }
AnnaBridge 125:2e9cc70d1897 333
AnnaBridge 125:2e9cc70d1897 334 /** \brief Get SCTLR
AnnaBridge 125:2e9cc70d1897 335
AnnaBridge 125:2e9cc70d1897 336 This function returns the value of the System Control Register.
AnnaBridge 125:2e9cc70d1897 337
AnnaBridge 125:2e9cc70d1897 338 \return System Control Register value
AnnaBridge 125:2e9cc70d1897 339 */
AnnaBridge 125:2e9cc70d1897 340 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 125:2e9cc70d1897 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 125:2e9cc70d1897 342 return(__regSCTLR);
AnnaBridge 125:2e9cc70d1897 343 }
AnnaBridge 125:2e9cc70d1897 344
AnnaBridge 125:2e9cc70d1897 345 /** \brief Enable Caches
AnnaBridge 125:2e9cc70d1897 346
AnnaBridge 125:2e9cc70d1897 347 Enable Caches
AnnaBridge 125:2e9cc70d1897 348 */
AnnaBridge 125:2e9cc70d1897 349 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 125:2e9cc70d1897 350 // Set I bit 12 to enable I Cache
AnnaBridge 125:2e9cc70d1897 351 // Set C bit 2 to enable D Cache
AnnaBridge 125:2e9cc70d1897 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 125:2e9cc70d1897 353 }
AnnaBridge 125:2e9cc70d1897 354
AnnaBridge 125:2e9cc70d1897 355 /** \brief Disable Caches
AnnaBridge 125:2e9cc70d1897 356
AnnaBridge 125:2e9cc70d1897 357 Disable Caches
AnnaBridge 125:2e9cc70d1897 358 */
AnnaBridge 125:2e9cc70d1897 359 __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 125:2e9cc70d1897 360 // Clear I bit 12 to disable I Cache
AnnaBridge 125:2e9cc70d1897 361 // Clear C bit 2 to disable D Cache
AnnaBridge 125:2e9cc70d1897 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 125:2e9cc70d1897 363 __ISB();
AnnaBridge 125:2e9cc70d1897 364 }
AnnaBridge 125:2e9cc70d1897 365
AnnaBridge 125:2e9cc70d1897 366 /** \brief Enable BTAC
AnnaBridge 125:2e9cc70d1897 367
AnnaBridge 125:2e9cc70d1897 368 Enable BTAC
AnnaBridge 125:2e9cc70d1897 369 */
AnnaBridge 125:2e9cc70d1897 370 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 125:2e9cc70d1897 371 // Set Z bit 11 to enable branch prediction
AnnaBridge 125:2e9cc70d1897 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 125:2e9cc70d1897 373 __ISB();
AnnaBridge 125:2e9cc70d1897 374 }
AnnaBridge 125:2e9cc70d1897 375
AnnaBridge 125:2e9cc70d1897 376 /** \brief Disable BTAC
AnnaBridge 125:2e9cc70d1897 377
AnnaBridge 125:2e9cc70d1897 378 Disable BTAC
AnnaBridge 125:2e9cc70d1897 379 */
AnnaBridge 125:2e9cc70d1897 380 __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 125:2e9cc70d1897 381 // Clear Z bit 11 to disable branch prediction
AnnaBridge 125:2e9cc70d1897 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 125:2e9cc70d1897 383 }
AnnaBridge 125:2e9cc70d1897 384
AnnaBridge 125:2e9cc70d1897 385
AnnaBridge 125:2e9cc70d1897 386 /** \brief Enable MMU
AnnaBridge 125:2e9cc70d1897 387
AnnaBridge 125:2e9cc70d1897 388 Enable MMU
AnnaBridge 125:2e9cc70d1897 389 */
AnnaBridge 125:2e9cc70d1897 390 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 125:2e9cc70d1897 391 // Set M bit 0 to enable the MMU
AnnaBridge 125:2e9cc70d1897 392 // Set AFE bit to enable simplified access permissions model
AnnaBridge 125:2e9cc70d1897 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 125:2e9cc70d1897 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 125:2e9cc70d1897 395 __ISB();
AnnaBridge 125:2e9cc70d1897 396 }
AnnaBridge 125:2e9cc70d1897 397
AnnaBridge 125:2e9cc70d1897 398 /** \brief Disable MMU
AnnaBridge 125:2e9cc70d1897 399
AnnaBridge 125:2e9cc70d1897 400 Disable MMU
AnnaBridge 125:2e9cc70d1897 401 */
AnnaBridge 125:2e9cc70d1897 402 __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 125:2e9cc70d1897 403 // Clear M bit 0 to disable the MMU
AnnaBridge 125:2e9cc70d1897 404 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 125:2e9cc70d1897 405 __ISB();
AnnaBridge 125:2e9cc70d1897 406 }
AnnaBridge 125:2e9cc70d1897 407
AnnaBridge 125:2e9cc70d1897 408 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 125:2e9cc70d1897 409 /** \brief Invalidate the whole tlb
AnnaBridge 125:2e9cc70d1897 410
AnnaBridge 125:2e9cc70d1897 411 TLBIALL. Invalidate the whole tlb
AnnaBridge 125:2e9cc70d1897 412 */
AnnaBridge 125:2e9cc70d1897 413
AnnaBridge 125:2e9cc70d1897 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 125:2e9cc70d1897 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 125:2e9cc70d1897 416 __TLBIALL = 0;
AnnaBridge 125:2e9cc70d1897 417 __DSB();
AnnaBridge 125:2e9cc70d1897 418 __ISB();
AnnaBridge 125:2e9cc70d1897 419 }
AnnaBridge 125:2e9cc70d1897 420
AnnaBridge 125:2e9cc70d1897 421 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 125:2e9cc70d1897 422 /** \brief Invalidate entire branch predictor array
AnnaBridge 125:2e9cc70d1897 423
AnnaBridge 125:2e9cc70d1897 424 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 125:2e9cc70d1897 425 */
AnnaBridge 125:2e9cc70d1897 426
AnnaBridge 125:2e9cc70d1897 427 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 125:2e9cc70d1897 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 125:2e9cc70d1897 429 __BPIALL = 0;
AnnaBridge 125:2e9cc70d1897 430 __DSB(); //ensure completion of the invalidation
AnnaBridge 125:2e9cc70d1897 431 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 125:2e9cc70d1897 432 }
AnnaBridge 125:2e9cc70d1897 433
AnnaBridge 125:2e9cc70d1897 434
AnnaBridge 125:2e9cc70d1897 435 /******************************** L1 cache operations ******************************************************/
AnnaBridge 125:2e9cc70d1897 436
AnnaBridge 125:2e9cc70d1897 437 /** \brief Invalidate the whole I$
AnnaBridge 125:2e9cc70d1897 438
AnnaBridge 125:2e9cc70d1897 439 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 125:2e9cc70d1897 440 */
AnnaBridge 125:2e9cc70d1897 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 125:2e9cc70d1897 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 125:2e9cc70d1897 443 __ICIALLU = 0;
AnnaBridge 125:2e9cc70d1897 444 __DSB(); //ensure completion of the invalidation
AnnaBridge 125:2e9cc70d1897 445 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 125:2e9cc70d1897 446 }
AnnaBridge 125:2e9cc70d1897 447
AnnaBridge 125:2e9cc70d1897 448 /** \brief Clean D$ by MVA
AnnaBridge 125:2e9cc70d1897 449
AnnaBridge 125:2e9cc70d1897 450 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 125:2e9cc70d1897 451 */
AnnaBridge 125:2e9cc70d1897 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 125:2e9cc70d1897 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 125:2e9cc70d1897 454 __DCCMVAC = (uint32_t)va;
AnnaBridge 125:2e9cc70d1897 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 125:2e9cc70d1897 456 }
AnnaBridge 125:2e9cc70d1897 457
AnnaBridge 125:2e9cc70d1897 458 /** \brief Invalidate D$ by MVA
AnnaBridge 125:2e9cc70d1897 459
AnnaBridge 125:2e9cc70d1897 460 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 125:2e9cc70d1897 461 */
AnnaBridge 125:2e9cc70d1897 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 125:2e9cc70d1897 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 125:2e9cc70d1897 464 __DCIMVAC = (uint32_t)va;
AnnaBridge 125:2e9cc70d1897 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 125:2e9cc70d1897 466 }
AnnaBridge 125:2e9cc70d1897 467
AnnaBridge 125:2e9cc70d1897 468 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 125:2e9cc70d1897 469
AnnaBridge 125:2e9cc70d1897 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 125:2e9cc70d1897 471 */
AnnaBridge 125:2e9cc70d1897 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 125:2e9cc70d1897 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 125:2e9cc70d1897 474 __DCCIMVAC = (uint32_t)va;
AnnaBridge 125:2e9cc70d1897 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 125:2e9cc70d1897 476 }
AnnaBridge 125:2e9cc70d1897 477
AnnaBridge 125:2e9cc70d1897 478 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 125:2e9cc70d1897 479
AnnaBridge 125:2e9cc70d1897 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 125:2e9cc70d1897 481 */
AnnaBridge 125:2e9cc70d1897 482 #pragma push
AnnaBridge 125:2e9cc70d1897 483 #pragma arm
AnnaBridge 125:2e9cc70d1897 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
AnnaBridge 125:2e9cc70d1897 485 ARM
AnnaBridge 125:2e9cc70d1897 486
AnnaBridge 125:2e9cc70d1897 487 PUSH {R4-R11}
AnnaBridge 125:2e9cc70d1897 488
AnnaBridge 125:2e9cc70d1897 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
AnnaBridge 125:2e9cc70d1897 490 ANDS R3, R6, #0x07000000 // Extract coherency level
AnnaBridge 125:2e9cc70d1897 491 MOV R3, R3, LSR #23 // Total cache levels << 1
AnnaBridge 125:2e9cc70d1897 492 BEQ Finished // If 0, no need to clean
AnnaBridge 125:2e9cc70d1897 493
AnnaBridge 125:2e9cc70d1897 494 MOV R10, #0 // R10 holds current cache level << 1
AnnaBridge 125:2e9cc70d1897 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
AnnaBridge 125:2e9cc70d1897 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
AnnaBridge 125:2e9cc70d1897 497 AND R1, R1, #7 // Isolate those lower 3 bits
AnnaBridge 125:2e9cc70d1897 498 CMP R1, #2
AnnaBridge 125:2e9cc70d1897 499 BLT Skip // No cache or only instruction cache at this level
AnnaBridge 125:2e9cc70d1897 500
AnnaBridge 125:2e9cc70d1897 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
AnnaBridge 125:2e9cc70d1897 502 ISB // ISB to sync the change to the CacheSizeID reg
AnnaBridge 125:2e9cc70d1897 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
AnnaBridge 125:2e9cc70d1897 504 AND R2, R1, #7 // Extract the line length field
AnnaBridge 125:2e9cc70d1897 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 125:2e9cc70d1897 506 LDR R4, =0x3FF
AnnaBridge 125:2e9cc70d1897 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
AnnaBridge 125:2e9cc70d1897 508 CLZ R5, R4 // R5 is the bit position of the way size increment
AnnaBridge 125:2e9cc70d1897 509 LDR R7, =0x7FFF
AnnaBridge 125:2e9cc70d1897 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
AnnaBridge 125:2e9cc70d1897 511
AnnaBridge 125:2e9cc70d1897 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
AnnaBridge 125:2e9cc70d1897 513
AnnaBridge 125:2e9cc70d1897 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
AnnaBridge 125:2e9cc70d1897 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
AnnaBridge 125:2e9cc70d1897 516 CMP R0, #0
AnnaBridge 125:2e9cc70d1897 517 BNE Dccsw
AnnaBridge 125:2e9cc70d1897 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 519 B cont
AnnaBridge 125:2e9cc70d1897 520 Dccsw CMP R0, #1
AnnaBridge 125:2e9cc70d1897 521 BNE Dccisw
AnnaBridge 125:2e9cc70d1897 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
AnnaBridge 125:2e9cc70d1897 523 B cont
AnnaBridge 125:2e9cc70d1897 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 525 cont SUBS R9, R9, #1 // Decrement the Way number
AnnaBridge 125:2e9cc70d1897 526 BGE Loop3
AnnaBridge 125:2e9cc70d1897 527 SUBS R7, R7, #1 // Decrement the Set number
AnnaBridge 125:2e9cc70d1897 528 BGE Loop2
AnnaBridge 125:2e9cc70d1897 529 Skip ADD R10, R10, #2 // Increment the cache number
AnnaBridge 125:2e9cc70d1897 530 CMP R3, R10
AnnaBridge 125:2e9cc70d1897 531 BGT Loop1
AnnaBridge 125:2e9cc70d1897 532
AnnaBridge 125:2e9cc70d1897 533 Finished
AnnaBridge 125:2e9cc70d1897 534 DSB
AnnaBridge 125:2e9cc70d1897 535 POP {R4-R11}
AnnaBridge 125:2e9cc70d1897 536 BX lr
AnnaBridge 125:2e9cc70d1897 537
AnnaBridge 125:2e9cc70d1897 538 }
AnnaBridge 125:2e9cc70d1897 539 #pragma pop
AnnaBridge 125:2e9cc70d1897 540
AnnaBridge 125:2e9cc70d1897 541
AnnaBridge 125:2e9cc70d1897 542 /** \brief Invalidate the whole D$
AnnaBridge 125:2e9cc70d1897 543
AnnaBridge 125:2e9cc70d1897 544 DCISW. Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 545 */
AnnaBridge 125:2e9cc70d1897 546
AnnaBridge 125:2e9cc70d1897 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 125:2e9cc70d1897 548 __v7_all_cache(0);
AnnaBridge 125:2e9cc70d1897 549 }
AnnaBridge 125:2e9cc70d1897 550
AnnaBridge 125:2e9cc70d1897 551 /** \brief Clean the whole D$
AnnaBridge 125:2e9cc70d1897 552
AnnaBridge 125:2e9cc70d1897 553 DCCSW. Clean by Set/Way
AnnaBridge 125:2e9cc70d1897 554 */
AnnaBridge 125:2e9cc70d1897 555
AnnaBridge 125:2e9cc70d1897 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 125:2e9cc70d1897 557 __v7_all_cache(1);
AnnaBridge 125:2e9cc70d1897 558 }
AnnaBridge 125:2e9cc70d1897 559
AnnaBridge 125:2e9cc70d1897 560 /** \brief Clean and invalidate the whole D$
AnnaBridge 125:2e9cc70d1897 561
AnnaBridge 125:2e9cc70d1897 562 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 563 */
AnnaBridge 125:2e9cc70d1897 564
AnnaBridge 125:2e9cc70d1897 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 125:2e9cc70d1897 566 __v7_all_cache(2);
AnnaBridge 125:2e9cc70d1897 567 }
AnnaBridge 125:2e9cc70d1897 568
AnnaBridge 125:2e9cc70d1897 569 #include "core_ca_mmu.h"
AnnaBridge 125:2e9cc70d1897 570
AnnaBridge 125:2e9cc70d1897 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
AnnaBridge 125:2e9cc70d1897 572
AnnaBridge 125:2e9cc70d1897 573 #define __inline inline
AnnaBridge 125:2e9cc70d1897 574
AnnaBridge 125:2e9cc70d1897 575 inline static uint32_t __disable_irq_iar() {
AnnaBridge 125:2e9cc70d1897 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
AnnaBridge 125:2e9cc70d1897 577 __disable_irq();
AnnaBridge 125:2e9cc70d1897 578 return irq_dis;
AnnaBridge 125:2e9cc70d1897 579 }
AnnaBridge 125:2e9cc70d1897 580
AnnaBridge 125:2e9cc70d1897 581 #define MODE_USR 0x10
AnnaBridge 125:2e9cc70d1897 582 #define MODE_FIQ 0x11
AnnaBridge 125:2e9cc70d1897 583 #define MODE_IRQ 0x12
AnnaBridge 125:2e9cc70d1897 584 #define MODE_SVC 0x13
AnnaBridge 125:2e9cc70d1897 585 #define MODE_MON 0x16
AnnaBridge 125:2e9cc70d1897 586 #define MODE_ABT 0x17
AnnaBridge 125:2e9cc70d1897 587 #define MODE_HYP 0x1A
AnnaBridge 125:2e9cc70d1897 588 #define MODE_UND 0x1B
AnnaBridge 125:2e9cc70d1897 589 #define MODE_SYS 0x1F
AnnaBridge 125:2e9cc70d1897 590
AnnaBridge 125:2e9cc70d1897 591 /** \brief Set Process Stack Pointer
AnnaBridge 125:2e9cc70d1897 592
AnnaBridge 125:2e9cc70d1897 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 125:2e9cc70d1897 594
AnnaBridge 125:2e9cc70d1897 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 125:2e9cc70d1897 596 */
AnnaBridge 125:2e9cc70d1897 597 // from rt_CMSIS.c
AnnaBridge 125:2e9cc70d1897 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
AnnaBridge 125:2e9cc70d1897 599 __asm(
AnnaBridge 125:2e9cc70d1897 600 " ARM\n"
AnnaBridge 125:2e9cc70d1897 601 // " PRESERVE8\n"
AnnaBridge 125:2e9cc70d1897 602
AnnaBridge 125:2e9cc70d1897 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
AnnaBridge 125:2e9cc70d1897 604 " MRS R1, CPSR \n"
AnnaBridge 125:2e9cc70d1897 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
AnnaBridge 125:2e9cc70d1897 606 " MOV SP, R0 \n"
AnnaBridge 125:2e9cc70d1897 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
AnnaBridge 125:2e9cc70d1897 608 " ISB \n"
AnnaBridge 125:2e9cc70d1897 609 " BX LR \n");
AnnaBridge 125:2e9cc70d1897 610 }
AnnaBridge 125:2e9cc70d1897 611
AnnaBridge 125:2e9cc70d1897 612 /** \brief Set User Mode
AnnaBridge 125:2e9cc70d1897 613
AnnaBridge 125:2e9cc70d1897 614 This function changes the processor state to User Mode
AnnaBridge 125:2e9cc70d1897 615 */
AnnaBridge 125:2e9cc70d1897 616 // from rt_CMSIS.c
AnnaBridge 125:2e9cc70d1897 617 __arm static inline void __set_CPS_USR(void) {
AnnaBridge 125:2e9cc70d1897 618 __asm(
AnnaBridge 125:2e9cc70d1897 619 " ARM \n"
AnnaBridge 125:2e9cc70d1897 620
AnnaBridge 125:2e9cc70d1897 621 " CPS #0x10 \n" // MODE_USR
AnnaBridge 125:2e9cc70d1897 622 " BX LR\n");
AnnaBridge 125:2e9cc70d1897 623 }
AnnaBridge 125:2e9cc70d1897 624
AnnaBridge 125:2e9cc70d1897 625 /** \brief Set TTBR0
AnnaBridge 125:2e9cc70d1897 626
AnnaBridge 125:2e9cc70d1897 627 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 125:2e9cc70d1897 628
AnnaBridge 125:2e9cc70d1897 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 125:2e9cc70d1897 630 */
AnnaBridge 125:2e9cc70d1897 631 // from mmu_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 125:2e9cc70d1897 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
AnnaBridge 125:2e9cc70d1897 634 __ISB();
AnnaBridge 125:2e9cc70d1897 635 }
AnnaBridge 125:2e9cc70d1897 636
AnnaBridge 125:2e9cc70d1897 637 /** \brief Set DACR
AnnaBridge 125:2e9cc70d1897 638
AnnaBridge 125:2e9cc70d1897 639 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 125:2e9cc70d1897 640
AnnaBridge 125:2e9cc70d1897 641 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 125:2e9cc70d1897 642 */
AnnaBridge 125:2e9cc70d1897 643 // from mmu_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 125:2e9cc70d1897 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
AnnaBridge 125:2e9cc70d1897 646 __ISB();
AnnaBridge 125:2e9cc70d1897 647 }
AnnaBridge 125:2e9cc70d1897 648
AnnaBridge 125:2e9cc70d1897 649
AnnaBridge 125:2e9cc70d1897 650 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 125:2e9cc70d1897 651 /** \brief Set SCTLR
AnnaBridge 125:2e9cc70d1897 652
AnnaBridge 125:2e9cc70d1897 653 This function assigns the given value to the System Control Register.
AnnaBridge 125:2e9cc70d1897 654
AnnaBridge 125:2e9cc70d1897 655 \param [in] sctlr System Control Register value to set
AnnaBridge 125:2e9cc70d1897 656 */
AnnaBridge 125:2e9cc70d1897 657 // from __enable_mmu()
AnnaBridge 125:2e9cc70d1897 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
AnnaBridge 125:2e9cc70d1897 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
AnnaBridge 125:2e9cc70d1897 660 }
AnnaBridge 125:2e9cc70d1897 661
AnnaBridge 125:2e9cc70d1897 662 /** \brief Get SCTLR
AnnaBridge 125:2e9cc70d1897 663
AnnaBridge 125:2e9cc70d1897 664 This function returns the value of the System Control Register.
AnnaBridge 125:2e9cc70d1897 665
AnnaBridge 125:2e9cc70d1897 666 \return System Control Register value
AnnaBridge 125:2e9cc70d1897 667 */
AnnaBridge 125:2e9cc70d1897 668 // from __enable_mmu()
AnnaBridge 125:2e9cc70d1897 669 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 125:2e9cc70d1897 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
AnnaBridge 125:2e9cc70d1897 671 return __regSCTLR;
AnnaBridge 125:2e9cc70d1897 672 }
AnnaBridge 125:2e9cc70d1897 673
AnnaBridge 125:2e9cc70d1897 674 /** \brief Enable Caches
AnnaBridge 125:2e9cc70d1897 675
AnnaBridge 125:2e9cc70d1897 676 Enable Caches
AnnaBridge 125:2e9cc70d1897 677 */
AnnaBridge 125:2e9cc70d1897 678 // from system_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 679 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 125:2e9cc70d1897 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 125:2e9cc70d1897 681 }
AnnaBridge 125:2e9cc70d1897 682
AnnaBridge 125:2e9cc70d1897 683 /** \brief Enable BTAC
AnnaBridge 125:2e9cc70d1897 684
AnnaBridge 125:2e9cc70d1897 685 Enable BTAC
AnnaBridge 125:2e9cc70d1897 686 */
AnnaBridge 125:2e9cc70d1897 687 // from system_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 688 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 125:2e9cc70d1897 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 125:2e9cc70d1897 690 __ISB();
AnnaBridge 125:2e9cc70d1897 691 }
AnnaBridge 125:2e9cc70d1897 692
AnnaBridge 125:2e9cc70d1897 693 /** \brief Enable MMU
AnnaBridge 125:2e9cc70d1897 694
AnnaBridge 125:2e9cc70d1897 695 Enable MMU
AnnaBridge 125:2e9cc70d1897 696 */
AnnaBridge 125:2e9cc70d1897 697 // from system_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 698 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 125:2e9cc70d1897 699 // Set M bit 0 to enable the MMU
AnnaBridge 125:2e9cc70d1897 700 // Set AFE bit to enable simplified access permissions model
AnnaBridge 125:2e9cc70d1897 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 125:2e9cc70d1897 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 125:2e9cc70d1897 703 __ISB();
AnnaBridge 125:2e9cc70d1897 704 }
AnnaBridge 125:2e9cc70d1897 705
AnnaBridge 125:2e9cc70d1897 706 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 125:2e9cc70d1897 707 /** \brief Invalidate the whole tlb
AnnaBridge 125:2e9cc70d1897 708
AnnaBridge 125:2e9cc70d1897 709 TLBIALL. Invalidate the whole tlb
AnnaBridge 125:2e9cc70d1897 710 */
AnnaBridge 125:2e9cc70d1897 711 // from system_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 125:2e9cc70d1897 713 uint32_t val = 0;
AnnaBridge 125:2e9cc70d1897 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
AnnaBridge 125:2e9cc70d1897 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
AnnaBridge 125:2e9cc70d1897 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
AnnaBridge 125:2e9cc70d1897 717 __DSB();
AnnaBridge 125:2e9cc70d1897 718 __ISB();
AnnaBridge 125:2e9cc70d1897 719 }
AnnaBridge 125:2e9cc70d1897 720
AnnaBridge 125:2e9cc70d1897 721 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 125:2e9cc70d1897 722 /** \brief Invalidate entire branch predictor array
AnnaBridge 125:2e9cc70d1897 723
AnnaBridge 125:2e9cc70d1897 724 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 125:2e9cc70d1897 725 */
AnnaBridge 125:2e9cc70d1897 726 // from system_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 727 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 125:2e9cc70d1897 728 uint32_t val = 0;
AnnaBridge 125:2e9cc70d1897 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
AnnaBridge 125:2e9cc70d1897 730 __DSB(); //ensure completion of the invalidation
AnnaBridge 125:2e9cc70d1897 731 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 125:2e9cc70d1897 732 }
AnnaBridge 125:2e9cc70d1897 733
AnnaBridge 125:2e9cc70d1897 734
AnnaBridge 125:2e9cc70d1897 735 /******************************** L1 cache operations ******************************************************/
AnnaBridge 125:2e9cc70d1897 736
AnnaBridge 125:2e9cc70d1897 737 /** \brief Invalidate the whole I$
AnnaBridge 125:2e9cc70d1897 738
AnnaBridge 125:2e9cc70d1897 739 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 125:2e9cc70d1897 740 */
AnnaBridge 125:2e9cc70d1897 741 // from system_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 125:2e9cc70d1897 743 uint32_t val = 0;
AnnaBridge 125:2e9cc70d1897 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
AnnaBridge 125:2e9cc70d1897 745 __DSB(); //ensure completion of the invalidation
AnnaBridge 125:2e9cc70d1897 746 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 125:2e9cc70d1897 747 }
AnnaBridge 125:2e9cc70d1897 748
AnnaBridge 125:2e9cc70d1897 749 // from __v7_inv_dcache_all()
AnnaBridge 125:2e9cc70d1897 750 __arm static inline void __v7_all_cache(uint32_t op) {
AnnaBridge 125:2e9cc70d1897 751 __asm(
AnnaBridge 125:2e9cc70d1897 752 " ARM \n"
AnnaBridge 125:2e9cc70d1897 753
AnnaBridge 125:2e9cc70d1897 754 " PUSH {R4-R11} \n"
AnnaBridge 125:2e9cc70d1897 755
AnnaBridge 125:2e9cc70d1897 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
AnnaBridge 125:2e9cc70d1897 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
AnnaBridge 125:2e9cc70d1897 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
AnnaBridge 125:2e9cc70d1897 759 " BEQ Finished\n" // If 0, no need to clean
AnnaBridge 125:2e9cc70d1897 760
AnnaBridge 125:2e9cc70d1897 761 " MOV R10, #0\n" // R10 holds current cache level << 1
AnnaBridge 125:2e9cc70d1897 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
AnnaBridge 125:2e9cc70d1897 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
AnnaBridge 125:2e9cc70d1897 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
AnnaBridge 125:2e9cc70d1897 765 " CMP R1, #2 \n"
AnnaBridge 125:2e9cc70d1897 766 " BLT Skip \n" // No cache or only instruction cache at this level
AnnaBridge 125:2e9cc70d1897 767
AnnaBridge 125:2e9cc70d1897 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
AnnaBridge 125:2e9cc70d1897 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
AnnaBridge 125:2e9cc70d1897 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
AnnaBridge 125:2e9cc70d1897 771 " AND R2, R1, #7 \n" // Extract the line length field
AnnaBridge 125:2e9cc70d1897 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 125:2e9cc70d1897 773 " movw R4, #0x3FF \n"
AnnaBridge 125:2e9cc70d1897 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
AnnaBridge 125:2e9cc70d1897 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
AnnaBridge 125:2e9cc70d1897 776 " movw R7, #0x7FFF \n"
AnnaBridge 125:2e9cc70d1897 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
AnnaBridge 125:2e9cc70d1897 778
AnnaBridge 125:2e9cc70d1897 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
AnnaBridge 125:2e9cc70d1897 780
AnnaBridge 125:2e9cc70d1897 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
AnnaBridge 125:2e9cc70d1897 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
AnnaBridge 125:2e9cc70d1897 783 " CMP R0, #0 \n"
AnnaBridge 125:2e9cc70d1897 784 " BNE Dccsw \n"
AnnaBridge 125:2e9cc70d1897 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 786 " B cont \n"
AnnaBridge 125:2e9cc70d1897 787 "Dccsw: CMP R0, #1 \n"
AnnaBridge 125:2e9cc70d1897 788 " BNE Dccisw \n"
AnnaBridge 125:2e9cc70d1897 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
AnnaBridge 125:2e9cc70d1897 790 " B cont \n"
AnnaBridge 125:2e9cc70d1897 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
AnnaBridge 125:2e9cc70d1897 793 " BGE Loop3 \n"
AnnaBridge 125:2e9cc70d1897 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
AnnaBridge 125:2e9cc70d1897 795 " BGE Loop2 \n"
AnnaBridge 125:2e9cc70d1897 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
AnnaBridge 125:2e9cc70d1897 797 " CMP R3, R10 \n"
AnnaBridge 125:2e9cc70d1897 798 " BGT Loop1 \n"
AnnaBridge 125:2e9cc70d1897 799
AnnaBridge 125:2e9cc70d1897 800 "Finished: \n"
AnnaBridge 125:2e9cc70d1897 801 " DSB \n"
AnnaBridge 125:2e9cc70d1897 802 " POP {R4-R11} \n"
AnnaBridge 125:2e9cc70d1897 803 " BX lr \n" );
AnnaBridge 125:2e9cc70d1897 804 }
AnnaBridge 125:2e9cc70d1897 805
AnnaBridge 125:2e9cc70d1897 806 /** \brief Invalidate the whole D$
AnnaBridge 125:2e9cc70d1897 807
AnnaBridge 125:2e9cc70d1897 808 DCISW. Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 809 */
AnnaBridge 125:2e9cc70d1897 810 // from system_Renesas_RZ_A1.c
AnnaBridge 125:2e9cc70d1897 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 125:2e9cc70d1897 812 __v7_all_cache(0);
AnnaBridge 125:2e9cc70d1897 813 }
AnnaBridge 125:2e9cc70d1897 814 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 125:2e9cc70d1897 815
AnnaBridge 125:2e9cc70d1897 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 125:2e9cc70d1897 817 */
AnnaBridge 125:2e9cc70d1897 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 125:2e9cc70d1897 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
AnnaBridge 125:2e9cc70d1897 820 __DMB();
AnnaBridge 125:2e9cc70d1897 821 }
AnnaBridge 125:2e9cc70d1897 822
AnnaBridge 125:2e9cc70d1897 823 #include "core_ca_mmu.h"
AnnaBridge 125:2e9cc70d1897 824
AnnaBridge 125:2e9cc70d1897 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
AnnaBridge 125:2e9cc70d1897 826 /* GNU gcc specific functions */
AnnaBridge 125:2e9cc70d1897 827
AnnaBridge 125:2e9cc70d1897 828 #define MODE_USR 0x10
AnnaBridge 125:2e9cc70d1897 829 #define MODE_FIQ 0x11
AnnaBridge 125:2e9cc70d1897 830 #define MODE_IRQ 0x12
AnnaBridge 125:2e9cc70d1897 831 #define MODE_SVC 0x13
AnnaBridge 125:2e9cc70d1897 832 #define MODE_MON 0x16
AnnaBridge 125:2e9cc70d1897 833 #define MODE_ABT 0x17
AnnaBridge 125:2e9cc70d1897 834 #define MODE_HYP 0x1A
AnnaBridge 125:2e9cc70d1897 835 #define MODE_UND 0x1B
AnnaBridge 125:2e9cc70d1897 836 #define MODE_SYS 0x1F
AnnaBridge 125:2e9cc70d1897 837
AnnaBridge 125:2e9cc70d1897 838
AnnaBridge 125:2e9cc70d1897 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
AnnaBridge 125:2e9cc70d1897 840 {
AnnaBridge 125:2e9cc70d1897 841 __ASM volatile ("cpsie i");
AnnaBridge 125:2e9cc70d1897 842 }
AnnaBridge 125:2e9cc70d1897 843
AnnaBridge 125:2e9cc70d1897 844 /** \brief Disable IRQ Interrupts
AnnaBridge 125:2e9cc70d1897 845
AnnaBridge 125:2e9cc70d1897 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 125:2e9cc70d1897 847 Can only be executed in Privileged modes.
AnnaBridge 125:2e9cc70d1897 848 */
AnnaBridge 125:2e9cc70d1897 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
AnnaBridge 125:2e9cc70d1897 850 {
AnnaBridge 125:2e9cc70d1897 851 uint32_t result;
AnnaBridge 125:2e9cc70d1897 852
AnnaBridge 125:2e9cc70d1897 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
AnnaBridge 125:2e9cc70d1897 854 __ASM volatile ("cpsid i");
AnnaBridge 125:2e9cc70d1897 855 return(result & 0x80);
AnnaBridge 125:2e9cc70d1897 856 }
AnnaBridge 125:2e9cc70d1897 857
AnnaBridge 125:2e9cc70d1897 858
AnnaBridge 125:2e9cc70d1897 859 /** \brief Get APSR Register
AnnaBridge 125:2e9cc70d1897 860
AnnaBridge 125:2e9cc70d1897 861 This function returns the content of the APSR Register.
AnnaBridge 125:2e9cc70d1897 862
AnnaBridge 125:2e9cc70d1897 863 \return APSR Register value
AnnaBridge 125:2e9cc70d1897 864 */
AnnaBridge 125:2e9cc70d1897 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 125:2e9cc70d1897 866 {
AnnaBridge 125:2e9cc70d1897 867 #if 1
AnnaBridge 125:2e9cc70d1897 868 register uint32_t __regAPSR;
AnnaBridge 125:2e9cc70d1897 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
AnnaBridge 125:2e9cc70d1897 870 #else
AnnaBridge 125:2e9cc70d1897 871 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 125:2e9cc70d1897 872 #endif
AnnaBridge 125:2e9cc70d1897 873 return(__regAPSR);
AnnaBridge 125:2e9cc70d1897 874 }
AnnaBridge 125:2e9cc70d1897 875
AnnaBridge 125:2e9cc70d1897 876
AnnaBridge 125:2e9cc70d1897 877 /** \brief Get CPSR Register
AnnaBridge 125:2e9cc70d1897 878
AnnaBridge 125:2e9cc70d1897 879 This function returns the content of the CPSR Register.
AnnaBridge 125:2e9cc70d1897 880
AnnaBridge 125:2e9cc70d1897 881 \return CPSR Register value
AnnaBridge 125:2e9cc70d1897 882 */
AnnaBridge 125:2e9cc70d1897 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 125:2e9cc70d1897 884 {
AnnaBridge 125:2e9cc70d1897 885 #if 1
AnnaBridge 125:2e9cc70d1897 886 register uint32_t __regCPSR;
AnnaBridge 125:2e9cc70d1897 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
AnnaBridge 125:2e9cc70d1897 888 #else
AnnaBridge 125:2e9cc70d1897 889 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 125:2e9cc70d1897 890 #endif
AnnaBridge 125:2e9cc70d1897 891 return(__regCPSR);
AnnaBridge 125:2e9cc70d1897 892 }
AnnaBridge 125:2e9cc70d1897 893
AnnaBridge 125:2e9cc70d1897 894 #if 0
AnnaBridge 125:2e9cc70d1897 895 /** \brief Set Stack Pointer
AnnaBridge 125:2e9cc70d1897 896
AnnaBridge 125:2e9cc70d1897 897 This function assigns the given value to the current stack pointer.
AnnaBridge 125:2e9cc70d1897 898
AnnaBridge 125:2e9cc70d1897 899 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 125:2e9cc70d1897 900 */
AnnaBridge 125:2e9cc70d1897 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 125:2e9cc70d1897 902 {
AnnaBridge 125:2e9cc70d1897 903 register uint32_t __regSP __ASM("sp");
AnnaBridge 125:2e9cc70d1897 904 __regSP = topOfStack;
AnnaBridge 125:2e9cc70d1897 905 }
AnnaBridge 125:2e9cc70d1897 906 #endif
AnnaBridge 125:2e9cc70d1897 907
AnnaBridge 125:2e9cc70d1897 908 /** \brief Get link register
AnnaBridge 125:2e9cc70d1897 909
AnnaBridge 125:2e9cc70d1897 910 This function returns the value of the link register
AnnaBridge 125:2e9cc70d1897 911
AnnaBridge 125:2e9cc70d1897 912 \return Value of link register
AnnaBridge 125:2e9cc70d1897 913 */
AnnaBridge 125:2e9cc70d1897 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 125:2e9cc70d1897 915 {
AnnaBridge 125:2e9cc70d1897 916 register uint32_t __reglr __ASM("lr");
AnnaBridge 125:2e9cc70d1897 917 return(__reglr);
AnnaBridge 125:2e9cc70d1897 918 }
AnnaBridge 125:2e9cc70d1897 919
AnnaBridge 125:2e9cc70d1897 920 #if 0
AnnaBridge 125:2e9cc70d1897 921 /** \brief Set link register
AnnaBridge 125:2e9cc70d1897 922
AnnaBridge 125:2e9cc70d1897 923 This function sets the value of the link register
AnnaBridge 125:2e9cc70d1897 924
AnnaBridge 125:2e9cc70d1897 925 \param [in] lr LR value to set
AnnaBridge 125:2e9cc70d1897 926 */
AnnaBridge 125:2e9cc70d1897 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 125:2e9cc70d1897 928 {
AnnaBridge 125:2e9cc70d1897 929 register uint32_t __reglr __ASM("lr");
AnnaBridge 125:2e9cc70d1897 930 __reglr = lr;
AnnaBridge 125:2e9cc70d1897 931 }
AnnaBridge 125:2e9cc70d1897 932 #endif
AnnaBridge 125:2e9cc70d1897 933
AnnaBridge 125:2e9cc70d1897 934 /** \brief Set Process Stack Pointer
AnnaBridge 125:2e9cc70d1897 935
AnnaBridge 125:2e9cc70d1897 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 125:2e9cc70d1897 937
AnnaBridge 125:2e9cc70d1897 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 125:2e9cc70d1897 939 */
AnnaBridge 125:2e9cc70d1897 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 125:2e9cc70d1897 941 {
AnnaBridge 125:2e9cc70d1897 942 __asm__ volatile (
AnnaBridge 125:2e9cc70d1897 943 ".ARM;"
AnnaBridge 125:2e9cc70d1897 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
AnnaBridge 125:2e9cc70d1897 945
AnnaBridge 125:2e9cc70d1897 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
AnnaBridge 125:2e9cc70d1897 947 "MRS R1, CPSR;"
AnnaBridge 125:2e9cc70d1897 948 "CPS %0;" /* ;no effect in USR mode */
AnnaBridge 125:2e9cc70d1897 949 "MOV SP, R0;"
AnnaBridge 125:2e9cc70d1897 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
AnnaBridge 125:2e9cc70d1897 951 "ISB;"
AnnaBridge 125:2e9cc70d1897 952 //"BX LR;"
AnnaBridge 125:2e9cc70d1897 953 :
AnnaBridge 125:2e9cc70d1897 954 : "i"(MODE_SYS)
AnnaBridge 125:2e9cc70d1897 955 : "r0", "r1");
AnnaBridge 125:2e9cc70d1897 956 return;
AnnaBridge 125:2e9cc70d1897 957 }
AnnaBridge 125:2e9cc70d1897 958
AnnaBridge 125:2e9cc70d1897 959 /** \brief Set User Mode
AnnaBridge 125:2e9cc70d1897 960
AnnaBridge 125:2e9cc70d1897 961 This function changes the processor state to User Mode
AnnaBridge 125:2e9cc70d1897 962 */
AnnaBridge 125:2e9cc70d1897 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
AnnaBridge 125:2e9cc70d1897 964 {
AnnaBridge 125:2e9cc70d1897 965 __asm__ volatile (
AnnaBridge 125:2e9cc70d1897 966 ".ARM;"
AnnaBridge 125:2e9cc70d1897 967
AnnaBridge 125:2e9cc70d1897 968 "CPS %0;"
AnnaBridge 125:2e9cc70d1897 969 //"BX LR;"
AnnaBridge 125:2e9cc70d1897 970 :
AnnaBridge 125:2e9cc70d1897 971 : "i"(MODE_USR)
AnnaBridge 125:2e9cc70d1897 972 : );
AnnaBridge 125:2e9cc70d1897 973 return;
AnnaBridge 125:2e9cc70d1897 974 }
AnnaBridge 125:2e9cc70d1897 975
AnnaBridge 125:2e9cc70d1897 976
AnnaBridge 125:2e9cc70d1897 977 /** \brief Enable FIQ
AnnaBridge 125:2e9cc70d1897 978
AnnaBridge 125:2e9cc70d1897 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 125:2e9cc70d1897 980 Can only be executed in Privileged modes.
AnnaBridge 125:2e9cc70d1897 981 */
AnnaBridge 125:2e9cc70d1897 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
AnnaBridge 125:2e9cc70d1897 983
AnnaBridge 125:2e9cc70d1897 984
AnnaBridge 125:2e9cc70d1897 985 /** \brief Disable FIQ
AnnaBridge 125:2e9cc70d1897 986
AnnaBridge 125:2e9cc70d1897 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 125:2e9cc70d1897 988 Can only be executed in Privileged modes.
AnnaBridge 125:2e9cc70d1897 989 */
AnnaBridge 125:2e9cc70d1897 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
AnnaBridge 125:2e9cc70d1897 991
AnnaBridge 125:2e9cc70d1897 992
AnnaBridge 125:2e9cc70d1897 993 /** \brief Get FPSCR
AnnaBridge 125:2e9cc70d1897 994
AnnaBridge 125:2e9cc70d1897 995 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 125:2e9cc70d1897 996
AnnaBridge 125:2e9cc70d1897 997 \return Floating Point Status/Control register value
AnnaBridge 125:2e9cc70d1897 998 */
AnnaBridge 125:2e9cc70d1897 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 125:2e9cc70d1897 1000 {
AnnaBridge 125:2e9cc70d1897 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 125:2e9cc70d1897 1002 #if 1
AnnaBridge 125:2e9cc70d1897 1003 uint32_t result;
AnnaBridge 125:2e9cc70d1897 1004
AnnaBridge 125:2e9cc70d1897 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
AnnaBridge 125:2e9cc70d1897 1006 return (result);
AnnaBridge 125:2e9cc70d1897 1007 #else
AnnaBridge 125:2e9cc70d1897 1008 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 125:2e9cc70d1897 1009 return(__regfpscr);
AnnaBridge 125:2e9cc70d1897 1010 #endif
AnnaBridge 125:2e9cc70d1897 1011 #else
AnnaBridge 125:2e9cc70d1897 1012 return(0);
AnnaBridge 125:2e9cc70d1897 1013 #endif
AnnaBridge 125:2e9cc70d1897 1014 }
AnnaBridge 125:2e9cc70d1897 1015
AnnaBridge 125:2e9cc70d1897 1016
AnnaBridge 125:2e9cc70d1897 1017 /** \brief Set FPSCR
AnnaBridge 125:2e9cc70d1897 1018
AnnaBridge 125:2e9cc70d1897 1019 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 125:2e9cc70d1897 1020
AnnaBridge 125:2e9cc70d1897 1021 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 125:2e9cc70d1897 1022 */
AnnaBridge 125:2e9cc70d1897 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 125:2e9cc70d1897 1024 {
AnnaBridge 125:2e9cc70d1897 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 125:2e9cc70d1897 1026 #if 1
AnnaBridge 125:2e9cc70d1897 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
AnnaBridge 125:2e9cc70d1897 1028 #else
AnnaBridge 125:2e9cc70d1897 1029 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 125:2e9cc70d1897 1030 __regfpscr = (fpscr);
AnnaBridge 125:2e9cc70d1897 1031 #endif
AnnaBridge 125:2e9cc70d1897 1032 #endif
AnnaBridge 125:2e9cc70d1897 1033 }
AnnaBridge 125:2e9cc70d1897 1034
AnnaBridge 125:2e9cc70d1897 1035 /** \brief Get FPEXC
AnnaBridge 125:2e9cc70d1897 1036
AnnaBridge 125:2e9cc70d1897 1037 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 125:2e9cc70d1897 1038
AnnaBridge 125:2e9cc70d1897 1039 \return Floating Point Exception Control register value
AnnaBridge 125:2e9cc70d1897 1040 */
AnnaBridge 125:2e9cc70d1897 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 125:2e9cc70d1897 1042 {
AnnaBridge 125:2e9cc70d1897 1043 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 1044 #if 1
AnnaBridge 125:2e9cc70d1897 1045 uint32_t result;
AnnaBridge 125:2e9cc70d1897 1046
AnnaBridge 125:2e9cc70d1897 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
AnnaBridge 125:2e9cc70d1897 1048 return (result);
AnnaBridge 125:2e9cc70d1897 1049 #else
AnnaBridge 125:2e9cc70d1897 1050 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 125:2e9cc70d1897 1051 return(__regfpexc);
AnnaBridge 125:2e9cc70d1897 1052 #endif
AnnaBridge 125:2e9cc70d1897 1053 #else
AnnaBridge 125:2e9cc70d1897 1054 return(0);
AnnaBridge 125:2e9cc70d1897 1055 #endif
AnnaBridge 125:2e9cc70d1897 1056 }
AnnaBridge 125:2e9cc70d1897 1057
AnnaBridge 125:2e9cc70d1897 1058
AnnaBridge 125:2e9cc70d1897 1059 /** \brief Set FPEXC
AnnaBridge 125:2e9cc70d1897 1060
AnnaBridge 125:2e9cc70d1897 1061 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 125:2e9cc70d1897 1062
AnnaBridge 125:2e9cc70d1897 1063 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 125:2e9cc70d1897 1064 */
AnnaBridge 125:2e9cc70d1897 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 125:2e9cc70d1897 1066 {
AnnaBridge 125:2e9cc70d1897 1067 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 1068 #if 1
AnnaBridge 125:2e9cc70d1897 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
AnnaBridge 125:2e9cc70d1897 1070 #else
AnnaBridge 125:2e9cc70d1897 1071 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 125:2e9cc70d1897 1072 __regfpexc = (fpexc);
AnnaBridge 125:2e9cc70d1897 1073 #endif
AnnaBridge 125:2e9cc70d1897 1074 #endif
AnnaBridge 125:2e9cc70d1897 1075 }
AnnaBridge 125:2e9cc70d1897 1076
AnnaBridge 125:2e9cc70d1897 1077 /** \brief Get CPACR
AnnaBridge 125:2e9cc70d1897 1078
AnnaBridge 125:2e9cc70d1897 1079 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 125:2e9cc70d1897 1080
AnnaBridge 125:2e9cc70d1897 1081 \return Coprocessor Access Control register value
AnnaBridge 125:2e9cc70d1897 1082 */
AnnaBridge 125:2e9cc70d1897 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 125:2e9cc70d1897 1084 {
AnnaBridge 125:2e9cc70d1897 1085 #if 1
AnnaBridge 125:2e9cc70d1897 1086 register uint32_t __regCPACR;
AnnaBridge 125:2e9cc70d1897 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
AnnaBridge 125:2e9cc70d1897 1088 #else
AnnaBridge 125:2e9cc70d1897 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 125:2e9cc70d1897 1090 #endif
AnnaBridge 125:2e9cc70d1897 1091 return __regCPACR;
AnnaBridge 125:2e9cc70d1897 1092 }
AnnaBridge 125:2e9cc70d1897 1093
AnnaBridge 125:2e9cc70d1897 1094 /** \brief Set CPACR
AnnaBridge 125:2e9cc70d1897 1095
AnnaBridge 125:2e9cc70d1897 1096 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 125:2e9cc70d1897 1097
AnnaBridge 125:2e9cc70d1897 1098 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 125:2e9cc70d1897 1099 */
AnnaBridge 125:2e9cc70d1897 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 125:2e9cc70d1897 1101 {
AnnaBridge 125:2e9cc70d1897 1102 #if 1
AnnaBridge 125:2e9cc70d1897 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
AnnaBridge 125:2e9cc70d1897 1104 #else
AnnaBridge 125:2e9cc70d1897 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 125:2e9cc70d1897 1106 __regCPACR = cpacr;
AnnaBridge 125:2e9cc70d1897 1107 #endif
AnnaBridge 125:2e9cc70d1897 1108 __ISB();
AnnaBridge 125:2e9cc70d1897 1109 }
AnnaBridge 125:2e9cc70d1897 1110
AnnaBridge 125:2e9cc70d1897 1111 /** \brief Get CBAR
AnnaBridge 125:2e9cc70d1897 1112
AnnaBridge 125:2e9cc70d1897 1113 This function returns the value of the Configuration Base Address register.
AnnaBridge 125:2e9cc70d1897 1114
AnnaBridge 125:2e9cc70d1897 1115 \return Configuration Base Address register value
AnnaBridge 125:2e9cc70d1897 1116 */
AnnaBridge 125:2e9cc70d1897 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 125:2e9cc70d1897 1118 #if 1
AnnaBridge 125:2e9cc70d1897 1119 register uint32_t __regCBAR;
AnnaBridge 125:2e9cc70d1897 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
AnnaBridge 125:2e9cc70d1897 1121 #else
AnnaBridge 125:2e9cc70d1897 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 125:2e9cc70d1897 1123 #endif
AnnaBridge 125:2e9cc70d1897 1124 return(__regCBAR);
AnnaBridge 125:2e9cc70d1897 1125 }
AnnaBridge 125:2e9cc70d1897 1126
AnnaBridge 125:2e9cc70d1897 1127 /** \brief Get TTBR0
AnnaBridge 125:2e9cc70d1897 1128
AnnaBridge 125:2e9cc70d1897 1129 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 125:2e9cc70d1897 1130
AnnaBridge 125:2e9cc70d1897 1131 \return Translation Table Base Register 0 value
AnnaBridge 125:2e9cc70d1897 1132 */
AnnaBridge 125:2e9cc70d1897 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 125:2e9cc70d1897 1134 #if 1
AnnaBridge 125:2e9cc70d1897 1135 register uint32_t __regTTBR0;
AnnaBridge 125:2e9cc70d1897 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
AnnaBridge 125:2e9cc70d1897 1137 #else
AnnaBridge 125:2e9cc70d1897 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 125:2e9cc70d1897 1139 #endif
AnnaBridge 125:2e9cc70d1897 1140 return(__regTTBR0);
AnnaBridge 125:2e9cc70d1897 1141 }
AnnaBridge 125:2e9cc70d1897 1142
AnnaBridge 125:2e9cc70d1897 1143 /** \brief Set TTBR0
AnnaBridge 125:2e9cc70d1897 1144
AnnaBridge 125:2e9cc70d1897 1145 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 125:2e9cc70d1897 1146
AnnaBridge 125:2e9cc70d1897 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 125:2e9cc70d1897 1148 */
AnnaBridge 125:2e9cc70d1897 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 125:2e9cc70d1897 1150 #if 1
AnnaBridge 125:2e9cc70d1897 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
AnnaBridge 125:2e9cc70d1897 1152 #else
AnnaBridge 125:2e9cc70d1897 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 125:2e9cc70d1897 1154 __regTTBR0 = ttbr0;
AnnaBridge 125:2e9cc70d1897 1155 #endif
AnnaBridge 125:2e9cc70d1897 1156 __ISB();
AnnaBridge 125:2e9cc70d1897 1157 }
AnnaBridge 125:2e9cc70d1897 1158
AnnaBridge 125:2e9cc70d1897 1159 /** \brief Get DACR
AnnaBridge 125:2e9cc70d1897 1160
AnnaBridge 125:2e9cc70d1897 1161 This function returns the value of the Domain Access Control Register.
AnnaBridge 125:2e9cc70d1897 1162
AnnaBridge 125:2e9cc70d1897 1163 \return Domain Access Control Register value
AnnaBridge 125:2e9cc70d1897 1164 */
AnnaBridge 125:2e9cc70d1897 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 125:2e9cc70d1897 1166 #if 1
AnnaBridge 125:2e9cc70d1897 1167 register uint32_t __regDACR;
AnnaBridge 125:2e9cc70d1897 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
AnnaBridge 125:2e9cc70d1897 1169 #else
AnnaBridge 125:2e9cc70d1897 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 125:2e9cc70d1897 1171 #endif
AnnaBridge 125:2e9cc70d1897 1172 return(__regDACR);
AnnaBridge 125:2e9cc70d1897 1173 }
AnnaBridge 125:2e9cc70d1897 1174
AnnaBridge 125:2e9cc70d1897 1175 /** \brief Set DACR
AnnaBridge 125:2e9cc70d1897 1176
AnnaBridge 125:2e9cc70d1897 1177 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 125:2e9cc70d1897 1178
AnnaBridge 125:2e9cc70d1897 1179 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 125:2e9cc70d1897 1180 */
AnnaBridge 125:2e9cc70d1897 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 125:2e9cc70d1897 1182 #if 1
AnnaBridge 125:2e9cc70d1897 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
AnnaBridge 125:2e9cc70d1897 1184 #else
AnnaBridge 125:2e9cc70d1897 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 125:2e9cc70d1897 1186 __regDACR = dacr;
AnnaBridge 125:2e9cc70d1897 1187 #endif
AnnaBridge 125:2e9cc70d1897 1188 __ISB();
AnnaBridge 125:2e9cc70d1897 1189 }
AnnaBridge 125:2e9cc70d1897 1190
AnnaBridge 125:2e9cc70d1897 1191 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 125:2e9cc70d1897 1192
AnnaBridge 125:2e9cc70d1897 1193 /** \brief Set SCTLR
AnnaBridge 125:2e9cc70d1897 1194
AnnaBridge 125:2e9cc70d1897 1195 This function assigns the given value to the System Control Register.
AnnaBridge 125:2e9cc70d1897 1196
AnnaBridge 125:2e9cc70d1897 1197 \param [in] sctlr System Control Register value to set
AnnaBridge 125:2e9cc70d1897 1198 */
AnnaBridge 125:2e9cc70d1897 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 125:2e9cc70d1897 1200 {
AnnaBridge 125:2e9cc70d1897 1201 #if 1
AnnaBridge 125:2e9cc70d1897 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
AnnaBridge 125:2e9cc70d1897 1203 #else
AnnaBridge 125:2e9cc70d1897 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 125:2e9cc70d1897 1205 __regSCTLR = sctlr;
AnnaBridge 125:2e9cc70d1897 1206 #endif
AnnaBridge 125:2e9cc70d1897 1207 }
AnnaBridge 125:2e9cc70d1897 1208
AnnaBridge 125:2e9cc70d1897 1209 /** \brief Get SCTLR
AnnaBridge 125:2e9cc70d1897 1210
AnnaBridge 125:2e9cc70d1897 1211 This function returns the value of the System Control Register.
AnnaBridge 125:2e9cc70d1897 1212
AnnaBridge 125:2e9cc70d1897 1213 \return System Control Register value
AnnaBridge 125:2e9cc70d1897 1214 */
AnnaBridge 125:2e9cc70d1897 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 125:2e9cc70d1897 1216 #if 1
AnnaBridge 125:2e9cc70d1897 1217 register uint32_t __regSCTLR;
AnnaBridge 125:2e9cc70d1897 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
AnnaBridge 125:2e9cc70d1897 1219 #else
AnnaBridge 125:2e9cc70d1897 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 125:2e9cc70d1897 1221 #endif
AnnaBridge 125:2e9cc70d1897 1222 return(__regSCTLR);
AnnaBridge 125:2e9cc70d1897 1223 }
AnnaBridge 125:2e9cc70d1897 1224
AnnaBridge 125:2e9cc70d1897 1225 /** \brief Enable Caches
AnnaBridge 125:2e9cc70d1897 1226
AnnaBridge 125:2e9cc70d1897 1227 Enable Caches
AnnaBridge 125:2e9cc70d1897 1228 */
AnnaBridge 125:2e9cc70d1897 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 125:2e9cc70d1897 1230 // Set I bit 12 to enable I Cache
AnnaBridge 125:2e9cc70d1897 1231 // Set C bit 2 to enable D Cache
AnnaBridge 125:2e9cc70d1897 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 125:2e9cc70d1897 1233 }
AnnaBridge 125:2e9cc70d1897 1234
AnnaBridge 125:2e9cc70d1897 1235 /** \brief Disable Caches
AnnaBridge 125:2e9cc70d1897 1236
AnnaBridge 125:2e9cc70d1897 1237 Disable Caches
AnnaBridge 125:2e9cc70d1897 1238 */
AnnaBridge 125:2e9cc70d1897 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 125:2e9cc70d1897 1240 // Clear I bit 12 to disable I Cache
AnnaBridge 125:2e9cc70d1897 1241 // Clear C bit 2 to disable D Cache
AnnaBridge 125:2e9cc70d1897 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 125:2e9cc70d1897 1243 __ISB();
AnnaBridge 125:2e9cc70d1897 1244 }
AnnaBridge 125:2e9cc70d1897 1245
AnnaBridge 125:2e9cc70d1897 1246 /** \brief Enable BTAC
AnnaBridge 125:2e9cc70d1897 1247
AnnaBridge 125:2e9cc70d1897 1248 Enable BTAC
AnnaBridge 125:2e9cc70d1897 1249 */
AnnaBridge 125:2e9cc70d1897 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 125:2e9cc70d1897 1251 // Set Z bit 11 to enable branch prediction
AnnaBridge 125:2e9cc70d1897 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 125:2e9cc70d1897 1253 __ISB();
AnnaBridge 125:2e9cc70d1897 1254 }
AnnaBridge 125:2e9cc70d1897 1255
AnnaBridge 125:2e9cc70d1897 1256 /** \brief Disable BTAC
AnnaBridge 125:2e9cc70d1897 1257
AnnaBridge 125:2e9cc70d1897 1258 Disable BTAC
AnnaBridge 125:2e9cc70d1897 1259 */
AnnaBridge 125:2e9cc70d1897 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 125:2e9cc70d1897 1261 // Clear Z bit 11 to disable branch prediction
AnnaBridge 125:2e9cc70d1897 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 125:2e9cc70d1897 1263 }
AnnaBridge 125:2e9cc70d1897 1264
AnnaBridge 125:2e9cc70d1897 1265
AnnaBridge 125:2e9cc70d1897 1266 /** \brief Enable MMU
AnnaBridge 125:2e9cc70d1897 1267
AnnaBridge 125:2e9cc70d1897 1268 Enable MMU
AnnaBridge 125:2e9cc70d1897 1269 */
AnnaBridge 125:2e9cc70d1897 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 125:2e9cc70d1897 1271 // Set M bit 0 to enable the MMU
AnnaBridge 125:2e9cc70d1897 1272 // Set AFE bit to enable simplified access permissions model
AnnaBridge 125:2e9cc70d1897 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 125:2e9cc70d1897 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 125:2e9cc70d1897 1275 __ISB();
AnnaBridge 125:2e9cc70d1897 1276 }
AnnaBridge 125:2e9cc70d1897 1277
AnnaBridge 125:2e9cc70d1897 1278 /** \brief Disable MMU
AnnaBridge 125:2e9cc70d1897 1279
AnnaBridge 125:2e9cc70d1897 1280 Disable MMU
AnnaBridge 125:2e9cc70d1897 1281 */
AnnaBridge 125:2e9cc70d1897 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 125:2e9cc70d1897 1283 // Clear M bit 0 to disable the MMU
AnnaBridge 125:2e9cc70d1897 1284 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 125:2e9cc70d1897 1285 __ISB();
AnnaBridge 125:2e9cc70d1897 1286 }
AnnaBridge 125:2e9cc70d1897 1287
AnnaBridge 125:2e9cc70d1897 1288 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 125:2e9cc70d1897 1289 /** \brief Invalidate the whole tlb
AnnaBridge 125:2e9cc70d1897 1290
AnnaBridge 125:2e9cc70d1897 1291 TLBIALL. Invalidate the whole tlb
AnnaBridge 125:2e9cc70d1897 1292 */
AnnaBridge 125:2e9cc70d1897 1293
AnnaBridge 125:2e9cc70d1897 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 125:2e9cc70d1897 1295 #if 1
AnnaBridge 125:2e9cc70d1897 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
AnnaBridge 125:2e9cc70d1897 1297 #else
AnnaBridge 125:2e9cc70d1897 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 125:2e9cc70d1897 1299 __TLBIALL = 0;
AnnaBridge 125:2e9cc70d1897 1300 #endif
AnnaBridge 125:2e9cc70d1897 1301 __DSB();
AnnaBridge 125:2e9cc70d1897 1302 __ISB();
AnnaBridge 125:2e9cc70d1897 1303 }
AnnaBridge 125:2e9cc70d1897 1304
AnnaBridge 125:2e9cc70d1897 1305 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 125:2e9cc70d1897 1306 /** \brief Invalidate entire branch predictor array
AnnaBridge 125:2e9cc70d1897 1307
AnnaBridge 125:2e9cc70d1897 1308 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 125:2e9cc70d1897 1309 */
AnnaBridge 125:2e9cc70d1897 1310
AnnaBridge 125:2e9cc70d1897 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 125:2e9cc70d1897 1312 #if 1
AnnaBridge 125:2e9cc70d1897 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
AnnaBridge 125:2e9cc70d1897 1314 #else
AnnaBridge 125:2e9cc70d1897 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 125:2e9cc70d1897 1316 __BPIALL = 0;
AnnaBridge 125:2e9cc70d1897 1317 #endif
AnnaBridge 125:2e9cc70d1897 1318 __DSB(); //ensure completion of the invalidation
AnnaBridge 125:2e9cc70d1897 1319 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 125:2e9cc70d1897 1320 }
AnnaBridge 125:2e9cc70d1897 1321
AnnaBridge 125:2e9cc70d1897 1322
AnnaBridge 125:2e9cc70d1897 1323 /******************************** L1 cache operations ******************************************************/
AnnaBridge 125:2e9cc70d1897 1324
AnnaBridge 125:2e9cc70d1897 1325 /** \brief Invalidate the whole I$
AnnaBridge 125:2e9cc70d1897 1326
AnnaBridge 125:2e9cc70d1897 1327 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 125:2e9cc70d1897 1328 */
AnnaBridge 125:2e9cc70d1897 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 125:2e9cc70d1897 1330 #if 1
AnnaBridge 125:2e9cc70d1897 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
AnnaBridge 125:2e9cc70d1897 1332 #else
AnnaBridge 125:2e9cc70d1897 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 125:2e9cc70d1897 1334 __ICIALLU = 0;
AnnaBridge 125:2e9cc70d1897 1335 #endif
AnnaBridge 125:2e9cc70d1897 1336 __DSB(); //ensure completion of the invalidation
AnnaBridge 125:2e9cc70d1897 1337 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 125:2e9cc70d1897 1338 }
AnnaBridge 125:2e9cc70d1897 1339
AnnaBridge 125:2e9cc70d1897 1340 /** \brief Clean D$ by MVA
AnnaBridge 125:2e9cc70d1897 1341
AnnaBridge 125:2e9cc70d1897 1342 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 125:2e9cc70d1897 1343 */
AnnaBridge 125:2e9cc70d1897 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 125:2e9cc70d1897 1345 #if 1
AnnaBridge 125:2e9cc70d1897 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
AnnaBridge 125:2e9cc70d1897 1347 #else
AnnaBridge 125:2e9cc70d1897 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 125:2e9cc70d1897 1349 __DCCMVAC = (uint32_t)va;
AnnaBridge 125:2e9cc70d1897 1350 #endif
AnnaBridge 125:2e9cc70d1897 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 125:2e9cc70d1897 1352 }
AnnaBridge 125:2e9cc70d1897 1353
AnnaBridge 125:2e9cc70d1897 1354 /** \brief Invalidate D$ by MVA
AnnaBridge 125:2e9cc70d1897 1355
AnnaBridge 125:2e9cc70d1897 1356 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 125:2e9cc70d1897 1357 */
AnnaBridge 125:2e9cc70d1897 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 125:2e9cc70d1897 1359 #if 1
AnnaBridge 125:2e9cc70d1897 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
AnnaBridge 125:2e9cc70d1897 1361 #else
AnnaBridge 125:2e9cc70d1897 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 125:2e9cc70d1897 1363 __DCIMVAC = (uint32_t)va;
AnnaBridge 125:2e9cc70d1897 1364 #endif
AnnaBridge 125:2e9cc70d1897 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 125:2e9cc70d1897 1366 }
AnnaBridge 125:2e9cc70d1897 1367
AnnaBridge 125:2e9cc70d1897 1368 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 125:2e9cc70d1897 1369
AnnaBridge 125:2e9cc70d1897 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 125:2e9cc70d1897 1371 */
AnnaBridge 125:2e9cc70d1897 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 125:2e9cc70d1897 1373 #if 1
AnnaBridge 125:2e9cc70d1897 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
AnnaBridge 125:2e9cc70d1897 1375 #else
AnnaBridge 125:2e9cc70d1897 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 125:2e9cc70d1897 1377 __DCCIMVAC = (uint32_t)va;
AnnaBridge 125:2e9cc70d1897 1378 #endif
AnnaBridge 125:2e9cc70d1897 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 125:2e9cc70d1897 1380 }
AnnaBridge 125:2e9cc70d1897 1381
AnnaBridge 125:2e9cc70d1897 1382 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 125:2e9cc70d1897 1383
AnnaBridge 125:2e9cc70d1897 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 125:2e9cc70d1897 1385 */
AnnaBridge 125:2e9cc70d1897 1386 extern void __v7_all_cache(uint32_t op);
AnnaBridge 125:2e9cc70d1897 1387
AnnaBridge 125:2e9cc70d1897 1388
AnnaBridge 125:2e9cc70d1897 1389 /** \brief Invalidate the whole D$
AnnaBridge 125:2e9cc70d1897 1390
AnnaBridge 125:2e9cc70d1897 1391 DCISW. Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 1392 */
AnnaBridge 125:2e9cc70d1897 1393
AnnaBridge 125:2e9cc70d1897 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 125:2e9cc70d1897 1395 __v7_all_cache(0);
AnnaBridge 125:2e9cc70d1897 1396 }
AnnaBridge 125:2e9cc70d1897 1397
AnnaBridge 125:2e9cc70d1897 1398 /** \brief Clean the whole D$
AnnaBridge 125:2e9cc70d1897 1399
AnnaBridge 125:2e9cc70d1897 1400 DCCSW. Clean by Set/Way
AnnaBridge 125:2e9cc70d1897 1401 */
AnnaBridge 125:2e9cc70d1897 1402
AnnaBridge 125:2e9cc70d1897 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 125:2e9cc70d1897 1404 __v7_all_cache(1);
AnnaBridge 125:2e9cc70d1897 1405 }
AnnaBridge 125:2e9cc70d1897 1406
AnnaBridge 125:2e9cc70d1897 1407 /** \brief Clean and invalidate the whole D$
AnnaBridge 125:2e9cc70d1897 1408
AnnaBridge 125:2e9cc70d1897 1409 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 125:2e9cc70d1897 1410 */
AnnaBridge 125:2e9cc70d1897 1411
AnnaBridge 125:2e9cc70d1897 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 125:2e9cc70d1897 1413 __v7_all_cache(2);
AnnaBridge 125:2e9cc70d1897 1414 }
AnnaBridge 125:2e9cc70d1897 1415
AnnaBridge 125:2e9cc70d1897 1416 #include "core_ca_mmu.h"
AnnaBridge 125:2e9cc70d1897 1417
AnnaBridge 125:2e9cc70d1897 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
AnnaBridge 125:2e9cc70d1897 1419
AnnaBridge 125:2e9cc70d1897 1420 #error TASKING Compiler support not implemented for Cortex-A
AnnaBridge 125:2e9cc70d1897 1421
AnnaBridge 125:2e9cc70d1897 1422 #endif
AnnaBridge 125:2e9cc70d1897 1423
AnnaBridge 125:2e9cc70d1897 1424 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 125:2e9cc70d1897 1425
AnnaBridge 125:2e9cc70d1897 1426
AnnaBridge 125:2e9cc70d1897 1427 #endif /* __CORE_CAFUNC_H__ */