mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_SAMD21G18A/core_cm3.h@127:25aea2a3f4e3, 2016-09-30 (annotated)

Committer:
<>
Date:
Fri Sep 30 16:49:46 2016 +0100
Revision:
127:25aea2a3f4e3
Parent:
111:4336505e4b1c
Child:
128:9bcdf88f62b0
Release 127 of the mbed library



Ports for Upcoming Targets



2669: Added u-blox C029 target https://github.com/ARMmbed/mbed-os/pull/2669

2707: [EFM32] Add IAR support for remaining Silicon Labs targets https://github.com/ARMmbed/mbed-os/pull/2707

2819: MultiTech xDot platform support - 09.26.2016 https://github.com/ARMmbed/mbed-os/pull/2819

2827: include MultiTech xDot in mbed 5 releases https://github.com/ARMmbed/mbed-os/pull/2827



Fixes and Changes



2522: Add CThunk for CM7 https://github.com/ARMmbed/mbed-os/pull/2522

2518: Enable uvisor on Beetle https://github.com/ARMmbed/mbed-os/pull/2518

2571: STM32F7 - Add asynchronous serial https://github.com/ARMmbed/mbed-os/pull/2571

2616: STM32F3xx - Add Serial Flow Control pins + enable it https://github.com/ARMmbed/mbed-os/pull/2616

2619: NUCLEO_L152RE - Add Serial Flow Control https://github.com/ARMmbed/mbed-os/pull/2619

2620: NUCLEO_F429ZI - Add SERIAL_FC macro https://github.com/ARMmbed/mbed-os/pull/2620

2666: [EFM32] Microsecond ticker optimization https://github.com/ARMmbed/mbed-os/pull/2666

2681: STM32F0xx - Add support of ADC internal channels https://github.com/ARMmbed/mbed-os/pull/2681

2687: [NRF5] Add fs_data symbol in data secton for gcc https://github.com/ARMmbed/mbed-os/pull/2687

2696: Add device_has to all nrf51 devices https://github.com/ARMmbed/mbed-os/pull/2696

2703: TARGET_NRF5: Changed 'serial_baud' implementation to support special baud rates. https://github.com/ARMmbed/mbed-os/pull/2703

2704: DISCO_L476VG: add SPI nicknames https://github.com/ARMmbed/mbed-os/pull/2704

2723: KSDK serial_api.c: Fix assertion error for ParityEven https://github.com/ARMmbed/mbed-os/pull/2723

2463: [STM32L0] Add asynchronous serial https://github.com/ARMmbed/mbed-os/pull/2463

2572: Fix STM32F407VG target name and LPC11U6X linker errors https://github.com/ARMmbed/mbed-os/pull/2572

2698: DELTA_DFBM_NQ620 target https://github.com/ARMmbed/mbed-os/pull/2698

2542: Dev spi asynch stm32f4 https://github.com/ARMmbed/mbed-os/pull/2542

2650: STM32F3 - Add low power timer https://github.com/ARMmbed/mbed-os/pull/2650

2415: [STM32F0] Add asynchronous serial https://github.com/ARMmbed/mbed-os/pull/2415

2585: Added support for ADC only pins in LPC43xx https://github.com/ARMmbed/mbed-os/pull/2585

2622: [STM32F4] Add asynchronous I2C https://github.com/ARMmbed/mbed-os/pull/2622

2719: Updated ARM linker scripts for Kinetis platforms that use SDK 2.0 https://github.com/ARMmbed/mbed-os/pull/2719

2728: Added ethernet and enabled IPV4 feature for the EVK-ODIN-W2/C029 target https://github.com/ARMmbed/mbed-os/pull/2728

2747: [LPC11U68] Fix pin interrupt select offset https://github.com/ARMmbed/mbed-os/pull/2747

2751: STM32L0xx - Add Serial Flow Control https://github.com/ARMmbed/mbed-os/pull/2751

2753: [NUCLEO_F767ZI] Add CAN capability https://github.com/ARMmbed/mbed-os/pull/2753

2759: STM32F0 - Add low power timer https://github.com/ARMmbed/mbed-os/pull/2759

2763: STM32L1 - Add low power timer https://github.com/ARMmbed/mbed-os/pull/2763

2764: STM32L4 - Add low power timer https://github.com/ARMmbed/mbed-os/pull/2764

2771: STM32L4 - Update deepsleep implementation https://github.com/ARMmbed/mbed-os/pull/2771

2775: Update KSDK SDHC driver for K64F & K66F https://github.com/ARMmbed/mbed-os/pull/2775

2792: [NUCLEO_F303ZE] MBED-OS5 capability https://github.com/ARMmbed/mbed-os/pull/2792

2762: STM32L0 - Add low power timer https://github.com/ARMmbed/mbed-os/pull/2762

2761: STM32F7 - Add low power timer https://github.com/ARMmbed/mbed-os/pull/2761

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**************************************************************************//**
Kojto 111:4336505e4b1c 2 * @file core_cm3.h
Kojto 111:4336505e4b1c 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto 111:4336505e4b1c 4 * @version V4.10
Kojto 111:4336505e4b1c 5 * @date 18. March 2015
Kojto 111:4336505e4b1c 6 *
Kojto 111:4336505e4b1c 7 * @note
Kojto 111:4336505e4b1c 8 *
Kojto 111:4336505e4b1c 9 ******************************************************************************/
Kojto 111:4336505e4b1c 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 111:4336505e4b1c 11
Kojto 111:4336505e4b1c 12 All rights reserved.
Kojto 111:4336505e4b1c 13 Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 14 modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 15 - Redistributions of source code must retain the above copyright
Kojto 111:4336505e4b1c 16 notice, this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 - Redistributions in binary form must reproduce the above copyright
Kojto 111:4336505e4b1c 18 notice, this list of conditions and the following disclaimer in the
Kojto 111:4336505e4b1c 19 documentation and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 111:4336505e4b1c 21 to endorse or promote products derived from this software without
Kojto 111:4336505e4b1c 22 specific prior written permission.
Kojto 111:4336505e4b1c 23 *
Kojto 111:4336505e4b1c 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 111:4336505e4b1c 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 111:4336505e4b1c 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 111:4336505e4b1c 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 111:4336505e4b1c 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 111:4336505e4b1c 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 111:4336505e4b1c 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 111:4336505e4b1c 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 111:4336505e4b1c 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 111:4336505e4b1c 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 35 ---------------------------------------------------------------------------*/
Kojto 111:4336505e4b1c 36
Kojto 111:4336505e4b1c 37
Kojto 111:4336505e4b1c 38 #if defined ( __ICCARM__ )
Kojto 111:4336505e4b1c 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 111:4336505e4b1c 40 #endif
Kojto 111:4336505e4b1c 41
Kojto 111:4336505e4b1c 42 #ifndef __CORE_CM3_H_GENERIC
Kojto 111:4336505e4b1c 43 #define __CORE_CM3_H_GENERIC
Kojto 111:4336505e4b1c 44
Kojto 111:4336505e4b1c 45 #ifdef __cplusplus
Kojto 111:4336505e4b1c 46 extern "C" {
Kojto 111:4336505e4b1c 47 #endif
Kojto 111:4336505e4b1c 48
Kojto 111:4336505e4b1c 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 111:4336505e4b1c 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 111:4336505e4b1c 51
Kojto 111:4336505e4b1c 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 111:4336505e4b1c 53 Function definitions in header files are used to allow 'inlining'.
Kojto 111:4336505e4b1c 54
Kojto 111:4336505e4b1c 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 111:4336505e4b1c 56 Unions are used for effective representation of core registers.
Kojto 111:4336505e4b1c 57
Kojto 111:4336505e4b1c 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 111:4336505e4b1c 59 Function-like macros are used to allow more efficient code.
Kojto 111:4336505e4b1c 60 */
Kojto 111:4336505e4b1c 61
Kojto 111:4336505e4b1c 62
Kojto 111:4336505e4b1c 63 /*******************************************************************************
Kojto 111:4336505e4b1c 64 * CMSIS definitions
Kojto 111:4336505e4b1c 65 ******************************************************************************/
Kojto 111:4336505e4b1c 66 /** \ingroup Cortex_M3
Kojto 111:4336505e4b1c 67 @{
Kojto 111:4336505e4b1c 68 */
Kojto 111:4336505e4b1c 69
Kojto 111:4336505e4b1c 70 /* CMSIS CM3 definitions */
Kojto 111:4336505e4b1c 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 111:4336505e4b1c 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 111:4336505e4b1c 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
Kojto 111:4336505e4b1c 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 111:4336505e4b1c 75
Kojto 111:4336505e4b1c 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
Kojto 111:4336505e4b1c 77
Kojto 111:4336505e4b1c 78
Kojto 111:4336505e4b1c 79 #if defined ( __CC_ARM )
Kojto 111:4336505e4b1c 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 111:4336505e4b1c 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 111:4336505e4b1c 82 #define __STATIC_INLINE static __inline
Kojto 111:4336505e4b1c 83
Kojto 111:4336505e4b1c 84 #elif defined ( __GNUC__ )
Kojto 111:4336505e4b1c 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 111:4336505e4b1c 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 111:4336505e4b1c 87 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 88
Kojto 111:4336505e4b1c 89 #elif defined ( __ICCARM__ )
Kojto 111:4336505e4b1c 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 111:4336505e4b1c 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 111:4336505e4b1c 92 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 93
Kojto 111:4336505e4b1c 94 #elif defined ( __TMS470__ )
Kojto 111:4336505e4b1c 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 111:4336505e4b1c 96 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 97
Kojto 111:4336505e4b1c 98 #elif defined ( __TASKING__ )
Kojto 111:4336505e4b1c 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 111:4336505e4b1c 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 111:4336505e4b1c 101 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 102
Kojto 111:4336505e4b1c 103 #elif defined ( __CSMC__ )
Kojto 111:4336505e4b1c 104 #define __packed
Kojto 111:4336505e4b1c 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 111:4336505e4b1c 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 111:4336505e4b1c 107 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 108
Kojto 111:4336505e4b1c 109 #endif
Kojto 111:4336505e4b1c 110
Kojto 111:4336505e4b1c 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 111:4336505e4b1c 112 This core does not support an FPU at all
Kojto 111:4336505e4b1c 113 */
Kojto 111:4336505e4b1c 114 #define __FPU_USED 0
Kojto 111:4336505e4b1c 115
Kojto 111:4336505e4b1c 116 #if defined ( __CC_ARM )
Kojto 111:4336505e4b1c 117 #if defined __TARGET_FPU_VFP
Kojto 111:4336505e4b1c 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 119 #endif
Kojto 111:4336505e4b1c 120
Kojto 111:4336505e4b1c 121 #elif defined ( __GNUC__ )
Kojto 111:4336505e4b1c 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 111:4336505e4b1c 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 124 #endif
Kojto 111:4336505e4b1c 125
Kojto 111:4336505e4b1c 126 #elif defined ( __ICCARM__ )
Kojto 111:4336505e4b1c 127 #if defined __ARMVFP__
Kojto 111:4336505e4b1c 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 129 #endif
Kojto 111:4336505e4b1c 130
Kojto 111:4336505e4b1c 131 #elif defined ( __TMS470__ )
Kojto 111:4336505e4b1c 132 #if defined __TI__VFP_SUPPORT____
Kojto 111:4336505e4b1c 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 134 #endif
Kojto 111:4336505e4b1c 135
Kojto 111:4336505e4b1c 136 #elif defined ( __TASKING__ )
Kojto 111:4336505e4b1c 137 #if defined __FPU_VFP__
Kojto 111:4336505e4b1c 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 139 #endif
Kojto 111:4336505e4b1c 140
Kojto 111:4336505e4b1c 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 111:4336505e4b1c 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 111:4336505e4b1c 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 144 #endif
Kojto 111:4336505e4b1c 145 #endif
Kojto 111:4336505e4b1c 146
Kojto 111:4336505e4b1c 147 #include <stdint.h> /* standard types definitions */
Kojto 111:4336505e4b1c 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 111:4336505e4b1c 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 111:4336505e4b1c 150
Kojto 111:4336505e4b1c 151 #ifdef __cplusplus
Kojto 111:4336505e4b1c 152 }
Kojto 111:4336505e4b1c 153 #endif
Kojto 111:4336505e4b1c 154
Kojto 111:4336505e4b1c 155 #endif /* __CORE_CM3_H_GENERIC */
Kojto 111:4336505e4b1c 156
Kojto 111:4336505e4b1c 157 #ifndef __CMSIS_GENERIC
Kojto 111:4336505e4b1c 158
Kojto 111:4336505e4b1c 159 #ifndef __CORE_CM3_H_DEPENDANT
Kojto 111:4336505e4b1c 160 #define __CORE_CM3_H_DEPENDANT
Kojto 111:4336505e4b1c 161
Kojto 111:4336505e4b1c 162 #ifdef __cplusplus
Kojto 111:4336505e4b1c 163 extern "C" {
Kojto 111:4336505e4b1c 164 #endif
Kojto 111:4336505e4b1c 165
Kojto 111:4336505e4b1c 166 /* check device defines and use defaults */
Kojto 111:4336505e4b1c 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 111:4336505e4b1c 168 #ifndef __CM3_REV
Kojto 111:4336505e4b1c 169 #define __CM3_REV 0x0200
Kojto 111:4336505e4b1c 170 #warning "__CM3_REV not defined in device header file; using default!"
Kojto 111:4336505e4b1c 171 #endif
Kojto 111:4336505e4b1c 172
Kojto 111:4336505e4b1c 173 #ifndef __MPU_PRESENT
Kojto 111:4336505e4b1c 174 #define __MPU_PRESENT 0
Kojto 111:4336505e4b1c 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 111:4336505e4b1c 176 #endif
Kojto 111:4336505e4b1c 177
Kojto 111:4336505e4b1c 178 #ifndef __NVIC_PRIO_BITS
Kojto 111:4336505e4b1c 179 #define __NVIC_PRIO_BITS 4
Kojto 111:4336505e4b1c 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 111:4336505e4b1c 181 #endif
Kojto 111:4336505e4b1c 182
Kojto 111:4336505e4b1c 183 #ifndef __Vendor_SysTickConfig
Kojto 111:4336505e4b1c 184 #define __Vendor_SysTickConfig 0
Kojto 111:4336505e4b1c 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 111:4336505e4b1c 186 #endif
Kojto 111:4336505e4b1c 187 #endif
Kojto 111:4336505e4b1c 188
Kojto 111:4336505e4b1c 189 /* IO definitions (access restrictions to peripheral registers) */
Kojto 111:4336505e4b1c 190 /**
Kojto 111:4336505e4b1c 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 111:4336505e4b1c 192
Kojto 111:4336505e4b1c 193 <strong>IO Type Qualifiers</strong> are used
Kojto 111:4336505e4b1c 194 \li to specify the access to peripheral variables.
Kojto 111:4336505e4b1c 195 \li for automatic generation of peripheral register debug information.
Kojto 111:4336505e4b1c 196 */
Kojto 111:4336505e4b1c 197 #ifdef __cplusplus
Kojto 111:4336505e4b1c 198 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 111:4336505e4b1c 199 #else
Kojto 111:4336505e4b1c 200 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 111:4336505e4b1c 201 #endif
Kojto 111:4336505e4b1c 202 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 111:4336505e4b1c 203 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 111:4336505e4b1c 204
Kojto 111:4336505e4b1c 205 /*@} end of group Cortex_M3 */
Kojto 111:4336505e4b1c 206
Kojto 111:4336505e4b1c 207
Kojto 111:4336505e4b1c 208
Kojto 111:4336505e4b1c 209 /*******************************************************************************
Kojto 111:4336505e4b1c 210 * Register Abstraction
Kojto 111:4336505e4b1c 211 Core Register contain:
Kojto 111:4336505e4b1c 212 - Core Register
Kojto 111:4336505e4b1c 213 - Core NVIC Register
Kojto 111:4336505e4b1c 214 - Core SCB Register
Kojto 111:4336505e4b1c 215 - Core SysTick Register
Kojto 111:4336505e4b1c 216 - Core Debug Register
Kojto 111:4336505e4b1c 217 - Core MPU Register
Kojto 111:4336505e4b1c 218 ******************************************************************************/
Kojto 111:4336505e4b1c 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 111:4336505e4b1c 220 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 111:4336505e4b1c 221 */
Kojto 111:4336505e4b1c 222
Kojto 111:4336505e4b1c 223 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 224 \defgroup CMSIS_CORE Status and Control Registers
Kojto 111:4336505e4b1c 225 \brief Core Register type definitions.
Kojto 111:4336505e4b1c 226 @{
Kojto 111:4336505e4b1c 227 */
Kojto 111:4336505e4b1c 228
Kojto 111:4336505e4b1c 229 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 111:4336505e4b1c 230 */
Kojto 111:4336505e4b1c 231 typedef union
Kojto 111:4336505e4b1c 232 {
Kojto 111:4336505e4b1c 233 struct
Kojto 111:4336505e4b1c 234 {
Kojto 111:4336505e4b1c 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 111:4336505e4b1c 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 111:4336505e4b1c 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 111:4336505e4b1c 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 111:4336505e4b1c 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 111:4336505e4b1c 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 111:4336505e4b1c 241 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 242 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 243 } APSR_Type;
Kojto 111:4336505e4b1c 244
Kojto 111:4336505e4b1c 245 /* APSR Register Definitions */
Kojto 111:4336505e4b1c 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 111:4336505e4b1c 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 111:4336505e4b1c 248
Kojto 111:4336505e4b1c 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 111:4336505e4b1c 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 111:4336505e4b1c 251
Kojto 111:4336505e4b1c 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 111:4336505e4b1c 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 111:4336505e4b1c 254
Kojto 111:4336505e4b1c 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 111:4336505e4b1c 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 111:4336505e4b1c 257
Kojto 111:4336505e4b1c 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 111:4336505e4b1c 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 111:4336505e4b1c 260
Kojto 111:4336505e4b1c 261
Kojto 111:4336505e4b1c 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 111:4336505e4b1c 263 */
Kojto 111:4336505e4b1c 264 typedef union
Kojto 111:4336505e4b1c 265 {
Kojto 111:4336505e4b1c 266 struct
Kojto 111:4336505e4b1c 267 {
Kojto 111:4336505e4b1c 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 111:4336505e4b1c 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 111:4336505e4b1c 270 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 271 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 272 } IPSR_Type;
Kojto 111:4336505e4b1c 273
Kojto 111:4336505e4b1c 274 /* IPSR Register Definitions */
Kojto 111:4336505e4b1c 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 111:4336505e4b1c 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 111:4336505e4b1c 277
Kojto 111:4336505e4b1c 278
Kojto 111:4336505e4b1c 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 111:4336505e4b1c 280 */
Kojto 111:4336505e4b1c 281 typedef union
Kojto 111:4336505e4b1c 282 {
Kojto 111:4336505e4b1c 283 struct
Kojto 111:4336505e4b1c 284 {
Kojto 111:4336505e4b1c 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 111:4336505e4b1c 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 111:4336505e4b1c 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 111:4336505e4b1c 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 111:4336505e4b1c 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 111:4336505e4b1c 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 111:4336505e4b1c 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 111:4336505e4b1c 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 111:4336505e4b1c 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 111:4336505e4b1c 294 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 295 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 296 } xPSR_Type;
Kojto 111:4336505e4b1c 297
Kojto 111:4336505e4b1c 298 /* xPSR Register Definitions */
Kojto 111:4336505e4b1c 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 111:4336505e4b1c 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 111:4336505e4b1c 301
Kojto 111:4336505e4b1c 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 111:4336505e4b1c 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 111:4336505e4b1c 304
Kojto 111:4336505e4b1c 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 111:4336505e4b1c 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 111:4336505e4b1c 307
Kojto 111:4336505e4b1c 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 111:4336505e4b1c 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 111:4336505e4b1c 310
Kojto 111:4336505e4b1c 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 111:4336505e4b1c 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 111:4336505e4b1c 313
Kojto 111:4336505e4b1c 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 111:4336505e4b1c 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 111:4336505e4b1c 316
Kojto 111:4336505e4b1c 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 111:4336505e4b1c 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 111:4336505e4b1c 319
Kojto 111:4336505e4b1c 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 111:4336505e4b1c 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 111:4336505e4b1c 322
Kojto 111:4336505e4b1c 323
Kojto 111:4336505e4b1c 324 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 111:4336505e4b1c 325 */
Kojto 111:4336505e4b1c 326 typedef union
Kojto 111:4336505e4b1c 327 {
Kojto 111:4336505e4b1c 328 struct
Kojto 111:4336505e4b1c 329 {
Kojto 111:4336505e4b1c 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 111:4336505e4b1c 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 111:4336505e4b1c 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 111:4336505e4b1c 333 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 334 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 335 } CONTROL_Type;
Kojto 111:4336505e4b1c 336
Kojto 111:4336505e4b1c 337 /* CONTROL Register Definitions */
Kojto 111:4336505e4b1c 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 111:4336505e4b1c 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 111:4336505e4b1c 340
Kojto 111:4336505e4b1c 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 111:4336505e4b1c 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 111:4336505e4b1c 343
Kojto 111:4336505e4b1c 344 /*@} end of group CMSIS_CORE */
Kojto 111:4336505e4b1c 345
Kojto 111:4336505e4b1c 346
Kojto 111:4336505e4b1c 347 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 111:4336505e4b1c 349 \brief Type definitions for the NVIC Registers
Kojto 111:4336505e4b1c 350 @{
Kojto 111:4336505e4b1c 351 */
Kojto 111:4336505e4b1c 352
Kojto 111:4336505e4b1c 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 111:4336505e4b1c 354 */
Kojto 111:4336505e4b1c 355 typedef struct
Kojto 111:4336505e4b1c 356 {
Kojto 111:4336505e4b1c 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 111:4336505e4b1c 358 uint32_t RESERVED0[24];
Kojto 111:4336505e4b1c 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 111:4336505e4b1c 360 uint32_t RSERVED1[24];
Kojto 111:4336505e4b1c 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 111:4336505e4b1c 362 uint32_t RESERVED2[24];
Kojto 111:4336505e4b1c 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 111:4336505e4b1c 364 uint32_t RESERVED3[24];
Kojto 111:4336505e4b1c 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 111:4336505e4b1c 366 uint32_t RESERVED4[56];
Kojto 111:4336505e4b1c 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 111:4336505e4b1c 368 uint32_t RESERVED5[644];
Kojto 111:4336505e4b1c 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 111:4336505e4b1c 370 } NVIC_Type;
Kojto 111:4336505e4b1c 371
Kojto 111:4336505e4b1c 372 /* Software Triggered Interrupt Register Definitions */
Kojto 111:4336505e4b1c 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 111:4336505e4b1c 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 111:4336505e4b1c 375
Kojto 111:4336505e4b1c 376 /*@} end of group CMSIS_NVIC */
Kojto 111:4336505e4b1c 377
Kojto 111:4336505e4b1c 378
Kojto 111:4336505e4b1c 379 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 380 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 111:4336505e4b1c 381 \brief Type definitions for the System Control Block Registers
Kojto 111:4336505e4b1c 382 @{
Kojto 111:4336505e4b1c 383 */
Kojto 111:4336505e4b1c 384
Kojto 111:4336505e4b1c 385 /** \brief Structure type to access the System Control Block (SCB).
Kojto 111:4336505e4b1c 386 */
Kojto 111:4336505e4b1c 387 typedef struct
Kojto 111:4336505e4b1c 388 {
Kojto 111:4336505e4b1c 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 111:4336505e4b1c 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 111:4336505e4b1c 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 111:4336505e4b1c 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 111:4336505e4b1c 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 111:4336505e4b1c 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 111:4336505e4b1c 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 111:4336505e4b1c 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 111:4336505e4b1c 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 111:4336505e4b1c 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 111:4336505e4b1c 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 111:4336505e4b1c 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 111:4336505e4b1c 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 111:4336505e4b1c 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 111:4336505e4b1c 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 111:4336505e4b1c 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 111:4336505e4b1c 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 111:4336505e4b1c 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 111:4336505e4b1c 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 111:4336505e4b1c 408 uint32_t RESERVED0[5];
Kojto 111:4336505e4b1c 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 111:4336505e4b1c 410 } SCB_Type;
Kojto 111:4336505e4b1c 411
Kojto 111:4336505e4b1c 412 /* SCB CPUID Register Definitions */
Kojto 111:4336505e4b1c 413 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 111:4336505e4b1c 414 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 111:4336505e4b1c 415
Kojto 111:4336505e4b1c 416 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 111:4336505e4b1c 417 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 111:4336505e4b1c 418
Kojto 111:4336505e4b1c 419 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 111:4336505e4b1c 420 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 111:4336505e4b1c 421
Kojto 111:4336505e4b1c 422 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 111:4336505e4b1c 423 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 111:4336505e4b1c 424
Kojto 111:4336505e4b1c 425 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 111:4336505e4b1c 426 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 111:4336505e4b1c 427
Kojto 111:4336505e4b1c 428 /* SCB Interrupt Control State Register Definitions */
Kojto 111:4336505e4b1c 429 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 111:4336505e4b1c 430 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 111:4336505e4b1c 431
Kojto 111:4336505e4b1c 432 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 111:4336505e4b1c 433 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 111:4336505e4b1c 434
Kojto 111:4336505e4b1c 435 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 111:4336505e4b1c 436 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 111:4336505e4b1c 437
Kojto 111:4336505e4b1c 438 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 111:4336505e4b1c 439 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 111:4336505e4b1c 440
Kojto 111:4336505e4b1c 441 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 111:4336505e4b1c 442 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 111:4336505e4b1c 443
Kojto 111:4336505e4b1c 444 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 111:4336505e4b1c 445 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 111:4336505e4b1c 446
Kojto 111:4336505e4b1c 447 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 111:4336505e4b1c 448 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 111:4336505e4b1c 449
Kojto 111:4336505e4b1c 450 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 111:4336505e4b1c 451 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 111:4336505e4b1c 452
Kojto 111:4336505e4b1c 453 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 111:4336505e4b1c 454 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 111:4336505e4b1c 455
Kojto 111:4336505e4b1c 456 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 111:4336505e4b1c 457 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 111:4336505e4b1c 458
Kojto 111:4336505e4b1c 459 /* SCB Vector Table Offset Register Definitions */
Kojto 111:4336505e4b1c 460 #if (__CM3_REV < 0x0201) /* core r2p1 */
Kojto 111:4336505e4b1c 461 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Kojto 111:4336505e4b1c 462 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kojto 111:4336505e4b1c 463
Kojto 111:4336505e4b1c 464 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 111:4336505e4b1c 465 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 111:4336505e4b1c 466 #else
Kojto 111:4336505e4b1c 467 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 111:4336505e4b1c 468 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 111:4336505e4b1c 469 #endif
Kojto 111:4336505e4b1c 470
Kojto 111:4336505e4b1c 471 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 111:4336505e4b1c 472 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 111:4336505e4b1c 473 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 111:4336505e4b1c 474
Kojto 111:4336505e4b1c 475 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 111:4336505e4b1c 476 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 111:4336505e4b1c 477
Kojto 111:4336505e4b1c 478 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 111:4336505e4b1c 479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 111:4336505e4b1c 480
Kojto 111:4336505e4b1c 481 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 111:4336505e4b1c 482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 111:4336505e4b1c 483
Kojto 111:4336505e4b1c 484 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 111:4336505e4b1c 485 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 111:4336505e4b1c 486
Kojto 111:4336505e4b1c 487 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 111:4336505e4b1c 488 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 111:4336505e4b1c 489
Kojto 111:4336505e4b1c 490 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 111:4336505e4b1c 491 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 111:4336505e4b1c 492
Kojto 111:4336505e4b1c 493 /* SCB System Control Register Definitions */
Kojto 111:4336505e4b1c 494 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 111:4336505e4b1c 495 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 111:4336505e4b1c 496
Kojto 111:4336505e4b1c 497 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 111:4336505e4b1c 498 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 111:4336505e4b1c 499
Kojto 111:4336505e4b1c 500 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 111:4336505e4b1c 501 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 111:4336505e4b1c 502
Kojto 111:4336505e4b1c 503 /* SCB Configuration Control Register Definitions */
Kojto 111:4336505e4b1c 504 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 111:4336505e4b1c 505 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 111:4336505e4b1c 506
Kojto 111:4336505e4b1c 507 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 111:4336505e4b1c 508 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 111:4336505e4b1c 509
Kojto 111:4336505e4b1c 510 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 111:4336505e4b1c 511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 111:4336505e4b1c 512
Kojto 111:4336505e4b1c 513 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 111:4336505e4b1c 514 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 111:4336505e4b1c 515
Kojto 111:4336505e4b1c 516 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 111:4336505e4b1c 517 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 111:4336505e4b1c 518
Kojto 111:4336505e4b1c 519 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 111:4336505e4b1c 520 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 111:4336505e4b1c 521
Kojto 111:4336505e4b1c 522 /* SCB System Handler Control and State Register Definitions */
Kojto 111:4336505e4b1c 523 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 111:4336505e4b1c 524 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 111:4336505e4b1c 525
Kojto 111:4336505e4b1c 526 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 111:4336505e4b1c 527 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 111:4336505e4b1c 528
Kojto 111:4336505e4b1c 529 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 111:4336505e4b1c 530 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 111:4336505e4b1c 531
Kojto 111:4336505e4b1c 532 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 111:4336505e4b1c 533 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 111:4336505e4b1c 534
Kojto 111:4336505e4b1c 535 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 111:4336505e4b1c 536 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 111:4336505e4b1c 537
Kojto 111:4336505e4b1c 538 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 111:4336505e4b1c 539 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 111:4336505e4b1c 540
Kojto 111:4336505e4b1c 541 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 111:4336505e4b1c 542 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 111:4336505e4b1c 543
Kojto 111:4336505e4b1c 544 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 111:4336505e4b1c 545 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 111:4336505e4b1c 546
Kojto 111:4336505e4b1c 547 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 111:4336505e4b1c 548 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 111:4336505e4b1c 549
Kojto 111:4336505e4b1c 550 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 111:4336505e4b1c 551 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 111:4336505e4b1c 552
Kojto 111:4336505e4b1c 553 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 111:4336505e4b1c 554 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 111:4336505e4b1c 555
Kojto 111:4336505e4b1c 556 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 111:4336505e4b1c 557 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 111:4336505e4b1c 558
Kojto 111:4336505e4b1c 559 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 111:4336505e4b1c 560 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 111:4336505e4b1c 561
Kojto 111:4336505e4b1c 562 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 111:4336505e4b1c 563 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 111:4336505e4b1c 564
Kojto 111:4336505e4b1c 565 /* SCB Configurable Fault Status Registers Definitions */
Kojto 111:4336505e4b1c 566 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 111:4336505e4b1c 567 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 111:4336505e4b1c 568
Kojto 111:4336505e4b1c 569 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 111:4336505e4b1c 570 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 111:4336505e4b1c 571
Kojto 111:4336505e4b1c 572 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 111:4336505e4b1c 573 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 111:4336505e4b1c 574
Kojto 111:4336505e4b1c 575 /* SCB Hard Fault Status Registers Definitions */
Kojto 111:4336505e4b1c 576 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 111:4336505e4b1c 577 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 111:4336505e4b1c 578
Kojto 111:4336505e4b1c 579 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 111:4336505e4b1c 580 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 111:4336505e4b1c 581
Kojto 111:4336505e4b1c 582 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 111:4336505e4b1c 583 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 111:4336505e4b1c 584
Kojto 111:4336505e4b1c 585 /* SCB Debug Fault Status Register Definitions */
Kojto 111:4336505e4b1c 586 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 111:4336505e4b1c 587 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 111:4336505e4b1c 588
Kojto 111:4336505e4b1c 589 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 111:4336505e4b1c 590 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 111:4336505e4b1c 591
Kojto 111:4336505e4b1c 592 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 111:4336505e4b1c 593 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 111:4336505e4b1c 594
Kojto 111:4336505e4b1c 595 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 111:4336505e4b1c 596 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 111:4336505e4b1c 597
Kojto 111:4336505e4b1c 598 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 111:4336505e4b1c 599 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 111:4336505e4b1c 600
Kojto 111:4336505e4b1c 601 /*@} end of group CMSIS_SCB */
Kojto 111:4336505e4b1c 602
Kojto 111:4336505e4b1c 603
Kojto 111:4336505e4b1c 604 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 605 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 111:4336505e4b1c 606 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 111:4336505e4b1c 607 @{
Kojto 111:4336505e4b1c 608 */
Kojto 111:4336505e4b1c 609
Kojto 111:4336505e4b1c 610 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 111:4336505e4b1c 611 */
Kojto 111:4336505e4b1c 612 typedef struct
Kojto 111:4336505e4b1c 613 {
Kojto 111:4336505e4b1c 614 uint32_t RESERVED0[1];
Kojto 111:4336505e4b1c 615 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 111:4336505e4b1c 616 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Kojto 111:4336505e4b1c 617 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 111:4336505e4b1c 618 #else
Kojto 111:4336505e4b1c 619 uint32_t RESERVED1[1];
Kojto 111:4336505e4b1c 620 #endif
Kojto 111:4336505e4b1c 621 } SCnSCB_Type;
Kojto 111:4336505e4b1c 622
Kojto 111:4336505e4b1c 623 /* Interrupt Controller Type Register Definitions */
Kojto 111:4336505e4b1c 624 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 111:4336505e4b1c 625 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 111:4336505e4b1c 626
Kojto 111:4336505e4b1c 627 /* Auxiliary Control Register Definitions */
Kojto 111:4336505e4b1c 628
Kojto 111:4336505e4b1c 629 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Kojto 111:4336505e4b1c 630 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Kojto 111:4336505e4b1c 631
Kojto 111:4336505e4b1c 632 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
Kojto 111:4336505e4b1c 633 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
Kojto 111:4336505e4b1c 634
Kojto 111:4336505e4b1c 635 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 111:4336505e4b1c 636 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 111:4336505e4b1c 637
Kojto 111:4336505e4b1c 638 /*@} end of group CMSIS_SCnotSCB */
Kojto 111:4336505e4b1c 639
Kojto 111:4336505e4b1c 640
Kojto 111:4336505e4b1c 641 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 642 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 111:4336505e4b1c 643 \brief Type definitions for the System Timer Registers.
Kojto 111:4336505e4b1c 644 @{
Kojto 111:4336505e4b1c 645 */
Kojto 111:4336505e4b1c 646
Kojto 111:4336505e4b1c 647 /** \brief Structure type to access the System Timer (SysTick).
Kojto 111:4336505e4b1c 648 */
Kojto 111:4336505e4b1c 649 typedef struct
Kojto 111:4336505e4b1c 650 {
Kojto 111:4336505e4b1c 651 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 111:4336505e4b1c 652 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 111:4336505e4b1c 653 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 111:4336505e4b1c 654 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 111:4336505e4b1c 655 } SysTick_Type;
Kojto 111:4336505e4b1c 656
Kojto 111:4336505e4b1c 657 /* SysTick Control / Status Register Definitions */
Kojto 111:4336505e4b1c 658 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 111:4336505e4b1c 659 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 111:4336505e4b1c 660
Kojto 111:4336505e4b1c 661 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 111:4336505e4b1c 662 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 111:4336505e4b1c 663
Kojto 111:4336505e4b1c 664 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 111:4336505e4b1c 665 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 111:4336505e4b1c 666
Kojto 111:4336505e4b1c 667 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 111:4336505e4b1c 668 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 111:4336505e4b1c 669
Kojto 111:4336505e4b1c 670 /* SysTick Reload Register Definitions */
Kojto 111:4336505e4b1c 671 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 111:4336505e4b1c 672 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 111:4336505e4b1c 673
Kojto 111:4336505e4b1c 674 /* SysTick Current Register Definitions */
Kojto 111:4336505e4b1c 675 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 111:4336505e4b1c 676 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 111:4336505e4b1c 677
Kojto 111:4336505e4b1c 678 /* SysTick Calibration Register Definitions */
Kojto 111:4336505e4b1c 679 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 111:4336505e4b1c 680 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 111:4336505e4b1c 681
Kojto 111:4336505e4b1c 682 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 111:4336505e4b1c 683 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 111:4336505e4b1c 684
Kojto 111:4336505e4b1c 685 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 111:4336505e4b1c 686 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 111:4336505e4b1c 687
Kojto 111:4336505e4b1c 688 /*@} end of group CMSIS_SysTick */
Kojto 111:4336505e4b1c 689
Kojto 111:4336505e4b1c 690
Kojto 111:4336505e4b1c 691 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 692 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 111:4336505e4b1c 693 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 111:4336505e4b1c 694 @{
Kojto 111:4336505e4b1c 695 */
Kojto 111:4336505e4b1c 696
Kojto 111:4336505e4b1c 697 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 111:4336505e4b1c 698 */
Kojto 111:4336505e4b1c 699 typedef struct
Kojto 111:4336505e4b1c 700 {
Kojto 111:4336505e4b1c 701 __O union
Kojto 111:4336505e4b1c 702 {
Kojto 111:4336505e4b1c 703 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 111:4336505e4b1c 704 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 111:4336505e4b1c 705 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 111:4336505e4b1c 706 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 111:4336505e4b1c 707 uint32_t RESERVED0[864];
Kojto 111:4336505e4b1c 708 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 111:4336505e4b1c 709 uint32_t RESERVED1[15];
Kojto 111:4336505e4b1c 710 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 111:4336505e4b1c 711 uint32_t RESERVED2[15];
Kojto 111:4336505e4b1c 712 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 111:4336505e4b1c 713 uint32_t RESERVED3[29];
Kojto 111:4336505e4b1c 714 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 111:4336505e4b1c 715 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 111:4336505e4b1c 716 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 111:4336505e4b1c 717 uint32_t RESERVED4[43];
Kojto 111:4336505e4b1c 718 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 111:4336505e4b1c 719 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 111:4336505e4b1c 720 uint32_t RESERVED5[6];
Kojto 111:4336505e4b1c 721 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 111:4336505e4b1c 722 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 111:4336505e4b1c 723 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 111:4336505e4b1c 724 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 111:4336505e4b1c 725 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 111:4336505e4b1c 726 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 111:4336505e4b1c 727 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 111:4336505e4b1c 728 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 111:4336505e4b1c 729 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 111:4336505e4b1c 730 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 111:4336505e4b1c 731 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 111:4336505e4b1c 732 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 111:4336505e4b1c 733 } ITM_Type;
Kojto 111:4336505e4b1c 734
Kojto 111:4336505e4b1c 735 /* ITM Trace Privilege Register Definitions */
Kojto 111:4336505e4b1c 736 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 111:4336505e4b1c 737 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 111:4336505e4b1c 738
Kojto 111:4336505e4b1c 739 /* ITM Trace Control Register Definitions */
Kojto 111:4336505e4b1c 740 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 111:4336505e4b1c 741 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 111:4336505e4b1c 742
Kojto 111:4336505e4b1c 743 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 111:4336505e4b1c 744 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 111:4336505e4b1c 745
Kojto 111:4336505e4b1c 746 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 111:4336505e4b1c 747 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 111:4336505e4b1c 748
Kojto 111:4336505e4b1c 749 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 111:4336505e4b1c 750 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 111:4336505e4b1c 751
Kojto 111:4336505e4b1c 752 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 111:4336505e4b1c 753 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 111:4336505e4b1c 754
Kojto 111:4336505e4b1c 755 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 111:4336505e4b1c 756 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 111:4336505e4b1c 757
Kojto 111:4336505e4b1c 758 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 111:4336505e4b1c 759 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 111:4336505e4b1c 760
Kojto 111:4336505e4b1c 761 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 111:4336505e4b1c 762 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 111:4336505e4b1c 763
Kojto 111:4336505e4b1c 764 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 111:4336505e4b1c 765 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 111:4336505e4b1c 766
Kojto 111:4336505e4b1c 767 /* ITM Integration Write Register Definitions */
Kojto 111:4336505e4b1c 768 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 111:4336505e4b1c 769 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 111:4336505e4b1c 770
Kojto 111:4336505e4b1c 771 /* ITM Integration Read Register Definitions */
Kojto 111:4336505e4b1c 772 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 111:4336505e4b1c 773 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 111:4336505e4b1c 774
Kojto 111:4336505e4b1c 775 /* ITM Integration Mode Control Register Definitions */
Kojto 111:4336505e4b1c 776 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 111:4336505e4b1c 777 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 111:4336505e4b1c 778
Kojto 111:4336505e4b1c 779 /* ITM Lock Status Register Definitions */
Kojto 111:4336505e4b1c 780 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 111:4336505e4b1c 781 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 111:4336505e4b1c 782
Kojto 111:4336505e4b1c 783 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 111:4336505e4b1c 784 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 111:4336505e4b1c 785
Kojto 111:4336505e4b1c 786 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 111:4336505e4b1c 787 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 111:4336505e4b1c 788
Kojto 111:4336505e4b1c 789 /*@}*/ /* end of group CMSIS_ITM */
Kojto 111:4336505e4b1c 790
Kojto 111:4336505e4b1c 791
Kojto 111:4336505e4b1c 792 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 793 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 111:4336505e4b1c 794 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 111:4336505e4b1c 795 @{
Kojto 111:4336505e4b1c 796 */
Kojto 111:4336505e4b1c 797
Kojto 111:4336505e4b1c 798 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 111:4336505e4b1c 799 */
Kojto 111:4336505e4b1c 800 typedef struct
Kojto 111:4336505e4b1c 801 {
Kojto 111:4336505e4b1c 802 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 111:4336505e4b1c 803 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 111:4336505e4b1c 804 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 111:4336505e4b1c 805 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 111:4336505e4b1c 806 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 111:4336505e4b1c 807 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 111:4336505e4b1c 808 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 111:4336505e4b1c 809 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 111:4336505e4b1c 810 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 111:4336505e4b1c 811 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 111:4336505e4b1c 812 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 111:4336505e4b1c 813 uint32_t RESERVED0[1];
Kojto 111:4336505e4b1c 814 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 111:4336505e4b1c 815 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 111:4336505e4b1c 816 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 111:4336505e4b1c 817 uint32_t RESERVED1[1];
Kojto 111:4336505e4b1c 818 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 111:4336505e4b1c 819 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 111:4336505e4b1c 820 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 111:4336505e4b1c 821 uint32_t RESERVED2[1];
Kojto 111:4336505e4b1c 822 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 111:4336505e4b1c 823 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 111:4336505e4b1c 824 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 111:4336505e4b1c 825 } DWT_Type;
Kojto 111:4336505e4b1c 826
Kojto 111:4336505e4b1c 827 /* DWT Control Register Definitions */
Kojto 111:4336505e4b1c 828 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 111:4336505e4b1c 829 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 111:4336505e4b1c 830
Kojto 111:4336505e4b1c 831 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 111:4336505e4b1c 832 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 111:4336505e4b1c 833
Kojto 111:4336505e4b1c 834 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 111:4336505e4b1c 835 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 111:4336505e4b1c 836
Kojto 111:4336505e4b1c 837 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 111:4336505e4b1c 838 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 111:4336505e4b1c 839
Kojto 111:4336505e4b1c 840 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 111:4336505e4b1c 841 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 111:4336505e4b1c 842
Kojto 111:4336505e4b1c 843 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 111:4336505e4b1c 844 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 111:4336505e4b1c 845
Kojto 111:4336505e4b1c 846 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 111:4336505e4b1c 847 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 111:4336505e4b1c 848
Kojto 111:4336505e4b1c 849 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 111:4336505e4b1c 850 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 111:4336505e4b1c 851
Kojto 111:4336505e4b1c 852 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 111:4336505e4b1c 853 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 111:4336505e4b1c 854
Kojto 111:4336505e4b1c 855 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 111:4336505e4b1c 856 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 111:4336505e4b1c 857
Kojto 111:4336505e4b1c 858 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 111:4336505e4b1c 859 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 111:4336505e4b1c 860
Kojto 111:4336505e4b1c 861 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 111:4336505e4b1c 862 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 111:4336505e4b1c 863
Kojto 111:4336505e4b1c 864 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 111:4336505e4b1c 865 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 111:4336505e4b1c 866
Kojto 111:4336505e4b1c 867 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 111:4336505e4b1c 868 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 111:4336505e4b1c 869
Kojto 111:4336505e4b1c 870 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 111:4336505e4b1c 871 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 111:4336505e4b1c 872
Kojto 111:4336505e4b1c 873 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 111:4336505e4b1c 874 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 111:4336505e4b1c 875
Kojto 111:4336505e4b1c 876 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 111:4336505e4b1c 877 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 111:4336505e4b1c 878
Kojto 111:4336505e4b1c 879 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 111:4336505e4b1c 880 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 111:4336505e4b1c 881
Kojto 111:4336505e4b1c 882 /* DWT CPI Count Register Definitions */
Kojto 111:4336505e4b1c 883 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 111:4336505e4b1c 884 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 111:4336505e4b1c 885
Kojto 111:4336505e4b1c 886 /* DWT Exception Overhead Count Register Definitions */
Kojto 111:4336505e4b1c 887 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 111:4336505e4b1c 888 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 111:4336505e4b1c 889
Kojto 111:4336505e4b1c 890 /* DWT Sleep Count Register Definitions */
Kojto 111:4336505e4b1c 891 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 111:4336505e4b1c 892 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 111:4336505e4b1c 893
Kojto 111:4336505e4b1c 894 /* DWT LSU Count Register Definitions */
Kojto 111:4336505e4b1c 895 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 111:4336505e4b1c 896 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 111:4336505e4b1c 897
Kojto 111:4336505e4b1c 898 /* DWT Folded-instruction Count Register Definitions */
Kojto 111:4336505e4b1c 899 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 111:4336505e4b1c 900 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 111:4336505e4b1c 901
Kojto 111:4336505e4b1c 902 /* DWT Comparator Mask Register Definitions */
Kojto 111:4336505e4b1c 903 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 111:4336505e4b1c 904 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 111:4336505e4b1c 905
Kojto 111:4336505e4b1c 906 /* DWT Comparator Function Register Definitions */
Kojto 111:4336505e4b1c 907 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 111:4336505e4b1c 908 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 111:4336505e4b1c 909
Kojto 111:4336505e4b1c 910 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 111:4336505e4b1c 911 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 111:4336505e4b1c 912
Kojto 111:4336505e4b1c 913 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 111:4336505e4b1c 914 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 111:4336505e4b1c 915
Kojto 111:4336505e4b1c 916 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 111:4336505e4b1c 917 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 111:4336505e4b1c 918
Kojto 111:4336505e4b1c 919 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 111:4336505e4b1c 920 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 111:4336505e4b1c 921
Kojto 111:4336505e4b1c 922 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 111:4336505e4b1c 923 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 111:4336505e4b1c 924
Kojto 111:4336505e4b1c 925 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 111:4336505e4b1c 926 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 111:4336505e4b1c 927
Kojto 111:4336505e4b1c 928 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 111:4336505e4b1c 929 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 111:4336505e4b1c 930
Kojto 111:4336505e4b1c 931 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 111:4336505e4b1c 932 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 111:4336505e4b1c 933
Kojto 111:4336505e4b1c 934 /*@}*/ /* end of group CMSIS_DWT */
Kojto 111:4336505e4b1c 935
Kojto 111:4336505e4b1c 936
Kojto 111:4336505e4b1c 937 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 938 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 111:4336505e4b1c 939 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 111:4336505e4b1c 940 @{
Kojto 111:4336505e4b1c 941 */
Kojto 111:4336505e4b1c 942
Kojto 111:4336505e4b1c 943 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 111:4336505e4b1c 944 */
Kojto 111:4336505e4b1c 945 typedef struct
Kojto 111:4336505e4b1c 946 {
Kojto 111:4336505e4b1c 947 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 111:4336505e4b1c 948 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 111:4336505e4b1c 949 uint32_t RESERVED0[2];
Kojto 111:4336505e4b1c 950 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 111:4336505e4b1c 951 uint32_t RESERVED1[55];
Kojto 111:4336505e4b1c 952 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 111:4336505e4b1c 953 uint32_t RESERVED2[131];
Kojto 111:4336505e4b1c 954 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 111:4336505e4b1c 955 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 111:4336505e4b1c 956 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 111:4336505e4b1c 957 uint32_t RESERVED3[759];
Kojto 111:4336505e4b1c 958 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 111:4336505e4b1c 959 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 111:4336505e4b1c 960 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 111:4336505e4b1c 961 uint32_t RESERVED4[1];
Kojto 111:4336505e4b1c 962 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 111:4336505e4b1c 963 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 111:4336505e4b1c 964 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 111:4336505e4b1c 965 uint32_t RESERVED5[39];
Kojto 111:4336505e4b1c 966 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 111:4336505e4b1c 967 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 111:4336505e4b1c 968 uint32_t RESERVED7[8];
Kojto 111:4336505e4b1c 969 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 111:4336505e4b1c 970 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 111:4336505e4b1c 971 } TPI_Type;
Kojto 111:4336505e4b1c 972
Kojto 111:4336505e4b1c 973 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 111:4336505e4b1c 974 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 111:4336505e4b1c 975 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 111:4336505e4b1c 976
Kojto 111:4336505e4b1c 977 /* TPI Selected Pin Protocol Register Definitions */
Kojto 111:4336505e4b1c 978 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 111:4336505e4b1c 979 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 111:4336505e4b1c 980
Kojto 111:4336505e4b1c 981 /* TPI Formatter and Flush Status Register Definitions */
Kojto 111:4336505e4b1c 982 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 111:4336505e4b1c 983 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 111:4336505e4b1c 984
Kojto 111:4336505e4b1c 985 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 111:4336505e4b1c 986 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 111:4336505e4b1c 987
Kojto 111:4336505e4b1c 988 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 111:4336505e4b1c 989 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 111:4336505e4b1c 990
Kojto 111:4336505e4b1c 991 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 111:4336505e4b1c 992 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 111:4336505e4b1c 993
Kojto 111:4336505e4b1c 994 /* TPI Formatter and Flush Control Register Definitions */
Kojto 111:4336505e4b1c 995 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 111:4336505e4b1c 996 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 111:4336505e4b1c 997
Kojto 111:4336505e4b1c 998 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 111:4336505e4b1c 999 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 111:4336505e4b1c 1000
Kojto 111:4336505e4b1c 1001 /* TPI TRIGGER Register Definitions */
Kojto 111:4336505e4b1c 1002 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 111:4336505e4b1c 1003 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 111:4336505e4b1c 1004
Kojto 111:4336505e4b1c 1005 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 111:4336505e4b1c 1006 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 111:4336505e4b1c 1007 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 111:4336505e4b1c 1008
Kojto 111:4336505e4b1c 1009 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 111:4336505e4b1c 1010 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 111:4336505e4b1c 1011
Kojto 111:4336505e4b1c 1012 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 111:4336505e4b1c 1013 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 111:4336505e4b1c 1014
Kojto 111:4336505e4b1c 1015 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 111:4336505e4b1c 1016 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 111:4336505e4b1c 1017
Kojto 111:4336505e4b1c 1018 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 111:4336505e4b1c 1019 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 111:4336505e4b1c 1020
Kojto 111:4336505e4b1c 1021 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 111:4336505e4b1c 1022 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 111:4336505e4b1c 1023
Kojto 111:4336505e4b1c 1024 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 111:4336505e4b1c 1025 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 111:4336505e4b1c 1026
Kojto 111:4336505e4b1c 1027 /* TPI ITATBCTR2 Register Definitions */
Kojto 111:4336505e4b1c 1028 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 111:4336505e4b1c 1029 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 111:4336505e4b1c 1030
Kojto 111:4336505e4b1c 1031 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 111:4336505e4b1c 1032 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 111:4336505e4b1c 1033 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 111:4336505e4b1c 1034
Kojto 111:4336505e4b1c 1035 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 111:4336505e4b1c 1036 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 111:4336505e4b1c 1037
Kojto 111:4336505e4b1c 1038 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 111:4336505e4b1c 1039 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 111:4336505e4b1c 1040
Kojto 111:4336505e4b1c 1041 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 111:4336505e4b1c 1042 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 111:4336505e4b1c 1043
Kojto 111:4336505e4b1c 1044 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 111:4336505e4b1c 1045 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 111:4336505e4b1c 1046
Kojto 111:4336505e4b1c 1047 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 111:4336505e4b1c 1048 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 111:4336505e4b1c 1049
Kojto 111:4336505e4b1c 1050 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 111:4336505e4b1c 1051 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 111:4336505e4b1c 1052
Kojto 111:4336505e4b1c 1053 /* TPI ITATBCTR0 Register Definitions */
Kojto 111:4336505e4b1c 1054 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 111:4336505e4b1c 1055 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 111:4336505e4b1c 1056
Kojto 111:4336505e4b1c 1057 /* TPI Integration Mode Control Register Definitions */
Kojto 111:4336505e4b1c 1058 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 111:4336505e4b1c 1059 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 111:4336505e4b1c 1060
Kojto 111:4336505e4b1c 1061 /* TPI DEVID Register Definitions */
Kojto 111:4336505e4b1c 1062 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 111:4336505e4b1c 1063 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 111:4336505e4b1c 1064
Kojto 111:4336505e4b1c 1065 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 111:4336505e4b1c 1066 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 111:4336505e4b1c 1067
Kojto 111:4336505e4b1c 1068 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 111:4336505e4b1c 1069 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 111:4336505e4b1c 1070
Kojto 111:4336505e4b1c 1071 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 111:4336505e4b1c 1072 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 111:4336505e4b1c 1073
Kojto 111:4336505e4b1c 1074 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 111:4336505e4b1c 1075 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 111:4336505e4b1c 1076
Kojto 111:4336505e4b1c 1077 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 111:4336505e4b1c 1078 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 111:4336505e4b1c 1079
Kojto 111:4336505e4b1c 1080 /* TPI DEVTYPE Register Definitions */
Kojto 111:4336505e4b1c 1081 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 111:4336505e4b1c 1082 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 111:4336505e4b1c 1083
Kojto 111:4336505e4b1c 1084 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 111:4336505e4b1c 1085 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 111:4336505e4b1c 1086
Kojto 111:4336505e4b1c 1087 /*@}*/ /* end of group CMSIS_TPI */
Kojto 111:4336505e4b1c 1088
Kojto 111:4336505e4b1c 1089
Kojto 111:4336505e4b1c 1090 #if (__MPU_PRESENT == 1)
Kojto 111:4336505e4b1c 1091 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 1092 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 111:4336505e4b1c 1093 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 111:4336505e4b1c 1094 @{
Kojto 111:4336505e4b1c 1095 */
Kojto 111:4336505e4b1c 1096
Kojto 111:4336505e4b1c 1097 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 111:4336505e4b1c 1098 */
Kojto 111:4336505e4b1c 1099 typedef struct
Kojto 111:4336505e4b1c 1100 {
Kojto 111:4336505e4b1c 1101 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 111:4336505e4b1c 1102 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 111:4336505e4b1c 1103 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 111:4336505e4b1c 1104 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 111:4336505e4b1c 1105 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 111:4336505e4b1c 1106 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 111:4336505e4b1c 1107 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 111:4336505e4b1c 1108 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 111:4336505e4b1c 1109 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 111:4336505e4b1c 1110 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 111:4336505e4b1c 1111 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 111:4336505e4b1c 1112 } MPU_Type;
Kojto 111:4336505e4b1c 1113
Kojto 111:4336505e4b1c 1114 /* MPU Type Register */
Kojto 111:4336505e4b1c 1115 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 111:4336505e4b1c 1116 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 111:4336505e4b1c 1117
Kojto 111:4336505e4b1c 1118 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 111:4336505e4b1c 1119 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 111:4336505e4b1c 1120
Kojto 111:4336505e4b1c 1121 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 111:4336505e4b1c 1122 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 111:4336505e4b1c 1123
Kojto 111:4336505e4b1c 1124 /* MPU Control Register */
Kojto 111:4336505e4b1c 1125 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 111:4336505e4b1c 1126 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 111:4336505e4b1c 1127
Kojto 111:4336505e4b1c 1128 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 111:4336505e4b1c 1129 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 111:4336505e4b1c 1130
Kojto 111:4336505e4b1c 1131 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 111:4336505e4b1c 1132 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 111:4336505e4b1c 1133
Kojto 111:4336505e4b1c 1134 /* MPU Region Number Register */
Kojto 111:4336505e4b1c 1135 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 111:4336505e4b1c 1136 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 111:4336505e4b1c 1137
Kojto 111:4336505e4b1c 1138 /* MPU Region Base Address Register */
Kojto 111:4336505e4b1c 1139 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 111:4336505e4b1c 1140 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 111:4336505e4b1c 1141
Kojto 111:4336505e4b1c 1142 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 111:4336505e4b1c 1143 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 111:4336505e4b1c 1144
Kojto 111:4336505e4b1c 1145 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 111:4336505e4b1c 1146 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 111:4336505e4b1c 1147
Kojto 111:4336505e4b1c 1148 /* MPU Region Attribute and Size Register */
Kojto 111:4336505e4b1c 1149 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 111:4336505e4b1c 1150 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 111:4336505e4b1c 1151
Kojto 111:4336505e4b1c 1152 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 111:4336505e4b1c 1153 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 111:4336505e4b1c 1154
Kojto 111:4336505e4b1c 1155 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 111:4336505e4b1c 1156 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 111:4336505e4b1c 1157
Kojto 111:4336505e4b1c 1158 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 111:4336505e4b1c 1159 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 111:4336505e4b1c 1160
Kojto 111:4336505e4b1c 1161 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 111:4336505e4b1c 1162 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 111:4336505e4b1c 1163
Kojto 111:4336505e4b1c 1164 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 111:4336505e4b1c 1165 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 111:4336505e4b1c 1166
Kojto 111:4336505e4b1c 1167 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 111:4336505e4b1c 1168 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 111:4336505e4b1c 1169
Kojto 111:4336505e4b1c 1170 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 111:4336505e4b1c 1171 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 111:4336505e4b1c 1172
Kojto 111:4336505e4b1c 1173 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 111:4336505e4b1c 1174 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 111:4336505e4b1c 1175
Kojto 111:4336505e4b1c 1176 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 111:4336505e4b1c 1177 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 111:4336505e4b1c 1178
Kojto 111:4336505e4b1c 1179 /*@} end of group CMSIS_MPU */
Kojto 111:4336505e4b1c 1180 #endif
Kojto 111:4336505e4b1c 1181
Kojto 111:4336505e4b1c 1182
Kojto 111:4336505e4b1c 1183 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 1184 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 111:4336505e4b1c 1185 \brief Type definitions for the Core Debug Registers
Kojto 111:4336505e4b1c 1186 @{
Kojto 111:4336505e4b1c 1187 */
Kojto 111:4336505e4b1c 1188
Kojto 111:4336505e4b1c 1189 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 111:4336505e4b1c 1190 */
Kojto 111:4336505e4b1c 1191 typedef struct
Kojto 111:4336505e4b1c 1192 {
Kojto 111:4336505e4b1c 1193 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 111:4336505e4b1c 1194 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 111:4336505e4b1c 1195 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 111:4336505e4b1c 1196 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 111:4336505e4b1c 1197 } CoreDebug_Type;
Kojto 111:4336505e4b1c 1198
Kojto 111:4336505e4b1c 1199 /* Debug Halting Control and Status Register */
Kojto 111:4336505e4b1c 1200 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 111:4336505e4b1c 1201 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 111:4336505e4b1c 1202
Kojto 111:4336505e4b1c 1203 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 111:4336505e4b1c 1204 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 111:4336505e4b1c 1205
Kojto 111:4336505e4b1c 1206 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 111:4336505e4b1c 1207 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 111:4336505e4b1c 1208
Kojto 111:4336505e4b1c 1209 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 111:4336505e4b1c 1210 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 111:4336505e4b1c 1211
Kojto 111:4336505e4b1c 1212 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 111:4336505e4b1c 1213 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 111:4336505e4b1c 1214
Kojto 111:4336505e4b1c 1215 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 111:4336505e4b1c 1216 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 111:4336505e4b1c 1217
Kojto 111:4336505e4b1c 1218 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 111:4336505e4b1c 1219 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 111:4336505e4b1c 1220
Kojto 111:4336505e4b1c 1221 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 111:4336505e4b1c 1222 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 111:4336505e4b1c 1223
Kojto 111:4336505e4b1c 1224 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 111:4336505e4b1c 1225 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 111:4336505e4b1c 1226
Kojto 111:4336505e4b1c 1227 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 111:4336505e4b1c 1228 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 111:4336505e4b1c 1229
Kojto 111:4336505e4b1c 1230 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 111:4336505e4b1c 1231 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 111:4336505e4b1c 1232
Kojto 111:4336505e4b1c 1233 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 111:4336505e4b1c 1234 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 111:4336505e4b1c 1235
Kojto 111:4336505e4b1c 1236 /* Debug Core Register Selector Register */
Kojto 111:4336505e4b1c 1237 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 111:4336505e4b1c 1238 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 111:4336505e4b1c 1239
Kojto 111:4336505e4b1c 1240 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 111:4336505e4b1c 1241 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 111:4336505e4b1c 1242
Kojto 111:4336505e4b1c 1243 /* Debug Exception and Monitor Control Register */
Kojto 111:4336505e4b1c 1244 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 111:4336505e4b1c 1245 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 111:4336505e4b1c 1246
Kojto 111:4336505e4b1c 1247 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 111:4336505e4b1c 1248 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 111:4336505e4b1c 1249
Kojto 111:4336505e4b1c 1250 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 111:4336505e4b1c 1251 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 111:4336505e4b1c 1252
Kojto 111:4336505e4b1c 1253 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 111:4336505e4b1c 1254 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 111:4336505e4b1c 1255
Kojto 111:4336505e4b1c 1256 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 111:4336505e4b1c 1257 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 111:4336505e4b1c 1258
Kojto 111:4336505e4b1c 1259 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 111:4336505e4b1c 1260 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 111:4336505e4b1c 1261
Kojto 111:4336505e4b1c 1262 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 111:4336505e4b1c 1263 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 111:4336505e4b1c 1264
Kojto 111:4336505e4b1c 1265 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 111:4336505e4b1c 1266 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 111:4336505e4b1c 1267
Kojto 111:4336505e4b1c 1268 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 111:4336505e4b1c 1269 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 111:4336505e4b1c 1270
Kojto 111:4336505e4b1c 1271 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 111:4336505e4b1c 1272 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 111:4336505e4b1c 1273
Kojto 111:4336505e4b1c 1274 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 111:4336505e4b1c 1275 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 111:4336505e4b1c 1276
Kojto 111:4336505e4b1c 1277 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 111:4336505e4b1c 1278 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 111:4336505e4b1c 1279
Kojto 111:4336505e4b1c 1280 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 111:4336505e4b1c 1281 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 111:4336505e4b1c 1282
Kojto 111:4336505e4b1c 1283 /*@} end of group CMSIS_CoreDebug */
Kojto 111:4336505e4b1c 1284
Kojto 111:4336505e4b1c 1285
Kojto 111:4336505e4b1c 1286 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 1287 \defgroup CMSIS_core_base Core Definitions
Kojto 111:4336505e4b1c 1288 \brief Definitions for base addresses, unions, and structures.
Kojto 111:4336505e4b1c 1289 @{
Kojto 111:4336505e4b1c 1290 */
Kojto 111:4336505e4b1c 1291
Kojto 111:4336505e4b1c 1292 /* Memory mapping of Cortex-M3 Hardware */
Kojto 111:4336505e4b1c 1293 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 111:4336505e4b1c 1294 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 111:4336505e4b1c 1295 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 111:4336505e4b1c 1296 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 111:4336505e4b1c 1297 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 111:4336505e4b1c 1298 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 111:4336505e4b1c 1299 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 111:4336505e4b1c 1300 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 111:4336505e4b1c 1301
Kojto 111:4336505e4b1c 1302 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 111:4336505e4b1c 1303 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 111:4336505e4b1c 1304 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 111:4336505e4b1c 1305 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 111:4336505e4b1c 1306 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 111:4336505e4b1c 1307 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 111:4336505e4b1c 1308 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 111:4336505e4b1c 1309 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 111:4336505e4b1c 1310
Kojto 111:4336505e4b1c 1311 #if (__MPU_PRESENT == 1)
Kojto 111:4336505e4b1c 1312 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 111:4336505e4b1c 1313 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 111:4336505e4b1c 1314 #endif
Kojto 111:4336505e4b1c 1315
Kojto 111:4336505e4b1c 1316 /*@} */
Kojto 111:4336505e4b1c 1317
Kojto 111:4336505e4b1c 1318
Kojto 111:4336505e4b1c 1319
Kojto 111:4336505e4b1c 1320 /*******************************************************************************
Kojto 111:4336505e4b1c 1321 * Hardware Abstraction Layer
Kojto 111:4336505e4b1c 1322 Core Function Interface contains:
Kojto 111:4336505e4b1c 1323 - Core NVIC Functions
Kojto 111:4336505e4b1c 1324 - Core SysTick Functions
Kojto 111:4336505e4b1c 1325 - Core Debug Functions
Kojto 111:4336505e4b1c 1326 - Core Register Access Functions
Kojto 111:4336505e4b1c 1327 ******************************************************************************/
Kojto 111:4336505e4b1c 1328 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 111:4336505e4b1c 1329 */
Kojto 111:4336505e4b1c 1330
Kojto 111:4336505e4b1c 1331
Kojto 111:4336505e4b1c 1332
Kojto 111:4336505e4b1c 1333 /* ########################## NVIC functions #################################### */
Kojto 111:4336505e4b1c 1334 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 111:4336505e4b1c 1335 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 111:4336505e4b1c 1336 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 111:4336505e4b1c 1337 @{
Kojto 111:4336505e4b1c 1338 */
Kojto 111:4336505e4b1c 1339
<> 127:25aea2a3f4e3 1340 #ifdef CMSIS_NVIC_VIRTUAL
<> 127:25aea2a3f4e3 1341 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1342 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 127:25aea2a3f4e3 1343 #endif
<> 127:25aea2a3f4e3 1344 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1345 #else
<> 127:25aea2a3f4e3 1346 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 127:25aea2a3f4e3 1347 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 127:25aea2a3f4e3 1348 #define NVIC_EnableIRQ __NVIC_EnableIRQ
<> 127:25aea2a3f4e3 1349 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 127:25aea2a3f4e3 1350 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 127:25aea2a3f4e3 1351 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 127:25aea2a3f4e3 1352 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 127:25aea2a3f4e3 1353 #define NVIC_GetActive __NVIC_GetActive
<> 127:25aea2a3f4e3 1354 #define NVIC_SetPriority __NVIC_SetPriority
<> 127:25aea2a3f4e3 1355 #define NVIC_GetPriority __NVIC_GetPriority
<> 127:25aea2a3f4e3 1356 #endif /* CMSIS_NVIC_VIRTUAL */
<> 127:25aea2a3f4e3 1357
<> 127:25aea2a3f4e3 1358 #ifdef CMSIS_VECTAB_VIRTUAL
<> 127:25aea2a3f4e3 1359 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1360 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 127:25aea2a3f4e3 1361 #endif
<> 127:25aea2a3f4e3 1362 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1363 #else
<> 127:25aea2a3f4e3 1364 #define NVIC_SetVector __NVIC_SetVector
<> 127:25aea2a3f4e3 1365 #define NVIC_GetVector __NVIC_GetVector
<> 127:25aea2a3f4e3 1366 #endif /* CMSIS_VECTAB_VIRTUAL */
<> 127:25aea2a3f4e3 1367
Kojto 111:4336505e4b1c 1368 /** \brief Set Priority Grouping
Kojto 111:4336505e4b1c 1369
Kojto 111:4336505e4b1c 1370 The function sets the priority grouping field using the required unlock sequence.
Kojto 111:4336505e4b1c 1371 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 111:4336505e4b1c 1372 Only values from 0..7 are used.
Kojto 111:4336505e4b1c 1373 In case of a conflict between priority grouping and available
Kojto 111:4336505e4b1c 1374 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 111:4336505e4b1c 1375
Kojto 111:4336505e4b1c 1376 \param [in] PriorityGroup Priority grouping field.
Kojto 111:4336505e4b1c 1377 */
<> 127:25aea2a3f4e3 1378 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 111:4336505e4b1c 1379 {
Kojto 111:4336505e4b1c 1380 uint32_t reg_value;
Kojto 111:4336505e4b1c 1381 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 111:4336505e4b1c 1382
Kojto 111:4336505e4b1c 1383 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 111:4336505e4b1c 1384 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 111:4336505e4b1c 1385 reg_value = (reg_value |
Kojto 111:4336505e4b1c 1386 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 111:4336505e4b1c 1387 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto 111:4336505e4b1c 1388 SCB->AIRCR = reg_value;
Kojto 111:4336505e4b1c 1389 }
Kojto 111:4336505e4b1c 1390
Kojto 111:4336505e4b1c 1391
Kojto 111:4336505e4b1c 1392 /** \brief Get Priority Grouping
Kojto 111:4336505e4b1c 1393
Kojto 111:4336505e4b1c 1394 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 111:4336505e4b1c 1395
Kojto 111:4336505e4b1c 1396 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 111:4336505e4b1c 1397 */
<> 127:25aea2a3f4e3 1398 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Kojto 111:4336505e4b1c 1399 {
Kojto 111:4336505e4b1c 1400 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 111:4336505e4b1c 1401 }
Kojto 111:4336505e4b1c 1402
Kojto 111:4336505e4b1c 1403
Kojto 111:4336505e4b1c 1404 /** \brief Enable External Interrupt
Kojto 111:4336505e4b1c 1405
Kojto 111:4336505e4b1c 1406 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 111:4336505e4b1c 1407
Kojto 111:4336505e4b1c 1408 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 1409 */
<> 127:25aea2a3f4e3 1410 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 1411 {
Kojto 111:4336505e4b1c 1412 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 111:4336505e4b1c 1413 }
Kojto 111:4336505e4b1c 1414
Kojto 111:4336505e4b1c 1415
Kojto 111:4336505e4b1c 1416 /** \brief Disable External Interrupt
Kojto 111:4336505e4b1c 1417
Kojto 111:4336505e4b1c 1418 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 111:4336505e4b1c 1419
Kojto 111:4336505e4b1c 1420 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 1421 */
<> 127:25aea2a3f4e3 1422 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 1423 {
Kojto 111:4336505e4b1c 1424 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 111:4336505e4b1c 1425 }
Kojto 111:4336505e4b1c 1426
Kojto 111:4336505e4b1c 1427
Kojto 111:4336505e4b1c 1428 /** \brief Get Pending Interrupt
Kojto 111:4336505e4b1c 1429
Kojto 111:4336505e4b1c 1430 The function reads the pending register in the NVIC and returns the pending bit
Kojto 111:4336505e4b1c 1431 for the specified interrupt.
Kojto 111:4336505e4b1c 1432
Kojto 111:4336505e4b1c 1433 \param [in] IRQn Interrupt number.
Kojto 111:4336505e4b1c 1434
Kojto 111:4336505e4b1c 1435 \return 0 Interrupt status is not pending.
Kojto 111:4336505e4b1c 1436 \return 1 Interrupt status is pending.
Kojto 111:4336505e4b1c 1437 */
<> 127:25aea2a3f4e3 1438 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 1439 {
Kojto 111:4336505e4b1c 1440 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 111:4336505e4b1c 1441 }
Kojto 111:4336505e4b1c 1442
Kojto 111:4336505e4b1c 1443
Kojto 111:4336505e4b1c 1444 /** \brief Set Pending Interrupt
Kojto 111:4336505e4b1c 1445
Kojto 111:4336505e4b1c 1446 The function sets the pending bit of an external interrupt.
Kojto 111:4336505e4b1c 1447
Kojto 111:4336505e4b1c 1448 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 1449 */
<> 127:25aea2a3f4e3 1450 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 1451 {
Kojto 111:4336505e4b1c 1452 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 111:4336505e4b1c 1453 }
Kojto 111:4336505e4b1c 1454
Kojto 111:4336505e4b1c 1455
Kojto 111:4336505e4b1c 1456 /** \brief Clear Pending Interrupt
Kojto 111:4336505e4b1c 1457
Kojto 111:4336505e4b1c 1458 The function clears the pending bit of an external interrupt.
Kojto 111:4336505e4b1c 1459
Kojto 111:4336505e4b1c 1460 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 1461 */
<> 127:25aea2a3f4e3 1462 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 1463 {
Kojto 111:4336505e4b1c 1464 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 111:4336505e4b1c 1465 }
Kojto 111:4336505e4b1c 1466
Kojto 111:4336505e4b1c 1467
Kojto 111:4336505e4b1c 1468 /** \brief Get Active Interrupt
Kojto 111:4336505e4b1c 1469
Kojto 111:4336505e4b1c 1470 The function reads the active register in NVIC and returns the active bit.
Kojto 111:4336505e4b1c 1471
Kojto 111:4336505e4b1c 1472 \param [in] IRQn Interrupt number.
Kojto 111:4336505e4b1c 1473
Kojto 111:4336505e4b1c 1474 \return 0 Interrupt status is not active.
Kojto 111:4336505e4b1c 1475 \return 1 Interrupt status is active.
Kojto 111:4336505e4b1c 1476 */
<> 127:25aea2a3f4e3 1477 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 1478 {
Kojto 111:4336505e4b1c 1479 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 111:4336505e4b1c 1480 }
Kojto 111:4336505e4b1c 1481
Kojto 111:4336505e4b1c 1482
Kojto 111:4336505e4b1c 1483 /** \brief Set Interrupt Priority
Kojto 111:4336505e4b1c 1484
Kojto 111:4336505e4b1c 1485 The function sets the priority of an interrupt.
Kojto 111:4336505e4b1c 1486
Kojto 111:4336505e4b1c 1487 \note The priority cannot be set for every core interrupt.
Kojto 111:4336505e4b1c 1488
Kojto 111:4336505e4b1c 1489 \param [in] IRQn Interrupt number.
Kojto 111:4336505e4b1c 1490 \param [in] priority Priority to set.
Kojto 111:4336505e4b1c 1491 */
<> 127:25aea2a3f4e3 1492 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 111:4336505e4b1c 1493 {
Kojto 111:4336505e4b1c 1494 if((int32_t)IRQn < 0) {
Kojto 111:4336505e4b1c 1495 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 111:4336505e4b1c 1496 }
Kojto 111:4336505e4b1c 1497 else {
Kojto 111:4336505e4b1c 1498 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 111:4336505e4b1c 1499 }
Kojto 111:4336505e4b1c 1500 }
Kojto 111:4336505e4b1c 1501
Kojto 111:4336505e4b1c 1502
Kojto 111:4336505e4b1c 1503 /** \brief Get Interrupt Priority
Kojto 111:4336505e4b1c 1504
Kojto 111:4336505e4b1c 1505 The function reads the priority of an interrupt. The interrupt
Kojto 111:4336505e4b1c 1506 number can be positive to specify an external (device specific)
Kojto 111:4336505e4b1c 1507 interrupt, or negative to specify an internal (core) interrupt.
Kojto 111:4336505e4b1c 1508
Kojto 111:4336505e4b1c 1509
Kojto 111:4336505e4b1c 1510 \param [in] IRQn Interrupt number.
Kojto 111:4336505e4b1c 1511 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 111:4336505e4b1c 1512 priority bits of the microcontroller.
Kojto 111:4336505e4b1c 1513 */
<> 127:25aea2a3f4e3 1514 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 1515 {
Kojto 111:4336505e4b1c 1516
Kojto 111:4336505e4b1c 1517 if((int32_t)IRQn < 0) {
Kojto 111:4336505e4b1c 1518 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 111:4336505e4b1c 1519 }
Kojto 111:4336505e4b1c 1520 else {
Kojto 111:4336505e4b1c 1521 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 111:4336505e4b1c 1522 }
Kojto 111:4336505e4b1c 1523 }
Kojto 111:4336505e4b1c 1524
Kojto 111:4336505e4b1c 1525
Kojto 111:4336505e4b1c 1526 /** \brief Encode Priority
Kojto 111:4336505e4b1c 1527
Kojto 111:4336505e4b1c 1528 The function encodes the priority for an interrupt with the given priority group,
Kojto 111:4336505e4b1c 1529 preemptive priority value, and subpriority value.
Kojto 111:4336505e4b1c 1530 In case of a conflict between priority grouping and available
Kojto 111:4336505e4b1c 1531 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 111:4336505e4b1c 1532
Kojto 111:4336505e4b1c 1533 \param [in] PriorityGroup Used priority group.
Kojto 111:4336505e4b1c 1534 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 111:4336505e4b1c 1535 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 111:4336505e4b1c 1536 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 111:4336505e4b1c 1537 */
Kojto 111:4336505e4b1c 1538 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 111:4336505e4b1c 1539 {
Kojto 111:4336505e4b1c 1540 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 111:4336505e4b1c 1541 uint32_t PreemptPriorityBits;
Kojto 111:4336505e4b1c 1542 uint32_t SubPriorityBits;
Kojto 111:4336505e4b1c 1543
Kojto 111:4336505e4b1c 1544 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 111:4336505e4b1c 1545 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 111:4336505e4b1c 1546
Kojto 111:4336505e4b1c 1547 return (
Kojto 111:4336505e4b1c 1548 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 111:4336505e4b1c 1549 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 111:4336505e4b1c 1550 );
Kojto 111:4336505e4b1c 1551 }
Kojto 111:4336505e4b1c 1552
Kojto 111:4336505e4b1c 1553
Kojto 111:4336505e4b1c 1554 /** \brief Decode Priority
Kojto 111:4336505e4b1c 1555
Kojto 111:4336505e4b1c 1556 The function decodes an interrupt priority value with a given priority group to
Kojto 111:4336505e4b1c 1557 preemptive priority value and subpriority value.
Kojto 111:4336505e4b1c 1558 In case of a conflict between priority grouping and available
Kojto 111:4336505e4b1c 1559 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 111:4336505e4b1c 1560
Kojto 111:4336505e4b1c 1561 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 111:4336505e4b1c 1562 \param [in] PriorityGroup Used priority group.
Kojto 111:4336505e4b1c 1563 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 111:4336505e4b1c 1564 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 111:4336505e4b1c 1565 */
Kojto 111:4336505e4b1c 1566 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 111:4336505e4b1c 1567 {
Kojto 111:4336505e4b1c 1568 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 111:4336505e4b1c 1569 uint32_t PreemptPriorityBits;
Kojto 111:4336505e4b1c 1570 uint32_t SubPriorityBits;
Kojto 111:4336505e4b1c 1571
Kojto 111:4336505e4b1c 1572 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 111:4336505e4b1c 1573 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 111:4336505e4b1c 1574
Kojto 111:4336505e4b1c 1575 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 111:4336505e4b1c 1576 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 111:4336505e4b1c 1577 }
Kojto 111:4336505e4b1c 1578
Kojto 111:4336505e4b1c 1579
Kojto 111:4336505e4b1c 1580 /** \brief System Reset
Kojto 111:4336505e4b1c 1581
Kojto 111:4336505e4b1c 1582 The function initiates a system reset request to reset the MCU.
Kojto 111:4336505e4b1c 1583 */
Kojto 111:4336505e4b1c 1584 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 111:4336505e4b1c 1585 {
Kojto 111:4336505e4b1c 1586 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 111:4336505e4b1c 1587 buffered write are completed before reset */
Kojto 111:4336505e4b1c 1588 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 111:4336505e4b1c 1589 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 111:4336505e4b1c 1590 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 111:4336505e4b1c 1591 __DSB(); /* Ensure completion of memory access */
Kojto 111:4336505e4b1c 1592 while(1) { __NOP(); } /* wait until reset */
Kojto 111:4336505e4b1c 1593 }
Kojto 111:4336505e4b1c 1594
Kojto 111:4336505e4b1c 1595 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 111:4336505e4b1c 1596
Kojto 111:4336505e4b1c 1597
Kojto 111:4336505e4b1c 1598
Kojto 111:4336505e4b1c 1599 /* ################################## SysTick function ############################################ */
Kojto 111:4336505e4b1c 1600 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 111:4336505e4b1c 1601 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 111:4336505e4b1c 1602 \brief Functions that configure the System.
Kojto 111:4336505e4b1c 1603 @{
Kojto 111:4336505e4b1c 1604 */
Kojto 111:4336505e4b1c 1605
Kojto 111:4336505e4b1c 1606 #if (__Vendor_SysTickConfig == 0)
Kojto 111:4336505e4b1c 1607
Kojto 111:4336505e4b1c 1608 /** \brief System Tick Configuration
Kojto 111:4336505e4b1c 1609
Kojto 111:4336505e4b1c 1610 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 111:4336505e4b1c 1611 Counter is in free running mode to generate periodic interrupts.
Kojto 111:4336505e4b1c 1612
Kojto 111:4336505e4b1c 1613 \param [in] ticks Number of ticks between two interrupts.
Kojto 111:4336505e4b1c 1614
Kojto 111:4336505e4b1c 1615 \return 0 Function succeeded.
Kojto 111:4336505e4b1c 1616 \return 1 Function failed.
Kojto 111:4336505e4b1c 1617
Kojto 111:4336505e4b1c 1618 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 111:4336505e4b1c 1619 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 111:4336505e4b1c 1620 must contain a vendor-specific implementation of this function.
Kojto 111:4336505e4b1c 1621
Kojto 111:4336505e4b1c 1622 */
Kojto 111:4336505e4b1c 1623 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 111:4336505e4b1c 1624 {
Kojto 111:4336505e4b1c 1625 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 111:4336505e4b1c 1626
Kojto 111:4336505e4b1c 1627 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 111:4336505e4b1c 1628 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 111:4336505e4b1c 1629 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 111:4336505e4b1c 1630 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 111:4336505e4b1c 1631 SysTick_CTRL_TICKINT_Msk |
Kojto 111:4336505e4b1c 1632 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 111:4336505e4b1c 1633 return (0UL); /* Function successful */
Kojto 111:4336505e4b1c 1634 }
Kojto 111:4336505e4b1c 1635
Kojto 111:4336505e4b1c 1636 #endif
Kojto 111:4336505e4b1c 1637
Kojto 111:4336505e4b1c 1638 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 111:4336505e4b1c 1639
Kojto 111:4336505e4b1c 1640
Kojto 111:4336505e4b1c 1641
Kojto 111:4336505e4b1c 1642 /* ##################################### Debug In/Output function ########################################### */
Kojto 111:4336505e4b1c 1643 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 111:4336505e4b1c 1644 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 111:4336505e4b1c 1645 \brief Functions that access the ITM debug interface.
Kojto 111:4336505e4b1c 1646 @{
Kojto 111:4336505e4b1c 1647 */
Kojto 111:4336505e4b1c 1648
Kojto 111:4336505e4b1c 1649 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 111:4336505e4b1c 1650 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 111:4336505e4b1c 1651
Kojto 111:4336505e4b1c 1652
Kojto 111:4336505e4b1c 1653 /** \brief ITM Send Character
Kojto 111:4336505e4b1c 1654
Kojto 111:4336505e4b1c 1655 The function transmits a character via the ITM channel 0, and
Kojto 111:4336505e4b1c 1656 \li Just returns when no debugger is connected that has booked the output.
Kojto 111:4336505e4b1c 1657 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 111:4336505e4b1c 1658
Kojto 111:4336505e4b1c 1659 \param [in] ch Character to transmit.
Kojto 111:4336505e4b1c 1660
Kojto 111:4336505e4b1c 1661 \returns Character to transmit.
Kojto 111:4336505e4b1c 1662 */
Kojto 111:4336505e4b1c 1663 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 111:4336505e4b1c 1664 {
Kojto 111:4336505e4b1c 1665 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 111:4336505e4b1c 1666 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 111:4336505e4b1c 1667 {
Kojto 111:4336505e4b1c 1668 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 111:4336505e4b1c 1669 ITM->PORT[0].u8 = (uint8_t)ch;
Kojto 111:4336505e4b1c 1670 }
Kojto 111:4336505e4b1c 1671 return (ch);
Kojto 111:4336505e4b1c 1672 }
Kojto 111:4336505e4b1c 1673
Kojto 111:4336505e4b1c 1674
Kojto 111:4336505e4b1c 1675 /** \brief ITM Receive Character
Kojto 111:4336505e4b1c 1676
Kojto 111:4336505e4b1c 1677 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 111:4336505e4b1c 1678
Kojto 111:4336505e4b1c 1679 \return Received character.
Kojto 111:4336505e4b1c 1680 \return -1 No character pending.
Kojto 111:4336505e4b1c 1681 */
Kojto 111:4336505e4b1c 1682 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 111:4336505e4b1c 1683 int32_t ch = -1; /* no character available */
Kojto 111:4336505e4b1c 1684
Kojto 111:4336505e4b1c 1685 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 111:4336505e4b1c 1686 ch = ITM_RxBuffer;
Kojto 111:4336505e4b1c 1687 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 111:4336505e4b1c 1688 }
Kojto 111:4336505e4b1c 1689
Kojto 111:4336505e4b1c 1690 return (ch);
Kojto 111:4336505e4b1c 1691 }
Kojto 111:4336505e4b1c 1692
Kojto 111:4336505e4b1c 1693
Kojto 111:4336505e4b1c 1694 /** \brief ITM Check Character
Kojto 111:4336505e4b1c 1695
Kojto 111:4336505e4b1c 1696 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 111:4336505e4b1c 1697
Kojto 111:4336505e4b1c 1698 \return 0 No character available.
Kojto 111:4336505e4b1c 1699 \return 1 Character available.
Kojto 111:4336505e4b1c 1700 */
Kojto 111:4336505e4b1c 1701 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 111:4336505e4b1c 1702
Kojto 111:4336505e4b1c 1703 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 111:4336505e4b1c 1704 return (0); /* no character available */
Kojto 111:4336505e4b1c 1705 } else {
Kojto 111:4336505e4b1c 1706 return (1); /* character available */
Kojto 111:4336505e4b1c 1707 }
Kojto 111:4336505e4b1c 1708 }
Kojto 111:4336505e4b1c 1709
Kojto 111:4336505e4b1c 1710 /*@} end of CMSIS_core_DebugFunctions */
Kojto 111:4336505e4b1c 1711
Kojto 111:4336505e4b1c 1712
Kojto 111:4336505e4b1c 1713
Kojto 111:4336505e4b1c 1714
Kojto 111:4336505e4b1c 1715 #ifdef __cplusplus
Kojto 111:4336505e4b1c 1716 }
Kojto 111:4336505e4b1c 1717 #endif
Kojto 111:4336505e4b1c 1718
Kojto 111:4336505e4b1c 1719 #endif /* __CORE_CM3_H_DEPENDANT */
Kojto 111:4336505e4b1c 1720
Kojto 111:4336505e4b1c 1721 #endif /* __CMSIS_GENERIC */