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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF51_MICROBIT/core_cm0plus.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
104:b9ad9a133dc7
Child:
128:9bcdf88f62b0
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 104:b9ad9a133dc7 1 /**************************************************************************//**
Kojto 104:b9ad9a133dc7 2 * @file core_cm0plus.h
Kojto 104:b9ad9a133dc7 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 104:b9ad9a133dc7 6 *
Kojto 104:b9ad9a133dc7 7 * @note
Kojto 104:b9ad9a133dc7 8 *
Kojto 104:b9ad9a133dc7 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 104:b9ad9a133dc7 11
Kojto 104:b9ad9a133dc7 12 All rights reserved.
Kojto 104:b9ad9a133dc7 13 Redistribution and use in source and binary forms, with or without
Kojto 104:b9ad9a133dc7 14 modification, are permitted provided that the following conditions are met:
Kojto 104:b9ad9a133dc7 15 - Redistributions of source code must retain the above copyright
Kojto 104:b9ad9a133dc7 16 notice, this list of conditions and the following disclaimer.
Kojto 104:b9ad9a133dc7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 104:b9ad9a133dc7 18 notice, this list of conditions and the following disclaimer in the
Kojto 104:b9ad9a133dc7 19 documentation and/or other materials provided with the distribution.
Kojto 104:b9ad9a133dc7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 104:b9ad9a133dc7 21 to endorse or promote products derived from this software without
Kojto 104:b9ad9a133dc7 22 specific prior written permission.
Kojto 104:b9ad9a133dc7 23 *
Kojto 104:b9ad9a133dc7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 104:b9ad9a133dc7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 104:b9ad9a133dc7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 104:b9ad9a133dc7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 104:b9ad9a133dc7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 104:b9ad9a133dc7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 104:b9ad9a133dc7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 104:b9ad9a133dc7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 104:b9ad9a133dc7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 104:b9ad9a133dc7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 104:b9ad9a133dc7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 104:b9ad9a133dc7 35 ---------------------------------------------------------------------------*/
Kojto 104:b9ad9a133dc7 36
Kojto 104:b9ad9a133dc7 37
Kojto 104:b9ad9a133dc7 38 #if defined ( __ICCARM__ )
Kojto 104:b9ad9a133dc7 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 104:b9ad9a133dc7 40 #endif
Kojto 104:b9ad9a133dc7 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 104:b9ad9a133dc7 45 #ifdef __cplusplus
Kojto 104:b9ad9a133dc7 46 extern "C" {
Kojto 104:b9ad9a133dc7 47 #endif
Kojto 104:b9ad9a133dc7 48
Kojto 104:b9ad9a133dc7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 104:b9ad9a133dc7 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 104:b9ad9a133dc7 51
Kojto 104:b9ad9a133dc7 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 104:b9ad9a133dc7 53 Function definitions in header files are used to allow 'inlining'.
Kojto 104:b9ad9a133dc7 54
Kojto 104:b9ad9a133dc7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 104:b9ad9a133dc7 56 Unions are used for effective representation of core registers.
Kojto 104:b9ad9a133dc7 57
Kojto 104:b9ad9a133dc7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 104:b9ad9a133dc7 59 Function-like macros are used to allow more efficient code.
Kojto 104:b9ad9a133dc7 60 */
Kojto 104:b9ad9a133dc7 61
Kojto 104:b9ad9a133dc7 62
Kojto 104:b9ad9a133dc7 63 /*******************************************************************************
Kojto 104:b9ad9a133dc7 64 * CMSIS definitions
Kojto 104:b9ad9a133dc7 65 ******************************************************************************/
Kojto 104:b9ad9a133dc7 66 /** \ingroup Cortex-M0+
Kojto 104:b9ad9a133dc7 67 @{
Kojto 104:b9ad9a133dc7 68 */
Kojto 104:b9ad9a133dc7 69
Kojto 104:b9ad9a133dc7 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 104:b9ad9a133dc7 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 104:b9ad9a133dc7 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 104:b9ad9a133dc7 75
Kojto 104:b9ad9a133dc7 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 104:b9ad9a133dc7 77
Kojto 104:b9ad9a133dc7 78
Kojto 104:b9ad9a133dc7 79 #if defined ( __CC_ARM )
Kojto 104:b9ad9a133dc7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 104:b9ad9a133dc7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 104:b9ad9a133dc7 82 #define __STATIC_INLINE static __inline
Kojto 104:b9ad9a133dc7 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 104:b9ad9a133dc7 89 #elif defined ( __ICCARM__ )
Kojto 104:b9ad9a133dc7 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 104:b9ad9a133dc7 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 104:b9ad9a133dc7 92 #define __STATIC_INLINE static inline
Kojto 104:b9ad9a133dc7 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 104:b9ad9a133dc7 96 #define __STATIC_INLINE static inline
Kojto 104:b9ad9a133dc7 97
Kojto 104:b9ad9a133dc7 98 #elif defined ( __TASKING__ )
Kojto 104:b9ad9a133dc7 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 104:b9ad9a133dc7 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 104:b9ad9a133dc7 101 #define __STATIC_INLINE static inline
Kojto 104:b9ad9a133dc7 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 104:b9ad9a133dc7 109 #endif
Kojto 104:b9ad9a133dc7 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 104:b9ad9a133dc7 113 */
Kojto 104:b9ad9a133dc7 114 #define __FPU_USED 0
Kojto 104:b9ad9a133dc7 115
Kojto 104:b9ad9a133dc7 116 #if defined ( __CC_ARM )
Kojto 104:b9ad9a133dc7 117 #if defined __TARGET_FPU_VFP
Kojto 104:b9ad9a133dc7 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 119 #endif
Kojto 104:b9ad9a133dc7 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 104:b9ad9a133dc7 126 #elif defined ( __ICCARM__ )
Kojto 104:b9ad9a133dc7 127 #if defined __ARMVFP__
Kojto 104:b9ad9a133dc7 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 129 #endif
Kojto 104:b9ad9a133dc7 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 104:b9ad9a133dc7 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 134 #endif
Kojto 104:b9ad9a133dc7 135
Kojto 104:b9ad9a133dc7 136 #elif defined ( __TASKING__ )
Kojto 104:b9ad9a133dc7 137 #if defined __FPU_VFP__
Kojto 104:b9ad9a133dc7 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 104:b9ad9a133dc7 145 #endif
Kojto 104:b9ad9a133dc7 146
Kojto 104:b9ad9a133dc7 147 #include <stdint.h> /* standard types definitions */
Kojto 104:b9ad9a133dc7 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 104:b9ad9a133dc7 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 104:b9ad9a133dc7 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 104:b9ad9a133dc7 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 104:b9ad9a133dc7 156
Kojto 104:b9ad9a133dc7 157 #ifndef __CMSIS_GENERIC
Kojto 104:b9ad9a133dc7 158
Kojto 104:b9ad9a133dc7 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 104:b9ad9a133dc7 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 104:b9ad9a133dc7 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 104:b9ad9a133dc7 166 /* check device defines and use defaults */
Kojto 104:b9ad9a133dc7 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 104:b9ad9a133dc7 168 #ifndef __CM0PLUS_REV
Kojto 104:b9ad9a133dc7 169 #define __CM0PLUS_REV 0x0000
Kojto 104:b9ad9a133dc7 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 171 #endif
Kojto 104:b9ad9a133dc7 172
Kojto 104:b9ad9a133dc7 173 #ifndef __MPU_PRESENT
Kojto 104:b9ad9a133dc7 174 #define __MPU_PRESENT 0
Kojto 104:b9ad9a133dc7 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 176 #endif
Kojto 104:b9ad9a133dc7 177
Kojto 104:b9ad9a133dc7 178 #ifndef __VTOR_PRESENT
Kojto 104:b9ad9a133dc7 179 #define __VTOR_PRESENT 0
Kojto 104:b9ad9a133dc7 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 181 #endif
Kojto 104:b9ad9a133dc7 182
Kojto 104:b9ad9a133dc7 183 #ifndef __NVIC_PRIO_BITS
Kojto 104:b9ad9a133dc7 184 #define __NVIC_PRIO_BITS 2
Kojto 104:b9ad9a133dc7 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 186 #endif
Kojto 104:b9ad9a133dc7 187
Kojto 104:b9ad9a133dc7 188 #ifndef __Vendor_SysTickConfig
Kojto 104:b9ad9a133dc7 189 #define __Vendor_SysTickConfig 0
Kojto 104:b9ad9a133dc7 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 191 #endif
Kojto 104:b9ad9a133dc7 192 #endif
Kojto 104:b9ad9a133dc7 193
Kojto 104:b9ad9a133dc7 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 104:b9ad9a133dc7 195 /**
Kojto 104:b9ad9a133dc7 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 104:b9ad9a133dc7 197
Kojto 104:b9ad9a133dc7 198 <strong>IO Type Qualifiers</strong> are used
Kojto 104:b9ad9a133dc7 199 \li to specify the access to peripheral variables.
Kojto 104:b9ad9a133dc7 200 \li for automatic generation of peripheral register debug information.
Kojto 104:b9ad9a133dc7 201 */
Kojto 104:b9ad9a133dc7 202 #ifdef __cplusplus
Kojto 104:b9ad9a133dc7 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 104:b9ad9a133dc7 204 #else
Kojto 104:b9ad9a133dc7 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 104:b9ad9a133dc7 206 #endif
Kojto 104:b9ad9a133dc7 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 104:b9ad9a133dc7 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 104:b9ad9a133dc7 209
Kojto 104:b9ad9a133dc7 210 /*@} end of group Cortex-M0+ */
Kojto 104:b9ad9a133dc7 211
Kojto 104:b9ad9a133dc7 212
Kojto 104:b9ad9a133dc7 213
Kojto 104:b9ad9a133dc7 214 /*******************************************************************************
Kojto 104:b9ad9a133dc7 215 * Register Abstraction
Kojto 104:b9ad9a133dc7 216 Core Register contain:
Kojto 104:b9ad9a133dc7 217 - Core Register
Kojto 104:b9ad9a133dc7 218 - Core NVIC Register
Kojto 104:b9ad9a133dc7 219 - Core SCB Register
Kojto 104:b9ad9a133dc7 220 - Core SysTick Register
Kojto 104:b9ad9a133dc7 221 - Core MPU Register
Kojto 104:b9ad9a133dc7 222 ******************************************************************************/
Kojto 104:b9ad9a133dc7 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 104:b9ad9a133dc7 224 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 104:b9ad9a133dc7 225 */
Kojto 104:b9ad9a133dc7 226
Kojto 104:b9ad9a133dc7 227 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 228 \defgroup CMSIS_CORE Status and Control Registers
Kojto 104:b9ad9a133dc7 229 \brief Core Register type definitions.
Kojto 104:b9ad9a133dc7 230 @{
Kojto 104:b9ad9a133dc7 231 */
Kojto 104:b9ad9a133dc7 232
Kojto 104:b9ad9a133dc7 233 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 104:b9ad9a133dc7 234 */
Kojto 104:b9ad9a133dc7 235 typedef union
Kojto 104:b9ad9a133dc7 236 {
Kojto 104:b9ad9a133dc7 237 struct
Kojto 104:b9ad9a133dc7 238 {
Kojto 110:165afa46840b 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 104:b9ad9a133dc7 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 104:b9ad9a133dc7 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 104:b9ad9a133dc7 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 104:b9ad9a133dc7 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 104:b9ad9a133dc7 244 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 245 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 246 } APSR_Type;
Kojto 104:b9ad9a133dc7 247
Kojto 110:165afa46840b 248 /* APSR Register Definitions */
Kojto 110:165afa46840b 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 257
Kojto 110:165afa46840b 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 260
Kojto 104:b9ad9a133dc7 261
Kojto 104:b9ad9a133dc7 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 104:b9ad9a133dc7 263 */
Kojto 104:b9ad9a133dc7 264 typedef union
Kojto 104:b9ad9a133dc7 265 {
Kojto 104:b9ad9a133dc7 266 struct
Kojto 104:b9ad9a133dc7 267 {
Kojto 104:b9ad9a133dc7 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 104:b9ad9a133dc7 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 104:b9ad9a133dc7 270 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 271 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 272 } IPSR_Type;
Kojto 104:b9ad9a133dc7 273
Kojto 110:165afa46840b 274 /* IPSR Register Definitions */
Kojto 110:165afa46840b 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 277
Kojto 104:b9ad9a133dc7 278
Kojto 104:b9ad9a133dc7 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 104:b9ad9a133dc7 280 */
Kojto 104:b9ad9a133dc7 281 typedef union
Kojto 104:b9ad9a133dc7 282 {
Kojto 104:b9ad9a133dc7 283 struct
Kojto 104:b9ad9a133dc7 284 {
Kojto 104:b9ad9a133dc7 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 104:b9ad9a133dc7 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 104:b9ad9a133dc7 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 104:b9ad9a133dc7 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 104:b9ad9a133dc7 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 104:b9ad9a133dc7 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 104:b9ad9a133dc7 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 104:b9ad9a133dc7 293 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 294 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 295 } xPSR_Type;
Kojto 104:b9ad9a133dc7 296
Kojto 110:165afa46840b 297 /* xPSR Register Definitions */
Kojto 110:165afa46840b 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 312
Kojto 110:165afa46840b 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 315
Kojto 104:b9ad9a133dc7 316
Kojto 104:b9ad9a133dc7 317 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 104:b9ad9a133dc7 318 */
Kojto 104:b9ad9a133dc7 319 typedef union
Kojto 104:b9ad9a133dc7 320 {
Kojto 104:b9ad9a133dc7 321 struct
Kojto 104:b9ad9a133dc7 322 {
Kojto 104:b9ad9a133dc7 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 104:b9ad9a133dc7 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 104:b9ad9a133dc7 326 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 327 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 328 } CONTROL_Type;
Kojto 104:b9ad9a133dc7 329
Kojto 110:165afa46840b 330 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 333
Kojto 110:165afa46840b 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 336
Kojto 104:b9ad9a133dc7 337 /*@} end of group CMSIS_CORE */
Kojto 104:b9ad9a133dc7 338
Kojto 104:b9ad9a133dc7 339
Kojto 104:b9ad9a133dc7 340 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 104:b9ad9a133dc7 342 \brief Type definitions for the NVIC Registers
Kojto 104:b9ad9a133dc7 343 @{
Kojto 104:b9ad9a133dc7 344 */
Kojto 104:b9ad9a133dc7 345
Kojto 104:b9ad9a133dc7 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 104:b9ad9a133dc7 347 */
Kojto 104:b9ad9a133dc7 348 typedef struct
Kojto 104:b9ad9a133dc7 349 {
Kojto 104:b9ad9a133dc7 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 104:b9ad9a133dc7 351 uint32_t RESERVED0[31];
Kojto 104:b9ad9a133dc7 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 104:b9ad9a133dc7 353 uint32_t RSERVED1[31];
Kojto 104:b9ad9a133dc7 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 104:b9ad9a133dc7 355 uint32_t RESERVED2[31];
Kojto 104:b9ad9a133dc7 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 104:b9ad9a133dc7 357 uint32_t RESERVED3[31];
Kojto 104:b9ad9a133dc7 358 uint32_t RESERVED4[64];
Kojto 104:b9ad9a133dc7 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 104:b9ad9a133dc7 360 } NVIC_Type;
Kojto 104:b9ad9a133dc7 361
Kojto 104:b9ad9a133dc7 362 /*@} end of group CMSIS_NVIC */
Kojto 104:b9ad9a133dc7 363
Kojto 104:b9ad9a133dc7 364
Kojto 104:b9ad9a133dc7 365 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 366 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 104:b9ad9a133dc7 367 \brief Type definitions for the System Control Block Registers
Kojto 104:b9ad9a133dc7 368 @{
Kojto 104:b9ad9a133dc7 369 */
Kojto 104:b9ad9a133dc7 370
Kojto 104:b9ad9a133dc7 371 /** \brief Structure type to access the System Control Block (SCB).
Kojto 104:b9ad9a133dc7 372 */
Kojto 104:b9ad9a133dc7 373 typedef struct
Kojto 104:b9ad9a133dc7 374 {
Kojto 104:b9ad9a133dc7 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 104:b9ad9a133dc7 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 104:b9ad9a133dc7 377 #if (__VTOR_PRESENT == 1)
Kojto 104:b9ad9a133dc7 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 104:b9ad9a133dc7 379 #else
Kojto 104:b9ad9a133dc7 380 uint32_t RESERVED0;
Kojto 104:b9ad9a133dc7 381 #endif
Kojto 104:b9ad9a133dc7 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 104:b9ad9a133dc7 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 104:b9ad9a133dc7 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 104:b9ad9a133dc7 385 uint32_t RESERVED1;
Kojto 104:b9ad9a133dc7 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 104:b9ad9a133dc7 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 104:b9ad9a133dc7 388 } SCB_Type;
Kojto 104:b9ad9a133dc7 389
Kojto 104:b9ad9a133dc7 390 /* SCB CPUID Register Definitions */
Kojto 104:b9ad9a133dc7 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 104:b9ad9a133dc7 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 104:b9ad9a133dc7 393
Kojto 104:b9ad9a133dc7 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 104:b9ad9a133dc7 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 104:b9ad9a133dc7 396
Kojto 104:b9ad9a133dc7 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 104:b9ad9a133dc7 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 104:b9ad9a133dc7 399
Kojto 104:b9ad9a133dc7 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 104:b9ad9a133dc7 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 104:b9ad9a133dc7 402
Kojto 104:b9ad9a133dc7 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 104:b9ad9a133dc7 405
Kojto 104:b9ad9a133dc7 406 /* SCB Interrupt Control State Register Definitions */
Kojto 104:b9ad9a133dc7 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 104:b9ad9a133dc7 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 104:b9ad9a133dc7 409
Kojto 104:b9ad9a133dc7 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 104:b9ad9a133dc7 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 104:b9ad9a133dc7 412
Kojto 104:b9ad9a133dc7 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 104:b9ad9a133dc7 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 104:b9ad9a133dc7 415
Kojto 104:b9ad9a133dc7 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 104:b9ad9a133dc7 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 104:b9ad9a133dc7 418
Kojto 104:b9ad9a133dc7 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 104:b9ad9a133dc7 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 104:b9ad9a133dc7 421
Kojto 104:b9ad9a133dc7 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 104:b9ad9a133dc7 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 104:b9ad9a133dc7 424
Kojto 104:b9ad9a133dc7 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 104:b9ad9a133dc7 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 104:b9ad9a133dc7 427
Kojto 104:b9ad9a133dc7 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 104:b9ad9a133dc7 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 104:b9ad9a133dc7 430
Kojto 104:b9ad9a133dc7 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 104:b9ad9a133dc7 433
Kojto 104:b9ad9a133dc7 434 #if (__VTOR_PRESENT == 1)
Kojto 104:b9ad9a133dc7 435 /* SCB Interrupt Control State Register Definitions */
Kojto 104:b9ad9a133dc7 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 104:b9ad9a133dc7 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 104:b9ad9a133dc7 438 #endif
Kojto 104:b9ad9a133dc7 439
Kojto 104:b9ad9a133dc7 440 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 104:b9ad9a133dc7 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 104:b9ad9a133dc7 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 104:b9ad9a133dc7 443
Kojto 104:b9ad9a133dc7 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 104:b9ad9a133dc7 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 104:b9ad9a133dc7 446
Kojto 104:b9ad9a133dc7 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 104:b9ad9a133dc7 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 104:b9ad9a133dc7 449
Kojto 104:b9ad9a133dc7 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 104:b9ad9a133dc7 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 104:b9ad9a133dc7 452
Kojto 104:b9ad9a133dc7 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 104:b9ad9a133dc7 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 104:b9ad9a133dc7 455
Kojto 104:b9ad9a133dc7 456 /* SCB System Control Register Definitions */
Kojto 104:b9ad9a133dc7 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 104:b9ad9a133dc7 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 104:b9ad9a133dc7 459
Kojto 104:b9ad9a133dc7 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 104:b9ad9a133dc7 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 104:b9ad9a133dc7 462
Kojto 104:b9ad9a133dc7 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 104:b9ad9a133dc7 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 104:b9ad9a133dc7 465
Kojto 104:b9ad9a133dc7 466 /* SCB Configuration Control Register Definitions */
Kojto 104:b9ad9a133dc7 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 104:b9ad9a133dc7 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 104:b9ad9a133dc7 469
Kojto 104:b9ad9a133dc7 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 104:b9ad9a133dc7 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 104:b9ad9a133dc7 472
Kojto 104:b9ad9a133dc7 473 /* SCB System Handler Control and State Register Definitions */
Kojto 104:b9ad9a133dc7 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 104:b9ad9a133dc7 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 104:b9ad9a133dc7 476
Kojto 104:b9ad9a133dc7 477 /*@} end of group CMSIS_SCB */
Kojto 104:b9ad9a133dc7 478
Kojto 104:b9ad9a133dc7 479
Kojto 104:b9ad9a133dc7 480 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 104:b9ad9a133dc7 482 \brief Type definitions for the System Timer Registers.
Kojto 104:b9ad9a133dc7 483 @{
Kojto 104:b9ad9a133dc7 484 */
Kojto 104:b9ad9a133dc7 485
Kojto 104:b9ad9a133dc7 486 /** \brief Structure type to access the System Timer (SysTick).
Kojto 104:b9ad9a133dc7 487 */
Kojto 104:b9ad9a133dc7 488 typedef struct
Kojto 104:b9ad9a133dc7 489 {
Kojto 104:b9ad9a133dc7 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 104:b9ad9a133dc7 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 104:b9ad9a133dc7 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 104:b9ad9a133dc7 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 104:b9ad9a133dc7 494 } SysTick_Type;
Kojto 104:b9ad9a133dc7 495
Kojto 104:b9ad9a133dc7 496 /* SysTick Control / Status Register Definitions */
Kojto 104:b9ad9a133dc7 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 104:b9ad9a133dc7 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 104:b9ad9a133dc7 499
Kojto 104:b9ad9a133dc7 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 104:b9ad9a133dc7 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 104:b9ad9a133dc7 502
Kojto 104:b9ad9a133dc7 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 104:b9ad9a133dc7 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 104:b9ad9a133dc7 505
Kojto 104:b9ad9a133dc7 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 104:b9ad9a133dc7 508
Kojto 104:b9ad9a133dc7 509 /* SysTick Reload Register Definitions */
Kojto 104:b9ad9a133dc7 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 104:b9ad9a133dc7 512
Kojto 104:b9ad9a133dc7 513 /* SysTick Current Register Definitions */
Kojto 104:b9ad9a133dc7 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 104:b9ad9a133dc7 516
Kojto 104:b9ad9a133dc7 517 /* SysTick Calibration Register Definitions */
Kojto 104:b9ad9a133dc7 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 104:b9ad9a133dc7 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 104:b9ad9a133dc7 520
Kojto 104:b9ad9a133dc7 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 104:b9ad9a133dc7 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 104:b9ad9a133dc7 523
Kojto 104:b9ad9a133dc7 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 104:b9ad9a133dc7 526
Kojto 104:b9ad9a133dc7 527 /*@} end of group CMSIS_SysTick */
Kojto 104:b9ad9a133dc7 528
Kojto 104:b9ad9a133dc7 529 #if (__MPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 530 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 104:b9ad9a133dc7 532 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 104:b9ad9a133dc7 533 @{
Kojto 104:b9ad9a133dc7 534 */
Kojto 104:b9ad9a133dc7 535
Kojto 104:b9ad9a133dc7 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 104:b9ad9a133dc7 537 */
Kojto 104:b9ad9a133dc7 538 typedef struct
Kojto 104:b9ad9a133dc7 539 {
Kojto 104:b9ad9a133dc7 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 104:b9ad9a133dc7 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 104:b9ad9a133dc7 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 104:b9ad9a133dc7 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 104:b9ad9a133dc7 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 104:b9ad9a133dc7 545 } MPU_Type;
Kojto 104:b9ad9a133dc7 546
Kojto 104:b9ad9a133dc7 547 /* MPU Type Register */
Kojto 104:b9ad9a133dc7 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 104:b9ad9a133dc7 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 104:b9ad9a133dc7 550
Kojto 104:b9ad9a133dc7 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 104:b9ad9a133dc7 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 104:b9ad9a133dc7 553
Kojto 104:b9ad9a133dc7 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 104:b9ad9a133dc7 556
Kojto 104:b9ad9a133dc7 557 /* MPU Control Register */
Kojto 104:b9ad9a133dc7 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 104:b9ad9a133dc7 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 104:b9ad9a133dc7 560
Kojto 104:b9ad9a133dc7 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 104:b9ad9a133dc7 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 104:b9ad9a133dc7 563
Kojto 104:b9ad9a133dc7 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 104:b9ad9a133dc7 566
Kojto 104:b9ad9a133dc7 567 /* MPU Region Number Register */
Kojto 104:b9ad9a133dc7 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 104:b9ad9a133dc7 570
Kojto 104:b9ad9a133dc7 571 /* MPU Region Base Address Register */
Kojto 104:b9ad9a133dc7 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 104:b9ad9a133dc7 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 104:b9ad9a133dc7 574
Kojto 104:b9ad9a133dc7 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 104:b9ad9a133dc7 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 104:b9ad9a133dc7 577
Kojto 104:b9ad9a133dc7 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 104:b9ad9a133dc7 580
Kojto 104:b9ad9a133dc7 581 /* MPU Region Attribute and Size Register */
Kojto 104:b9ad9a133dc7 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 104:b9ad9a133dc7 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 104:b9ad9a133dc7 584
Kojto 104:b9ad9a133dc7 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 104:b9ad9a133dc7 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 104:b9ad9a133dc7 587
Kojto 104:b9ad9a133dc7 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 104:b9ad9a133dc7 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 104:b9ad9a133dc7 590
Kojto 104:b9ad9a133dc7 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 104:b9ad9a133dc7 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 104:b9ad9a133dc7 593
Kojto 104:b9ad9a133dc7 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 104:b9ad9a133dc7 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 104:b9ad9a133dc7 596
Kojto 104:b9ad9a133dc7 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 104:b9ad9a133dc7 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 104:b9ad9a133dc7 599
Kojto 104:b9ad9a133dc7 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 104:b9ad9a133dc7 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 104:b9ad9a133dc7 602
Kojto 104:b9ad9a133dc7 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 104:b9ad9a133dc7 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 104:b9ad9a133dc7 605
Kojto 104:b9ad9a133dc7 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 104:b9ad9a133dc7 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 104:b9ad9a133dc7 608
Kojto 104:b9ad9a133dc7 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 104:b9ad9a133dc7 611
Kojto 104:b9ad9a133dc7 612 /*@} end of group CMSIS_MPU */
Kojto 104:b9ad9a133dc7 613 #endif
Kojto 104:b9ad9a133dc7 614
Kojto 104:b9ad9a133dc7 615
Kojto 104:b9ad9a133dc7 616 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 104:b9ad9a133dc7 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 104:b9ad9a133dc7 619 are only accessible over DAP and not via processor. Therefore
Kojto 104:b9ad9a133dc7 620 they are not covered by the Cortex-M0 header file.
Kojto 104:b9ad9a133dc7 621 @{
Kojto 104:b9ad9a133dc7 622 */
Kojto 104:b9ad9a133dc7 623 /*@} end of group CMSIS_CoreDebug */
Kojto 104:b9ad9a133dc7 624
Kojto 104:b9ad9a133dc7 625
Kojto 104:b9ad9a133dc7 626 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 627 \defgroup CMSIS_core_base Core Definitions
Kojto 104:b9ad9a133dc7 628 \brief Definitions for base addresses, unions, and structures.
Kojto 104:b9ad9a133dc7 629 @{
Kojto 104:b9ad9a133dc7 630 */
Kojto 104:b9ad9a133dc7 631
Kojto 104:b9ad9a133dc7 632 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 104:b9ad9a133dc7 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 104:b9ad9a133dc7 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 104:b9ad9a133dc7 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 104:b9ad9a133dc7 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 104:b9ad9a133dc7 637
Kojto 104:b9ad9a133dc7 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 104:b9ad9a133dc7 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 104:b9ad9a133dc7 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 104:b9ad9a133dc7 641
Kojto 104:b9ad9a133dc7 642 #if (__MPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 104:b9ad9a133dc7 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 104:b9ad9a133dc7 645 #endif
Kojto 104:b9ad9a133dc7 646
Kojto 104:b9ad9a133dc7 647 /*@} */
Kojto 104:b9ad9a133dc7 648
Kojto 104:b9ad9a133dc7 649
Kojto 104:b9ad9a133dc7 650
Kojto 104:b9ad9a133dc7 651 /*******************************************************************************
Kojto 104:b9ad9a133dc7 652 * Hardware Abstraction Layer
Kojto 104:b9ad9a133dc7 653 Core Function Interface contains:
Kojto 104:b9ad9a133dc7 654 - Core NVIC Functions
Kojto 104:b9ad9a133dc7 655 - Core SysTick Functions
Kojto 104:b9ad9a133dc7 656 - Core Register Access Functions
Kojto 104:b9ad9a133dc7 657 ******************************************************************************/
Kojto 104:b9ad9a133dc7 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 104:b9ad9a133dc7 659 */
Kojto 104:b9ad9a133dc7 660
Kojto 104:b9ad9a133dc7 661
Kojto 104:b9ad9a133dc7 662
Kojto 104:b9ad9a133dc7 663 /* ########################## NVIC functions #################################### */
Kojto 104:b9ad9a133dc7 664 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 104:b9ad9a133dc7 666 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 104:b9ad9a133dc7 667 @{
Kojto 104:b9ad9a133dc7 668 */
Kojto 104:b9ad9a133dc7 669
Kojto 104:b9ad9a133dc7 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 104:b9ad9a133dc7 671 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 104:b9ad9a133dc7 675
Kojto 104:b9ad9a133dc7 676
Kojto 104:b9ad9a133dc7 677 /** \brief Enable External Interrupt
Kojto 104:b9ad9a133dc7 678
Kojto 104:b9ad9a133dc7 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 104:b9ad9a133dc7 680
Kojto 104:b9ad9a133dc7 681 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 682 */
Kojto 104:b9ad9a133dc7 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 684 {
Kojto 110:165afa46840b 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 104:b9ad9a133dc7 686 }
Kojto 104:b9ad9a133dc7 687
Kojto 104:b9ad9a133dc7 688
Kojto 104:b9ad9a133dc7 689 /** \brief Disable External Interrupt
Kojto 104:b9ad9a133dc7 690
Kojto 104:b9ad9a133dc7 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 104:b9ad9a133dc7 692
Kojto 104:b9ad9a133dc7 693 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 694 */
Kojto 104:b9ad9a133dc7 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 696 {
Kojto 110:165afa46840b 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 104:b9ad9a133dc7 698 }
Kojto 104:b9ad9a133dc7 699
Kojto 104:b9ad9a133dc7 700
Kojto 104:b9ad9a133dc7 701 /** \brief Get Pending Interrupt
Kojto 104:b9ad9a133dc7 702
Kojto 104:b9ad9a133dc7 703 The function reads the pending register in the NVIC and returns the pending bit
Kojto 104:b9ad9a133dc7 704 for the specified interrupt.
Kojto 104:b9ad9a133dc7 705
Kojto 104:b9ad9a133dc7 706 \param [in] IRQn Interrupt number.
Kojto 104:b9ad9a133dc7 707
Kojto 104:b9ad9a133dc7 708 \return 0 Interrupt status is not pending.
Kojto 104:b9ad9a133dc7 709 \return 1 Interrupt status is pending.
Kojto 104:b9ad9a133dc7 710 */
Kojto 104:b9ad9a133dc7 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 712 {
Kojto 110:165afa46840b 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 104:b9ad9a133dc7 714 }
Kojto 104:b9ad9a133dc7 715
Kojto 104:b9ad9a133dc7 716
Kojto 104:b9ad9a133dc7 717 /** \brief Set Pending Interrupt
Kojto 104:b9ad9a133dc7 718
Kojto 104:b9ad9a133dc7 719 The function sets the pending bit of an external interrupt.
Kojto 104:b9ad9a133dc7 720
Kojto 104:b9ad9a133dc7 721 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 722 */
Kojto 104:b9ad9a133dc7 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 724 {
Kojto 110:165afa46840b 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 104:b9ad9a133dc7 726 }
Kojto 104:b9ad9a133dc7 727
Kojto 104:b9ad9a133dc7 728
Kojto 104:b9ad9a133dc7 729 /** \brief Clear Pending Interrupt
Kojto 104:b9ad9a133dc7 730
Kojto 104:b9ad9a133dc7 731 The function clears the pending bit of an external interrupt.
Kojto 104:b9ad9a133dc7 732
Kojto 104:b9ad9a133dc7 733 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 734 */
Kojto 104:b9ad9a133dc7 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 736 {
Kojto 110:165afa46840b 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 104:b9ad9a133dc7 738 }
Kojto 104:b9ad9a133dc7 739
Kojto 104:b9ad9a133dc7 740
Kojto 104:b9ad9a133dc7 741 /** \brief Set Interrupt Priority
Kojto 104:b9ad9a133dc7 742
Kojto 104:b9ad9a133dc7 743 The function sets the priority of an interrupt.
Kojto 104:b9ad9a133dc7 744
Kojto 104:b9ad9a133dc7 745 \note The priority cannot be set for every core interrupt.
Kojto 104:b9ad9a133dc7 746
Kojto 104:b9ad9a133dc7 747 \param [in] IRQn Interrupt number.
Kojto 104:b9ad9a133dc7 748 \param [in] priority Priority to set.
Kojto 104:b9ad9a133dc7 749 */
Kojto 104:b9ad9a133dc7 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 104:b9ad9a133dc7 751 {
Kojto 110:165afa46840b 752 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 755 }
Kojto 104:b9ad9a133dc7 756 else {
Kojto 110:165afa46840b 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 759 }
Kojto 104:b9ad9a133dc7 760 }
Kojto 104:b9ad9a133dc7 761
Kojto 104:b9ad9a133dc7 762
Kojto 104:b9ad9a133dc7 763 /** \brief Get Interrupt Priority
Kojto 104:b9ad9a133dc7 764
Kojto 104:b9ad9a133dc7 765 The function reads the priority of an interrupt. The interrupt
Kojto 104:b9ad9a133dc7 766 number can be positive to specify an external (device specific)
Kojto 104:b9ad9a133dc7 767 interrupt, or negative to specify an internal (core) interrupt.
Kojto 104:b9ad9a133dc7 768
Kojto 104:b9ad9a133dc7 769
Kojto 104:b9ad9a133dc7 770 \param [in] IRQn Interrupt number.
Kojto 104:b9ad9a133dc7 771 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 104:b9ad9a133dc7 772 priority bits of the microcontroller.
Kojto 104:b9ad9a133dc7 773 */
Kojto 104:b9ad9a133dc7 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 775 {
Kojto 104:b9ad9a133dc7 776
Kojto 110:165afa46840b 777 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 779 }
Kojto 104:b9ad9a133dc7 780 else {
Kojto 110:165afa46840b 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 782 }
Kojto 104:b9ad9a133dc7 783 }
Kojto 104:b9ad9a133dc7 784
Kojto 104:b9ad9a133dc7 785
Kojto 104:b9ad9a133dc7 786 /** \brief System Reset
Kojto 104:b9ad9a133dc7 787
Kojto 104:b9ad9a133dc7 788 The function initiates a system reset request to reset the MCU.
Kojto 104:b9ad9a133dc7 789 */
Kojto 104:b9ad9a133dc7 790 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 104:b9ad9a133dc7 791 {
Kojto 104:b9ad9a133dc7 792 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 104:b9ad9a133dc7 793 buffered write are completed before reset */
Kojto 110:165afa46840b 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 104:b9ad9a133dc7 795 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 104:b9ad9a133dc7 796 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 797 while(1) { __NOP(); } /* wait until reset */
Kojto 104:b9ad9a133dc7 798 }
Kojto 104:b9ad9a133dc7 799
Kojto 104:b9ad9a133dc7 800 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 104:b9ad9a133dc7 801
Kojto 104:b9ad9a133dc7 802
Kojto 104:b9ad9a133dc7 803
Kojto 104:b9ad9a133dc7 804 /* ################################## SysTick function ############################################ */
Kojto 104:b9ad9a133dc7 805 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 104:b9ad9a133dc7 807 \brief Functions that configure the System.
Kojto 104:b9ad9a133dc7 808 @{
Kojto 104:b9ad9a133dc7 809 */
Kojto 104:b9ad9a133dc7 810
Kojto 104:b9ad9a133dc7 811 #if (__Vendor_SysTickConfig == 0)
Kojto 104:b9ad9a133dc7 812
Kojto 104:b9ad9a133dc7 813 /** \brief System Tick Configuration
Kojto 104:b9ad9a133dc7 814
Kojto 104:b9ad9a133dc7 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 104:b9ad9a133dc7 816 Counter is in free running mode to generate periodic interrupts.
Kojto 104:b9ad9a133dc7 817
Kojto 104:b9ad9a133dc7 818 \param [in] ticks Number of ticks between two interrupts.
Kojto 104:b9ad9a133dc7 819
Kojto 104:b9ad9a133dc7 820 \return 0 Function succeeded.
Kojto 104:b9ad9a133dc7 821 \return 1 Function failed.
Kojto 104:b9ad9a133dc7 822
Kojto 104:b9ad9a133dc7 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 104:b9ad9a133dc7 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 104:b9ad9a133dc7 825 must contain a vendor-specific implementation of this function.
Kojto 104:b9ad9a133dc7 826
Kojto 104:b9ad9a133dc7 827 */
Kojto 104:b9ad9a133dc7 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 104:b9ad9a133dc7 829 {
Kojto 110:165afa46840b 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 104:b9ad9a133dc7 831
Kojto 110:165afa46840b 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 104:b9ad9a133dc7 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 104:b9ad9a133dc7 836 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 838 return (0UL); /* Function successful */
Kojto 104:b9ad9a133dc7 839 }
Kojto 104:b9ad9a133dc7 840
Kojto 104:b9ad9a133dc7 841 #endif
Kojto 104:b9ad9a133dc7 842
Kojto 104:b9ad9a133dc7 843 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 104:b9ad9a133dc7 844
Kojto 104:b9ad9a133dc7 845
Kojto 104:b9ad9a133dc7 846
Kojto 104:b9ad9a133dc7 847
Kojto 110:165afa46840b 848 #ifdef __cplusplus
Kojto 110:165afa46840b 849 }
Kojto 110:165afa46840b 850 #endif
Kojto 110:165afa46840b 851
Kojto 104:b9ad9a133dc7 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 104:b9ad9a133dc7 853
Kojto 104:b9ad9a133dc7 854 #endif /* __CMSIS_GENERIC */