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TARGET_LPC1549/core_cm3.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:: Kojto
Date:: Wed Nov 25 13:21:40 2015 +0000
Revision:: 110:165afa46840b
Parent:: 79:0c05e21ae27e
Child:: 127:25aea2a3f4e3

Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	79:0c05e21ae27e	1	/************************************************************************//
emilmont	79:0c05e21ae27e	2	* @file core_cm3.h
emilmont	79:0c05e21ae27e	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto	110:165afa46840b	4	* @version V4.10
Kojto	110:165afa46840b	5	* @date 18. March 2015
emilmont	79:0c05e21ae27e	6	*
emilmont	79:0c05e21ae27e	7	* @note
emilmont	79:0c05e21ae27e	8	*
emilmont	79:0c05e21ae27e	9	******************************************************************************/
Kojto	110:165afa46840b	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont	79:0c05e21ae27e	11
emilmont	79:0c05e21ae27e	12	All rights reserved.
emilmont	79:0c05e21ae27e	13	Redistribution and use in source and binary forms, with or without
emilmont	79:0c05e21ae27e	14	modification, are permitted provided that the following conditions are met:
emilmont	79:0c05e21ae27e	15	- Redistributions of source code must retain the above copyright
emilmont	79:0c05e21ae27e	16	notice, this list of conditions and the following disclaimer.
emilmont	79:0c05e21ae27e	17	- Redistributions in binary form must reproduce the above copyright
emilmont	79:0c05e21ae27e	18	notice, this list of conditions and the following disclaimer in the
emilmont	79:0c05e21ae27e	19	documentation and/or other materials provided with the distribution.
emilmont	79:0c05e21ae27e	20	- Neither the name of ARM nor the names of its contributors may be used
emilmont	79:0c05e21ae27e	21	to endorse or promote products derived from this software without
emilmont	79:0c05e21ae27e	22	specific prior written permission.
emilmont	79:0c05e21ae27e	23	*
emilmont	79:0c05e21ae27e	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	79:0c05e21ae27e	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	79:0c05e21ae27e	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont	79:0c05e21ae27e	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont	79:0c05e21ae27e	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont	79:0c05e21ae27e	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont	79:0c05e21ae27e	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont	79:0c05e21ae27e	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont	79:0c05e21ae27e	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont	79:0c05e21ae27e	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont	79:0c05e21ae27e	34	POSSIBILITY OF SUCH DAMAGE.
emilmont	79:0c05e21ae27e	35	---------------------------------------------------------------------------*/
emilmont	79:0c05e21ae27e	36
emilmont	79:0c05e21ae27e	37
emilmont	79:0c05e21ae27e	38	#if defined ( __ICCARM__ )
emilmont	79:0c05e21ae27e	39	#pragma system_include /* treat file as system include file for MISRA check */
emilmont	79:0c05e21ae27e	40	#endif
emilmont	79:0c05e21ae27e	41
Kojto	110:165afa46840b	42	#ifndef __CORE_CM3_H_GENERIC
Kojto	110:165afa46840b	43	#define __CORE_CM3_H_GENERIC
Kojto	110:165afa46840b	44
emilmont	79:0c05e21ae27e	45	#ifdef __cplusplus
emilmont	79:0c05e21ae27e	46	extern "C" {
emilmont	79:0c05e21ae27e	47	#endif
emilmont	79:0c05e21ae27e	48
emilmont	79:0c05e21ae27e	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont	79:0c05e21ae27e	50	CMSIS violates the following MISRA-C:2004 rules:
emilmont	79:0c05e21ae27e	51
emilmont	79:0c05e21ae27e	52	\li Required Rule 8.5, object/function definition in header file.<br>
emilmont	79:0c05e21ae27e	53	Function definitions in header files are used to allow 'inlining'.
emilmont	79:0c05e21ae27e	54
emilmont	79:0c05e21ae27e	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont	79:0c05e21ae27e	56	Unions are used for effective representation of core registers.
emilmont	79:0c05e21ae27e	57
emilmont	79:0c05e21ae27e	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont	79:0c05e21ae27e	59	Function-like macros are used to allow more efficient code.
emilmont	79:0c05e21ae27e	60	*/
emilmont	79:0c05e21ae27e	61
emilmont	79:0c05e21ae27e	62
emilmont	79:0c05e21ae27e	63	/*******************************************************************************
emilmont	79:0c05e21ae27e	64	* CMSIS definitions
emilmont	79:0c05e21ae27e	65	******************************************************************************/
emilmont	79:0c05e21ae27e	66	/** \ingroup Cortex_M3
emilmont	79:0c05e21ae27e	67	@{
emilmont	79:0c05e21ae27e	68	*/
emilmont	79:0c05e21ae27e	69
emilmont	79:0c05e21ae27e	70	/* CMSIS CM3 definitions */
Kojto	110:165afa46840b	71	#define __CM3_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Kojto	110:165afa46840b	72	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
emilmont	79:0c05e21ae27e	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
emilmont	79:0c05e21ae27e	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
emilmont	79:0c05e21ae27e	75
emilmont	79:0c05e21ae27e	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
emilmont	79:0c05e21ae27e	77
emilmont	79:0c05e21ae27e	78
emilmont	79:0c05e21ae27e	79	#if defined ( __CC_ARM )
emilmont	79:0c05e21ae27e	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
emilmont	79:0c05e21ae27e	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
emilmont	79:0c05e21ae27e	82	#define __STATIC_INLINE static __inline
emilmont	79:0c05e21ae27e	83
Kojto	110:165afa46840b	84	#elif defined ( __GNUC__ )
Kojto	110:165afa46840b	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	110:165afa46840b	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	110:165afa46840b	87	#define __STATIC_INLINE static inline
Kojto	110:165afa46840b	88
emilmont	79:0c05e21ae27e	89	#elif defined ( __ICCARM__ )
emilmont	79:0c05e21ae27e	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
emilmont	79:0c05e21ae27e	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
emilmont	79:0c05e21ae27e	92	#define __STATIC_INLINE static inline
emilmont	79:0c05e21ae27e	93
emilmont	79:0c05e21ae27e	94	#elif defined ( __TMS470__ )
emilmont	79:0c05e21ae27e	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
emilmont	79:0c05e21ae27e	96	#define __STATIC_INLINE static inline
emilmont	79:0c05e21ae27e	97
emilmont	79:0c05e21ae27e	98	#elif defined ( __TASKING__ )
emilmont	79:0c05e21ae27e	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
emilmont	79:0c05e21ae27e	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
emilmont	79:0c05e21ae27e	101	#define __STATIC_INLINE static inline
emilmont	79:0c05e21ae27e	102
Kojto	110:165afa46840b	103	#elif defined ( __CSMC__ )
Kojto	110:165afa46840b	104	#define __packed
Kojto	110:165afa46840b	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Kojto	110:165afa46840b	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Kojto	110:165afa46840b	107	#define __STATIC_INLINE static inline
Kojto	110:165afa46840b	108
emilmont	79:0c05e21ae27e	109	#endif
emilmont	79:0c05e21ae27e	110
Kojto	110:165afa46840b	111	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	110:165afa46840b	112	This core does not support an FPU at all
emilmont	79:0c05e21ae27e	113	*/
emilmont	79:0c05e21ae27e	114	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	115
emilmont	79:0c05e21ae27e	116	#if defined ( __CC_ARM )
emilmont	79:0c05e21ae27e	117	#if defined __TARGET_FPU_VFP
emilmont	79:0c05e21ae27e	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	119	#endif
emilmont	79:0c05e21ae27e	120
Kojto	110:165afa46840b	121	#elif defined ( __GNUC__ )
Kojto	110:165afa46840b	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	110:165afa46840b	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	110:165afa46840b	124	#endif
Kojto	110:165afa46840b	125
emilmont	79:0c05e21ae27e	126	#elif defined ( __ICCARM__ )
emilmont	79:0c05e21ae27e	127	#if defined __ARMVFP__
emilmont	79:0c05e21ae27e	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	129	#endif
emilmont	79:0c05e21ae27e	130
emilmont	79:0c05e21ae27e	131	#elif defined ( __TMS470__ )
emilmont	79:0c05e21ae27e	132	#if defined __TI__VFP_SUPPORT____
emilmont	79:0c05e21ae27e	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	134	#endif
emilmont	79:0c05e21ae27e	135
Kojto	110:165afa46840b	136	#elif defined ( __TASKING__ )
Kojto	110:165afa46840b	137	#if defined __FPU_VFP__
Kojto	110:165afa46840b	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	139	#endif
emilmont	79:0c05e21ae27e	140
Kojto	110:165afa46840b	141	#elif defined ( __CSMC__ ) /* Cosmic */
Kojto	110:165afa46840b	142	#if ( __CSMC__ & 0x400) // FPU present for parser
emilmont	79:0c05e21ae27e	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	144	#endif
emilmont	79:0c05e21ae27e	145	#endif
emilmont	79:0c05e21ae27e	146
emilmont	79:0c05e21ae27e	147	#include <stdint.h> /* standard types definitions */
emilmont	79:0c05e21ae27e	148	#include <core_cmInstr.h> /* Core Instruction Access */
emilmont	79:0c05e21ae27e	149	#include <core_cmFunc.h> /* Core Function Access */
emilmont	79:0c05e21ae27e	150
Kojto	110:165afa46840b	151	#ifdef __cplusplus
Kojto	110:165afa46840b	152	}
Kojto	110:165afa46840b	153	#endif
Kojto	110:165afa46840b	154
emilmont	79:0c05e21ae27e	155	#endif /* __CORE_CM3_H_GENERIC */
emilmont	79:0c05e21ae27e	156
emilmont	79:0c05e21ae27e	157	#ifndef __CMSIS_GENERIC
emilmont	79:0c05e21ae27e	158
emilmont	79:0c05e21ae27e	159	#ifndef __CORE_CM3_H_DEPENDANT
emilmont	79:0c05e21ae27e	160	#define __CORE_CM3_H_DEPENDANT
emilmont	79:0c05e21ae27e	161
Kojto	110:165afa46840b	162	#ifdef __cplusplus
Kojto	110:165afa46840b	163	extern "C" {
Kojto	110:165afa46840b	164	#endif
Kojto	110:165afa46840b	165
emilmont	79:0c05e21ae27e	166	/* check device defines and use defaults */
emilmont	79:0c05e21ae27e	167	#if defined __CHECK_DEVICE_DEFINES
emilmont	79:0c05e21ae27e	168	#ifndef __CM3_REV
emilmont	79:0c05e21ae27e	169	#define __CM3_REV 0x0200
emilmont	79:0c05e21ae27e	170	#warning "__CM3_REV not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	171	#endif
emilmont	79:0c05e21ae27e	172
emilmont	79:0c05e21ae27e	173	#ifndef __MPU_PRESENT
emilmont	79:0c05e21ae27e	174	#define __MPU_PRESENT 0
emilmont	79:0c05e21ae27e	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	176	#endif
emilmont	79:0c05e21ae27e	177
emilmont	79:0c05e21ae27e	178	#ifndef __NVIC_PRIO_BITS
emilmont	79:0c05e21ae27e	179	#define __NVIC_PRIO_BITS 4
emilmont	79:0c05e21ae27e	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	181	#endif
emilmont	79:0c05e21ae27e	182
emilmont	79:0c05e21ae27e	183	#ifndef __Vendor_SysTickConfig
emilmont	79:0c05e21ae27e	184	#define __Vendor_SysTickConfig 0
emilmont	79:0c05e21ae27e	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	186	#endif
emilmont	79:0c05e21ae27e	187	#endif
emilmont	79:0c05e21ae27e	188
emilmont	79:0c05e21ae27e	189	/* IO definitions (access restrictions to peripheral registers) */
emilmont	79:0c05e21ae27e	190	/**
emilmont	79:0c05e21ae27e	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont	79:0c05e21ae27e	192
emilmont	79:0c05e21ae27e	193	<strong>IO Type Qualifiers</strong> are used
emilmont	79:0c05e21ae27e	194	\li to specify the access to peripheral variables.
emilmont	79:0c05e21ae27e	195	\li for automatic generation of peripheral register debug information.
emilmont	79:0c05e21ae27e	196	*/
emilmont	79:0c05e21ae27e	197	#ifdef __cplusplus
emilmont	79:0c05e21ae27e	198	#define __I volatile /!< Defines 'read only' permissions /
emilmont	79:0c05e21ae27e	199	#else
emilmont	79:0c05e21ae27e	200	#define __I volatile const /!< Defines 'read only' permissions /
emilmont	79:0c05e21ae27e	201	#endif
emilmont	79:0c05e21ae27e	202	#define __O volatile /!< Defines 'write only' permissions /
emilmont	79:0c05e21ae27e	203	#define __IO volatile /!< Defines 'read / write' permissions /
emilmont	79:0c05e21ae27e	204
emilmont	79:0c05e21ae27e	205	/@} end of group Cortex_M3 /
emilmont	79:0c05e21ae27e	206
emilmont	79:0c05e21ae27e	207
emilmont	79:0c05e21ae27e	208
emilmont	79:0c05e21ae27e	209	/*******************************************************************************
emilmont	79:0c05e21ae27e	210	* Register Abstraction
emilmont	79:0c05e21ae27e	211	Core Register contain:
emilmont	79:0c05e21ae27e	212	- Core Register
emilmont	79:0c05e21ae27e	213	- Core NVIC Register
emilmont	79:0c05e21ae27e	214	- Core SCB Register
emilmont	79:0c05e21ae27e	215	- Core SysTick Register
emilmont	79:0c05e21ae27e	216	- Core Debug Register
emilmont	79:0c05e21ae27e	217	- Core MPU Register
emilmont	79:0c05e21ae27e	218	******************************************************************************/
emilmont	79:0c05e21ae27e	219	/** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont	79:0c05e21ae27e	220	\brief Type definitions and defines for Cortex-M processor based devices.
emilmont	79:0c05e21ae27e	221	*/
emilmont	79:0c05e21ae27e	222
emilmont	79:0c05e21ae27e	223	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	224	\defgroup CMSIS_CORE Status and Control Registers
emilmont	79:0c05e21ae27e	225	\brief Core Register type definitions.
emilmont	79:0c05e21ae27e	226	@{
emilmont	79:0c05e21ae27e	227	*/
emilmont	79:0c05e21ae27e	228
emilmont	79:0c05e21ae27e	229	/** \brief Union type to access the Application Program Status Register (APSR).
emilmont	79:0c05e21ae27e	230	*/
emilmont	79:0c05e21ae27e	231	typedef union
emilmont	79:0c05e21ae27e	232	{
emilmont	79:0c05e21ae27e	233	struct
emilmont	79:0c05e21ae27e	234	{
emilmont	79:0c05e21ae27e	235	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
emilmont	79:0c05e21ae27e	236	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	79:0c05e21ae27e	237	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	79:0c05e21ae27e	238	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	79:0c05e21ae27e	239	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	79:0c05e21ae27e	240	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	79:0c05e21ae27e	241	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	242	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	243	} APSR_Type;
emilmont	79:0c05e21ae27e	244
Kojto	110:165afa46840b	245	/* APSR Register Definitions */
Kojto	110:165afa46840b	246	#define APSR_N_Pos 31 /!< APSR: N Position /
Kojto	110:165afa46840b	247	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	110:165afa46840b	248
Kojto	110:165afa46840b	249	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Kojto	110:165afa46840b	250	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	110:165afa46840b	251
Kojto	110:165afa46840b	252	#define APSR_C_Pos 29 /!< APSR: C Position /
Kojto	110:165afa46840b	253	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	110:165afa46840b	254
Kojto	110:165afa46840b	255	#define APSR_V_Pos 28 /!< APSR: V Position /
Kojto	110:165afa46840b	256	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	110:165afa46840b	257
Kojto	110:165afa46840b	258	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Kojto	110:165afa46840b	259	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	110:165afa46840b	260
emilmont	79:0c05e21ae27e	261
emilmont	79:0c05e21ae27e	262	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont	79:0c05e21ae27e	263	*/
emilmont	79:0c05e21ae27e	264	typedef union
emilmont	79:0c05e21ae27e	265	{
emilmont	79:0c05e21ae27e	266	struct
emilmont	79:0c05e21ae27e	267	{
emilmont	79:0c05e21ae27e	268	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	79:0c05e21ae27e	269	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
emilmont	79:0c05e21ae27e	270	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	271	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	272	} IPSR_Type;
emilmont	79:0c05e21ae27e	273
Kojto	110:165afa46840b	274	/* IPSR Register Definitions */
Kojto	110:165afa46840b	275	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Kojto	110:165afa46840b	276	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	110:165afa46840b	277
emilmont	79:0c05e21ae27e	278
emilmont	79:0c05e21ae27e	279	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont	79:0c05e21ae27e	280	*/
emilmont	79:0c05e21ae27e	281	typedef union
emilmont	79:0c05e21ae27e	282	{
emilmont	79:0c05e21ae27e	283	struct
emilmont	79:0c05e21ae27e	284	{
emilmont	79:0c05e21ae27e	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	79:0c05e21ae27e	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
emilmont	79:0c05e21ae27e	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
emilmont	79:0c05e21ae27e	288	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
emilmont	79:0c05e21ae27e	289	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	79:0c05e21ae27e	290	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	79:0c05e21ae27e	291	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	79:0c05e21ae27e	292	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	79:0c05e21ae27e	293	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	79:0c05e21ae27e	294	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	295	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	296	} xPSR_Type;
emilmont	79:0c05e21ae27e	297
Kojto	110:165afa46840b	298	/* xPSR Register Definitions */
Kojto	110:165afa46840b	299	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Kojto	110:165afa46840b	300	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	110:165afa46840b	301
Kojto	110:165afa46840b	302	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Kojto	110:165afa46840b	303	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	110:165afa46840b	304
Kojto	110:165afa46840b	305	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Kojto	110:165afa46840b	306	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	110:165afa46840b	307
Kojto	110:165afa46840b	308	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Kojto	110:165afa46840b	309	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	110:165afa46840b	310
Kojto	110:165afa46840b	311	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Kojto	110:165afa46840b	312	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	110:165afa46840b	313
Kojto	110:165afa46840b	314	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Kojto	110:165afa46840b	315	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	110:165afa46840b	316
Kojto	110:165afa46840b	317	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Kojto	110:165afa46840b	318	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	110:165afa46840b	319
Kojto	110:165afa46840b	320	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Kojto	110:165afa46840b	321	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	110:165afa46840b	322
emilmont	79:0c05e21ae27e	323
emilmont	79:0c05e21ae27e	324	/** \brief Union type to access the Control Registers (CONTROL).
emilmont	79:0c05e21ae27e	325	*/
emilmont	79:0c05e21ae27e	326	typedef union
emilmont	79:0c05e21ae27e	327	{
emilmont	79:0c05e21ae27e	328	struct
emilmont	79:0c05e21ae27e	329	{
emilmont	79:0c05e21ae27e	330	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
emilmont	79:0c05e21ae27e	331	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Kojto	110:165afa46840b	332	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
emilmont	79:0c05e21ae27e	333	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	334	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	335	} CONTROL_Type;
emilmont	79:0c05e21ae27e	336
Kojto	110:165afa46840b	337	/* CONTROL Register Definitions */
Kojto	110:165afa46840b	338	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Kojto	110:165afa46840b	339	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	110:165afa46840b	340
Kojto	110:165afa46840b	341	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Kojto	110:165afa46840b	342	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	110:165afa46840b	343
emilmont	79:0c05e21ae27e	344	/@} end of group CMSIS_CORE /
emilmont	79:0c05e21ae27e	345
emilmont	79:0c05e21ae27e	346
emilmont	79:0c05e21ae27e	347	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	348	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont	79:0c05e21ae27e	349	\brief Type definitions for the NVIC Registers
emilmont	79:0c05e21ae27e	350	@{
emilmont	79:0c05e21ae27e	351	*/
emilmont	79:0c05e21ae27e	352
emilmont	79:0c05e21ae27e	353	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont	79:0c05e21ae27e	354	*/
emilmont	79:0c05e21ae27e	355	typedef struct
emilmont	79:0c05e21ae27e	356	{
emilmont	79:0c05e21ae27e	357	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
emilmont	79:0c05e21ae27e	358	uint32_t RESERVED0[24];
emilmont	79:0c05e21ae27e	359	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
emilmont	79:0c05e21ae27e	360	uint32_t RSERVED1[24];
emilmont	79:0c05e21ae27e	361	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
emilmont	79:0c05e21ae27e	362	uint32_t RESERVED2[24];
emilmont	79:0c05e21ae27e	363	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
emilmont	79:0c05e21ae27e	364	uint32_t RESERVED3[24];
emilmont	79:0c05e21ae27e	365	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
emilmont	79:0c05e21ae27e	366	uint32_t RESERVED4[56];
emilmont	79:0c05e21ae27e	367	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
emilmont	79:0c05e21ae27e	368	uint32_t RESERVED5[644];
emilmont	79:0c05e21ae27e	369	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
emilmont	79:0c05e21ae27e	370	} NVIC_Type;
emilmont	79:0c05e21ae27e	371
emilmont	79:0c05e21ae27e	372	/* Software Triggered Interrupt Register Definitions */
emilmont	79:0c05e21ae27e	373	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	110:165afa46840b	374	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
emilmont	79:0c05e21ae27e	375
emilmont	79:0c05e21ae27e	376	/@} end of group CMSIS_NVIC /
emilmont	79:0c05e21ae27e	377
emilmont	79:0c05e21ae27e	378
emilmont	79:0c05e21ae27e	379	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	380	\defgroup CMSIS_SCB System Control Block (SCB)
emilmont	79:0c05e21ae27e	381	\brief Type definitions for the System Control Block Registers
emilmont	79:0c05e21ae27e	382	@{
emilmont	79:0c05e21ae27e	383	*/
emilmont	79:0c05e21ae27e	384
emilmont	79:0c05e21ae27e	385	/** \brief Structure type to access the System Control Block (SCB).
emilmont	79:0c05e21ae27e	386	*/
emilmont	79:0c05e21ae27e	387	typedef struct
emilmont	79:0c05e21ae27e	388	{
emilmont	79:0c05e21ae27e	389	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
emilmont	79:0c05e21ae27e	390	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
emilmont	79:0c05e21ae27e	391	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
emilmont	79:0c05e21ae27e	392	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
emilmont	79:0c05e21ae27e	393	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
emilmont	79:0c05e21ae27e	394	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
emilmont	79:0c05e21ae27e	395	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
emilmont	79:0c05e21ae27e	396	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
emilmont	79:0c05e21ae27e	397	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
emilmont	79:0c05e21ae27e	398	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
emilmont	79:0c05e21ae27e	399	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
emilmont	79:0c05e21ae27e	400	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
emilmont	79:0c05e21ae27e	401	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
emilmont	79:0c05e21ae27e	402	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
emilmont	79:0c05e21ae27e	403	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
emilmont	79:0c05e21ae27e	404	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
emilmont	79:0c05e21ae27e	405	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
emilmont	79:0c05e21ae27e	406	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
emilmont	79:0c05e21ae27e	407	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
emilmont	79:0c05e21ae27e	408	uint32_t RESERVED0[5];
emilmont	79:0c05e21ae27e	409	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
emilmont	79:0c05e21ae27e	410	} SCB_Type;
emilmont	79:0c05e21ae27e	411
emilmont	79:0c05e21ae27e	412	/* SCB CPUID Register Definitions */
emilmont	79:0c05e21ae27e	413	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
emilmont	79:0c05e21ae27e	414	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
emilmont	79:0c05e21ae27e	415
emilmont	79:0c05e21ae27e	416	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
emilmont	79:0c05e21ae27e	417	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
emilmont	79:0c05e21ae27e	418
emilmont	79:0c05e21ae27e	419	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
emilmont	79:0c05e21ae27e	420	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
emilmont	79:0c05e21ae27e	421
emilmont	79:0c05e21ae27e	422	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
emilmont	79:0c05e21ae27e	423	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
emilmont	79:0c05e21ae27e	424
emilmont	79:0c05e21ae27e	425	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	110:165afa46840b	426	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
emilmont	79:0c05e21ae27e	427
emilmont	79:0c05e21ae27e	428	/* SCB Interrupt Control State Register Definitions */
emilmont	79:0c05e21ae27e	429	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
emilmont	79:0c05e21ae27e	430	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
emilmont	79:0c05e21ae27e	431
emilmont	79:0c05e21ae27e	432	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
emilmont	79:0c05e21ae27e	433	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
emilmont	79:0c05e21ae27e	434
emilmont	79:0c05e21ae27e	435	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
emilmont	79:0c05e21ae27e	436	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
emilmont	79:0c05e21ae27e	437
emilmont	79:0c05e21ae27e	438	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
emilmont	79:0c05e21ae27e	439	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
emilmont	79:0c05e21ae27e	440
emilmont	79:0c05e21ae27e	441	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
emilmont	79:0c05e21ae27e	442	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
emilmont	79:0c05e21ae27e	443
emilmont	79:0c05e21ae27e	444	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
emilmont	79:0c05e21ae27e	445	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
emilmont	79:0c05e21ae27e	446
emilmont	79:0c05e21ae27e	447	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
emilmont	79:0c05e21ae27e	448	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
emilmont	79:0c05e21ae27e	449
emilmont	79:0c05e21ae27e	450	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
emilmont	79:0c05e21ae27e	451	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
emilmont	79:0c05e21ae27e	452
emilmont	79:0c05e21ae27e	453	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
emilmont	79:0c05e21ae27e	454	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
emilmont	79:0c05e21ae27e	455
emilmont	79:0c05e21ae27e	456	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	110:165afa46840b	457	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
emilmont	79:0c05e21ae27e	458
emilmont	79:0c05e21ae27e	459	/* SCB Vector Table Offset Register Definitions */
emilmont	79:0c05e21ae27e	460	#if (__CM3_REV < 0x0201) /* core r2p1 */
emilmont	79:0c05e21ae27e	461	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
emilmont	79:0c05e21ae27e	462	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
emilmont	79:0c05e21ae27e	463
emilmont	79:0c05e21ae27e	464	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	79:0c05e21ae27e	465	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	79:0c05e21ae27e	466	#else
emilmont	79:0c05e21ae27e	467	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	79:0c05e21ae27e	468	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	79:0c05e21ae27e	469	#endif
emilmont	79:0c05e21ae27e	470
emilmont	79:0c05e21ae27e	471	/* SCB Application Interrupt and Reset Control Register Definitions */
emilmont	79:0c05e21ae27e	472	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
emilmont	79:0c05e21ae27e	473	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
emilmont	79:0c05e21ae27e	474
emilmont	79:0c05e21ae27e	475	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
emilmont	79:0c05e21ae27e	476	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
emilmont	79:0c05e21ae27e	477
emilmont	79:0c05e21ae27e	478	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
emilmont	79:0c05e21ae27e	479	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
emilmont	79:0c05e21ae27e	480
emilmont	79:0c05e21ae27e	481	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
emilmont	79:0c05e21ae27e	482	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
emilmont	79:0c05e21ae27e	483
emilmont	79:0c05e21ae27e	484	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
emilmont	79:0c05e21ae27e	485	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
emilmont	79:0c05e21ae27e	486
emilmont	79:0c05e21ae27e	487	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
emilmont	79:0c05e21ae27e	488	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
emilmont	79:0c05e21ae27e	489
emilmont	79:0c05e21ae27e	490	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	110:165afa46840b	491	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
emilmont	79:0c05e21ae27e	492
emilmont	79:0c05e21ae27e	493	/* SCB System Control Register Definitions */
emilmont	79:0c05e21ae27e	494	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
emilmont	79:0c05e21ae27e	495	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
emilmont	79:0c05e21ae27e	496
emilmont	79:0c05e21ae27e	497	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
emilmont	79:0c05e21ae27e	498	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
emilmont	79:0c05e21ae27e	499
emilmont	79:0c05e21ae27e	500	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
emilmont	79:0c05e21ae27e	501	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
emilmont	79:0c05e21ae27e	502
emilmont	79:0c05e21ae27e	503	/* SCB Configuration Control Register Definitions */
emilmont	79:0c05e21ae27e	504	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
emilmont	79:0c05e21ae27e	505	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
emilmont	79:0c05e21ae27e	506
emilmont	79:0c05e21ae27e	507	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
emilmont	79:0c05e21ae27e	508	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
emilmont	79:0c05e21ae27e	509
emilmont	79:0c05e21ae27e	510	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
emilmont	79:0c05e21ae27e	511	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
emilmont	79:0c05e21ae27e	512
emilmont	79:0c05e21ae27e	513	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
emilmont	79:0c05e21ae27e	514	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
emilmont	79:0c05e21ae27e	515
emilmont	79:0c05e21ae27e	516	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
emilmont	79:0c05e21ae27e	517	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
emilmont	79:0c05e21ae27e	518
emilmont	79:0c05e21ae27e	519	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	110:165afa46840b	520	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
emilmont	79:0c05e21ae27e	521
emilmont	79:0c05e21ae27e	522	/* SCB System Handler Control and State Register Definitions */
emilmont	79:0c05e21ae27e	523	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
emilmont	79:0c05e21ae27e	524	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
emilmont	79:0c05e21ae27e	525
emilmont	79:0c05e21ae27e	526	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
emilmont	79:0c05e21ae27e	527	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
emilmont	79:0c05e21ae27e	528
emilmont	79:0c05e21ae27e	529	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
emilmont	79:0c05e21ae27e	530	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
emilmont	79:0c05e21ae27e	531
emilmont	79:0c05e21ae27e	532	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
emilmont	79:0c05e21ae27e	533	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
emilmont	79:0c05e21ae27e	534
emilmont	79:0c05e21ae27e	535	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
emilmont	79:0c05e21ae27e	536	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
emilmont	79:0c05e21ae27e	537
emilmont	79:0c05e21ae27e	538	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
emilmont	79:0c05e21ae27e	539	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
emilmont	79:0c05e21ae27e	540
emilmont	79:0c05e21ae27e	541	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
emilmont	79:0c05e21ae27e	542	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
emilmont	79:0c05e21ae27e	543
emilmont	79:0c05e21ae27e	544	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
emilmont	79:0c05e21ae27e	545	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
emilmont	79:0c05e21ae27e	546
emilmont	79:0c05e21ae27e	547	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
emilmont	79:0c05e21ae27e	548	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
emilmont	79:0c05e21ae27e	549
emilmont	79:0c05e21ae27e	550	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
emilmont	79:0c05e21ae27e	551	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
emilmont	79:0c05e21ae27e	552
emilmont	79:0c05e21ae27e	553	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
emilmont	79:0c05e21ae27e	554	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
emilmont	79:0c05e21ae27e	555
emilmont	79:0c05e21ae27e	556	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
emilmont	79:0c05e21ae27e	557	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
emilmont	79:0c05e21ae27e	558
emilmont	79:0c05e21ae27e	559	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
emilmont	79:0c05e21ae27e	560	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
emilmont	79:0c05e21ae27e	561
emilmont	79:0c05e21ae27e	562	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	110:165afa46840b	563	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
emilmont	79:0c05e21ae27e	564
emilmont	79:0c05e21ae27e	565	/* SCB Configurable Fault Status Registers Definitions */
emilmont	79:0c05e21ae27e	566	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
emilmont	79:0c05e21ae27e	567	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
emilmont	79:0c05e21ae27e	568
emilmont	79:0c05e21ae27e	569	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
emilmont	79:0c05e21ae27e	570	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
emilmont	79:0c05e21ae27e	571
emilmont	79:0c05e21ae27e	572	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	110:165afa46840b	573	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
emilmont	79:0c05e21ae27e	574
emilmont	79:0c05e21ae27e	575	/* SCB Hard Fault Status Registers Definitions */
emilmont	79:0c05e21ae27e	576	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
emilmont	79:0c05e21ae27e	577	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
emilmont	79:0c05e21ae27e	578
emilmont	79:0c05e21ae27e	579	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
emilmont	79:0c05e21ae27e	580	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
emilmont	79:0c05e21ae27e	581
emilmont	79:0c05e21ae27e	582	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
emilmont	79:0c05e21ae27e	583	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
emilmont	79:0c05e21ae27e	584
emilmont	79:0c05e21ae27e	585	/* SCB Debug Fault Status Register Definitions */
emilmont	79:0c05e21ae27e	586	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
emilmont	79:0c05e21ae27e	587	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
emilmont	79:0c05e21ae27e	588
emilmont	79:0c05e21ae27e	589	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
emilmont	79:0c05e21ae27e	590	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
emilmont	79:0c05e21ae27e	591
emilmont	79:0c05e21ae27e	592	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
emilmont	79:0c05e21ae27e	593	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
emilmont	79:0c05e21ae27e	594
emilmont	79:0c05e21ae27e	595	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
emilmont	79:0c05e21ae27e	596	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
emilmont	79:0c05e21ae27e	597
emilmont	79:0c05e21ae27e	598	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	110:165afa46840b	599	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
emilmont	79:0c05e21ae27e	600
emilmont	79:0c05e21ae27e	601	/@} end of group CMSIS_SCB /
emilmont	79:0c05e21ae27e	602
emilmont	79:0c05e21ae27e	603
emilmont	79:0c05e21ae27e	604	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	605	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont	79:0c05e21ae27e	606	\brief Type definitions for the System Control and ID Register not in the SCB
emilmont	79:0c05e21ae27e	607	@{
emilmont	79:0c05e21ae27e	608	*/
emilmont	79:0c05e21ae27e	609
emilmont	79:0c05e21ae27e	610	/** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont	79:0c05e21ae27e	611	*/
emilmont	79:0c05e21ae27e	612	typedef struct
emilmont	79:0c05e21ae27e	613	{
emilmont	79:0c05e21ae27e	614	uint32_t RESERVED0[1];
emilmont	79:0c05e21ae27e	615	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
emilmont	79:0c05e21ae27e	616	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
emilmont	79:0c05e21ae27e	617	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
emilmont	79:0c05e21ae27e	618	#else
emilmont	79:0c05e21ae27e	619	uint32_t RESERVED1[1];
emilmont	79:0c05e21ae27e	620	#endif
emilmont	79:0c05e21ae27e	621	} SCnSCB_Type;
emilmont	79:0c05e21ae27e	622
emilmont	79:0c05e21ae27e	623	/* Interrupt Controller Type Register Definitions */
emilmont	79:0c05e21ae27e	624	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	110:165afa46840b	625	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
emilmont	79:0c05e21ae27e	626
emilmont	79:0c05e21ae27e	627	/* Auxiliary Control Register Definitions */
emilmont	79:0c05e21ae27e	628
emilmont	79:0c05e21ae27e	629	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
emilmont	79:0c05e21ae27e	630	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
emilmont	79:0c05e21ae27e	631
emilmont	79:0c05e21ae27e	632	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
emilmont	79:0c05e21ae27e	633	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
emilmont	79:0c05e21ae27e	634
emilmont	79:0c05e21ae27e	635	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	110:165afa46840b	636	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
emilmont	79:0c05e21ae27e	637
emilmont	79:0c05e21ae27e	638	/@} end of group CMSIS_SCnotSCB /
emilmont	79:0c05e21ae27e	639
emilmont	79:0c05e21ae27e	640
emilmont	79:0c05e21ae27e	641	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	642	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont	79:0c05e21ae27e	643	\brief Type definitions for the System Timer Registers.
emilmont	79:0c05e21ae27e	644	@{
emilmont	79:0c05e21ae27e	645	*/
emilmont	79:0c05e21ae27e	646
emilmont	79:0c05e21ae27e	647	/** \brief Structure type to access the System Timer (SysTick).
emilmont	79:0c05e21ae27e	648	*/
emilmont	79:0c05e21ae27e	649	typedef struct
emilmont	79:0c05e21ae27e	650	{
emilmont	79:0c05e21ae27e	651	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
emilmont	79:0c05e21ae27e	652	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
emilmont	79:0c05e21ae27e	653	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
emilmont	79:0c05e21ae27e	654	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
emilmont	79:0c05e21ae27e	655	} SysTick_Type;
emilmont	79:0c05e21ae27e	656
emilmont	79:0c05e21ae27e	657	/* SysTick Control / Status Register Definitions */
emilmont	79:0c05e21ae27e	658	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
emilmont	79:0c05e21ae27e	659	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
emilmont	79:0c05e21ae27e	660
emilmont	79:0c05e21ae27e	661	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
emilmont	79:0c05e21ae27e	662	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
emilmont	79:0c05e21ae27e	663
emilmont	79:0c05e21ae27e	664	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
emilmont	79:0c05e21ae27e	665	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
emilmont	79:0c05e21ae27e	666
emilmont	79:0c05e21ae27e	667	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	110:165afa46840b	668	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
emilmont	79:0c05e21ae27e	669
emilmont	79:0c05e21ae27e	670	/* SysTick Reload Register Definitions */
emilmont	79:0c05e21ae27e	671	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	110:165afa46840b	672	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
emilmont	79:0c05e21ae27e	673
emilmont	79:0c05e21ae27e	674	/* SysTick Current Register Definitions */
emilmont	79:0c05e21ae27e	675	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	110:165afa46840b	676	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
emilmont	79:0c05e21ae27e	677
emilmont	79:0c05e21ae27e	678	/* SysTick Calibration Register Definitions */
emilmont	79:0c05e21ae27e	679	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
emilmont	79:0c05e21ae27e	680	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
emilmont	79:0c05e21ae27e	681
emilmont	79:0c05e21ae27e	682	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
emilmont	79:0c05e21ae27e	683	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
emilmont	79:0c05e21ae27e	684
emilmont	79:0c05e21ae27e	685	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	110:165afa46840b	686	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
emilmont	79:0c05e21ae27e	687
emilmont	79:0c05e21ae27e	688	/@} end of group CMSIS_SysTick /
emilmont	79:0c05e21ae27e	689
emilmont	79:0c05e21ae27e	690
emilmont	79:0c05e21ae27e	691	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	692	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont	79:0c05e21ae27e	693	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont	79:0c05e21ae27e	694	@{
emilmont	79:0c05e21ae27e	695	*/
emilmont	79:0c05e21ae27e	696
emilmont	79:0c05e21ae27e	697	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont	79:0c05e21ae27e	698	*/
emilmont	79:0c05e21ae27e	699	typedef struct
emilmont	79:0c05e21ae27e	700	{
emilmont	79:0c05e21ae27e	701	__O union
emilmont	79:0c05e21ae27e	702	{
emilmont	79:0c05e21ae27e	703	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
emilmont	79:0c05e21ae27e	704	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
emilmont	79:0c05e21ae27e	705	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
emilmont	79:0c05e21ae27e	706	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
emilmont	79:0c05e21ae27e	707	uint32_t RESERVED0[864];
emilmont	79:0c05e21ae27e	708	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
emilmont	79:0c05e21ae27e	709	uint32_t RESERVED1[15];
emilmont	79:0c05e21ae27e	710	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
emilmont	79:0c05e21ae27e	711	uint32_t RESERVED2[15];
emilmont	79:0c05e21ae27e	712	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
emilmont	79:0c05e21ae27e	713	uint32_t RESERVED3[29];
emilmont	79:0c05e21ae27e	714	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
emilmont	79:0c05e21ae27e	715	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
emilmont	79:0c05e21ae27e	716	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
emilmont	79:0c05e21ae27e	717	uint32_t RESERVED4[43];
emilmont	79:0c05e21ae27e	718	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
emilmont	79:0c05e21ae27e	719	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
emilmont	79:0c05e21ae27e	720	uint32_t RESERVED5[6];
emilmont	79:0c05e21ae27e	721	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
emilmont	79:0c05e21ae27e	722	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
emilmont	79:0c05e21ae27e	723	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
emilmont	79:0c05e21ae27e	724	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
emilmont	79:0c05e21ae27e	725	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
emilmont	79:0c05e21ae27e	726	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
emilmont	79:0c05e21ae27e	727	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
emilmont	79:0c05e21ae27e	728	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
emilmont	79:0c05e21ae27e	729	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
emilmont	79:0c05e21ae27e	730	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
emilmont	79:0c05e21ae27e	731	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
emilmont	79:0c05e21ae27e	732	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
emilmont	79:0c05e21ae27e	733	} ITM_Type;
emilmont	79:0c05e21ae27e	734
emilmont	79:0c05e21ae27e	735	/* ITM Trace Privilege Register Definitions */
emilmont	79:0c05e21ae27e	736	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	110:165afa46840b	737	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
emilmont	79:0c05e21ae27e	738
emilmont	79:0c05e21ae27e	739	/* ITM Trace Control Register Definitions */
emilmont	79:0c05e21ae27e	740	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
emilmont	79:0c05e21ae27e	741	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
emilmont	79:0c05e21ae27e	742
emilmont	79:0c05e21ae27e	743	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
emilmont	79:0c05e21ae27e	744	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
emilmont	79:0c05e21ae27e	745
emilmont	79:0c05e21ae27e	746	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
emilmont	79:0c05e21ae27e	747	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
emilmont	79:0c05e21ae27e	748
emilmont	79:0c05e21ae27e	749	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
emilmont	79:0c05e21ae27e	750	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
emilmont	79:0c05e21ae27e	751
emilmont	79:0c05e21ae27e	752	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
emilmont	79:0c05e21ae27e	753	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
emilmont	79:0c05e21ae27e	754
emilmont	79:0c05e21ae27e	755	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
emilmont	79:0c05e21ae27e	756	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
emilmont	79:0c05e21ae27e	757
emilmont	79:0c05e21ae27e	758	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
emilmont	79:0c05e21ae27e	759	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
emilmont	79:0c05e21ae27e	760
emilmont	79:0c05e21ae27e	761	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
emilmont	79:0c05e21ae27e	762	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
emilmont	79:0c05e21ae27e	763
emilmont	79:0c05e21ae27e	764	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	110:165afa46840b	765	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
emilmont	79:0c05e21ae27e	766
emilmont	79:0c05e21ae27e	767	/* ITM Integration Write Register Definitions */
emilmont	79:0c05e21ae27e	768	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	110:165afa46840b	769	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
emilmont	79:0c05e21ae27e	770
emilmont	79:0c05e21ae27e	771	/* ITM Integration Read Register Definitions */
emilmont	79:0c05e21ae27e	772	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	110:165afa46840b	773	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
emilmont	79:0c05e21ae27e	774
emilmont	79:0c05e21ae27e	775	/* ITM Integration Mode Control Register Definitions */
emilmont	79:0c05e21ae27e	776	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	110:165afa46840b	777	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
emilmont	79:0c05e21ae27e	778
emilmont	79:0c05e21ae27e	779	/* ITM Lock Status Register Definitions */
emilmont	79:0c05e21ae27e	780	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
emilmont	79:0c05e21ae27e	781	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
emilmont	79:0c05e21ae27e	782
emilmont	79:0c05e21ae27e	783	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
emilmont	79:0c05e21ae27e	784	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
emilmont	79:0c05e21ae27e	785
emilmont	79:0c05e21ae27e	786	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	110:165afa46840b	787	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
emilmont	79:0c05e21ae27e	788
emilmont	79:0c05e21ae27e	789	/@}/ /* end of group CMSIS_ITM */
emilmont	79:0c05e21ae27e	790
emilmont	79:0c05e21ae27e	791
emilmont	79:0c05e21ae27e	792	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	793	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont	79:0c05e21ae27e	794	\brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont	79:0c05e21ae27e	795	@{
emilmont	79:0c05e21ae27e	796	*/
emilmont	79:0c05e21ae27e	797
emilmont	79:0c05e21ae27e	798	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont	79:0c05e21ae27e	799	*/
emilmont	79:0c05e21ae27e	800	typedef struct
emilmont	79:0c05e21ae27e	801	{
emilmont	79:0c05e21ae27e	802	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
emilmont	79:0c05e21ae27e	803	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
emilmont	79:0c05e21ae27e	804	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
emilmont	79:0c05e21ae27e	805	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
emilmont	79:0c05e21ae27e	806	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
emilmont	79:0c05e21ae27e	807	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
emilmont	79:0c05e21ae27e	808	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
emilmont	79:0c05e21ae27e	809	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
emilmont	79:0c05e21ae27e	810	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
emilmont	79:0c05e21ae27e	811	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
emilmont	79:0c05e21ae27e	812	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
emilmont	79:0c05e21ae27e	813	uint32_t RESERVED0[1];
emilmont	79:0c05e21ae27e	814	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
emilmont	79:0c05e21ae27e	815	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
emilmont	79:0c05e21ae27e	816	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
emilmont	79:0c05e21ae27e	817	uint32_t RESERVED1[1];
emilmont	79:0c05e21ae27e	818	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
emilmont	79:0c05e21ae27e	819	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
emilmont	79:0c05e21ae27e	820	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
emilmont	79:0c05e21ae27e	821	uint32_t RESERVED2[1];
emilmont	79:0c05e21ae27e	822	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
emilmont	79:0c05e21ae27e	823	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
emilmont	79:0c05e21ae27e	824	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
emilmont	79:0c05e21ae27e	825	} DWT_Type;
emilmont	79:0c05e21ae27e	826
emilmont	79:0c05e21ae27e	827	/* DWT Control Register Definitions */
emilmont	79:0c05e21ae27e	828	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
emilmont	79:0c05e21ae27e	829	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
emilmont	79:0c05e21ae27e	830
emilmont	79:0c05e21ae27e	831	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
emilmont	79:0c05e21ae27e	832	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
emilmont	79:0c05e21ae27e	833
emilmont	79:0c05e21ae27e	834	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
emilmont	79:0c05e21ae27e	835	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
emilmont	79:0c05e21ae27e	836
emilmont	79:0c05e21ae27e	837	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
emilmont	79:0c05e21ae27e	838	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
emilmont	79:0c05e21ae27e	839
emilmont	79:0c05e21ae27e	840	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
emilmont	79:0c05e21ae27e	841	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
emilmont	79:0c05e21ae27e	842
emilmont	79:0c05e21ae27e	843	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
emilmont	79:0c05e21ae27e	844	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
emilmont	79:0c05e21ae27e	845
emilmont	79:0c05e21ae27e	846	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
emilmont	79:0c05e21ae27e	847	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
emilmont	79:0c05e21ae27e	848
emilmont	79:0c05e21ae27e	849	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
emilmont	79:0c05e21ae27e	850	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
emilmont	79:0c05e21ae27e	851
emilmont	79:0c05e21ae27e	852	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
emilmont	79:0c05e21ae27e	853	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
emilmont	79:0c05e21ae27e	854
emilmont	79:0c05e21ae27e	855	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
emilmont	79:0c05e21ae27e	856	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
emilmont	79:0c05e21ae27e	857
emilmont	79:0c05e21ae27e	858	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
emilmont	79:0c05e21ae27e	859	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
emilmont	79:0c05e21ae27e	860
emilmont	79:0c05e21ae27e	861	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
emilmont	79:0c05e21ae27e	862	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
emilmont	79:0c05e21ae27e	863
emilmont	79:0c05e21ae27e	864	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
emilmont	79:0c05e21ae27e	865	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
emilmont	79:0c05e21ae27e	866
emilmont	79:0c05e21ae27e	867	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
emilmont	79:0c05e21ae27e	868	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
emilmont	79:0c05e21ae27e	869
emilmont	79:0c05e21ae27e	870	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
emilmont	79:0c05e21ae27e	871	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
emilmont	79:0c05e21ae27e	872
emilmont	79:0c05e21ae27e	873	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
emilmont	79:0c05e21ae27e	874	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
emilmont	79:0c05e21ae27e	875
emilmont	79:0c05e21ae27e	876	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
emilmont	79:0c05e21ae27e	877	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
emilmont	79:0c05e21ae27e	878
emilmont	79:0c05e21ae27e	879	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	110:165afa46840b	880	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
emilmont	79:0c05e21ae27e	881
emilmont	79:0c05e21ae27e	882	/* DWT CPI Count Register Definitions */
emilmont	79:0c05e21ae27e	883	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	110:165afa46840b	884	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
emilmont	79:0c05e21ae27e	885
emilmont	79:0c05e21ae27e	886	/* DWT Exception Overhead Count Register Definitions */
emilmont	79:0c05e21ae27e	887	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	110:165afa46840b	888	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
emilmont	79:0c05e21ae27e	889
emilmont	79:0c05e21ae27e	890	/* DWT Sleep Count Register Definitions */
emilmont	79:0c05e21ae27e	891	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	110:165afa46840b	892	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
emilmont	79:0c05e21ae27e	893
emilmont	79:0c05e21ae27e	894	/* DWT LSU Count Register Definitions */
emilmont	79:0c05e21ae27e	895	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	110:165afa46840b	896	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
emilmont	79:0c05e21ae27e	897
emilmont	79:0c05e21ae27e	898	/* DWT Folded-instruction Count Register Definitions */
emilmont	79:0c05e21ae27e	899	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	110:165afa46840b	900	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
emilmont	79:0c05e21ae27e	901
emilmont	79:0c05e21ae27e	902	/* DWT Comparator Mask Register Definitions */
emilmont	79:0c05e21ae27e	903	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	110:165afa46840b	904	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
emilmont	79:0c05e21ae27e	905
emilmont	79:0c05e21ae27e	906	/* DWT Comparator Function Register Definitions */
emilmont	79:0c05e21ae27e	907	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
emilmont	79:0c05e21ae27e	908	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
emilmont	79:0c05e21ae27e	909
emilmont	79:0c05e21ae27e	910	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
emilmont	79:0c05e21ae27e	911	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
emilmont	79:0c05e21ae27e	912
emilmont	79:0c05e21ae27e	913	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
emilmont	79:0c05e21ae27e	914	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
emilmont	79:0c05e21ae27e	915
emilmont	79:0c05e21ae27e	916	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
emilmont	79:0c05e21ae27e	917	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
emilmont	79:0c05e21ae27e	918
emilmont	79:0c05e21ae27e	919	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
emilmont	79:0c05e21ae27e	920	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
emilmont	79:0c05e21ae27e	921
emilmont	79:0c05e21ae27e	922	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
emilmont	79:0c05e21ae27e	923	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
emilmont	79:0c05e21ae27e	924
emilmont	79:0c05e21ae27e	925	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
emilmont	79:0c05e21ae27e	926	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
emilmont	79:0c05e21ae27e	927
emilmont	79:0c05e21ae27e	928	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
emilmont	79:0c05e21ae27e	929	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
emilmont	79:0c05e21ae27e	930
emilmont	79:0c05e21ae27e	931	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	110:165afa46840b	932	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
emilmont	79:0c05e21ae27e	933
emilmont	79:0c05e21ae27e	934	/@}/ /* end of group CMSIS_DWT */
emilmont	79:0c05e21ae27e	935
emilmont	79:0c05e21ae27e	936
emilmont	79:0c05e21ae27e	937	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	938	\defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont	79:0c05e21ae27e	939	\brief Type definitions for the Trace Port Interface (TPI)
emilmont	79:0c05e21ae27e	940	@{
emilmont	79:0c05e21ae27e	941	*/
emilmont	79:0c05e21ae27e	942
emilmont	79:0c05e21ae27e	943	/** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont	79:0c05e21ae27e	944	*/
emilmont	79:0c05e21ae27e	945	typedef struct
emilmont	79:0c05e21ae27e	946	{
emilmont	79:0c05e21ae27e	947	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
emilmont	79:0c05e21ae27e	948	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
emilmont	79:0c05e21ae27e	949	uint32_t RESERVED0[2];
emilmont	79:0c05e21ae27e	950	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
emilmont	79:0c05e21ae27e	951	uint32_t RESERVED1[55];
emilmont	79:0c05e21ae27e	952	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
emilmont	79:0c05e21ae27e	953	uint32_t RESERVED2[131];
emilmont	79:0c05e21ae27e	954	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
emilmont	79:0c05e21ae27e	955	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
emilmont	79:0c05e21ae27e	956	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
emilmont	79:0c05e21ae27e	957	uint32_t RESERVED3[759];
emilmont	79:0c05e21ae27e	958	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
emilmont	79:0c05e21ae27e	959	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
emilmont	79:0c05e21ae27e	960	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
emilmont	79:0c05e21ae27e	961	uint32_t RESERVED4[1];
emilmont	79:0c05e21ae27e	962	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
emilmont	79:0c05e21ae27e	963	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
emilmont	79:0c05e21ae27e	964	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
emilmont	79:0c05e21ae27e	965	uint32_t RESERVED5[39];
emilmont	79:0c05e21ae27e	966	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
emilmont	79:0c05e21ae27e	967	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
emilmont	79:0c05e21ae27e	968	uint32_t RESERVED7[8];
emilmont	79:0c05e21ae27e	969	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
emilmont	79:0c05e21ae27e	970	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
emilmont	79:0c05e21ae27e	971	} TPI_Type;
emilmont	79:0c05e21ae27e	972
emilmont	79:0c05e21ae27e	973	/* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont	79:0c05e21ae27e	974	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	110:165afa46840b	975	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
emilmont	79:0c05e21ae27e	976
emilmont	79:0c05e21ae27e	977	/* TPI Selected Pin Protocol Register Definitions */
emilmont	79:0c05e21ae27e	978	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	110:165afa46840b	979	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
emilmont	79:0c05e21ae27e	980
emilmont	79:0c05e21ae27e	981	/* TPI Formatter and Flush Status Register Definitions */
emilmont	79:0c05e21ae27e	982	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
emilmont	79:0c05e21ae27e	983	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
emilmont	79:0c05e21ae27e	984
emilmont	79:0c05e21ae27e	985	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
emilmont	79:0c05e21ae27e	986	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
emilmont	79:0c05e21ae27e	987
emilmont	79:0c05e21ae27e	988	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
emilmont	79:0c05e21ae27e	989	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
emilmont	79:0c05e21ae27e	990
emilmont	79:0c05e21ae27e	991	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	110:165afa46840b	992	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
emilmont	79:0c05e21ae27e	993
emilmont	79:0c05e21ae27e	994	/* TPI Formatter and Flush Control Register Definitions */
emilmont	79:0c05e21ae27e	995	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
emilmont	79:0c05e21ae27e	996	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
emilmont	79:0c05e21ae27e	997
emilmont	79:0c05e21ae27e	998	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
emilmont	79:0c05e21ae27e	999	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
emilmont	79:0c05e21ae27e	1000
emilmont	79:0c05e21ae27e	1001	/* TPI TRIGGER Register Definitions */
emilmont	79:0c05e21ae27e	1002	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	110:165afa46840b	1003	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
emilmont	79:0c05e21ae27e	1004
emilmont	79:0c05e21ae27e	1005	/* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont	79:0c05e21ae27e	1006	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
emilmont	79:0c05e21ae27e	1007	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1008
emilmont	79:0c05e21ae27e	1009	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
emilmont	79:0c05e21ae27e	1010	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
emilmont	79:0c05e21ae27e	1011
emilmont	79:0c05e21ae27e	1012	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
emilmont	79:0c05e21ae27e	1013	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1014
emilmont	79:0c05e21ae27e	1015	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
emilmont	79:0c05e21ae27e	1016	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
emilmont	79:0c05e21ae27e	1017
emilmont	79:0c05e21ae27e	1018	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
emilmont	79:0c05e21ae27e	1019	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
emilmont	79:0c05e21ae27e	1020
emilmont	79:0c05e21ae27e	1021	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
emilmont	79:0c05e21ae27e	1022	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
emilmont	79:0c05e21ae27e	1023
emilmont	79:0c05e21ae27e	1024	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	110:165afa46840b	1025	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
emilmont	79:0c05e21ae27e	1026
emilmont	79:0c05e21ae27e	1027	/* TPI ITATBCTR2 Register Definitions */
emilmont	79:0c05e21ae27e	1028	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	110:165afa46840b	1029	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
emilmont	79:0c05e21ae27e	1030
emilmont	79:0c05e21ae27e	1031	/* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont	79:0c05e21ae27e	1032	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
emilmont	79:0c05e21ae27e	1033	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1034
emilmont	79:0c05e21ae27e	1035	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
emilmont	79:0c05e21ae27e	1036	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
emilmont	79:0c05e21ae27e	1037
emilmont	79:0c05e21ae27e	1038	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
emilmont	79:0c05e21ae27e	1039	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1040
emilmont	79:0c05e21ae27e	1041	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
emilmont	79:0c05e21ae27e	1042	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
emilmont	79:0c05e21ae27e	1043
emilmont	79:0c05e21ae27e	1044	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
emilmont	79:0c05e21ae27e	1045	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
emilmont	79:0c05e21ae27e	1046
emilmont	79:0c05e21ae27e	1047	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
emilmont	79:0c05e21ae27e	1048	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
emilmont	79:0c05e21ae27e	1049
emilmont	79:0c05e21ae27e	1050	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	110:165afa46840b	1051	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
emilmont	79:0c05e21ae27e	1052
emilmont	79:0c05e21ae27e	1053	/* TPI ITATBCTR0 Register Definitions */
emilmont	79:0c05e21ae27e	1054	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	110:165afa46840b	1055	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
emilmont	79:0c05e21ae27e	1056
emilmont	79:0c05e21ae27e	1057	/* TPI Integration Mode Control Register Definitions */
emilmont	79:0c05e21ae27e	1058	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	110:165afa46840b	1059	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
emilmont	79:0c05e21ae27e	1060
emilmont	79:0c05e21ae27e	1061	/* TPI DEVID Register Definitions */
emilmont	79:0c05e21ae27e	1062	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
emilmont	79:0c05e21ae27e	1063	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
emilmont	79:0c05e21ae27e	1064
emilmont	79:0c05e21ae27e	1065	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
emilmont	79:0c05e21ae27e	1066	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
emilmont	79:0c05e21ae27e	1067
emilmont	79:0c05e21ae27e	1068	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
emilmont	79:0c05e21ae27e	1069	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
emilmont	79:0c05e21ae27e	1070
emilmont	79:0c05e21ae27e	1071	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
emilmont	79:0c05e21ae27e	1072	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
emilmont	79:0c05e21ae27e	1073
emilmont	79:0c05e21ae27e	1074	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
emilmont	79:0c05e21ae27e	1075	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
emilmont	79:0c05e21ae27e	1076
emilmont	79:0c05e21ae27e	1077	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	110:165afa46840b	1078	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
emilmont	79:0c05e21ae27e	1079
emilmont	79:0c05e21ae27e	1080	/* TPI DEVTYPE Register Definitions */
emilmont	79:0c05e21ae27e	1081	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
emilmont	79:0c05e21ae27e	1082	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
emilmont	79:0c05e21ae27e	1083
Kojto	110:165afa46840b	1084	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	110:165afa46840b	1085	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	110:165afa46840b	1086
emilmont	79:0c05e21ae27e	1087	/@}/ /* end of group CMSIS_TPI */
emilmont	79:0c05e21ae27e	1088
emilmont	79:0c05e21ae27e	1089
emilmont	79:0c05e21ae27e	1090	#if (__MPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	1091	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1092	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont	79:0c05e21ae27e	1093	\brief Type definitions for the Memory Protection Unit (MPU)
emilmont	79:0c05e21ae27e	1094	@{
emilmont	79:0c05e21ae27e	1095	*/
emilmont	79:0c05e21ae27e	1096
emilmont	79:0c05e21ae27e	1097	/** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont	79:0c05e21ae27e	1098	*/
emilmont	79:0c05e21ae27e	1099	typedef struct
emilmont	79:0c05e21ae27e	1100	{
emilmont	79:0c05e21ae27e	1101	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
emilmont	79:0c05e21ae27e	1102	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
emilmont	79:0c05e21ae27e	1103	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
emilmont	79:0c05e21ae27e	1104	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
emilmont	79:0c05e21ae27e	1105	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1106	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
emilmont	79:0c05e21ae27e	1107	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1108	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
emilmont	79:0c05e21ae27e	1109	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1110	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
emilmont	79:0c05e21ae27e	1111	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1112	} MPU_Type;
emilmont	79:0c05e21ae27e	1113
emilmont	79:0c05e21ae27e	1114	/* MPU Type Register */
emilmont	79:0c05e21ae27e	1115	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
emilmont	79:0c05e21ae27e	1116	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
emilmont	79:0c05e21ae27e	1117
emilmont	79:0c05e21ae27e	1118	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
emilmont	79:0c05e21ae27e	1119	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
emilmont	79:0c05e21ae27e	1120
emilmont	79:0c05e21ae27e	1121	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	110:165afa46840b	1122	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
emilmont	79:0c05e21ae27e	1123
emilmont	79:0c05e21ae27e	1124	/* MPU Control Register */
emilmont	79:0c05e21ae27e	1125	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
emilmont	79:0c05e21ae27e	1126	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
emilmont	79:0c05e21ae27e	1127
emilmont	79:0c05e21ae27e	1128	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
emilmont	79:0c05e21ae27e	1129	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
emilmont	79:0c05e21ae27e	1130
emilmont	79:0c05e21ae27e	1131	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	110:165afa46840b	1132	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
emilmont	79:0c05e21ae27e	1133
emilmont	79:0c05e21ae27e	1134	/* MPU Region Number Register */
emilmont	79:0c05e21ae27e	1135	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	110:165afa46840b	1136	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
emilmont	79:0c05e21ae27e	1137
emilmont	79:0c05e21ae27e	1138	/* MPU Region Base Address Register */
emilmont	79:0c05e21ae27e	1139	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
emilmont	79:0c05e21ae27e	1140	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
emilmont	79:0c05e21ae27e	1141
emilmont	79:0c05e21ae27e	1142	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
emilmont	79:0c05e21ae27e	1143	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
emilmont	79:0c05e21ae27e	1144
emilmont	79:0c05e21ae27e	1145	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	110:165afa46840b	1146	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
emilmont	79:0c05e21ae27e	1147
emilmont	79:0c05e21ae27e	1148	/* MPU Region Attribute and Size Register */
emilmont	79:0c05e21ae27e	1149	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
emilmont	79:0c05e21ae27e	1150	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
emilmont	79:0c05e21ae27e	1151
emilmont	79:0c05e21ae27e	1152	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
emilmont	79:0c05e21ae27e	1153	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
emilmont	79:0c05e21ae27e	1154
emilmont	79:0c05e21ae27e	1155	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
emilmont	79:0c05e21ae27e	1156	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
emilmont	79:0c05e21ae27e	1157
emilmont	79:0c05e21ae27e	1158	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
emilmont	79:0c05e21ae27e	1159	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
emilmont	79:0c05e21ae27e	1160
emilmont	79:0c05e21ae27e	1161	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
emilmont	79:0c05e21ae27e	1162	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
emilmont	79:0c05e21ae27e	1163
emilmont	79:0c05e21ae27e	1164	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
emilmont	79:0c05e21ae27e	1165	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
emilmont	79:0c05e21ae27e	1166
emilmont	79:0c05e21ae27e	1167	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
emilmont	79:0c05e21ae27e	1168	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
emilmont	79:0c05e21ae27e	1169
emilmont	79:0c05e21ae27e	1170	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
emilmont	79:0c05e21ae27e	1171	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
emilmont	79:0c05e21ae27e	1172
emilmont	79:0c05e21ae27e	1173	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
emilmont	79:0c05e21ae27e	1174	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
emilmont	79:0c05e21ae27e	1175
emilmont	79:0c05e21ae27e	1176	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	110:165afa46840b	1177	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
emilmont	79:0c05e21ae27e	1178
emilmont	79:0c05e21ae27e	1179	/@} end of group CMSIS_MPU /
emilmont	79:0c05e21ae27e	1180	#endif
emilmont	79:0c05e21ae27e	1181
emilmont	79:0c05e21ae27e	1182
emilmont	79:0c05e21ae27e	1183	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1184	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont	79:0c05e21ae27e	1185	\brief Type definitions for the Core Debug Registers
emilmont	79:0c05e21ae27e	1186	@{
emilmont	79:0c05e21ae27e	1187	*/
emilmont	79:0c05e21ae27e	1188
emilmont	79:0c05e21ae27e	1189	/** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont	79:0c05e21ae27e	1190	*/
emilmont	79:0c05e21ae27e	1191	typedef struct
emilmont	79:0c05e21ae27e	1192	{
emilmont	79:0c05e21ae27e	1193	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
emilmont	79:0c05e21ae27e	1194	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
emilmont	79:0c05e21ae27e	1195	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
emilmont	79:0c05e21ae27e	1196	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
emilmont	79:0c05e21ae27e	1197	} CoreDebug_Type;
emilmont	79:0c05e21ae27e	1198
emilmont	79:0c05e21ae27e	1199	/* Debug Halting Control and Status Register */
emilmont	79:0c05e21ae27e	1200	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
emilmont	79:0c05e21ae27e	1201	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
emilmont	79:0c05e21ae27e	1202
emilmont	79:0c05e21ae27e	1203	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
emilmont	79:0c05e21ae27e	1204	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
emilmont	79:0c05e21ae27e	1205
emilmont	79:0c05e21ae27e	1206	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
emilmont	79:0c05e21ae27e	1207	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
emilmont	79:0c05e21ae27e	1208
emilmont	79:0c05e21ae27e	1209	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
emilmont	79:0c05e21ae27e	1210	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
emilmont	79:0c05e21ae27e	1211
emilmont	79:0c05e21ae27e	1212	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
emilmont	79:0c05e21ae27e	1213	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
emilmont	79:0c05e21ae27e	1214
emilmont	79:0c05e21ae27e	1215	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
emilmont	79:0c05e21ae27e	1216	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
emilmont	79:0c05e21ae27e	1217
emilmont	79:0c05e21ae27e	1218	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
emilmont	79:0c05e21ae27e	1219	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
emilmont	79:0c05e21ae27e	1220
emilmont	79:0c05e21ae27e	1221	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
emilmont	79:0c05e21ae27e	1222	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
emilmont	79:0c05e21ae27e	1223
emilmont	79:0c05e21ae27e	1224	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
emilmont	79:0c05e21ae27e	1225	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
emilmont	79:0c05e21ae27e	1226
emilmont	79:0c05e21ae27e	1227	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
emilmont	79:0c05e21ae27e	1228	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
emilmont	79:0c05e21ae27e	1229
emilmont	79:0c05e21ae27e	1230	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
emilmont	79:0c05e21ae27e	1231	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
emilmont	79:0c05e21ae27e	1232
emilmont	79:0c05e21ae27e	1233	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	110:165afa46840b	1234	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
emilmont	79:0c05e21ae27e	1235
emilmont	79:0c05e21ae27e	1236	/* Debug Core Register Selector Register */
emilmont	79:0c05e21ae27e	1237	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
emilmont	79:0c05e21ae27e	1238	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
emilmont	79:0c05e21ae27e	1239
emilmont	79:0c05e21ae27e	1240	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	110:165afa46840b	1241	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
emilmont	79:0c05e21ae27e	1242
emilmont	79:0c05e21ae27e	1243	/* Debug Exception and Monitor Control Register */
emilmont	79:0c05e21ae27e	1244	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
emilmont	79:0c05e21ae27e	1245	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
emilmont	79:0c05e21ae27e	1246
emilmont	79:0c05e21ae27e	1247	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
emilmont	79:0c05e21ae27e	1248	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
emilmont	79:0c05e21ae27e	1249
emilmont	79:0c05e21ae27e	1250	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
emilmont	79:0c05e21ae27e	1251	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
emilmont	79:0c05e21ae27e	1252
emilmont	79:0c05e21ae27e	1253	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
emilmont	79:0c05e21ae27e	1254	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
emilmont	79:0c05e21ae27e	1255
emilmont	79:0c05e21ae27e	1256	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
emilmont	79:0c05e21ae27e	1257	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
emilmont	79:0c05e21ae27e	1258
emilmont	79:0c05e21ae27e	1259	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
emilmont	79:0c05e21ae27e	1260	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
emilmont	79:0c05e21ae27e	1261
emilmont	79:0c05e21ae27e	1262	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
emilmont	79:0c05e21ae27e	1263	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
emilmont	79:0c05e21ae27e	1264
emilmont	79:0c05e21ae27e	1265	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
emilmont	79:0c05e21ae27e	1266	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
emilmont	79:0c05e21ae27e	1267
emilmont	79:0c05e21ae27e	1268	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
emilmont	79:0c05e21ae27e	1269	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
emilmont	79:0c05e21ae27e	1270
emilmont	79:0c05e21ae27e	1271	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
emilmont	79:0c05e21ae27e	1272	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
emilmont	79:0c05e21ae27e	1273
emilmont	79:0c05e21ae27e	1274	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
emilmont	79:0c05e21ae27e	1275	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
emilmont	79:0c05e21ae27e	1276
emilmont	79:0c05e21ae27e	1277	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
emilmont	79:0c05e21ae27e	1278	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
emilmont	79:0c05e21ae27e	1279
emilmont	79:0c05e21ae27e	1280	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	110:165afa46840b	1281	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
emilmont	79:0c05e21ae27e	1282
emilmont	79:0c05e21ae27e	1283	/@} end of group CMSIS_CoreDebug /
emilmont	79:0c05e21ae27e	1284
emilmont	79:0c05e21ae27e	1285
emilmont	79:0c05e21ae27e	1286	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1287	\defgroup CMSIS_core_base Core Definitions
emilmont	79:0c05e21ae27e	1288	\brief Definitions for base addresses, unions, and structures.
emilmont	79:0c05e21ae27e	1289	@{
emilmont	79:0c05e21ae27e	1290	*/
emilmont	79:0c05e21ae27e	1291
emilmont	79:0c05e21ae27e	1292	/* Memory mapping of Cortex-M3 Hardware */
emilmont	79:0c05e21ae27e	1293	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
emilmont	79:0c05e21ae27e	1294	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
emilmont	79:0c05e21ae27e	1295	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
emilmont	79:0c05e21ae27e	1296	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
emilmont	79:0c05e21ae27e	1297	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
emilmont	79:0c05e21ae27e	1298	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
emilmont	79:0c05e21ae27e	1299	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
emilmont	79:0c05e21ae27e	1300	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
emilmont	79:0c05e21ae27e	1301
emilmont	79:0c05e21ae27e	1302	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
emilmont	79:0c05e21ae27e	1303	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
emilmont	79:0c05e21ae27e	1304	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
emilmont	79:0c05e21ae27e	1305	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
emilmont	79:0c05e21ae27e	1306	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
emilmont	79:0c05e21ae27e	1307	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
emilmont	79:0c05e21ae27e	1308	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
emilmont	79:0c05e21ae27e	1309	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
emilmont	79:0c05e21ae27e	1310
emilmont	79:0c05e21ae27e	1311	#if (__MPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	1312	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
emilmont	79:0c05e21ae27e	1313	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
emilmont	79:0c05e21ae27e	1314	#endif
emilmont	79:0c05e21ae27e	1315
emilmont	79:0c05e21ae27e	1316	/@} /
emilmont	79:0c05e21ae27e	1317
emilmont	79:0c05e21ae27e	1318
emilmont	79:0c05e21ae27e	1319
emilmont	79:0c05e21ae27e	1320	/*******************************************************************************
emilmont	79:0c05e21ae27e	1321	* Hardware Abstraction Layer
emilmont	79:0c05e21ae27e	1322	Core Function Interface contains:
emilmont	79:0c05e21ae27e	1323	- Core NVIC Functions
emilmont	79:0c05e21ae27e	1324	- Core SysTick Functions
emilmont	79:0c05e21ae27e	1325	- Core Debug Functions
emilmont	79:0c05e21ae27e	1326	- Core Register Access Functions
emilmont	79:0c05e21ae27e	1327	******************************************************************************/
emilmont	79:0c05e21ae27e	1328	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont	79:0c05e21ae27e	1329	*/
emilmont	79:0c05e21ae27e	1330
emilmont	79:0c05e21ae27e	1331
emilmont	79:0c05e21ae27e	1332
emilmont	79:0c05e21ae27e	1333	/* ########################## NVIC functions #################################### */
emilmont	79:0c05e21ae27e	1334	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	79:0c05e21ae27e	1335	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont	79:0c05e21ae27e	1336	\brief Functions that manage interrupts and exceptions via the NVIC.
emilmont	79:0c05e21ae27e	1337	@{
emilmont	79:0c05e21ae27e	1338	*/
emilmont	79:0c05e21ae27e	1339
emilmont	79:0c05e21ae27e	1340	/** \brief Set Priority Grouping
emilmont	79:0c05e21ae27e	1341
emilmont	79:0c05e21ae27e	1342	The function sets the priority grouping field using the required unlock sequence.
emilmont	79:0c05e21ae27e	1343	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont	79:0c05e21ae27e	1344	Only values from 0..7 are used.
emilmont	79:0c05e21ae27e	1345	In case of a conflict between priority grouping and available
emilmont	79:0c05e21ae27e	1346	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont	79:0c05e21ae27e	1347
emilmont	79:0c05e21ae27e	1348	\param [in] PriorityGroup Priority grouping field.
emilmont	79:0c05e21ae27e	1349	*/
emilmont	79:0c05e21ae27e	1350	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont	79:0c05e21ae27e	1351	{
emilmont	79:0c05e21ae27e	1352	uint32_t reg_value;
Kojto	110:165afa46840b	1353	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont	79:0c05e21ae27e	1354
emilmont	79:0c05e21ae27e	1355	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	110:165afa46840b	1356	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	110:165afa46840b	1357	reg_value = (reg_value \|
Kojto	110:165afa46840b	1358	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	110:165afa46840b	1359	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
emilmont	79:0c05e21ae27e	1360	SCB->AIRCR = reg_value;
emilmont	79:0c05e21ae27e	1361	}
emilmont	79:0c05e21ae27e	1362
emilmont	79:0c05e21ae27e	1363
emilmont	79:0c05e21ae27e	1364	/** \brief Get Priority Grouping
emilmont	79:0c05e21ae27e	1365
emilmont	79:0c05e21ae27e	1366	The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont	79:0c05e21ae27e	1367
emilmont	79:0c05e21ae27e	1368	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont	79:0c05e21ae27e	1369	*/
emilmont	79:0c05e21ae27e	1370	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
emilmont	79:0c05e21ae27e	1371	{
Kojto	110:165afa46840b	1372	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
emilmont	79:0c05e21ae27e	1373	}
emilmont	79:0c05e21ae27e	1374
emilmont	79:0c05e21ae27e	1375
emilmont	79:0c05e21ae27e	1376	/** \brief Enable External Interrupt
emilmont	79:0c05e21ae27e	1377
emilmont	79:0c05e21ae27e	1378	The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont	79:0c05e21ae27e	1379
emilmont	79:0c05e21ae27e	1380	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1381	*/
emilmont	79:0c05e21ae27e	1382	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1383	{
Kojto	110:165afa46840b	1384	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont	79:0c05e21ae27e	1385	}
emilmont	79:0c05e21ae27e	1386
emilmont	79:0c05e21ae27e	1387
emilmont	79:0c05e21ae27e	1388	/** \brief Disable External Interrupt
emilmont	79:0c05e21ae27e	1389
emilmont	79:0c05e21ae27e	1390	The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont	79:0c05e21ae27e	1391
emilmont	79:0c05e21ae27e	1392	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1393	*/
emilmont	79:0c05e21ae27e	1394	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1395	{
Kojto	110:165afa46840b	1396	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont	79:0c05e21ae27e	1397	}
emilmont	79:0c05e21ae27e	1398
emilmont	79:0c05e21ae27e	1399
emilmont	79:0c05e21ae27e	1400	/** \brief Get Pending Interrupt
emilmont	79:0c05e21ae27e	1401
emilmont	79:0c05e21ae27e	1402	The function reads the pending register in the NVIC and returns the pending bit
emilmont	79:0c05e21ae27e	1403	for the specified interrupt.
emilmont	79:0c05e21ae27e	1404
emilmont	79:0c05e21ae27e	1405	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1406
emilmont	79:0c05e21ae27e	1407	\return 0 Interrupt status is not pending.
emilmont	79:0c05e21ae27e	1408	\return 1 Interrupt status is pending.
emilmont	79:0c05e21ae27e	1409	*/
emilmont	79:0c05e21ae27e	1410	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1411	{
Kojto	110:165afa46840b	1412	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont	79:0c05e21ae27e	1413	}
emilmont	79:0c05e21ae27e	1414
emilmont	79:0c05e21ae27e	1415
emilmont	79:0c05e21ae27e	1416	/** \brief Set Pending Interrupt
emilmont	79:0c05e21ae27e	1417
emilmont	79:0c05e21ae27e	1418	The function sets the pending bit of an external interrupt.
emilmont	79:0c05e21ae27e	1419
emilmont	79:0c05e21ae27e	1420	\param [in] IRQn Interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1421	*/
emilmont	79:0c05e21ae27e	1422	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1423	{
Kojto	110:165afa46840b	1424	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont	79:0c05e21ae27e	1425	}
emilmont	79:0c05e21ae27e	1426
emilmont	79:0c05e21ae27e	1427
emilmont	79:0c05e21ae27e	1428	/** \brief Clear Pending Interrupt
emilmont	79:0c05e21ae27e	1429
emilmont	79:0c05e21ae27e	1430	The function clears the pending bit of an external interrupt.
emilmont	79:0c05e21ae27e	1431
emilmont	79:0c05e21ae27e	1432	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1433	*/
emilmont	79:0c05e21ae27e	1434	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1435	{
Kojto	110:165afa46840b	1436	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont	79:0c05e21ae27e	1437	}
emilmont	79:0c05e21ae27e	1438
emilmont	79:0c05e21ae27e	1439
emilmont	79:0c05e21ae27e	1440	/** \brief Get Active Interrupt
emilmont	79:0c05e21ae27e	1441
emilmont	79:0c05e21ae27e	1442	The function reads the active register in NVIC and returns the active bit.
emilmont	79:0c05e21ae27e	1443
emilmont	79:0c05e21ae27e	1444	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1445
emilmont	79:0c05e21ae27e	1446	\return 0 Interrupt status is not active.
emilmont	79:0c05e21ae27e	1447	\return 1 Interrupt status is active.
emilmont	79:0c05e21ae27e	1448	*/
emilmont	79:0c05e21ae27e	1449	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1450	{
Kojto	110:165afa46840b	1451	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont	79:0c05e21ae27e	1452	}
emilmont	79:0c05e21ae27e	1453
emilmont	79:0c05e21ae27e	1454
emilmont	79:0c05e21ae27e	1455	/** \brief Set Interrupt Priority
emilmont	79:0c05e21ae27e	1456
emilmont	79:0c05e21ae27e	1457	The function sets the priority of an interrupt.
emilmont	79:0c05e21ae27e	1458
emilmont	79:0c05e21ae27e	1459	\note The priority cannot be set for every core interrupt.
emilmont	79:0c05e21ae27e	1460
emilmont	79:0c05e21ae27e	1461	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1462	\param [in] priority Priority to set.
emilmont	79:0c05e21ae27e	1463	*/
emilmont	79:0c05e21ae27e	1464	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont	79:0c05e21ae27e	1465	{
Kojto	110:165afa46840b	1466	if((int32_t)IRQn < 0) {
Kojto	110:165afa46840b	1467	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	110:165afa46840b	1468	}
emilmont	79:0c05e21ae27e	1469	else {
Kojto	110:165afa46840b	1470	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	110:165afa46840b	1471	}
emilmont	79:0c05e21ae27e	1472	}
emilmont	79:0c05e21ae27e	1473
emilmont	79:0c05e21ae27e	1474
emilmont	79:0c05e21ae27e	1475	/** \brief Get Interrupt Priority
emilmont	79:0c05e21ae27e	1476
emilmont	79:0c05e21ae27e	1477	The function reads the priority of an interrupt. The interrupt
emilmont	79:0c05e21ae27e	1478	number can be positive to specify an external (device specific)
emilmont	79:0c05e21ae27e	1479	interrupt, or negative to specify an internal (core) interrupt.
emilmont	79:0c05e21ae27e	1480
emilmont	79:0c05e21ae27e	1481
emilmont	79:0c05e21ae27e	1482	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1483	\return Interrupt Priority. Value is aligned automatically to the implemented
emilmont	79:0c05e21ae27e	1484	priority bits of the microcontroller.
emilmont	79:0c05e21ae27e	1485	*/
emilmont	79:0c05e21ae27e	1486	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1487	{
emilmont	79:0c05e21ae27e	1488
Kojto	110:165afa46840b	1489	if((int32_t)IRQn < 0) {
Kojto	110:165afa46840b	1490	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto	110:165afa46840b	1491	}
emilmont	79:0c05e21ae27e	1492	else {
Kojto	110:165afa46840b	1493	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto	110:165afa46840b	1494	}
emilmont	79:0c05e21ae27e	1495	}
emilmont	79:0c05e21ae27e	1496
emilmont	79:0c05e21ae27e	1497
emilmont	79:0c05e21ae27e	1498	/** \brief Encode Priority
emilmont	79:0c05e21ae27e	1499
emilmont	79:0c05e21ae27e	1500	The function encodes the priority for an interrupt with the given priority group,
emilmont	79:0c05e21ae27e	1501	preemptive priority value, and subpriority value.
emilmont	79:0c05e21ae27e	1502	In case of a conflict between priority grouping and available
Kojto	110:165afa46840b	1503	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont	79:0c05e21ae27e	1504
emilmont	79:0c05e21ae27e	1505	\param [in] PriorityGroup Used priority group.
emilmont	79:0c05e21ae27e	1506	\param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont	79:0c05e21ae27e	1507	\param [in] SubPriority Subpriority value (starting from 0).
emilmont	79:0c05e21ae27e	1508	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont	79:0c05e21ae27e	1509	*/
emilmont	79:0c05e21ae27e	1510	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont	79:0c05e21ae27e	1511	{
Kojto	110:165afa46840b	1512	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont	79:0c05e21ae27e	1513	uint32_t PreemptPriorityBits;
emilmont	79:0c05e21ae27e	1514	uint32_t SubPriorityBits;
emilmont	79:0c05e21ae27e	1515
Kojto	110:165afa46840b	1516	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	110:165afa46840b	1517	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont	79:0c05e21ae27e	1518
emilmont	79:0c05e21ae27e	1519	return (
Kojto	110:165afa46840b	1520	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	110:165afa46840b	1521	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
emilmont	79:0c05e21ae27e	1522	);
emilmont	79:0c05e21ae27e	1523	}
emilmont	79:0c05e21ae27e	1524
emilmont	79:0c05e21ae27e	1525
emilmont	79:0c05e21ae27e	1526	/** \brief Decode Priority
emilmont	79:0c05e21ae27e	1527
emilmont	79:0c05e21ae27e	1528	The function decodes an interrupt priority value with a given priority group to
emilmont	79:0c05e21ae27e	1529	preemptive priority value and subpriority value.
emilmont	79:0c05e21ae27e	1530	In case of a conflict between priority grouping and available
Kojto	110:165afa46840b	1531	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
emilmont	79:0c05e21ae27e	1532
emilmont	79:0c05e21ae27e	1533	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont	79:0c05e21ae27e	1534	\param [in] PriorityGroup Used priority group.
emilmont	79:0c05e21ae27e	1535	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont	79:0c05e21ae27e	1536	\param [out] pSubPriority Subpriority value (starting from 0).
emilmont	79:0c05e21ae27e	1537	*/
emilmont	79:0c05e21ae27e	1538	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont	79:0c05e21ae27e	1539	{
Kojto	110:165afa46840b	1540	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont	79:0c05e21ae27e	1541	uint32_t PreemptPriorityBits;
emilmont	79:0c05e21ae27e	1542	uint32_t SubPriorityBits;
emilmont	79:0c05e21ae27e	1543
Kojto	110:165afa46840b	1544	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	110:165afa46840b	1545	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont	79:0c05e21ae27e	1546
Kojto	110:165afa46840b	1547	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	110:165afa46840b	1548	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
emilmont	79:0c05e21ae27e	1549	}
emilmont	79:0c05e21ae27e	1550
emilmont	79:0c05e21ae27e	1551
emilmont	79:0c05e21ae27e	1552	/** \brief System Reset
emilmont	79:0c05e21ae27e	1553
emilmont	79:0c05e21ae27e	1554	The function initiates a system reset request to reset the MCU.
emilmont	79:0c05e21ae27e	1555	*/
emilmont	79:0c05e21ae27e	1556	__STATIC_INLINE void NVIC_SystemReset(void)
emilmont	79:0c05e21ae27e	1557	{
Kojto	110:165afa46840b	1558	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	110:165afa46840b	1559	buffered write are completed before reset */
Kojto	110:165afa46840b	1560	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	110:165afa46840b	1561	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	110:165afa46840b	1562	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	110:165afa46840b	1563	__DSB(); /* Ensure completion of memory access */
Kojto	110:165afa46840b	1564	while(1) { __NOP(); } /* wait until reset */
emilmont	79:0c05e21ae27e	1565	}
emilmont	79:0c05e21ae27e	1566
emilmont	79:0c05e21ae27e	1567	/@} end of CMSIS_Core_NVICFunctions /
emilmont	79:0c05e21ae27e	1568
emilmont	79:0c05e21ae27e	1569
emilmont	79:0c05e21ae27e	1570
emilmont	79:0c05e21ae27e	1571	/* ################################## SysTick function ############################################ */
emilmont	79:0c05e21ae27e	1572	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	79:0c05e21ae27e	1573	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont	79:0c05e21ae27e	1574	\brief Functions that configure the System.
emilmont	79:0c05e21ae27e	1575	@{
emilmont	79:0c05e21ae27e	1576	*/
emilmont	79:0c05e21ae27e	1577
emilmont	79:0c05e21ae27e	1578	#if (__Vendor_SysTickConfig == 0)
emilmont	79:0c05e21ae27e	1579
emilmont	79:0c05e21ae27e	1580	/** \brief System Tick Configuration
emilmont	79:0c05e21ae27e	1581
emilmont	79:0c05e21ae27e	1582	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont	79:0c05e21ae27e	1583	Counter is in free running mode to generate periodic interrupts.
emilmont	79:0c05e21ae27e	1584
emilmont	79:0c05e21ae27e	1585	\param [in] ticks Number of ticks between two interrupts.
emilmont	79:0c05e21ae27e	1586
emilmont	79:0c05e21ae27e	1587	\return 0 Function succeeded.
emilmont	79:0c05e21ae27e	1588	\return 1 Function failed.
emilmont	79:0c05e21ae27e	1589
emilmont	79:0c05e21ae27e	1590	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont	79:0c05e21ae27e	1591	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont	79:0c05e21ae27e	1592	must contain a vendor-specific implementation of this function.
emilmont	79:0c05e21ae27e	1593
emilmont	79:0c05e21ae27e	1594	*/
emilmont	79:0c05e21ae27e	1595	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont	79:0c05e21ae27e	1596	{
Kojto	110:165afa46840b	1597	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
emilmont	79:0c05e21ae27e	1598
Kojto	110:165afa46840b	1599	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	110:165afa46840b	1600	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	110:165afa46840b	1601	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont	79:0c05e21ae27e	1602	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
emilmont	79:0c05e21ae27e	1603	SysTick_CTRL_TICKINT_Msk \|
Kojto	110:165afa46840b	1604	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	110:165afa46840b	1605	return (0UL); /* Function successful */
emilmont	79:0c05e21ae27e	1606	}
emilmont	79:0c05e21ae27e	1607
emilmont	79:0c05e21ae27e	1608	#endif
emilmont	79:0c05e21ae27e	1609
emilmont	79:0c05e21ae27e	1610	/@} end of CMSIS_Core_SysTickFunctions /
emilmont	79:0c05e21ae27e	1611
emilmont	79:0c05e21ae27e	1612
emilmont	79:0c05e21ae27e	1613
emilmont	79:0c05e21ae27e	1614	/* ##################################### Debug In/Output function ########################################### */
emilmont	79:0c05e21ae27e	1615	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	79:0c05e21ae27e	1616	\defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont	79:0c05e21ae27e	1617	\brief Functions that access the ITM debug interface.
emilmont	79:0c05e21ae27e	1618	@{
emilmont	79:0c05e21ae27e	1619	*/
emilmont	79:0c05e21ae27e	1620
emilmont	79:0c05e21ae27e	1621	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
emilmont	79:0c05e21ae27e	1622	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
emilmont	79:0c05e21ae27e	1623
emilmont	79:0c05e21ae27e	1624
emilmont	79:0c05e21ae27e	1625	/** \brief ITM Send Character
emilmont	79:0c05e21ae27e	1626
emilmont	79:0c05e21ae27e	1627	The function transmits a character via the ITM channel 0, and
emilmont	79:0c05e21ae27e	1628	\li Just returns when no debugger is connected that has booked the output.
emilmont	79:0c05e21ae27e	1629	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont	79:0c05e21ae27e	1630
emilmont	79:0c05e21ae27e	1631	\param [in] ch Character to transmit.
emilmont	79:0c05e21ae27e	1632
emilmont	79:0c05e21ae27e	1633	\returns Character to transmit.
emilmont	79:0c05e21ae27e	1634	*/
emilmont	79:0c05e21ae27e	1635	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont	79:0c05e21ae27e	1636	{
Kojto	110:165afa46840b	1637	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	110:165afa46840b	1638	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
emilmont	79:0c05e21ae27e	1639	{
Kojto	110:165afa46840b	1640	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto	110:165afa46840b	1641	ITM->PORT[0].u8 = (uint8_t)ch;
emilmont	79:0c05e21ae27e	1642	}
emilmont	79:0c05e21ae27e	1643	return (ch);
emilmont	79:0c05e21ae27e	1644	}
emilmont	79:0c05e21ae27e	1645
emilmont	79:0c05e21ae27e	1646
emilmont	79:0c05e21ae27e	1647	/** \brief ITM Receive Character
emilmont	79:0c05e21ae27e	1648
emilmont	79:0c05e21ae27e	1649	The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont	79:0c05e21ae27e	1650
emilmont	79:0c05e21ae27e	1651	\return Received character.
emilmont	79:0c05e21ae27e	1652	\return -1 No character pending.
emilmont	79:0c05e21ae27e	1653	*/
emilmont	79:0c05e21ae27e	1654	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont	79:0c05e21ae27e	1655	int32_t ch = -1; /* no character available */
emilmont	79:0c05e21ae27e	1656
emilmont	79:0c05e21ae27e	1657	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont	79:0c05e21ae27e	1658	ch = ITM_RxBuffer;
emilmont	79:0c05e21ae27e	1659	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont	79:0c05e21ae27e	1660	}
emilmont	79:0c05e21ae27e	1661
emilmont	79:0c05e21ae27e	1662	return (ch);
emilmont	79:0c05e21ae27e	1663	}
emilmont	79:0c05e21ae27e	1664
emilmont	79:0c05e21ae27e	1665
emilmont	79:0c05e21ae27e	1666	/** \brief ITM Check Character
emilmont	79:0c05e21ae27e	1667
emilmont	79:0c05e21ae27e	1668	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont	79:0c05e21ae27e	1669
emilmont	79:0c05e21ae27e	1670	\return 0 No character available.
emilmont	79:0c05e21ae27e	1671	\return 1 Character available.
emilmont	79:0c05e21ae27e	1672	*/
emilmont	79:0c05e21ae27e	1673	__STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont	79:0c05e21ae27e	1674
emilmont	79:0c05e21ae27e	1675	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont	79:0c05e21ae27e	1676	return (0); /* no character available */
emilmont	79:0c05e21ae27e	1677	} else {
emilmont	79:0c05e21ae27e	1678	return (1); /* character available */
emilmont	79:0c05e21ae27e	1679	}
emilmont	79:0c05e21ae27e	1680	}
emilmont	79:0c05e21ae27e	1681
emilmont	79:0c05e21ae27e	1682	/@} end of CMSIS_core_DebugFunctions /
emilmont	79:0c05e21ae27e	1683
emilmont	79:0c05e21ae27e	1684
Kojto	110:165afa46840b	1685
emilmont	79:0c05e21ae27e	1686
emilmont	79:0c05e21ae27e	1687	#ifdef __cplusplus
emilmont	79:0c05e21ae27e	1688	}
emilmont	79:0c05e21ae27e	1689	#endif
Kojto	110:165afa46840b	1690
Kojto	110:165afa46840b	1691	#endif /* __CORE_CM3_H_DEPENDANT */
Kojto	110:165afa46840b	1692
Kojto	110:165afa46840b	1693	#endif /* __CMSIS_GENERIC */