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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_MPS2_M7/core_cm0.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
102:da0ca467f8b5
Child:
128:9bcdf88f62b0
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /**************************************************************************//**
Kojto 102:da0ca467f8b5 2 * @file core_cm0.h
Kojto 102:da0ca467f8b5 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 102:da0ca467f8b5 6 *
Kojto 102:da0ca467f8b5 7 * @note
Kojto 102:da0ca467f8b5 8 *
Kojto 102:da0ca467f8b5 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 102:da0ca467f8b5 11
Kojto 102:da0ca467f8b5 12 All rights reserved.
Kojto 102:da0ca467f8b5 13 Redistribution and use in source and binary forms, with or without
Kojto 102:da0ca467f8b5 14 modification, are permitted provided that the following conditions are met:
Kojto 102:da0ca467f8b5 15 - Redistributions of source code must retain the above copyright
Kojto 102:da0ca467f8b5 16 notice, this list of conditions and the following disclaimer.
Kojto 102:da0ca467f8b5 17 - Redistributions in binary form must reproduce the above copyright
Kojto 102:da0ca467f8b5 18 notice, this list of conditions and the following disclaimer in the
Kojto 102:da0ca467f8b5 19 documentation and/or other materials provided with the distribution.
Kojto 102:da0ca467f8b5 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 102:da0ca467f8b5 21 to endorse or promote products derived from this software without
Kojto 102:da0ca467f8b5 22 specific prior written permission.
Kojto 102:da0ca467f8b5 23 *
Kojto 102:da0ca467f8b5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 102:da0ca467f8b5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 102:da0ca467f8b5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 102:da0ca467f8b5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 102:da0ca467f8b5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 102:da0ca467f8b5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 102:da0ca467f8b5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 102:da0ca467f8b5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 102:da0ca467f8b5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 102:da0ca467f8b5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 102:da0ca467f8b5 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 102:da0ca467f8b5 35 ---------------------------------------------------------------------------*/
Kojto 102:da0ca467f8b5 36
Kojto 102:da0ca467f8b5 37
Kojto 102:da0ca467f8b5 38 #if defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 102:da0ca467f8b5 40 #endif
Kojto 102:da0ca467f8b5 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 102:da0ca467f8b5 45 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 46 extern "C" {
Kojto 102:da0ca467f8b5 47 #endif
Kojto 102:da0ca467f8b5 48
Kojto 102:da0ca467f8b5 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 102:da0ca467f8b5 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 102:da0ca467f8b5 51
Kojto 102:da0ca467f8b5 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 102:da0ca467f8b5 53 Function definitions in header files are used to allow 'inlining'.
Kojto 102:da0ca467f8b5 54
Kojto 102:da0ca467f8b5 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 102:da0ca467f8b5 56 Unions are used for effective representation of core registers.
Kojto 102:da0ca467f8b5 57
Kojto 102:da0ca467f8b5 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 102:da0ca467f8b5 59 Function-like macros are used to allow more efficient code.
Kojto 102:da0ca467f8b5 60 */
Kojto 102:da0ca467f8b5 61
Kojto 102:da0ca467f8b5 62
Kojto 102:da0ca467f8b5 63 /*******************************************************************************
Kojto 102:da0ca467f8b5 64 * CMSIS definitions
Kojto 102:da0ca467f8b5 65 ******************************************************************************/
Kojto 102:da0ca467f8b5 66 /** \ingroup Cortex_M0
Kojto 102:da0ca467f8b5 67 @{
Kojto 102:da0ca467f8b5 68 */
Kojto 102:da0ca467f8b5 69
Kojto 102:da0ca467f8b5 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 102:da0ca467f8b5 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 102:da0ca467f8b5 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 102:da0ca467f8b5 75
Kojto 102:da0ca467f8b5 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 102:da0ca467f8b5 77
Kojto 102:da0ca467f8b5 78
Kojto 102:da0ca467f8b5 79 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 82 #define __STATIC_INLINE static __inline
Kojto 102:da0ca467f8b5 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 102:da0ca467f8b5 89 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 102:da0ca467f8b5 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 102:da0ca467f8b5 92 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 102:da0ca467f8b5 96 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 97
Kojto 102:da0ca467f8b5 98 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 101 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 102:da0ca467f8b5 109 #endif
Kojto 102:da0ca467f8b5 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 102:da0ca467f8b5 113 */
Kojto 102:da0ca467f8b5 114 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 115
Kojto 102:da0ca467f8b5 116 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 117 #if defined __TARGET_FPU_VFP
Kojto 102:da0ca467f8b5 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 119 #endif
Kojto 102:da0ca467f8b5 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 102:da0ca467f8b5 126 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 127 #if defined __ARMVFP__
Kojto 102:da0ca467f8b5 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 129 #endif
Kojto 102:da0ca467f8b5 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 102:da0ca467f8b5 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 134 #endif
Kojto 102:da0ca467f8b5 135
Kojto 102:da0ca467f8b5 136 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 137 #if defined __FPU_VFP__
Kojto 102:da0ca467f8b5 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 102:da0ca467f8b5 145 #endif
Kojto 102:da0ca467f8b5 146
Kojto 102:da0ca467f8b5 147 #include <stdint.h> /* standard types definitions */
Kojto 102:da0ca467f8b5 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 102:da0ca467f8b5 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 102:da0ca467f8b5 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 102:da0ca467f8b5 155 #endif /* __CORE_CM0_H_GENERIC */
Kojto 102:da0ca467f8b5 156
Kojto 102:da0ca467f8b5 157 #ifndef __CMSIS_GENERIC
Kojto 102:da0ca467f8b5 158
Kojto 102:da0ca467f8b5 159 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 102:da0ca467f8b5 160 #define __CORE_CM0_H_DEPENDANT
Kojto 102:da0ca467f8b5 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 102:da0ca467f8b5 166 /* check device defines and use defaults */
Kojto 102:da0ca467f8b5 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 102:da0ca467f8b5 168 #ifndef __CM0_REV
Kojto 102:da0ca467f8b5 169 #define __CM0_REV 0x0000
Kojto 102:da0ca467f8b5 170 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 171 #endif
Kojto 102:da0ca467f8b5 172
Kojto 102:da0ca467f8b5 173 #ifndef __NVIC_PRIO_BITS
Kojto 102:da0ca467f8b5 174 #define __NVIC_PRIO_BITS 2
Kojto 102:da0ca467f8b5 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 176 #endif
Kojto 102:da0ca467f8b5 177
Kojto 102:da0ca467f8b5 178 #ifndef __Vendor_SysTickConfig
Kojto 102:da0ca467f8b5 179 #define __Vendor_SysTickConfig 0
Kojto 102:da0ca467f8b5 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 181 #endif
Kojto 102:da0ca467f8b5 182 #endif
Kojto 102:da0ca467f8b5 183
Kojto 102:da0ca467f8b5 184 /* IO definitions (access restrictions to peripheral registers) */
Kojto 102:da0ca467f8b5 185 /**
Kojto 102:da0ca467f8b5 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 102:da0ca467f8b5 187
Kojto 102:da0ca467f8b5 188 <strong>IO Type Qualifiers</strong> are used
Kojto 102:da0ca467f8b5 189 \li to specify the access to peripheral variables.
Kojto 102:da0ca467f8b5 190 \li for automatic generation of peripheral register debug information.
Kojto 102:da0ca467f8b5 191 */
Kojto 102:da0ca467f8b5 192 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 193 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 194 #else
Kojto 102:da0ca467f8b5 195 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 196 #endif
Kojto 102:da0ca467f8b5 197 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 102:da0ca467f8b5 198 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 102:da0ca467f8b5 199
Kojto 102:da0ca467f8b5 200 /*@} end of group Cortex_M0 */
Kojto 102:da0ca467f8b5 201
Kojto 102:da0ca467f8b5 202
Kojto 102:da0ca467f8b5 203
Kojto 102:da0ca467f8b5 204 /*******************************************************************************
Kojto 102:da0ca467f8b5 205 * Register Abstraction
Kojto 102:da0ca467f8b5 206 Core Register contain:
Kojto 102:da0ca467f8b5 207 - Core Register
Kojto 102:da0ca467f8b5 208 - Core NVIC Register
Kojto 102:da0ca467f8b5 209 - Core SCB Register
Kojto 102:da0ca467f8b5 210 - Core SysTick Register
Kojto 102:da0ca467f8b5 211 ******************************************************************************/
Kojto 102:da0ca467f8b5 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 102:da0ca467f8b5 213 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 102:da0ca467f8b5 214 */
Kojto 102:da0ca467f8b5 215
Kojto 102:da0ca467f8b5 216 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 217 \defgroup CMSIS_CORE Status and Control Registers
Kojto 102:da0ca467f8b5 218 \brief Core Register type definitions.
Kojto 102:da0ca467f8b5 219 @{
Kojto 102:da0ca467f8b5 220 */
Kojto 102:da0ca467f8b5 221
Kojto 102:da0ca467f8b5 222 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 102:da0ca467f8b5 223 */
Kojto 102:da0ca467f8b5 224 typedef union
Kojto 102:da0ca467f8b5 225 {
Kojto 102:da0ca467f8b5 226 struct
Kojto 102:da0ca467f8b5 227 {
Kojto 110:165afa46840b 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 102:da0ca467f8b5 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 233 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 234 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 235 } APSR_Type;
Kojto 102:da0ca467f8b5 236
Kojto 110:165afa46840b 237 /* APSR Register Definitions */
Kojto 110:165afa46840b 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 240
Kojto 110:165afa46840b 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 243
Kojto 110:165afa46840b 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 246
Kojto 110:165afa46840b 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 249
Kojto 102:da0ca467f8b5 250
Kojto 102:da0ca467f8b5 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 102:da0ca467f8b5 252 */
Kojto 102:da0ca467f8b5 253 typedef union
Kojto 102:da0ca467f8b5 254 {
Kojto 102:da0ca467f8b5 255 struct
Kojto 102:da0ca467f8b5 256 {
Kojto 102:da0ca467f8b5 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 102:da0ca467f8b5 259 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 260 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 261 } IPSR_Type;
Kojto 102:da0ca467f8b5 262
Kojto 110:165afa46840b 263 /* IPSR Register Definitions */
Kojto 110:165afa46840b 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 266
Kojto 102:da0ca467f8b5 267
Kojto 102:da0ca467f8b5 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 102:da0ca467f8b5 269 */
Kojto 102:da0ca467f8b5 270 typedef union
Kojto 102:da0ca467f8b5 271 {
Kojto 102:da0ca467f8b5 272 struct
Kojto 102:da0ca467f8b5 273 {
Kojto 102:da0ca467f8b5 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 102:da0ca467f8b5 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 102:da0ca467f8b5 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 282 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 283 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 284 } xPSR_Type;
Kojto 102:da0ca467f8b5 285
Kojto 110:165afa46840b 286 /* xPSR Register Definitions */
Kojto 110:165afa46840b 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 289
Kojto 110:165afa46840b 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 292
Kojto 110:165afa46840b 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 295
Kojto 110:165afa46840b 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 298
Kojto 110:165afa46840b 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 301
Kojto 110:165afa46840b 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 304
Kojto 102:da0ca467f8b5 305
Kojto 102:da0ca467f8b5 306 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 102:da0ca467f8b5 307 */
Kojto 102:da0ca467f8b5 308 typedef union
Kojto 102:da0ca467f8b5 309 {
Kojto 102:da0ca467f8b5 310 struct
Kojto 102:da0ca467f8b5 311 {
Kojto 110:165afa46840b 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Kojto 102:da0ca467f8b5 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 102:da0ca467f8b5 315 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 316 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 317 } CONTROL_Type;
Kojto 102:da0ca467f8b5 318
Kojto 110:165afa46840b 319 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 322
Kojto 102:da0ca467f8b5 323 /*@} end of group CMSIS_CORE */
Kojto 102:da0ca467f8b5 324
Kojto 102:da0ca467f8b5 325
Kojto 102:da0ca467f8b5 326 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 102:da0ca467f8b5 328 \brief Type definitions for the NVIC Registers
Kojto 102:da0ca467f8b5 329 @{
Kojto 102:da0ca467f8b5 330 */
Kojto 102:da0ca467f8b5 331
Kojto 102:da0ca467f8b5 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 102:da0ca467f8b5 333 */
Kojto 102:da0ca467f8b5 334 typedef struct
Kojto 102:da0ca467f8b5 335 {
Kojto 102:da0ca467f8b5 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 102:da0ca467f8b5 337 uint32_t RESERVED0[31];
Kojto 102:da0ca467f8b5 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 102:da0ca467f8b5 339 uint32_t RSERVED1[31];
Kojto 102:da0ca467f8b5 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 102:da0ca467f8b5 341 uint32_t RESERVED2[31];
Kojto 102:da0ca467f8b5 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 102:da0ca467f8b5 343 uint32_t RESERVED3[31];
Kojto 102:da0ca467f8b5 344 uint32_t RESERVED4[64];
Kojto 102:da0ca467f8b5 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 102:da0ca467f8b5 346 } NVIC_Type;
Kojto 102:da0ca467f8b5 347
Kojto 102:da0ca467f8b5 348 /*@} end of group CMSIS_NVIC */
Kojto 102:da0ca467f8b5 349
Kojto 102:da0ca467f8b5 350
Kojto 102:da0ca467f8b5 351 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 352 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 102:da0ca467f8b5 353 \brief Type definitions for the System Control Block Registers
Kojto 102:da0ca467f8b5 354 @{
Kojto 102:da0ca467f8b5 355 */
Kojto 102:da0ca467f8b5 356
Kojto 102:da0ca467f8b5 357 /** \brief Structure type to access the System Control Block (SCB).
Kojto 102:da0ca467f8b5 358 */
Kojto 102:da0ca467f8b5 359 typedef struct
Kojto 102:da0ca467f8b5 360 {
Kojto 102:da0ca467f8b5 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 102:da0ca467f8b5 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 102:da0ca467f8b5 363 uint32_t RESERVED0;
Kojto 102:da0ca467f8b5 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 102:da0ca467f8b5 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 102:da0ca467f8b5 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 102:da0ca467f8b5 367 uint32_t RESERVED1;
Kojto 102:da0ca467f8b5 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 102:da0ca467f8b5 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 102:da0ca467f8b5 370 } SCB_Type;
Kojto 102:da0ca467f8b5 371
Kojto 102:da0ca467f8b5 372 /* SCB CPUID Register Definitions */
Kojto 102:da0ca467f8b5 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 102:da0ca467f8b5 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 102:da0ca467f8b5 375
Kojto 102:da0ca467f8b5 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 102:da0ca467f8b5 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 102:da0ca467f8b5 378
Kojto 102:da0ca467f8b5 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 102:da0ca467f8b5 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 102:da0ca467f8b5 381
Kojto 102:da0ca467f8b5 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 102:da0ca467f8b5 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 102:da0ca467f8b5 384
Kojto 102:da0ca467f8b5 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 102:da0ca467f8b5 387
Kojto 102:da0ca467f8b5 388 /* SCB Interrupt Control State Register Definitions */
Kojto 102:da0ca467f8b5 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 102:da0ca467f8b5 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 102:da0ca467f8b5 391
Kojto 102:da0ca467f8b5 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 102:da0ca467f8b5 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 102:da0ca467f8b5 394
Kojto 102:da0ca467f8b5 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 102:da0ca467f8b5 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 102:da0ca467f8b5 397
Kojto 102:da0ca467f8b5 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 102:da0ca467f8b5 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 102:da0ca467f8b5 400
Kojto 102:da0ca467f8b5 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 102:da0ca467f8b5 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 102:da0ca467f8b5 403
Kojto 102:da0ca467f8b5 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 102:da0ca467f8b5 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 102:da0ca467f8b5 406
Kojto 102:da0ca467f8b5 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 102:da0ca467f8b5 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 102:da0ca467f8b5 409
Kojto 102:da0ca467f8b5 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 102:da0ca467f8b5 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 102:da0ca467f8b5 412
Kojto 102:da0ca467f8b5 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 102:da0ca467f8b5 415
Kojto 102:da0ca467f8b5 416 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 102:da0ca467f8b5 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 102:da0ca467f8b5 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 102:da0ca467f8b5 419
Kojto 102:da0ca467f8b5 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 102:da0ca467f8b5 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 102:da0ca467f8b5 422
Kojto 102:da0ca467f8b5 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 102:da0ca467f8b5 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 102:da0ca467f8b5 425
Kojto 102:da0ca467f8b5 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 102:da0ca467f8b5 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 102:da0ca467f8b5 428
Kojto 102:da0ca467f8b5 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 102:da0ca467f8b5 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 102:da0ca467f8b5 431
Kojto 102:da0ca467f8b5 432 /* SCB System Control Register Definitions */
Kojto 102:da0ca467f8b5 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 102:da0ca467f8b5 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 102:da0ca467f8b5 435
Kojto 102:da0ca467f8b5 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 102:da0ca467f8b5 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 102:da0ca467f8b5 438
Kojto 102:da0ca467f8b5 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 102:da0ca467f8b5 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 102:da0ca467f8b5 441
Kojto 102:da0ca467f8b5 442 /* SCB Configuration Control Register Definitions */
Kojto 102:da0ca467f8b5 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 102:da0ca467f8b5 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 102:da0ca467f8b5 445
Kojto 102:da0ca467f8b5 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 102:da0ca467f8b5 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 102:da0ca467f8b5 448
Kojto 102:da0ca467f8b5 449 /* SCB System Handler Control and State Register Definitions */
Kojto 102:da0ca467f8b5 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 102:da0ca467f8b5 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 102:da0ca467f8b5 452
Kojto 102:da0ca467f8b5 453 /*@} end of group CMSIS_SCB */
Kojto 102:da0ca467f8b5 454
Kojto 102:da0ca467f8b5 455
Kojto 102:da0ca467f8b5 456 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 102:da0ca467f8b5 458 \brief Type definitions for the System Timer Registers.
Kojto 102:da0ca467f8b5 459 @{
Kojto 102:da0ca467f8b5 460 */
Kojto 102:da0ca467f8b5 461
Kojto 102:da0ca467f8b5 462 /** \brief Structure type to access the System Timer (SysTick).
Kojto 102:da0ca467f8b5 463 */
Kojto 102:da0ca467f8b5 464 typedef struct
Kojto 102:da0ca467f8b5 465 {
Kojto 102:da0ca467f8b5 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 102:da0ca467f8b5 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 102:da0ca467f8b5 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 102:da0ca467f8b5 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 102:da0ca467f8b5 470 } SysTick_Type;
Kojto 102:da0ca467f8b5 471
Kojto 102:da0ca467f8b5 472 /* SysTick Control / Status Register Definitions */
Kojto 102:da0ca467f8b5 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 102:da0ca467f8b5 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 102:da0ca467f8b5 475
Kojto 102:da0ca467f8b5 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 102:da0ca467f8b5 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 102:da0ca467f8b5 478
Kojto 102:da0ca467f8b5 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 102:da0ca467f8b5 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 102:da0ca467f8b5 481
Kojto 102:da0ca467f8b5 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 102:da0ca467f8b5 484
Kojto 102:da0ca467f8b5 485 /* SysTick Reload Register Definitions */
Kojto 102:da0ca467f8b5 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 102:da0ca467f8b5 488
Kojto 102:da0ca467f8b5 489 /* SysTick Current Register Definitions */
Kojto 102:da0ca467f8b5 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 102:da0ca467f8b5 492
Kojto 102:da0ca467f8b5 493 /* SysTick Calibration Register Definitions */
Kojto 102:da0ca467f8b5 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 102:da0ca467f8b5 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 102:da0ca467f8b5 496
Kojto 102:da0ca467f8b5 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 102:da0ca467f8b5 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 102:da0ca467f8b5 499
Kojto 102:da0ca467f8b5 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 102:da0ca467f8b5 502
Kojto 102:da0ca467f8b5 503 /*@} end of group CMSIS_SysTick */
Kojto 102:da0ca467f8b5 504
Kojto 102:da0ca467f8b5 505
Kojto 102:da0ca467f8b5 506 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 102:da0ca467f8b5 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 102:da0ca467f8b5 509 are only accessible over DAP and not via processor. Therefore
Kojto 102:da0ca467f8b5 510 they are not covered by the Cortex-M0 header file.
Kojto 102:da0ca467f8b5 511 @{
Kojto 102:da0ca467f8b5 512 */
Kojto 102:da0ca467f8b5 513 /*@} end of group CMSIS_CoreDebug */
Kojto 102:da0ca467f8b5 514
Kojto 102:da0ca467f8b5 515
Kojto 102:da0ca467f8b5 516 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 517 \defgroup CMSIS_core_base Core Definitions
Kojto 102:da0ca467f8b5 518 \brief Definitions for base addresses, unions, and structures.
Kojto 102:da0ca467f8b5 519 @{
Kojto 102:da0ca467f8b5 520 */
Kojto 102:da0ca467f8b5 521
Kojto 102:da0ca467f8b5 522 /* Memory mapping of Cortex-M0 Hardware */
Kojto 102:da0ca467f8b5 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 102:da0ca467f8b5 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 102:da0ca467f8b5 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 102:da0ca467f8b5 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 102:da0ca467f8b5 527
Kojto 102:da0ca467f8b5 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 102:da0ca467f8b5 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 102:da0ca467f8b5 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 102:da0ca467f8b5 531
Kojto 102:da0ca467f8b5 532
Kojto 102:da0ca467f8b5 533 /*@} */
Kojto 102:da0ca467f8b5 534
Kojto 102:da0ca467f8b5 535
Kojto 102:da0ca467f8b5 536
Kojto 102:da0ca467f8b5 537 /*******************************************************************************
Kojto 102:da0ca467f8b5 538 * Hardware Abstraction Layer
Kojto 102:da0ca467f8b5 539 Core Function Interface contains:
Kojto 102:da0ca467f8b5 540 - Core NVIC Functions
Kojto 102:da0ca467f8b5 541 - Core SysTick Functions
Kojto 102:da0ca467f8b5 542 - Core Register Access Functions
Kojto 102:da0ca467f8b5 543 ******************************************************************************/
Kojto 102:da0ca467f8b5 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 102:da0ca467f8b5 545 */
Kojto 102:da0ca467f8b5 546
Kojto 102:da0ca467f8b5 547
Kojto 102:da0ca467f8b5 548
Kojto 102:da0ca467f8b5 549 /* ########################## NVIC functions #################################### */
Kojto 102:da0ca467f8b5 550 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 102:da0ca467f8b5 552 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 102:da0ca467f8b5 553 @{
Kojto 102:da0ca467f8b5 554 */
Kojto 102:da0ca467f8b5 555
Kojto 102:da0ca467f8b5 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 102:da0ca467f8b5 557 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 102:da0ca467f8b5 561
Kojto 102:da0ca467f8b5 562
Kojto 102:da0ca467f8b5 563 /** \brief Enable External Interrupt
Kojto 102:da0ca467f8b5 564
Kojto 102:da0ca467f8b5 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 566
Kojto 102:da0ca467f8b5 567 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 568 */
Kojto 102:da0ca467f8b5 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 570 {
Kojto 110:165afa46840b 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 572 }
Kojto 102:da0ca467f8b5 573
Kojto 102:da0ca467f8b5 574
Kojto 102:da0ca467f8b5 575 /** \brief Disable External Interrupt
Kojto 102:da0ca467f8b5 576
Kojto 102:da0ca467f8b5 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 578
Kojto 102:da0ca467f8b5 579 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 580 */
Kojto 102:da0ca467f8b5 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 582 {
Kojto 110:165afa46840b 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 584 }
Kojto 102:da0ca467f8b5 585
Kojto 102:da0ca467f8b5 586
Kojto 102:da0ca467f8b5 587 /** \brief Get Pending Interrupt
Kojto 102:da0ca467f8b5 588
Kojto 102:da0ca467f8b5 589 The function reads the pending register in the NVIC and returns the pending bit
Kojto 102:da0ca467f8b5 590 for the specified interrupt.
Kojto 102:da0ca467f8b5 591
Kojto 102:da0ca467f8b5 592 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 593
Kojto 102:da0ca467f8b5 594 \return 0 Interrupt status is not pending.
Kojto 102:da0ca467f8b5 595 \return 1 Interrupt status is pending.
Kojto 102:da0ca467f8b5 596 */
Kojto 102:da0ca467f8b5 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 598 {
Kojto 110:165afa46840b 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 102:da0ca467f8b5 600 }
Kojto 102:da0ca467f8b5 601
Kojto 102:da0ca467f8b5 602
Kojto 102:da0ca467f8b5 603 /** \brief Set Pending Interrupt
Kojto 102:da0ca467f8b5 604
Kojto 102:da0ca467f8b5 605 The function sets the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 606
Kojto 102:da0ca467f8b5 607 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 608 */
Kojto 102:da0ca467f8b5 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 610 {
Kojto 110:165afa46840b 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 612 }
Kojto 102:da0ca467f8b5 613
Kojto 102:da0ca467f8b5 614
Kojto 102:da0ca467f8b5 615 /** \brief Clear Pending Interrupt
Kojto 102:da0ca467f8b5 616
Kojto 102:da0ca467f8b5 617 The function clears the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 618
Kojto 102:da0ca467f8b5 619 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 620 */
Kojto 102:da0ca467f8b5 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 622 {
Kojto 110:165afa46840b 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 624 }
Kojto 102:da0ca467f8b5 625
Kojto 102:da0ca467f8b5 626
Kojto 102:da0ca467f8b5 627 /** \brief Set Interrupt Priority
Kojto 102:da0ca467f8b5 628
Kojto 102:da0ca467f8b5 629 The function sets the priority of an interrupt.
Kojto 102:da0ca467f8b5 630
Kojto 102:da0ca467f8b5 631 \note The priority cannot be set for every core interrupt.
Kojto 102:da0ca467f8b5 632
Kojto 102:da0ca467f8b5 633 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 634 \param [in] priority Priority to set.
Kojto 102:da0ca467f8b5 635 */
Kojto 102:da0ca467f8b5 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 102:da0ca467f8b5 637 {
Kojto 110:165afa46840b 638 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 641 }
Kojto 102:da0ca467f8b5 642 else {
Kojto 110:165afa46840b 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 645 }
Kojto 102:da0ca467f8b5 646 }
Kojto 102:da0ca467f8b5 647
Kojto 102:da0ca467f8b5 648
Kojto 102:da0ca467f8b5 649 /** \brief Get Interrupt Priority
Kojto 102:da0ca467f8b5 650
Kojto 102:da0ca467f8b5 651 The function reads the priority of an interrupt. The interrupt
Kojto 102:da0ca467f8b5 652 number can be positive to specify an external (device specific)
Kojto 102:da0ca467f8b5 653 interrupt, or negative to specify an internal (core) interrupt.
Kojto 102:da0ca467f8b5 654
Kojto 102:da0ca467f8b5 655
Kojto 102:da0ca467f8b5 656 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 657 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 102:da0ca467f8b5 658 priority bits of the microcontroller.
Kojto 102:da0ca467f8b5 659 */
Kojto 102:da0ca467f8b5 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 661 {
Kojto 102:da0ca467f8b5 662
Kojto 110:165afa46840b 663 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 665 }
Kojto 102:da0ca467f8b5 666 else {
Kojto 110:165afa46840b 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 668 }
Kojto 102:da0ca467f8b5 669 }
Kojto 102:da0ca467f8b5 670
Kojto 102:da0ca467f8b5 671
Kojto 102:da0ca467f8b5 672 /** \brief System Reset
Kojto 102:da0ca467f8b5 673
Kojto 102:da0ca467f8b5 674 The function initiates a system reset request to reset the MCU.
Kojto 102:da0ca467f8b5 675 */
Kojto 102:da0ca467f8b5 676 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 102:da0ca467f8b5 677 {
Kojto 102:da0ca467f8b5 678 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 102:da0ca467f8b5 679 buffered write are completed before reset */
Kojto 110:165afa46840b 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 102:da0ca467f8b5 681 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 102:da0ca467f8b5 682 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 683 while(1) { __NOP(); } /* wait until reset */
Kojto 102:da0ca467f8b5 684 }
Kojto 102:da0ca467f8b5 685
Kojto 102:da0ca467f8b5 686 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 102:da0ca467f8b5 687
Kojto 102:da0ca467f8b5 688
Kojto 102:da0ca467f8b5 689
Kojto 102:da0ca467f8b5 690 /* ################################## SysTick function ############################################ */
Kojto 102:da0ca467f8b5 691 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 102:da0ca467f8b5 693 \brief Functions that configure the System.
Kojto 102:da0ca467f8b5 694 @{
Kojto 102:da0ca467f8b5 695 */
Kojto 102:da0ca467f8b5 696
Kojto 102:da0ca467f8b5 697 #if (__Vendor_SysTickConfig == 0)
Kojto 102:da0ca467f8b5 698
Kojto 102:da0ca467f8b5 699 /** \brief System Tick Configuration
Kojto 102:da0ca467f8b5 700
Kojto 102:da0ca467f8b5 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 102:da0ca467f8b5 702 Counter is in free running mode to generate periodic interrupts.
Kojto 102:da0ca467f8b5 703
Kojto 102:da0ca467f8b5 704 \param [in] ticks Number of ticks between two interrupts.
Kojto 102:da0ca467f8b5 705
Kojto 102:da0ca467f8b5 706 \return 0 Function succeeded.
Kojto 102:da0ca467f8b5 707 \return 1 Function failed.
Kojto 102:da0ca467f8b5 708
Kojto 102:da0ca467f8b5 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 102:da0ca467f8b5 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 102:da0ca467f8b5 711 must contain a vendor-specific implementation of this function.
Kojto 102:da0ca467f8b5 712
Kojto 102:da0ca467f8b5 713 */
Kojto 102:da0ca467f8b5 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 102:da0ca467f8b5 715 {
Kojto 110:165afa46840b 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 102:da0ca467f8b5 717
Kojto 110:165afa46840b 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 102:da0ca467f8b5 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 102:da0ca467f8b5 722 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 724 return (0UL); /* Function successful */
Kojto 102:da0ca467f8b5 725 }
Kojto 102:da0ca467f8b5 726
Kojto 102:da0ca467f8b5 727 #endif
Kojto 102:da0ca467f8b5 728
Kojto 102:da0ca467f8b5 729 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 102:da0ca467f8b5 730
Kojto 102:da0ca467f8b5 731
Kojto 102:da0ca467f8b5 732
Kojto 102:da0ca467f8b5 733
Kojto 110:165afa46840b 734 #ifdef __cplusplus
Kojto 110:165afa46840b 735 }
Kojto 110:165afa46840b 736 #endif
Kojto 110:165afa46840b 737
Kojto 102:da0ca467f8b5 738 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 102:da0ca467f8b5 739
Kojto 102:da0ca467f8b5 740 #endif /* __CMSIS_GENERIC */