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TARGET_LPC1549/core_cmInstr.h@79:0c05e21ae27e, 2014-02-21 (annotated)

Committer:
emilmont
Date:
Fri Feb 21 10:26:12 2014 +0000
Revision:
79:0c05e21ae27e
Child:
110:165afa46840b
Add LPC1549 Target

Change "us_ticker" implementation to 32-bit timer for NUCLEO_L152RE and NUCLEO_F401RE

Update KL05Z CMSIS-CORE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 79:0c05e21ae27e 1 /**************************************************************************//**
emilmont 79:0c05e21ae27e 2 * @file core_cmInstr.h
emilmont 79:0c05e21ae27e 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 79:0c05e21ae27e 4 * @version V3.20
emilmont 79:0c05e21ae27e 5 * @date 05. March 2013
emilmont 79:0c05e21ae27e 6 *
emilmont 79:0c05e21ae27e 7 * @note
emilmont 79:0c05e21ae27e 8 *
emilmont 79:0c05e21ae27e 9 ******************************************************************************/
emilmont 79:0c05e21ae27e 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 79:0c05e21ae27e 11
emilmont 79:0c05e21ae27e 12 All rights reserved.
emilmont 79:0c05e21ae27e 13 Redistribution and use in source and binary forms, with or without
emilmont 79:0c05e21ae27e 14 modification, are permitted provided that the following conditions are met:
emilmont 79:0c05e21ae27e 15 - Redistributions of source code must retain the above copyright
emilmont 79:0c05e21ae27e 16 notice, this list of conditions and the following disclaimer.
emilmont 79:0c05e21ae27e 17 - Redistributions in binary form must reproduce the above copyright
emilmont 79:0c05e21ae27e 18 notice, this list of conditions and the following disclaimer in the
emilmont 79:0c05e21ae27e 19 documentation and/or other materials provided with the distribution.
emilmont 79:0c05e21ae27e 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 79:0c05e21ae27e 21 to endorse or promote products derived from this software without
emilmont 79:0c05e21ae27e 22 specific prior written permission.
emilmont 79:0c05e21ae27e 23 *
emilmont 79:0c05e21ae27e 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 79:0c05e21ae27e 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 79:0c05e21ae27e 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 79:0c05e21ae27e 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 79:0c05e21ae27e 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 79:0c05e21ae27e 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 79:0c05e21ae27e 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 79:0c05e21ae27e 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 79:0c05e21ae27e 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 79:0c05e21ae27e 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 79:0c05e21ae27e 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 79:0c05e21ae27e 35 ---------------------------------------------------------------------------*/
emilmont 79:0c05e21ae27e 36
emilmont 79:0c05e21ae27e 37
emilmont 79:0c05e21ae27e 38 #ifndef __CORE_CMINSTR_H
emilmont 79:0c05e21ae27e 39 #define __CORE_CMINSTR_H
emilmont 79:0c05e21ae27e 40
emilmont 79:0c05e21ae27e 41
emilmont 79:0c05e21ae27e 42 /* ########################## Core Instruction Access ######################### */
emilmont 79:0c05e21ae27e 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 79:0c05e21ae27e 44 Access to dedicated instructions
emilmont 79:0c05e21ae27e 45 @{
emilmont 79:0c05e21ae27e 46 */
emilmont 79:0c05e21ae27e 47
emilmont 79:0c05e21ae27e 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 79:0c05e21ae27e 49 /* ARM armcc specific functions */
emilmont 79:0c05e21ae27e 50
emilmont 79:0c05e21ae27e 51 #if (__ARMCC_VERSION < 400677)
emilmont 79:0c05e21ae27e 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 79:0c05e21ae27e 53 #endif
emilmont 79:0c05e21ae27e 54
emilmont 79:0c05e21ae27e 55
emilmont 79:0c05e21ae27e 56 /** \brief No Operation
emilmont 79:0c05e21ae27e 57
emilmont 79:0c05e21ae27e 58 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 79:0c05e21ae27e 59 */
emilmont 79:0c05e21ae27e 60 #define __NOP __nop
emilmont 79:0c05e21ae27e 61
emilmont 79:0c05e21ae27e 62
emilmont 79:0c05e21ae27e 63 /** \brief Wait For Interrupt
emilmont 79:0c05e21ae27e 64
emilmont 79:0c05e21ae27e 65 Wait For Interrupt is a hint instruction that suspends execution
emilmont 79:0c05e21ae27e 66 until one of a number of events occurs.
emilmont 79:0c05e21ae27e 67 */
emilmont 79:0c05e21ae27e 68 #define __WFI __wfi
emilmont 79:0c05e21ae27e 69
emilmont 79:0c05e21ae27e 70
emilmont 79:0c05e21ae27e 71 /** \brief Wait For Event
emilmont 79:0c05e21ae27e 72
emilmont 79:0c05e21ae27e 73 Wait For Event is a hint instruction that permits the processor to enter
emilmont 79:0c05e21ae27e 74 a low-power state until one of a number of events occurs.
emilmont 79:0c05e21ae27e 75 */
emilmont 79:0c05e21ae27e 76 #define __WFE __wfe
emilmont 79:0c05e21ae27e 77
emilmont 79:0c05e21ae27e 78
emilmont 79:0c05e21ae27e 79 /** \brief Send Event
emilmont 79:0c05e21ae27e 80
emilmont 79:0c05e21ae27e 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 79:0c05e21ae27e 82 */
emilmont 79:0c05e21ae27e 83 #define __SEV __sev
emilmont 79:0c05e21ae27e 84
emilmont 79:0c05e21ae27e 85
emilmont 79:0c05e21ae27e 86 /** \brief Instruction Synchronization Barrier
emilmont 79:0c05e21ae27e 87
emilmont 79:0c05e21ae27e 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 79:0c05e21ae27e 89 so that all instructions following the ISB are fetched from cache or
emilmont 79:0c05e21ae27e 90 memory, after the instruction has been completed.
emilmont 79:0c05e21ae27e 91 */
emilmont 79:0c05e21ae27e 92 #define __ISB() __isb(0xF)
emilmont 79:0c05e21ae27e 93
emilmont 79:0c05e21ae27e 94
emilmont 79:0c05e21ae27e 95 /** \brief Data Synchronization Barrier
emilmont 79:0c05e21ae27e 96
emilmont 79:0c05e21ae27e 97 This function acts as a special kind of Data Memory Barrier.
emilmont 79:0c05e21ae27e 98 It completes when all explicit memory accesses before this instruction complete.
emilmont 79:0c05e21ae27e 99 */
emilmont 79:0c05e21ae27e 100 #define __DSB() __dsb(0xF)
emilmont 79:0c05e21ae27e 101
emilmont 79:0c05e21ae27e 102
emilmont 79:0c05e21ae27e 103 /** \brief Data Memory Barrier
emilmont 79:0c05e21ae27e 104
emilmont 79:0c05e21ae27e 105 This function ensures the apparent order of the explicit memory operations before
emilmont 79:0c05e21ae27e 106 and after the instruction, without ensuring their completion.
emilmont 79:0c05e21ae27e 107 */
emilmont 79:0c05e21ae27e 108 #define __DMB() __dmb(0xF)
emilmont 79:0c05e21ae27e 109
emilmont 79:0c05e21ae27e 110
emilmont 79:0c05e21ae27e 111 /** \brief Reverse byte order (32 bit)
emilmont 79:0c05e21ae27e 112
emilmont 79:0c05e21ae27e 113 This function reverses the byte order in integer value.
emilmont 79:0c05e21ae27e 114
emilmont 79:0c05e21ae27e 115 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 116 \return Reversed value
emilmont 79:0c05e21ae27e 117 */
emilmont 79:0c05e21ae27e 118 #define __REV __rev
emilmont 79:0c05e21ae27e 119
emilmont 79:0c05e21ae27e 120
emilmont 79:0c05e21ae27e 121 /** \brief Reverse byte order (16 bit)
emilmont 79:0c05e21ae27e 122
emilmont 79:0c05e21ae27e 123 This function reverses the byte order in two unsigned short values.
emilmont 79:0c05e21ae27e 124
emilmont 79:0c05e21ae27e 125 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 126 \return Reversed value
emilmont 79:0c05e21ae27e 127 */
emilmont 79:0c05e21ae27e 128 #ifndef __NO_EMBEDDED_ASM
emilmont 79:0c05e21ae27e 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 79:0c05e21ae27e 130 {
emilmont 79:0c05e21ae27e 131 rev16 r0, r0
emilmont 79:0c05e21ae27e 132 bx lr
emilmont 79:0c05e21ae27e 133 }
emilmont 79:0c05e21ae27e 134 #endif
emilmont 79:0c05e21ae27e 135
emilmont 79:0c05e21ae27e 136 /** \brief Reverse byte order in signed short value
emilmont 79:0c05e21ae27e 137
emilmont 79:0c05e21ae27e 138 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 79:0c05e21ae27e 139
emilmont 79:0c05e21ae27e 140 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 141 \return Reversed value
emilmont 79:0c05e21ae27e 142 */
emilmont 79:0c05e21ae27e 143 #ifndef __NO_EMBEDDED_ASM
emilmont 79:0c05e21ae27e 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 79:0c05e21ae27e 145 {
emilmont 79:0c05e21ae27e 146 revsh r0, r0
emilmont 79:0c05e21ae27e 147 bx lr
emilmont 79:0c05e21ae27e 148 }
emilmont 79:0c05e21ae27e 149 #endif
emilmont 79:0c05e21ae27e 150
emilmont 79:0c05e21ae27e 151
emilmont 79:0c05e21ae27e 152 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 79:0c05e21ae27e 153
emilmont 79:0c05e21ae27e 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 79:0c05e21ae27e 155
emilmont 79:0c05e21ae27e 156 \param [in] value Value to rotate
emilmont 79:0c05e21ae27e 157 \param [in] value Number of Bits to rotate
emilmont 79:0c05e21ae27e 158 \return Rotated value
emilmont 79:0c05e21ae27e 159 */
emilmont 79:0c05e21ae27e 160 #define __ROR __ror
emilmont 79:0c05e21ae27e 161
emilmont 79:0c05e21ae27e 162
emilmont 79:0c05e21ae27e 163 /** \brief Breakpoint
emilmont 79:0c05e21ae27e 164
emilmont 79:0c05e21ae27e 165 This function causes the processor to enter Debug state.
emilmont 79:0c05e21ae27e 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 79:0c05e21ae27e 167
emilmont 79:0c05e21ae27e 168 \param [in] value is ignored by the processor.
emilmont 79:0c05e21ae27e 169 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 79:0c05e21ae27e 170 */
emilmont 79:0c05e21ae27e 171 #define __BKPT(value) __breakpoint(value)
emilmont 79:0c05e21ae27e 172
emilmont 79:0c05e21ae27e 173
emilmont 79:0c05e21ae27e 174 #if (__CORTEX_M >= 0x03)
emilmont 79:0c05e21ae27e 175
emilmont 79:0c05e21ae27e 176 /** \brief Reverse bit order of value
emilmont 79:0c05e21ae27e 177
emilmont 79:0c05e21ae27e 178 This function reverses the bit order of the given value.
emilmont 79:0c05e21ae27e 179
emilmont 79:0c05e21ae27e 180 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 181 \return Reversed value
emilmont 79:0c05e21ae27e 182 */
emilmont 79:0c05e21ae27e 183 #define __RBIT __rbit
emilmont 79:0c05e21ae27e 184
emilmont 79:0c05e21ae27e 185
emilmont 79:0c05e21ae27e 186 /** \brief LDR Exclusive (8 bit)
emilmont 79:0c05e21ae27e 187
emilmont 79:0c05e21ae27e 188 This function performs a exclusive LDR command for 8 bit value.
emilmont 79:0c05e21ae27e 189
emilmont 79:0c05e21ae27e 190 \param [in] ptr Pointer to data
emilmont 79:0c05e21ae27e 191 \return value of type uint8_t at (*ptr)
emilmont 79:0c05e21ae27e 192 */
emilmont 79:0c05e21ae27e 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 79:0c05e21ae27e 194
emilmont 79:0c05e21ae27e 195
emilmont 79:0c05e21ae27e 196 /** \brief LDR Exclusive (16 bit)
emilmont 79:0c05e21ae27e 197
emilmont 79:0c05e21ae27e 198 This function performs a exclusive LDR command for 16 bit values.
emilmont 79:0c05e21ae27e 199
emilmont 79:0c05e21ae27e 200 \param [in] ptr Pointer to data
emilmont 79:0c05e21ae27e 201 \return value of type uint16_t at (*ptr)
emilmont 79:0c05e21ae27e 202 */
emilmont 79:0c05e21ae27e 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 79:0c05e21ae27e 204
emilmont 79:0c05e21ae27e 205
emilmont 79:0c05e21ae27e 206 /** \brief LDR Exclusive (32 bit)
emilmont 79:0c05e21ae27e 207
emilmont 79:0c05e21ae27e 208 This function performs a exclusive LDR command for 32 bit values.
emilmont 79:0c05e21ae27e 209
emilmont 79:0c05e21ae27e 210 \param [in] ptr Pointer to data
emilmont 79:0c05e21ae27e 211 \return value of type uint32_t at (*ptr)
emilmont 79:0c05e21ae27e 212 */
emilmont 79:0c05e21ae27e 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 79:0c05e21ae27e 214
emilmont 79:0c05e21ae27e 215
emilmont 79:0c05e21ae27e 216 /** \brief STR Exclusive (8 bit)
emilmont 79:0c05e21ae27e 217
emilmont 79:0c05e21ae27e 218 This function performs a exclusive STR command for 8 bit values.
emilmont 79:0c05e21ae27e 219
emilmont 79:0c05e21ae27e 220 \param [in] value Value to store
emilmont 79:0c05e21ae27e 221 \param [in] ptr Pointer to location
emilmont 79:0c05e21ae27e 222 \return 0 Function succeeded
emilmont 79:0c05e21ae27e 223 \return 1 Function failed
emilmont 79:0c05e21ae27e 224 */
emilmont 79:0c05e21ae27e 225 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 79:0c05e21ae27e 226
emilmont 79:0c05e21ae27e 227
emilmont 79:0c05e21ae27e 228 /** \brief STR Exclusive (16 bit)
emilmont 79:0c05e21ae27e 229
emilmont 79:0c05e21ae27e 230 This function performs a exclusive STR command for 16 bit values.
emilmont 79:0c05e21ae27e 231
emilmont 79:0c05e21ae27e 232 \param [in] value Value to store
emilmont 79:0c05e21ae27e 233 \param [in] ptr Pointer to location
emilmont 79:0c05e21ae27e 234 \return 0 Function succeeded
emilmont 79:0c05e21ae27e 235 \return 1 Function failed
emilmont 79:0c05e21ae27e 236 */
emilmont 79:0c05e21ae27e 237 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 79:0c05e21ae27e 238
emilmont 79:0c05e21ae27e 239
emilmont 79:0c05e21ae27e 240 /** \brief STR Exclusive (32 bit)
emilmont 79:0c05e21ae27e 241
emilmont 79:0c05e21ae27e 242 This function performs a exclusive STR command for 32 bit values.
emilmont 79:0c05e21ae27e 243
emilmont 79:0c05e21ae27e 244 \param [in] value Value to store
emilmont 79:0c05e21ae27e 245 \param [in] ptr Pointer to location
emilmont 79:0c05e21ae27e 246 \return 0 Function succeeded
emilmont 79:0c05e21ae27e 247 \return 1 Function failed
emilmont 79:0c05e21ae27e 248 */
emilmont 79:0c05e21ae27e 249 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 79:0c05e21ae27e 250
emilmont 79:0c05e21ae27e 251
emilmont 79:0c05e21ae27e 252 /** \brief Remove the exclusive lock
emilmont 79:0c05e21ae27e 253
emilmont 79:0c05e21ae27e 254 This function removes the exclusive lock which is created by LDREX.
emilmont 79:0c05e21ae27e 255
emilmont 79:0c05e21ae27e 256 */
emilmont 79:0c05e21ae27e 257 #define __CLREX __clrex
emilmont 79:0c05e21ae27e 258
emilmont 79:0c05e21ae27e 259
emilmont 79:0c05e21ae27e 260 /** \brief Signed Saturate
emilmont 79:0c05e21ae27e 261
emilmont 79:0c05e21ae27e 262 This function saturates a signed value.
emilmont 79:0c05e21ae27e 263
emilmont 79:0c05e21ae27e 264 \param [in] value Value to be saturated
emilmont 79:0c05e21ae27e 265 \param [in] sat Bit position to saturate to (1..32)
emilmont 79:0c05e21ae27e 266 \return Saturated value
emilmont 79:0c05e21ae27e 267 */
emilmont 79:0c05e21ae27e 268 #define __SSAT __ssat
emilmont 79:0c05e21ae27e 269
emilmont 79:0c05e21ae27e 270
emilmont 79:0c05e21ae27e 271 /** \brief Unsigned Saturate
emilmont 79:0c05e21ae27e 272
emilmont 79:0c05e21ae27e 273 This function saturates an unsigned value.
emilmont 79:0c05e21ae27e 274
emilmont 79:0c05e21ae27e 275 \param [in] value Value to be saturated
emilmont 79:0c05e21ae27e 276 \param [in] sat Bit position to saturate to (0..31)
emilmont 79:0c05e21ae27e 277 \return Saturated value
emilmont 79:0c05e21ae27e 278 */
emilmont 79:0c05e21ae27e 279 #define __USAT __usat
emilmont 79:0c05e21ae27e 280
emilmont 79:0c05e21ae27e 281
emilmont 79:0c05e21ae27e 282 /** \brief Count leading zeros
emilmont 79:0c05e21ae27e 283
emilmont 79:0c05e21ae27e 284 This function counts the number of leading zeros of a data value.
emilmont 79:0c05e21ae27e 285
emilmont 79:0c05e21ae27e 286 \param [in] value Value to count the leading zeros
emilmont 79:0c05e21ae27e 287 \return number of leading zeros in value
emilmont 79:0c05e21ae27e 288 */
emilmont 79:0c05e21ae27e 289 #define __CLZ __clz
emilmont 79:0c05e21ae27e 290
emilmont 79:0c05e21ae27e 291 #endif /* (__CORTEX_M >= 0x03) */
emilmont 79:0c05e21ae27e 292
emilmont 79:0c05e21ae27e 293
emilmont 79:0c05e21ae27e 294
emilmont 79:0c05e21ae27e 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 79:0c05e21ae27e 296 /* IAR iccarm specific functions */
emilmont 79:0c05e21ae27e 297
emilmont 79:0c05e21ae27e 298 #include <cmsis_iar.h>
emilmont 79:0c05e21ae27e 299
emilmont 79:0c05e21ae27e 300
emilmont 79:0c05e21ae27e 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 79:0c05e21ae27e 302 /* TI CCS specific functions */
emilmont 79:0c05e21ae27e 303
emilmont 79:0c05e21ae27e 304 #include <cmsis_ccs.h>
emilmont 79:0c05e21ae27e 305
emilmont 79:0c05e21ae27e 306
emilmont 79:0c05e21ae27e 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 79:0c05e21ae27e 308 /* GNU gcc specific functions */
emilmont 79:0c05e21ae27e 309
emilmont 79:0c05e21ae27e 310 /* Define macros for porting to both thumb1 and thumb2.
emilmont 79:0c05e21ae27e 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
emilmont 79:0c05e21ae27e 312 * Otherwise, use general registers, specified by constrant "r" */
emilmont 79:0c05e21ae27e 313 #if defined (__thumb__) && !defined (__thumb2__)
emilmont 79:0c05e21ae27e 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
emilmont 79:0c05e21ae27e 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
emilmont 79:0c05e21ae27e 316 #else
emilmont 79:0c05e21ae27e 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
emilmont 79:0c05e21ae27e 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
emilmont 79:0c05e21ae27e 319 #endif
emilmont 79:0c05e21ae27e 320
emilmont 79:0c05e21ae27e 321 /** \brief No Operation
emilmont 79:0c05e21ae27e 322
emilmont 79:0c05e21ae27e 323 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 79:0c05e21ae27e 324 */
emilmont 79:0c05e21ae27e 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
emilmont 79:0c05e21ae27e 326 {
emilmont 79:0c05e21ae27e 327 __ASM volatile ("nop");
emilmont 79:0c05e21ae27e 328 }
emilmont 79:0c05e21ae27e 329
emilmont 79:0c05e21ae27e 330
emilmont 79:0c05e21ae27e 331 /** \brief Wait For Interrupt
emilmont 79:0c05e21ae27e 332
emilmont 79:0c05e21ae27e 333 Wait For Interrupt is a hint instruction that suspends execution
emilmont 79:0c05e21ae27e 334 until one of a number of events occurs.
emilmont 79:0c05e21ae27e 335 */
emilmont 79:0c05e21ae27e 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
emilmont 79:0c05e21ae27e 337 {
emilmont 79:0c05e21ae27e 338 __ASM volatile ("wfi");
emilmont 79:0c05e21ae27e 339 }
emilmont 79:0c05e21ae27e 340
emilmont 79:0c05e21ae27e 341
emilmont 79:0c05e21ae27e 342 /** \brief Wait For Event
emilmont 79:0c05e21ae27e 343
emilmont 79:0c05e21ae27e 344 Wait For Event is a hint instruction that permits the processor to enter
emilmont 79:0c05e21ae27e 345 a low-power state until one of a number of events occurs.
emilmont 79:0c05e21ae27e 346 */
emilmont 79:0c05e21ae27e 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
emilmont 79:0c05e21ae27e 348 {
emilmont 79:0c05e21ae27e 349 __ASM volatile ("wfe");
emilmont 79:0c05e21ae27e 350 }
emilmont 79:0c05e21ae27e 351
emilmont 79:0c05e21ae27e 352
emilmont 79:0c05e21ae27e 353 /** \brief Send Event
emilmont 79:0c05e21ae27e 354
emilmont 79:0c05e21ae27e 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 79:0c05e21ae27e 356 */
emilmont 79:0c05e21ae27e 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
emilmont 79:0c05e21ae27e 358 {
emilmont 79:0c05e21ae27e 359 __ASM volatile ("sev");
emilmont 79:0c05e21ae27e 360 }
emilmont 79:0c05e21ae27e 361
emilmont 79:0c05e21ae27e 362
emilmont 79:0c05e21ae27e 363 /** \brief Instruction Synchronization Barrier
emilmont 79:0c05e21ae27e 364
emilmont 79:0c05e21ae27e 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 79:0c05e21ae27e 366 so that all instructions following the ISB are fetched from cache or
emilmont 79:0c05e21ae27e 367 memory, after the instruction has been completed.
emilmont 79:0c05e21ae27e 368 */
emilmont 79:0c05e21ae27e 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
emilmont 79:0c05e21ae27e 370 {
emilmont 79:0c05e21ae27e 371 __ASM volatile ("isb");
emilmont 79:0c05e21ae27e 372 }
emilmont 79:0c05e21ae27e 373
emilmont 79:0c05e21ae27e 374
emilmont 79:0c05e21ae27e 375 /** \brief Data Synchronization Barrier
emilmont 79:0c05e21ae27e 376
emilmont 79:0c05e21ae27e 377 This function acts as a special kind of Data Memory Barrier.
emilmont 79:0c05e21ae27e 378 It completes when all explicit memory accesses before this instruction complete.
emilmont 79:0c05e21ae27e 379 */
emilmont 79:0c05e21ae27e 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
emilmont 79:0c05e21ae27e 381 {
emilmont 79:0c05e21ae27e 382 __ASM volatile ("dsb");
emilmont 79:0c05e21ae27e 383 }
emilmont 79:0c05e21ae27e 384
emilmont 79:0c05e21ae27e 385
emilmont 79:0c05e21ae27e 386 /** \brief Data Memory Barrier
emilmont 79:0c05e21ae27e 387
emilmont 79:0c05e21ae27e 388 This function ensures the apparent order of the explicit memory operations before
emilmont 79:0c05e21ae27e 389 and after the instruction, without ensuring their completion.
emilmont 79:0c05e21ae27e 390 */
emilmont 79:0c05e21ae27e 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
emilmont 79:0c05e21ae27e 392 {
emilmont 79:0c05e21ae27e 393 __ASM volatile ("dmb");
emilmont 79:0c05e21ae27e 394 }
emilmont 79:0c05e21ae27e 395
emilmont 79:0c05e21ae27e 396
emilmont 79:0c05e21ae27e 397 /** \brief Reverse byte order (32 bit)
emilmont 79:0c05e21ae27e 398
emilmont 79:0c05e21ae27e 399 This function reverses the byte order in integer value.
emilmont 79:0c05e21ae27e 400
emilmont 79:0c05e21ae27e 401 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 402 \return Reversed value
emilmont 79:0c05e21ae27e 403 */
emilmont 79:0c05e21ae27e 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 79:0c05e21ae27e 405 {
emilmont 79:0c05e21ae27e 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
emilmont 79:0c05e21ae27e 407 return __builtin_bswap32(value);
emilmont 79:0c05e21ae27e 408 #else
emilmont 79:0c05e21ae27e 409 uint32_t result;
emilmont 79:0c05e21ae27e 410
emilmont 79:0c05e21ae27e 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 79:0c05e21ae27e 412 return(result);
emilmont 79:0c05e21ae27e 413 #endif
emilmont 79:0c05e21ae27e 414 }
emilmont 79:0c05e21ae27e 415
emilmont 79:0c05e21ae27e 416
emilmont 79:0c05e21ae27e 417 /** \brief Reverse byte order (16 bit)
emilmont 79:0c05e21ae27e 418
emilmont 79:0c05e21ae27e 419 This function reverses the byte order in two unsigned short values.
emilmont 79:0c05e21ae27e 420
emilmont 79:0c05e21ae27e 421 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 422 \return Reversed value
emilmont 79:0c05e21ae27e 423 */
emilmont 79:0c05e21ae27e 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 79:0c05e21ae27e 425 {
emilmont 79:0c05e21ae27e 426 uint32_t result;
emilmont 79:0c05e21ae27e 427
emilmont 79:0c05e21ae27e 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 79:0c05e21ae27e 429 return(result);
emilmont 79:0c05e21ae27e 430 }
emilmont 79:0c05e21ae27e 431
emilmont 79:0c05e21ae27e 432
emilmont 79:0c05e21ae27e 433 /** \brief Reverse byte order in signed short value
emilmont 79:0c05e21ae27e 434
emilmont 79:0c05e21ae27e 435 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 79:0c05e21ae27e 436
emilmont 79:0c05e21ae27e 437 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 438 \return Reversed value
emilmont 79:0c05e21ae27e 439 */
emilmont 79:0c05e21ae27e 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 79:0c05e21ae27e 441 {
emilmont 79:0c05e21ae27e 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 79:0c05e21ae27e 443 return (short)__builtin_bswap16(value);
emilmont 79:0c05e21ae27e 444 #else
emilmont 79:0c05e21ae27e 445 uint32_t result;
emilmont 79:0c05e21ae27e 446
emilmont 79:0c05e21ae27e 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 79:0c05e21ae27e 448 return(result);
emilmont 79:0c05e21ae27e 449 #endif
emilmont 79:0c05e21ae27e 450 }
emilmont 79:0c05e21ae27e 451
emilmont 79:0c05e21ae27e 452
emilmont 79:0c05e21ae27e 453 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 79:0c05e21ae27e 454
emilmont 79:0c05e21ae27e 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 79:0c05e21ae27e 456
emilmont 79:0c05e21ae27e 457 \param [in] value Value to rotate
emilmont 79:0c05e21ae27e 458 \param [in] value Number of Bits to rotate
emilmont 79:0c05e21ae27e 459 \return Rotated value
emilmont 79:0c05e21ae27e 460 */
emilmont 79:0c05e21ae27e 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 462 {
emilmont 79:0c05e21ae27e 463 return (op1 >> op2) | (op1 << (32 - op2));
emilmont 79:0c05e21ae27e 464 }
emilmont 79:0c05e21ae27e 465
emilmont 79:0c05e21ae27e 466
emilmont 79:0c05e21ae27e 467 /** \brief Breakpoint
emilmont 79:0c05e21ae27e 468
emilmont 79:0c05e21ae27e 469 This function causes the processor to enter Debug state.
emilmont 79:0c05e21ae27e 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 79:0c05e21ae27e 471
emilmont 79:0c05e21ae27e 472 \param [in] value is ignored by the processor.
emilmont 79:0c05e21ae27e 473 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 79:0c05e21ae27e 474 */
emilmont 79:0c05e21ae27e 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
emilmont 79:0c05e21ae27e 476
emilmont 79:0c05e21ae27e 477
emilmont 79:0c05e21ae27e 478 #if (__CORTEX_M >= 0x03)
emilmont 79:0c05e21ae27e 479
emilmont 79:0c05e21ae27e 480 /** \brief Reverse bit order of value
emilmont 79:0c05e21ae27e 481
emilmont 79:0c05e21ae27e 482 This function reverses the bit order of the given value.
emilmont 79:0c05e21ae27e 483
emilmont 79:0c05e21ae27e 484 \param [in] value Value to reverse
emilmont 79:0c05e21ae27e 485 \return Reversed value
emilmont 79:0c05e21ae27e 486 */
emilmont 79:0c05e21ae27e 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 79:0c05e21ae27e 488 {
emilmont 79:0c05e21ae27e 489 uint32_t result;
emilmont 79:0c05e21ae27e 490
emilmont 79:0c05e21ae27e 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 79:0c05e21ae27e 492 return(result);
emilmont 79:0c05e21ae27e 493 }
emilmont 79:0c05e21ae27e 494
emilmont 79:0c05e21ae27e 495
emilmont 79:0c05e21ae27e 496 /** \brief LDR Exclusive (8 bit)
emilmont 79:0c05e21ae27e 497
emilmont 79:0c05e21ae27e 498 This function performs a exclusive LDR command for 8 bit value.
emilmont 79:0c05e21ae27e 499
emilmont 79:0c05e21ae27e 500 \param [in] ptr Pointer to data
emilmont 79:0c05e21ae27e 501 \return value of type uint8_t at (*ptr)
emilmont 79:0c05e21ae27e 502 */
emilmont 79:0c05e21ae27e 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 79:0c05e21ae27e 504 {
emilmont 79:0c05e21ae27e 505 uint32_t result;
emilmont 79:0c05e21ae27e 506
emilmont 79:0c05e21ae27e 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 79:0c05e21ae27e 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 79:0c05e21ae27e 509 #else
emilmont 79:0c05e21ae27e 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 79:0c05e21ae27e 511 accepted by assembler. So has to use following less efficient pattern.
emilmont 79:0c05e21ae27e 512 */
emilmont 79:0c05e21ae27e 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 79:0c05e21ae27e 514 #endif
emilmont 79:0c05e21ae27e 515 return(result);
emilmont 79:0c05e21ae27e 516 }
emilmont 79:0c05e21ae27e 517
emilmont 79:0c05e21ae27e 518
emilmont 79:0c05e21ae27e 519 /** \brief LDR Exclusive (16 bit)
emilmont 79:0c05e21ae27e 520
emilmont 79:0c05e21ae27e 521 This function performs a exclusive LDR command for 16 bit values.
emilmont 79:0c05e21ae27e 522
emilmont 79:0c05e21ae27e 523 \param [in] ptr Pointer to data
emilmont 79:0c05e21ae27e 524 \return value of type uint16_t at (*ptr)
emilmont 79:0c05e21ae27e 525 */
emilmont 79:0c05e21ae27e 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 79:0c05e21ae27e 527 {
emilmont 79:0c05e21ae27e 528 uint32_t result;
emilmont 79:0c05e21ae27e 529
emilmont 79:0c05e21ae27e 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 79:0c05e21ae27e 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 79:0c05e21ae27e 532 #else
emilmont 79:0c05e21ae27e 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 79:0c05e21ae27e 534 accepted by assembler. So has to use following less efficient pattern.
emilmont 79:0c05e21ae27e 535 */
emilmont 79:0c05e21ae27e 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 79:0c05e21ae27e 537 #endif
emilmont 79:0c05e21ae27e 538 return(result);
emilmont 79:0c05e21ae27e 539 }
emilmont 79:0c05e21ae27e 540
emilmont 79:0c05e21ae27e 541
emilmont 79:0c05e21ae27e 542 /** \brief LDR Exclusive (32 bit)
emilmont 79:0c05e21ae27e 543
emilmont 79:0c05e21ae27e 544 This function performs a exclusive LDR command for 32 bit values.
emilmont 79:0c05e21ae27e 545
emilmont 79:0c05e21ae27e 546 \param [in] ptr Pointer to data
emilmont 79:0c05e21ae27e 547 \return value of type uint32_t at (*ptr)
emilmont 79:0c05e21ae27e 548 */
emilmont 79:0c05e21ae27e 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 79:0c05e21ae27e 550 {
emilmont 79:0c05e21ae27e 551 uint32_t result;
emilmont 79:0c05e21ae27e 552
emilmont 79:0c05e21ae27e 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 79:0c05e21ae27e 554 return(result);
emilmont 79:0c05e21ae27e 555 }
emilmont 79:0c05e21ae27e 556
emilmont 79:0c05e21ae27e 557
emilmont 79:0c05e21ae27e 558 /** \brief STR Exclusive (8 bit)
emilmont 79:0c05e21ae27e 559
emilmont 79:0c05e21ae27e 560 This function performs a exclusive STR command for 8 bit values.
emilmont 79:0c05e21ae27e 561
emilmont 79:0c05e21ae27e 562 \param [in] value Value to store
emilmont 79:0c05e21ae27e 563 \param [in] ptr Pointer to location
emilmont 79:0c05e21ae27e 564 \return 0 Function succeeded
emilmont 79:0c05e21ae27e 565 \return 1 Function failed
emilmont 79:0c05e21ae27e 566 */
emilmont 79:0c05e21ae27e 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 79:0c05e21ae27e 568 {
emilmont 79:0c05e21ae27e 569 uint32_t result;
emilmont 79:0c05e21ae27e 570
emilmont 79:0c05e21ae27e 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 79:0c05e21ae27e 572 return(result);
emilmont 79:0c05e21ae27e 573 }
emilmont 79:0c05e21ae27e 574
emilmont 79:0c05e21ae27e 575
emilmont 79:0c05e21ae27e 576 /** \brief STR Exclusive (16 bit)
emilmont 79:0c05e21ae27e 577
emilmont 79:0c05e21ae27e 578 This function performs a exclusive STR command for 16 bit values.
emilmont 79:0c05e21ae27e 579
emilmont 79:0c05e21ae27e 580 \param [in] value Value to store
emilmont 79:0c05e21ae27e 581 \param [in] ptr Pointer to location
emilmont 79:0c05e21ae27e 582 \return 0 Function succeeded
emilmont 79:0c05e21ae27e 583 \return 1 Function failed
emilmont 79:0c05e21ae27e 584 */
emilmont 79:0c05e21ae27e 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 79:0c05e21ae27e 586 {
emilmont 79:0c05e21ae27e 587 uint32_t result;
emilmont 79:0c05e21ae27e 588
emilmont 79:0c05e21ae27e 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 79:0c05e21ae27e 590 return(result);
emilmont 79:0c05e21ae27e 591 }
emilmont 79:0c05e21ae27e 592
emilmont 79:0c05e21ae27e 593
emilmont 79:0c05e21ae27e 594 /** \brief STR Exclusive (32 bit)
emilmont 79:0c05e21ae27e 595
emilmont 79:0c05e21ae27e 596 This function performs a exclusive STR command for 32 bit values.
emilmont 79:0c05e21ae27e 597
emilmont 79:0c05e21ae27e 598 \param [in] value Value to store
emilmont 79:0c05e21ae27e 599 \param [in] ptr Pointer to location
emilmont 79:0c05e21ae27e 600 \return 0 Function succeeded
emilmont 79:0c05e21ae27e 601 \return 1 Function failed
emilmont 79:0c05e21ae27e 602 */
emilmont 79:0c05e21ae27e 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 79:0c05e21ae27e 604 {
emilmont 79:0c05e21ae27e 605 uint32_t result;
emilmont 79:0c05e21ae27e 606
emilmont 79:0c05e21ae27e 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 79:0c05e21ae27e 608 return(result);
emilmont 79:0c05e21ae27e 609 }
emilmont 79:0c05e21ae27e 610
emilmont 79:0c05e21ae27e 611
emilmont 79:0c05e21ae27e 612 /** \brief Remove the exclusive lock
emilmont 79:0c05e21ae27e 613
emilmont 79:0c05e21ae27e 614 This function removes the exclusive lock which is created by LDREX.
emilmont 79:0c05e21ae27e 615
emilmont 79:0c05e21ae27e 616 */
emilmont 79:0c05e21ae27e 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
emilmont 79:0c05e21ae27e 618 {
emilmont 79:0c05e21ae27e 619 __ASM volatile ("clrex" ::: "memory");
emilmont 79:0c05e21ae27e 620 }
emilmont 79:0c05e21ae27e 621
emilmont 79:0c05e21ae27e 622
emilmont 79:0c05e21ae27e 623 /** \brief Signed Saturate
emilmont 79:0c05e21ae27e 624
emilmont 79:0c05e21ae27e 625 This function saturates a signed value.
emilmont 79:0c05e21ae27e 626
emilmont 79:0c05e21ae27e 627 \param [in] value Value to be saturated
emilmont 79:0c05e21ae27e 628 \param [in] sat Bit position to saturate to (1..32)
emilmont 79:0c05e21ae27e 629 \return Saturated value
emilmont 79:0c05e21ae27e 630 */
emilmont 79:0c05e21ae27e 631 #define __SSAT(ARG1,ARG2) \
emilmont 79:0c05e21ae27e 632 ({ \
emilmont 79:0c05e21ae27e 633 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 79:0c05e21ae27e 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 79:0c05e21ae27e 635 __RES; \
emilmont 79:0c05e21ae27e 636 })
emilmont 79:0c05e21ae27e 637
emilmont 79:0c05e21ae27e 638
emilmont 79:0c05e21ae27e 639 /** \brief Unsigned Saturate
emilmont 79:0c05e21ae27e 640
emilmont 79:0c05e21ae27e 641 This function saturates an unsigned value.
emilmont 79:0c05e21ae27e 642
emilmont 79:0c05e21ae27e 643 \param [in] value Value to be saturated
emilmont 79:0c05e21ae27e 644 \param [in] sat Bit position to saturate to (0..31)
emilmont 79:0c05e21ae27e 645 \return Saturated value
emilmont 79:0c05e21ae27e 646 */
emilmont 79:0c05e21ae27e 647 #define __USAT(ARG1,ARG2) \
emilmont 79:0c05e21ae27e 648 ({ \
emilmont 79:0c05e21ae27e 649 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 79:0c05e21ae27e 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 79:0c05e21ae27e 651 __RES; \
emilmont 79:0c05e21ae27e 652 })
emilmont 79:0c05e21ae27e 653
emilmont 79:0c05e21ae27e 654
emilmont 79:0c05e21ae27e 655 /** \brief Count leading zeros
emilmont 79:0c05e21ae27e 656
emilmont 79:0c05e21ae27e 657 This function counts the number of leading zeros of a data value.
emilmont 79:0c05e21ae27e 658
emilmont 79:0c05e21ae27e 659 \param [in] value Value to count the leading zeros
emilmont 79:0c05e21ae27e 660 \return number of leading zeros in value
emilmont 79:0c05e21ae27e 661 */
emilmont 79:0c05e21ae27e 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
emilmont 79:0c05e21ae27e 663 {
emilmont 79:0c05e21ae27e 664 uint32_t result;
emilmont 79:0c05e21ae27e 665
emilmont 79:0c05e21ae27e 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 79:0c05e21ae27e 667 return(result);
emilmont 79:0c05e21ae27e 668 }
emilmont 79:0c05e21ae27e 669
emilmont 79:0c05e21ae27e 670 #endif /* (__CORTEX_M >= 0x03) */
emilmont 79:0c05e21ae27e 671
emilmont 79:0c05e21ae27e 672
emilmont 79:0c05e21ae27e 673
emilmont 79:0c05e21ae27e 674
emilmont 79:0c05e21ae27e 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 79:0c05e21ae27e 676 /* TASKING carm specific functions */
emilmont 79:0c05e21ae27e 677
emilmont 79:0c05e21ae27e 678 /*
emilmont 79:0c05e21ae27e 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 79:0c05e21ae27e 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 79:0c05e21ae27e 681 * Including the CMSIS ones.
emilmont 79:0c05e21ae27e 682 */
emilmont 79:0c05e21ae27e 683
emilmont 79:0c05e21ae27e 684 #endif
emilmont 79:0c05e21ae27e 685
emilmont 79:0c05e21ae27e 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 79:0c05e21ae27e 687
emilmont 79:0c05e21ae27e 688 #endif /* __CORE_CMINSTR_H */