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TARGET_LPC1549/core_cmFunc.h@79:0c05e21ae27e, 2014-02-21 (annotated)

Committer:
emilmont
Date:
Fri Feb 21 10:26:12 2014 +0000
Revision:
79:0c05e21ae27e
Child:
110:165afa46840b
Add LPC1549 Target

Change "us_ticker" implementation to 32-bit timer for NUCLEO_L152RE and NUCLEO_F401RE

Update KL05Z CMSIS-CORE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 79:0c05e21ae27e 1 /**************************************************************************//**
emilmont 79:0c05e21ae27e 2 * @file core_cmFunc.h
emilmont 79:0c05e21ae27e 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 79:0c05e21ae27e 4 * @version V3.20
emilmont 79:0c05e21ae27e 5 * @date 25. February 2013
emilmont 79:0c05e21ae27e 6 *
emilmont 79:0c05e21ae27e 7 * @note
emilmont 79:0c05e21ae27e 8 *
emilmont 79:0c05e21ae27e 9 ******************************************************************************/
emilmont 79:0c05e21ae27e 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 79:0c05e21ae27e 11
emilmont 79:0c05e21ae27e 12 All rights reserved.
emilmont 79:0c05e21ae27e 13 Redistribution and use in source and binary forms, with or without
emilmont 79:0c05e21ae27e 14 modification, are permitted provided that the following conditions are met:
emilmont 79:0c05e21ae27e 15 - Redistributions of source code must retain the above copyright
emilmont 79:0c05e21ae27e 16 notice, this list of conditions and the following disclaimer.
emilmont 79:0c05e21ae27e 17 - Redistributions in binary form must reproduce the above copyright
emilmont 79:0c05e21ae27e 18 notice, this list of conditions and the following disclaimer in the
emilmont 79:0c05e21ae27e 19 documentation and/or other materials provided with the distribution.
emilmont 79:0c05e21ae27e 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 79:0c05e21ae27e 21 to endorse or promote products derived from this software without
emilmont 79:0c05e21ae27e 22 specific prior written permission.
emilmont 79:0c05e21ae27e 23 *
emilmont 79:0c05e21ae27e 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 79:0c05e21ae27e 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 79:0c05e21ae27e 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 79:0c05e21ae27e 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 79:0c05e21ae27e 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 79:0c05e21ae27e 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 79:0c05e21ae27e 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 79:0c05e21ae27e 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 79:0c05e21ae27e 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 79:0c05e21ae27e 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 79:0c05e21ae27e 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 79:0c05e21ae27e 35 ---------------------------------------------------------------------------*/
emilmont 79:0c05e21ae27e 36
emilmont 79:0c05e21ae27e 37
emilmont 79:0c05e21ae27e 38 #ifndef __CORE_CMFUNC_H
emilmont 79:0c05e21ae27e 39 #define __CORE_CMFUNC_H
emilmont 79:0c05e21ae27e 40
emilmont 79:0c05e21ae27e 41
emilmont 79:0c05e21ae27e 42 /* ########################### Core Function Access ########################### */
emilmont 79:0c05e21ae27e 43 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 79:0c05e21ae27e 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 79:0c05e21ae27e 45 @{
emilmont 79:0c05e21ae27e 46 */
emilmont 79:0c05e21ae27e 47
emilmont 79:0c05e21ae27e 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 79:0c05e21ae27e 49 /* ARM armcc specific functions */
emilmont 79:0c05e21ae27e 50
emilmont 79:0c05e21ae27e 51 #if (__ARMCC_VERSION < 400677)
emilmont 79:0c05e21ae27e 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 79:0c05e21ae27e 53 #endif
emilmont 79:0c05e21ae27e 54
emilmont 79:0c05e21ae27e 55 /* intrinsic void __enable_irq(); */
emilmont 79:0c05e21ae27e 56 /* intrinsic void __disable_irq(); */
emilmont 79:0c05e21ae27e 57
emilmont 79:0c05e21ae27e 58 /** \brief Get Control Register
emilmont 79:0c05e21ae27e 59
emilmont 79:0c05e21ae27e 60 This function returns the content of the Control Register.
emilmont 79:0c05e21ae27e 61
emilmont 79:0c05e21ae27e 62 \return Control Register value
emilmont 79:0c05e21ae27e 63 */
emilmont 79:0c05e21ae27e 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 79:0c05e21ae27e 65 {
emilmont 79:0c05e21ae27e 66 register uint32_t __regControl __ASM("control");
emilmont 79:0c05e21ae27e 67 return(__regControl);
emilmont 79:0c05e21ae27e 68 }
emilmont 79:0c05e21ae27e 69
emilmont 79:0c05e21ae27e 70
emilmont 79:0c05e21ae27e 71 /** \brief Set Control Register
emilmont 79:0c05e21ae27e 72
emilmont 79:0c05e21ae27e 73 This function writes the given value to the Control Register.
emilmont 79:0c05e21ae27e 74
emilmont 79:0c05e21ae27e 75 \param [in] control Control Register value to set
emilmont 79:0c05e21ae27e 76 */
emilmont 79:0c05e21ae27e 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 79:0c05e21ae27e 78 {
emilmont 79:0c05e21ae27e 79 register uint32_t __regControl __ASM("control");
emilmont 79:0c05e21ae27e 80 __regControl = control;
emilmont 79:0c05e21ae27e 81 }
emilmont 79:0c05e21ae27e 82
emilmont 79:0c05e21ae27e 83
emilmont 79:0c05e21ae27e 84 /** \brief Get IPSR Register
emilmont 79:0c05e21ae27e 85
emilmont 79:0c05e21ae27e 86 This function returns the content of the IPSR Register.
emilmont 79:0c05e21ae27e 87
emilmont 79:0c05e21ae27e 88 \return IPSR Register value
emilmont 79:0c05e21ae27e 89 */
emilmont 79:0c05e21ae27e 90 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 79:0c05e21ae27e 91 {
emilmont 79:0c05e21ae27e 92 register uint32_t __regIPSR __ASM("ipsr");
emilmont 79:0c05e21ae27e 93 return(__regIPSR);
emilmont 79:0c05e21ae27e 94 }
emilmont 79:0c05e21ae27e 95
emilmont 79:0c05e21ae27e 96
emilmont 79:0c05e21ae27e 97 /** \brief Get APSR Register
emilmont 79:0c05e21ae27e 98
emilmont 79:0c05e21ae27e 99 This function returns the content of the APSR Register.
emilmont 79:0c05e21ae27e 100
emilmont 79:0c05e21ae27e 101 \return APSR Register value
emilmont 79:0c05e21ae27e 102 */
emilmont 79:0c05e21ae27e 103 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 79:0c05e21ae27e 104 {
emilmont 79:0c05e21ae27e 105 register uint32_t __regAPSR __ASM("apsr");
emilmont 79:0c05e21ae27e 106 return(__regAPSR);
emilmont 79:0c05e21ae27e 107 }
emilmont 79:0c05e21ae27e 108
emilmont 79:0c05e21ae27e 109
emilmont 79:0c05e21ae27e 110 /** \brief Get xPSR Register
emilmont 79:0c05e21ae27e 111
emilmont 79:0c05e21ae27e 112 This function returns the content of the xPSR Register.
emilmont 79:0c05e21ae27e 113
emilmont 79:0c05e21ae27e 114 \return xPSR Register value
emilmont 79:0c05e21ae27e 115 */
emilmont 79:0c05e21ae27e 116 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 79:0c05e21ae27e 117 {
emilmont 79:0c05e21ae27e 118 register uint32_t __regXPSR __ASM("xpsr");
emilmont 79:0c05e21ae27e 119 return(__regXPSR);
emilmont 79:0c05e21ae27e 120 }
emilmont 79:0c05e21ae27e 121
emilmont 79:0c05e21ae27e 122
emilmont 79:0c05e21ae27e 123 /** \brief Get Process Stack Pointer
emilmont 79:0c05e21ae27e 124
emilmont 79:0c05e21ae27e 125 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 79:0c05e21ae27e 126
emilmont 79:0c05e21ae27e 127 \return PSP Register value
emilmont 79:0c05e21ae27e 128 */
emilmont 79:0c05e21ae27e 129 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 79:0c05e21ae27e 130 {
emilmont 79:0c05e21ae27e 131 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 79:0c05e21ae27e 132 return(__regProcessStackPointer);
emilmont 79:0c05e21ae27e 133 }
emilmont 79:0c05e21ae27e 134
emilmont 79:0c05e21ae27e 135
emilmont 79:0c05e21ae27e 136 /** \brief Set Process Stack Pointer
emilmont 79:0c05e21ae27e 137
emilmont 79:0c05e21ae27e 138 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 79:0c05e21ae27e 139
emilmont 79:0c05e21ae27e 140 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 79:0c05e21ae27e 141 */
emilmont 79:0c05e21ae27e 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 79:0c05e21ae27e 143 {
emilmont 79:0c05e21ae27e 144 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 79:0c05e21ae27e 145 __regProcessStackPointer = topOfProcStack;
emilmont 79:0c05e21ae27e 146 }
emilmont 79:0c05e21ae27e 147
emilmont 79:0c05e21ae27e 148
emilmont 79:0c05e21ae27e 149 /** \brief Get Main Stack Pointer
emilmont 79:0c05e21ae27e 150
emilmont 79:0c05e21ae27e 151 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 79:0c05e21ae27e 152
emilmont 79:0c05e21ae27e 153 \return MSP Register value
emilmont 79:0c05e21ae27e 154 */
emilmont 79:0c05e21ae27e 155 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 79:0c05e21ae27e 156 {
emilmont 79:0c05e21ae27e 157 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 79:0c05e21ae27e 158 return(__regMainStackPointer);
emilmont 79:0c05e21ae27e 159 }
emilmont 79:0c05e21ae27e 160
emilmont 79:0c05e21ae27e 161
emilmont 79:0c05e21ae27e 162 /** \brief Set Main Stack Pointer
emilmont 79:0c05e21ae27e 163
emilmont 79:0c05e21ae27e 164 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 79:0c05e21ae27e 165
emilmont 79:0c05e21ae27e 166 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 79:0c05e21ae27e 167 */
emilmont 79:0c05e21ae27e 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 79:0c05e21ae27e 169 {
emilmont 79:0c05e21ae27e 170 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 79:0c05e21ae27e 171 __regMainStackPointer = topOfMainStack;
emilmont 79:0c05e21ae27e 172 }
emilmont 79:0c05e21ae27e 173
emilmont 79:0c05e21ae27e 174
emilmont 79:0c05e21ae27e 175 /** \brief Get Priority Mask
emilmont 79:0c05e21ae27e 176
emilmont 79:0c05e21ae27e 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 79:0c05e21ae27e 178
emilmont 79:0c05e21ae27e 179 \return Priority Mask value
emilmont 79:0c05e21ae27e 180 */
emilmont 79:0c05e21ae27e 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 79:0c05e21ae27e 182 {
emilmont 79:0c05e21ae27e 183 register uint32_t __regPriMask __ASM("primask");
emilmont 79:0c05e21ae27e 184 return(__regPriMask);
emilmont 79:0c05e21ae27e 185 }
emilmont 79:0c05e21ae27e 186
emilmont 79:0c05e21ae27e 187
emilmont 79:0c05e21ae27e 188 /** \brief Set Priority Mask
emilmont 79:0c05e21ae27e 189
emilmont 79:0c05e21ae27e 190 This function assigns the given value to the Priority Mask Register.
emilmont 79:0c05e21ae27e 191
emilmont 79:0c05e21ae27e 192 \param [in] priMask Priority Mask
emilmont 79:0c05e21ae27e 193 */
emilmont 79:0c05e21ae27e 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 79:0c05e21ae27e 195 {
emilmont 79:0c05e21ae27e 196 register uint32_t __regPriMask __ASM("primask");
emilmont 79:0c05e21ae27e 197 __regPriMask = (priMask);
emilmont 79:0c05e21ae27e 198 }
emilmont 79:0c05e21ae27e 199
emilmont 79:0c05e21ae27e 200
emilmont 79:0c05e21ae27e 201 #if (__CORTEX_M >= 0x03)
emilmont 79:0c05e21ae27e 202
emilmont 79:0c05e21ae27e 203 /** \brief Enable FIQ
emilmont 79:0c05e21ae27e 204
emilmont 79:0c05e21ae27e 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 79:0c05e21ae27e 206 Can only be executed in Privileged modes.
emilmont 79:0c05e21ae27e 207 */
emilmont 79:0c05e21ae27e 208 #define __enable_fault_irq __enable_fiq
emilmont 79:0c05e21ae27e 209
emilmont 79:0c05e21ae27e 210
emilmont 79:0c05e21ae27e 211 /** \brief Disable FIQ
emilmont 79:0c05e21ae27e 212
emilmont 79:0c05e21ae27e 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 79:0c05e21ae27e 214 Can only be executed in Privileged modes.
emilmont 79:0c05e21ae27e 215 */
emilmont 79:0c05e21ae27e 216 #define __disable_fault_irq __disable_fiq
emilmont 79:0c05e21ae27e 217
emilmont 79:0c05e21ae27e 218
emilmont 79:0c05e21ae27e 219 /** \brief Get Base Priority
emilmont 79:0c05e21ae27e 220
emilmont 79:0c05e21ae27e 221 This function returns the current value of the Base Priority register.
emilmont 79:0c05e21ae27e 222
emilmont 79:0c05e21ae27e 223 \return Base Priority register value
emilmont 79:0c05e21ae27e 224 */
emilmont 79:0c05e21ae27e 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 79:0c05e21ae27e 226 {
emilmont 79:0c05e21ae27e 227 register uint32_t __regBasePri __ASM("basepri");
emilmont 79:0c05e21ae27e 228 return(__regBasePri);
emilmont 79:0c05e21ae27e 229 }
emilmont 79:0c05e21ae27e 230
emilmont 79:0c05e21ae27e 231
emilmont 79:0c05e21ae27e 232 /** \brief Set Base Priority
emilmont 79:0c05e21ae27e 233
emilmont 79:0c05e21ae27e 234 This function assigns the given value to the Base Priority register.
emilmont 79:0c05e21ae27e 235
emilmont 79:0c05e21ae27e 236 \param [in] basePri Base Priority value to set
emilmont 79:0c05e21ae27e 237 */
emilmont 79:0c05e21ae27e 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 79:0c05e21ae27e 239 {
emilmont 79:0c05e21ae27e 240 register uint32_t __regBasePri __ASM("basepri");
emilmont 79:0c05e21ae27e 241 __regBasePri = (basePri & 0xff);
emilmont 79:0c05e21ae27e 242 }
emilmont 79:0c05e21ae27e 243
emilmont 79:0c05e21ae27e 244
emilmont 79:0c05e21ae27e 245 /** \brief Get Fault Mask
emilmont 79:0c05e21ae27e 246
emilmont 79:0c05e21ae27e 247 This function returns the current value of the Fault Mask register.
emilmont 79:0c05e21ae27e 248
emilmont 79:0c05e21ae27e 249 \return Fault Mask register value
emilmont 79:0c05e21ae27e 250 */
emilmont 79:0c05e21ae27e 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 79:0c05e21ae27e 252 {
emilmont 79:0c05e21ae27e 253 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 79:0c05e21ae27e 254 return(__regFaultMask);
emilmont 79:0c05e21ae27e 255 }
emilmont 79:0c05e21ae27e 256
emilmont 79:0c05e21ae27e 257
emilmont 79:0c05e21ae27e 258 /** \brief Set Fault Mask
emilmont 79:0c05e21ae27e 259
emilmont 79:0c05e21ae27e 260 This function assigns the given value to the Fault Mask register.
emilmont 79:0c05e21ae27e 261
emilmont 79:0c05e21ae27e 262 \param [in] faultMask Fault Mask value to set
emilmont 79:0c05e21ae27e 263 */
emilmont 79:0c05e21ae27e 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 79:0c05e21ae27e 265 {
emilmont 79:0c05e21ae27e 266 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 79:0c05e21ae27e 267 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 79:0c05e21ae27e 268 }
emilmont 79:0c05e21ae27e 269
emilmont 79:0c05e21ae27e 270 #endif /* (__CORTEX_M >= 0x03) */
emilmont 79:0c05e21ae27e 271
emilmont 79:0c05e21ae27e 272
emilmont 79:0c05e21ae27e 273 #if (__CORTEX_M == 0x04)
emilmont 79:0c05e21ae27e 274
emilmont 79:0c05e21ae27e 275 /** \brief Get FPSCR
emilmont 79:0c05e21ae27e 276
emilmont 79:0c05e21ae27e 277 This function returns the current value of the Floating Point Status/Control register.
emilmont 79:0c05e21ae27e 278
emilmont 79:0c05e21ae27e 279 \return Floating Point Status/Control register value
emilmont 79:0c05e21ae27e 280 */
emilmont 79:0c05e21ae27e 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 79:0c05e21ae27e 282 {
emilmont 79:0c05e21ae27e 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 79:0c05e21ae27e 284 register uint32_t __regfpscr __ASM("fpscr");
emilmont 79:0c05e21ae27e 285 return(__regfpscr);
emilmont 79:0c05e21ae27e 286 #else
emilmont 79:0c05e21ae27e 287 return(0);
emilmont 79:0c05e21ae27e 288 #endif
emilmont 79:0c05e21ae27e 289 }
emilmont 79:0c05e21ae27e 290
emilmont 79:0c05e21ae27e 291
emilmont 79:0c05e21ae27e 292 /** \brief Set FPSCR
emilmont 79:0c05e21ae27e 293
emilmont 79:0c05e21ae27e 294 This function assigns the given value to the Floating Point Status/Control register.
emilmont 79:0c05e21ae27e 295
emilmont 79:0c05e21ae27e 296 \param [in] fpscr Floating Point Status/Control value to set
emilmont 79:0c05e21ae27e 297 */
emilmont 79:0c05e21ae27e 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 79:0c05e21ae27e 299 {
emilmont 79:0c05e21ae27e 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 79:0c05e21ae27e 301 register uint32_t __regfpscr __ASM("fpscr");
emilmont 79:0c05e21ae27e 302 __regfpscr = (fpscr);
emilmont 79:0c05e21ae27e 303 #endif
emilmont 79:0c05e21ae27e 304 }
emilmont 79:0c05e21ae27e 305
emilmont 79:0c05e21ae27e 306 #endif /* (__CORTEX_M == 0x04) */
emilmont 79:0c05e21ae27e 307
emilmont 79:0c05e21ae27e 308
emilmont 79:0c05e21ae27e 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 79:0c05e21ae27e 310 /* IAR iccarm specific functions */
emilmont 79:0c05e21ae27e 311
emilmont 79:0c05e21ae27e 312 #include <cmsis_iar.h>
emilmont 79:0c05e21ae27e 313
emilmont 79:0c05e21ae27e 314
emilmont 79:0c05e21ae27e 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 79:0c05e21ae27e 316 /* TI CCS specific functions */
emilmont 79:0c05e21ae27e 317
emilmont 79:0c05e21ae27e 318 #include <cmsis_ccs.h>
emilmont 79:0c05e21ae27e 319
emilmont 79:0c05e21ae27e 320
emilmont 79:0c05e21ae27e 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 79:0c05e21ae27e 322 /* GNU gcc specific functions */
emilmont 79:0c05e21ae27e 323
emilmont 79:0c05e21ae27e 324 /** \brief Enable IRQ Interrupts
emilmont 79:0c05e21ae27e 325
emilmont 79:0c05e21ae27e 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 79:0c05e21ae27e 327 Can only be executed in Privileged modes.
emilmont 79:0c05e21ae27e 328 */
emilmont 79:0c05e21ae27e 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 79:0c05e21ae27e 330 {
emilmont 79:0c05e21ae27e 331 __ASM volatile ("cpsie i" : : : "memory");
emilmont 79:0c05e21ae27e 332 }
emilmont 79:0c05e21ae27e 333
emilmont 79:0c05e21ae27e 334
emilmont 79:0c05e21ae27e 335 /** \brief Disable IRQ Interrupts
emilmont 79:0c05e21ae27e 336
emilmont 79:0c05e21ae27e 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 79:0c05e21ae27e 338 Can only be executed in Privileged modes.
emilmont 79:0c05e21ae27e 339 */
emilmont 79:0c05e21ae27e 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 79:0c05e21ae27e 341 {
emilmont 79:0c05e21ae27e 342 __ASM volatile ("cpsid i" : : : "memory");
emilmont 79:0c05e21ae27e 343 }
emilmont 79:0c05e21ae27e 344
emilmont 79:0c05e21ae27e 345
emilmont 79:0c05e21ae27e 346 /** \brief Get Control Register
emilmont 79:0c05e21ae27e 347
emilmont 79:0c05e21ae27e 348 This function returns the content of the Control Register.
emilmont 79:0c05e21ae27e 349
emilmont 79:0c05e21ae27e 350 \return Control Register value
emilmont 79:0c05e21ae27e 351 */
emilmont 79:0c05e21ae27e 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 79:0c05e21ae27e 353 {
emilmont 79:0c05e21ae27e 354 uint32_t result;
emilmont 79:0c05e21ae27e 355
emilmont 79:0c05e21ae27e 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 79:0c05e21ae27e 357 return(result);
emilmont 79:0c05e21ae27e 358 }
emilmont 79:0c05e21ae27e 359
emilmont 79:0c05e21ae27e 360
emilmont 79:0c05e21ae27e 361 /** \brief Set Control Register
emilmont 79:0c05e21ae27e 362
emilmont 79:0c05e21ae27e 363 This function writes the given value to the Control Register.
emilmont 79:0c05e21ae27e 364
emilmont 79:0c05e21ae27e 365 \param [in] control Control Register value to set
emilmont 79:0c05e21ae27e 366 */
emilmont 79:0c05e21ae27e 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 79:0c05e21ae27e 368 {
emilmont 79:0c05e21ae27e 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
emilmont 79:0c05e21ae27e 370 }
emilmont 79:0c05e21ae27e 371
emilmont 79:0c05e21ae27e 372
emilmont 79:0c05e21ae27e 373 /** \brief Get IPSR Register
emilmont 79:0c05e21ae27e 374
emilmont 79:0c05e21ae27e 375 This function returns the content of the IPSR Register.
emilmont 79:0c05e21ae27e 376
emilmont 79:0c05e21ae27e 377 \return IPSR Register value
emilmont 79:0c05e21ae27e 378 */
emilmont 79:0c05e21ae27e 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 79:0c05e21ae27e 380 {
emilmont 79:0c05e21ae27e 381 uint32_t result;
emilmont 79:0c05e21ae27e 382
emilmont 79:0c05e21ae27e 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 79:0c05e21ae27e 384 return(result);
emilmont 79:0c05e21ae27e 385 }
emilmont 79:0c05e21ae27e 386
emilmont 79:0c05e21ae27e 387
emilmont 79:0c05e21ae27e 388 /** \brief Get APSR Register
emilmont 79:0c05e21ae27e 389
emilmont 79:0c05e21ae27e 390 This function returns the content of the APSR Register.
emilmont 79:0c05e21ae27e 391
emilmont 79:0c05e21ae27e 392 \return APSR Register value
emilmont 79:0c05e21ae27e 393 */
emilmont 79:0c05e21ae27e 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 79:0c05e21ae27e 395 {
emilmont 79:0c05e21ae27e 396 uint32_t result;
emilmont 79:0c05e21ae27e 397
emilmont 79:0c05e21ae27e 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 79:0c05e21ae27e 399 return(result);
emilmont 79:0c05e21ae27e 400 }
emilmont 79:0c05e21ae27e 401
emilmont 79:0c05e21ae27e 402
emilmont 79:0c05e21ae27e 403 /** \brief Get xPSR Register
emilmont 79:0c05e21ae27e 404
emilmont 79:0c05e21ae27e 405 This function returns the content of the xPSR Register.
emilmont 79:0c05e21ae27e 406
emilmont 79:0c05e21ae27e 407 \return xPSR Register value
emilmont 79:0c05e21ae27e 408 */
emilmont 79:0c05e21ae27e 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 79:0c05e21ae27e 410 {
emilmont 79:0c05e21ae27e 411 uint32_t result;
emilmont 79:0c05e21ae27e 412
emilmont 79:0c05e21ae27e 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 79:0c05e21ae27e 414 return(result);
emilmont 79:0c05e21ae27e 415 }
emilmont 79:0c05e21ae27e 416
emilmont 79:0c05e21ae27e 417
emilmont 79:0c05e21ae27e 418 /** \brief Get Process Stack Pointer
emilmont 79:0c05e21ae27e 419
emilmont 79:0c05e21ae27e 420 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 79:0c05e21ae27e 421
emilmont 79:0c05e21ae27e 422 \return PSP Register value
emilmont 79:0c05e21ae27e 423 */
emilmont 79:0c05e21ae27e 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 79:0c05e21ae27e 425 {
emilmont 79:0c05e21ae27e 426 register uint32_t result;
emilmont 79:0c05e21ae27e 427
emilmont 79:0c05e21ae27e 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 79:0c05e21ae27e 429 return(result);
emilmont 79:0c05e21ae27e 430 }
emilmont 79:0c05e21ae27e 431
emilmont 79:0c05e21ae27e 432
emilmont 79:0c05e21ae27e 433 /** \brief Set Process Stack Pointer
emilmont 79:0c05e21ae27e 434
emilmont 79:0c05e21ae27e 435 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 79:0c05e21ae27e 436
emilmont 79:0c05e21ae27e 437 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 79:0c05e21ae27e 438 */
emilmont 79:0c05e21ae27e 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 79:0c05e21ae27e 440 {
emilmont 79:0c05e21ae27e 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
emilmont 79:0c05e21ae27e 442 }
emilmont 79:0c05e21ae27e 443
emilmont 79:0c05e21ae27e 444
emilmont 79:0c05e21ae27e 445 /** \brief Get Main Stack Pointer
emilmont 79:0c05e21ae27e 446
emilmont 79:0c05e21ae27e 447 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 79:0c05e21ae27e 448
emilmont 79:0c05e21ae27e 449 \return MSP Register value
emilmont 79:0c05e21ae27e 450 */
emilmont 79:0c05e21ae27e 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 79:0c05e21ae27e 452 {
emilmont 79:0c05e21ae27e 453 register uint32_t result;
emilmont 79:0c05e21ae27e 454
emilmont 79:0c05e21ae27e 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 79:0c05e21ae27e 456 return(result);
emilmont 79:0c05e21ae27e 457 }
emilmont 79:0c05e21ae27e 458
emilmont 79:0c05e21ae27e 459
emilmont 79:0c05e21ae27e 460 /** \brief Set Main Stack Pointer
emilmont 79:0c05e21ae27e 461
emilmont 79:0c05e21ae27e 462 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 79:0c05e21ae27e 463
emilmont 79:0c05e21ae27e 464 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 79:0c05e21ae27e 465 */
emilmont 79:0c05e21ae27e 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 79:0c05e21ae27e 467 {
emilmont 79:0c05e21ae27e 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
emilmont 79:0c05e21ae27e 469 }
emilmont 79:0c05e21ae27e 470
emilmont 79:0c05e21ae27e 471
emilmont 79:0c05e21ae27e 472 /** \brief Get Priority Mask
emilmont 79:0c05e21ae27e 473
emilmont 79:0c05e21ae27e 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 79:0c05e21ae27e 475
emilmont 79:0c05e21ae27e 476 \return Priority Mask value
emilmont 79:0c05e21ae27e 477 */
emilmont 79:0c05e21ae27e 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 79:0c05e21ae27e 479 {
emilmont 79:0c05e21ae27e 480 uint32_t result;
emilmont 79:0c05e21ae27e 481
emilmont 79:0c05e21ae27e 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 79:0c05e21ae27e 483 return(result);
emilmont 79:0c05e21ae27e 484 }
emilmont 79:0c05e21ae27e 485
emilmont 79:0c05e21ae27e 486
emilmont 79:0c05e21ae27e 487 /** \brief Set Priority Mask
emilmont 79:0c05e21ae27e 488
emilmont 79:0c05e21ae27e 489 This function assigns the given value to the Priority Mask Register.
emilmont 79:0c05e21ae27e 490
emilmont 79:0c05e21ae27e 491 \param [in] priMask Priority Mask
emilmont 79:0c05e21ae27e 492 */
emilmont 79:0c05e21ae27e 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 79:0c05e21ae27e 494 {
emilmont 79:0c05e21ae27e 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
emilmont 79:0c05e21ae27e 496 }
emilmont 79:0c05e21ae27e 497
emilmont 79:0c05e21ae27e 498
emilmont 79:0c05e21ae27e 499 #if (__CORTEX_M >= 0x03)
emilmont 79:0c05e21ae27e 500
emilmont 79:0c05e21ae27e 501 /** \brief Enable FIQ
emilmont 79:0c05e21ae27e 502
emilmont 79:0c05e21ae27e 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 79:0c05e21ae27e 504 Can only be executed in Privileged modes.
emilmont 79:0c05e21ae27e 505 */
emilmont 79:0c05e21ae27e 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 79:0c05e21ae27e 507 {
emilmont 79:0c05e21ae27e 508 __ASM volatile ("cpsie f" : : : "memory");
emilmont 79:0c05e21ae27e 509 }
emilmont 79:0c05e21ae27e 510
emilmont 79:0c05e21ae27e 511
emilmont 79:0c05e21ae27e 512 /** \brief Disable FIQ
emilmont 79:0c05e21ae27e 513
emilmont 79:0c05e21ae27e 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 79:0c05e21ae27e 515 Can only be executed in Privileged modes.
emilmont 79:0c05e21ae27e 516 */
emilmont 79:0c05e21ae27e 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 79:0c05e21ae27e 518 {
emilmont 79:0c05e21ae27e 519 __ASM volatile ("cpsid f" : : : "memory");
emilmont 79:0c05e21ae27e 520 }
emilmont 79:0c05e21ae27e 521
emilmont 79:0c05e21ae27e 522
emilmont 79:0c05e21ae27e 523 /** \brief Get Base Priority
emilmont 79:0c05e21ae27e 524
emilmont 79:0c05e21ae27e 525 This function returns the current value of the Base Priority register.
emilmont 79:0c05e21ae27e 526
emilmont 79:0c05e21ae27e 527 \return Base Priority register value
emilmont 79:0c05e21ae27e 528 */
emilmont 79:0c05e21ae27e 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 79:0c05e21ae27e 530 {
emilmont 79:0c05e21ae27e 531 uint32_t result;
emilmont 79:0c05e21ae27e 532
emilmont 79:0c05e21ae27e 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 79:0c05e21ae27e 534 return(result);
emilmont 79:0c05e21ae27e 535 }
emilmont 79:0c05e21ae27e 536
emilmont 79:0c05e21ae27e 537
emilmont 79:0c05e21ae27e 538 /** \brief Set Base Priority
emilmont 79:0c05e21ae27e 539
emilmont 79:0c05e21ae27e 540 This function assigns the given value to the Base Priority register.
emilmont 79:0c05e21ae27e 541
emilmont 79:0c05e21ae27e 542 \param [in] basePri Base Priority value to set
emilmont 79:0c05e21ae27e 543 */
emilmont 79:0c05e21ae27e 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 79:0c05e21ae27e 545 {
emilmont 79:0c05e21ae27e 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
emilmont 79:0c05e21ae27e 547 }
emilmont 79:0c05e21ae27e 548
emilmont 79:0c05e21ae27e 549
emilmont 79:0c05e21ae27e 550 /** \brief Get Fault Mask
emilmont 79:0c05e21ae27e 551
emilmont 79:0c05e21ae27e 552 This function returns the current value of the Fault Mask register.
emilmont 79:0c05e21ae27e 553
emilmont 79:0c05e21ae27e 554 \return Fault Mask register value
emilmont 79:0c05e21ae27e 555 */
emilmont 79:0c05e21ae27e 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 79:0c05e21ae27e 557 {
emilmont 79:0c05e21ae27e 558 uint32_t result;
emilmont 79:0c05e21ae27e 559
emilmont 79:0c05e21ae27e 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 79:0c05e21ae27e 561 return(result);
emilmont 79:0c05e21ae27e 562 }
emilmont 79:0c05e21ae27e 563
emilmont 79:0c05e21ae27e 564
emilmont 79:0c05e21ae27e 565 /** \brief Set Fault Mask
emilmont 79:0c05e21ae27e 566
emilmont 79:0c05e21ae27e 567 This function assigns the given value to the Fault Mask register.
emilmont 79:0c05e21ae27e 568
emilmont 79:0c05e21ae27e 569 \param [in] faultMask Fault Mask value to set
emilmont 79:0c05e21ae27e 570 */
emilmont 79:0c05e21ae27e 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 79:0c05e21ae27e 572 {
emilmont 79:0c05e21ae27e 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
emilmont 79:0c05e21ae27e 574 }
emilmont 79:0c05e21ae27e 575
emilmont 79:0c05e21ae27e 576 #endif /* (__CORTEX_M >= 0x03) */
emilmont 79:0c05e21ae27e 577
emilmont 79:0c05e21ae27e 578
emilmont 79:0c05e21ae27e 579 #if (__CORTEX_M == 0x04)
emilmont 79:0c05e21ae27e 580
emilmont 79:0c05e21ae27e 581 /** \brief Get FPSCR
emilmont 79:0c05e21ae27e 582
emilmont 79:0c05e21ae27e 583 This function returns the current value of the Floating Point Status/Control register.
emilmont 79:0c05e21ae27e 584
emilmont 79:0c05e21ae27e 585 \return Floating Point Status/Control register value
emilmont 79:0c05e21ae27e 586 */
emilmont 79:0c05e21ae27e 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 79:0c05e21ae27e 588 {
emilmont 79:0c05e21ae27e 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 79:0c05e21ae27e 590 uint32_t result;
emilmont 79:0c05e21ae27e 591
emilmont 79:0c05e21ae27e 592 /* Empty asm statement works as a scheduling barrier */
emilmont 79:0c05e21ae27e 593 __ASM volatile ("");
emilmont 79:0c05e21ae27e 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 79:0c05e21ae27e 595 __ASM volatile ("");
emilmont 79:0c05e21ae27e 596 return(result);
emilmont 79:0c05e21ae27e 597 #else
emilmont 79:0c05e21ae27e 598 return(0);
emilmont 79:0c05e21ae27e 599 #endif
emilmont 79:0c05e21ae27e 600 }
emilmont 79:0c05e21ae27e 601
emilmont 79:0c05e21ae27e 602
emilmont 79:0c05e21ae27e 603 /** \brief Set FPSCR
emilmont 79:0c05e21ae27e 604
emilmont 79:0c05e21ae27e 605 This function assigns the given value to the Floating Point Status/Control register.
emilmont 79:0c05e21ae27e 606
emilmont 79:0c05e21ae27e 607 \param [in] fpscr Floating Point Status/Control value to set
emilmont 79:0c05e21ae27e 608 */
emilmont 79:0c05e21ae27e 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 79:0c05e21ae27e 610 {
emilmont 79:0c05e21ae27e 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 79:0c05e21ae27e 612 /* Empty asm statement works as a scheduling barrier */
emilmont 79:0c05e21ae27e 613 __ASM volatile ("");
emilmont 79:0c05e21ae27e 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
emilmont 79:0c05e21ae27e 615 __ASM volatile ("");
emilmont 79:0c05e21ae27e 616 #endif
emilmont 79:0c05e21ae27e 617 }
emilmont 79:0c05e21ae27e 618
emilmont 79:0c05e21ae27e 619 #endif /* (__CORTEX_M == 0x04) */
emilmont 79:0c05e21ae27e 620
emilmont 79:0c05e21ae27e 621
emilmont 79:0c05e21ae27e 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 79:0c05e21ae27e 623 /* TASKING carm specific functions */
emilmont 79:0c05e21ae27e 624
emilmont 79:0c05e21ae27e 625 /*
emilmont 79:0c05e21ae27e 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 79:0c05e21ae27e 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 79:0c05e21ae27e 628 * Including the CMSIS ones.
emilmont 79:0c05e21ae27e 629 */
emilmont 79:0c05e21ae27e 630
emilmont 79:0c05e21ae27e 631 #endif
emilmont 79:0c05e21ae27e 632
emilmont 79:0c05e21ae27e 633 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 79:0c05e21ae27e 634
emilmont 79:0c05e21ae27e 635
emilmont 79:0c05e21ae27e 636 #endif /* __CORE_CMFUNC_H */