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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_UBLOX_EVK_NINA_B1/core_sc000.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
133:99b5ccf27215
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 133:99b5ccf27215 1 /**************************************************************************//**
<> 133:99b5ccf27215 2 * @file core_sc000.h
<> 133:99b5ccf27215 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
<> 133:99b5ccf27215 4 * @version V4.10
<> 133:99b5ccf27215 5 * @date 18. March 2015
<> 133:99b5ccf27215 6 *
<> 133:99b5ccf27215 7 * @note
<> 133:99b5ccf27215 8 *
<> 133:99b5ccf27215 9 ******************************************************************************/
<> 133:99b5ccf27215 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 133:99b5ccf27215 11
<> 133:99b5ccf27215 12 All rights reserved.
<> 133:99b5ccf27215 13 Redistribution and use in source and binary forms, with or without
<> 133:99b5ccf27215 14 modification, are permitted provided that the following conditions are met:
<> 133:99b5ccf27215 15 - Redistributions of source code must retain the above copyright
<> 133:99b5ccf27215 16 notice, this list of conditions and the following disclaimer.
<> 133:99b5ccf27215 17 - Redistributions in binary form must reproduce the above copyright
<> 133:99b5ccf27215 18 notice, this list of conditions and the following disclaimer in the
<> 133:99b5ccf27215 19 documentation and/or other materials provided with the distribution.
<> 133:99b5ccf27215 20 - Neither the name of ARM nor the names of its contributors may be used
<> 133:99b5ccf27215 21 to endorse or promote products derived from this software without
<> 133:99b5ccf27215 22 specific prior written permission.
<> 133:99b5ccf27215 23 *
<> 133:99b5ccf27215 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 133:99b5ccf27215 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 133:99b5ccf27215 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 133:99b5ccf27215 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 133:99b5ccf27215 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 133:99b5ccf27215 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 133:99b5ccf27215 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 133:99b5ccf27215 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 133:99b5ccf27215 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 133:99b5ccf27215 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 133:99b5ccf27215 34 POSSIBILITY OF SUCH DAMAGE.
<> 133:99b5ccf27215 35 ---------------------------------------------------------------------------*/
<> 133:99b5ccf27215 36
<> 133:99b5ccf27215 37
<> 133:99b5ccf27215 38 #if defined ( __ICCARM__ )
<> 133:99b5ccf27215 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 133:99b5ccf27215 40 #endif
<> 133:99b5ccf27215 41
<> 133:99b5ccf27215 42 #ifndef __CORE_SC000_H_GENERIC
<> 133:99b5ccf27215 43 #define __CORE_SC000_H_GENERIC
<> 133:99b5ccf27215 44
<> 133:99b5ccf27215 45 #ifdef __cplusplus
<> 133:99b5ccf27215 46 extern "C" {
<> 133:99b5ccf27215 47 #endif
<> 133:99b5ccf27215 48
<> 133:99b5ccf27215 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 133:99b5ccf27215 50 CMSIS violates the following MISRA-C:2004 rules:
<> 133:99b5ccf27215 51
<> 133:99b5ccf27215 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 133:99b5ccf27215 53 Function definitions in header files are used to allow 'inlining'.
<> 133:99b5ccf27215 54
<> 133:99b5ccf27215 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 133:99b5ccf27215 56 Unions are used for effective representation of core registers.
<> 133:99b5ccf27215 57
<> 133:99b5ccf27215 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 133:99b5ccf27215 59 Function-like macros are used to allow more efficient code.
<> 133:99b5ccf27215 60 */
<> 133:99b5ccf27215 61
<> 133:99b5ccf27215 62
<> 133:99b5ccf27215 63 /*******************************************************************************
<> 133:99b5ccf27215 64 * CMSIS definitions
<> 133:99b5ccf27215 65 ******************************************************************************/
<> 133:99b5ccf27215 66 /** \ingroup SC000
<> 133:99b5ccf27215 67 @{
<> 133:99b5ccf27215 68 */
<> 133:99b5ccf27215 69
<> 133:99b5ccf27215 70 /* CMSIS SC000 definitions */
<> 133:99b5ccf27215 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 133:99b5ccf27215 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 133:99b5ccf27215 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
<> 133:99b5ccf27215 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 133:99b5ccf27215 75
<> 133:99b5ccf27215 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
<> 133:99b5ccf27215 77
<> 133:99b5ccf27215 78
<> 133:99b5ccf27215 79 #if defined ( __CC_ARM )
<> 133:99b5ccf27215 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 133:99b5ccf27215 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 133:99b5ccf27215 82 #define __STATIC_INLINE static __inline
<> 133:99b5ccf27215 83
<> 133:99b5ccf27215 84 #elif defined ( __GNUC__ )
<> 133:99b5ccf27215 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 133:99b5ccf27215 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 133:99b5ccf27215 87 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 88
<> 133:99b5ccf27215 89 #elif defined ( __ICCARM__ )
<> 133:99b5ccf27215 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 133:99b5ccf27215 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 133:99b5ccf27215 92 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 93
<> 133:99b5ccf27215 94 #elif defined ( __TMS470__ )
<> 133:99b5ccf27215 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 133:99b5ccf27215 96 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 97
<> 133:99b5ccf27215 98 #elif defined ( __TASKING__ )
<> 133:99b5ccf27215 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 133:99b5ccf27215 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 133:99b5ccf27215 101 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 102
<> 133:99b5ccf27215 103 #elif defined ( __CSMC__ )
<> 133:99b5ccf27215 104 #define __packed
<> 133:99b5ccf27215 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 133:99b5ccf27215 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 133:99b5ccf27215 107 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 108
<> 133:99b5ccf27215 109 #endif
<> 133:99b5ccf27215 110
<> 133:99b5ccf27215 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 133:99b5ccf27215 112 This core does not support an FPU at all
<> 133:99b5ccf27215 113 */
<> 133:99b5ccf27215 114 #define __FPU_USED 0
<> 133:99b5ccf27215 115
<> 133:99b5ccf27215 116 #if defined ( __CC_ARM )
<> 133:99b5ccf27215 117 #if defined __TARGET_FPU_VFP
<> 133:99b5ccf27215 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 119 #endif
<> 133:99b5ccf27215 120
<> 133:99b5ccf27215 121 #elif defined ( __GNUC__ )
<> 133:99b5ccf27215 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 133:99b5ccf27215 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 124 #endif
<> 133:99b5ccf27215 125
<> 133:99b5ccf27215 126 #elif defined ( __ICCARM__ )
<> 133:99b5ccf27215 127 #if defined __ARMVFP__
<> 133:99b5ccf27215 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 129 #endif
<> 133:99b5ccf27215 130
<> 133:99b5ccf27215 131 #elif defined ( __TMS470__ )
<> 133:99b5ccf27215 132 #if defined __TI__VFP_SUPPORT____
<> 133:99b5ccf27215 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 134 #endif
<> 133:99b5ccf27215 135
<> 133:99b5ccf27215 136 #elif defined ( __TASKING__ )
<> 133:99b5ccf27215 137 #if defined __FPU_VFP__
<> 133:99b5ccf27215 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 139 #endif
<> 133:99b5ccf27215 140
<> 133:99b5ccf27215 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 133:99b5ccf27215 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 133:99b5ccf27215 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 144 #endif
<> 133:99b5ccf27215 145 #endif
<> 133:99b5ccf27215 146
<> 133:99b5ccf27215 147 #include <stdint.h> /* standard types definitions */
<> 133:99b5ccf27215 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 133:99b5ccf27215 149 #include <core_cmFunc.h> /* Core Function Access */
<> 133:99b5ccf27215 150
<> 133:99b5ccf27215 151 #ifdef __cplusplus
<> 133:99b5ccf27215 152 }
<> 133:99b5ccf27215 153 #endif
<> 133:99b5ccf27215 154
<> 133:99b5ccf27215 155 #endif /* __CORE_SC000_H_GENERIC */
<> 133:99b5ccf27215 156
<> 133:99b5ccf27215 157 #ifndef __CMSIS_GENERIC
<> 133:99b5ccf27215 158
<> 133:99b5ccf27215 159 #ifndef __CORE_SC000_H_DEPENDANT
<> 133:99b5ccf27215 160 #define __CORE_SC000_H_DEPENDANT
<> 133:99b5ccf27215 161
<> 133:99b5ccf27215 162 #ifdef __cplusplus
<> 133:99b5ccf27215 163 extern "C" {
<> 133:99b5ccf27215 164 #endif
<> 133:99b5ccf27215 165
<> 133:99b5ccf27215 166 /* check device defines and use defaults */
<> 133:99b5ccf27215 167 #if defined __CHECK_DEVICE_DEFINES
<> 133:99b5ccf27215 168 #ifndef __SC000_REV
<> 133:99b5ccf27215 169 #define __SC000_REV 0x0000
<> 133:99b5ccf27215 170 #warning "__SC000_REV not defined in device header file; using default!"
<> 133:99b5ccf27215 171 #endif
<> 133:99b5ccf27215 172
<> 133:99b5ccf27215 173 #ifndef __MPU_PRESENT
<> 133:99b5ccf27215 174 #define __MPU_PRESENT 0
<> 133:99b5ccf27215 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 133:99b5ccf27215 176 #endif
<> 133:99b5ccf27215 177
<> 133:99b5ccf27215 178 #ifndef __NVIC_PRIO_BITS
<> 133:99b5ccf27215 179 #define __NVIC_PRIO_BITS 2
<> 133:99b5ccf27215 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 133:99b5ccf27215 181 #endif
<> 133:99b5ccf27215 182
<> 133:99b5ccf27215 183 #ifndef __Vendor_SysTickConfig
<> 133:99b5ccf27215 184 #define __Vendor_SysTickConfig 0
<> 133:99b5ccf27215 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 133:99b5ccf27215 186 #endif
<> 133:99b5ccf27215 187 #endif
<> 133:99b5ccf27215 188
<> 133:99b5ccf27215 189 /* IO definitions (access restrictions to peripheral registers) */
<> 133:99b5ccf27215 190 /**
<> 133:99b5ccf27215 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 133:99b5ccf27215 192
<> 133:99b5ccf27215 193 <strong>IO Type Qualifiers</strong> are used
<> 133:99b5ccf27215 194 \li to specify the access to peripheral variables.
<> 133:99b5ccf27215 195 \li for automatic generation of peripheral register debug information.
<> 133:99b5ccf27215 196 */
<> 133:99b5ccf27215 197 #ifdef __cplusplus
<> 133:99b5ccf27215 198 #define __I volatile /*!< Defines 'read only' permissions */
<> 133:99b5ccf27215 199 #else
<> 133:99b5ccf27215 200 #define __I volatile const /*!< Defines 'read only' permissions */
<> 133:99b5ccf27215 201 #endif
<> 133:99b5ccf27215 202 #define __O volatile /*!< Defines 'write only' permissions */
<> 133:99b5ccf27215 203 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 133:99b5ccf27215 204
<> 133:99b5ccf27215 205 /*@} end of group SC000 */
<> 133:99b5ccf27215 206
<> 133:99b5ccf27215 207
<> 133:99b5ccf27215 208
<> 133:99b5ccf27215 209 /*******************************************************************************
<> 133:99b5ccf27215 210 * Register Abstraction
<> 133:99b5ccf27215 211 Core Register contain:
<> 133:99b5ccf27215 212 - Core Register
<> 133:99b5ccf27215 213 - Core NVIC Register
<> 133:99b5ccf27215 214 - Core SCB Register
<> 133:99b5ccf27215 215 - Core SysTick Register
<> 133:99b5ccf27215 216 - Core MPU Register
<> 133:99b5ccf27215 217 ******************************************************************************/
<> 133:99b5ccf27215 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 133:99b5ccf27215 219 \brief Type definitions and defines for Cortex-M processor based devices.
<> 133:99b5ccf27215 220 */
<> 133:99b5ccf27215 221
<> 133:99b5ccf27215 222 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 223 \defgroup CMSIS_CORE Status and Control Registers
<> 133:99b5ccf27215 224 \brief Core Register type definitions.
<> 133:99b5ccf27215 225 @{
<> 133:99b5ccf27215 226 */
<> 133:99b5ccf27215 227
<> 133:99b5ccf27215 228 /** \brief Union type to access the Application Program Status Register (APSR).
<> 133:99b5ccf27215 229 */
<> 133:99b5ccf27215 230 typedef union
<> 133:99b5ccf27215 231 {
<> 133:99b5ccf27215 232 struct
<> 133:99b5ccf27215 233 {
<> 133:99b5ccf27215 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 133:99b5ccf27215 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 133:99b5ccf27215 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 133:99b5ccf27215 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 133:99b5ccf27215 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 133:99b5ccf27215 239 } b; /*!< Structure used for bit access */
<> 133:99b5ccf27215 240 uint32_t w; /*!< Type used for word access */
<> 133:99b5ccf27215 241 } APSR_Type;
<> 133:99b5ccf27215 242
<> 133:99b5ccf27215 243 /* APSR Register Definitions */
<> 133:99b5ccf27215 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 133:99b5ccf27215 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 133:99b5ccf27215 246
<> 133:99b5ccf27215 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 133:99b5ccf27215 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 133:99b5ccf27215 249
<> 133:99b5ccf27215 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 133:99b5ccf27215 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 133:99b5ccf27215 252
<> 133:99b5ccf27215 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 133:99b5ccf27215 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 133:99b5ccf27215 255
<> 133:99b5ccf27215 256
<> 133:99b5ccf27215 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 133:99b5ccf27215 258 */
<> 133:99b5ccf27215 259 typedef union
<> 133:99b5ccf27215 260 {
<> 133:99b5ccf27215 261 struct
<> 133:99b5ccf27215 262 {
<> 133:99b5ccf27215 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 133:99b5ccf27215 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 133:99b5ccf27215 265 } b; /*!< Structure used for bit access */
<> 133:99b5ccf27215 266 uint32_t w; /*!< Type used for word access */
<> 133:99b5ccf27215 267 } IPSR_Type;
<> 133:99b5ccf27215 268
<> 133:99b5ccf27215 269 /* IPSR Register Definitions */
<> 133:99b5ccf27215 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 133:99b5ccf27215 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 133:99b5ccf27215 272
<> 133:99b5ccf27215 273
<> 133:99b5ccf27215 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 133:99b5ccf27215 275 */
<> 133:99b5ccf27215 276 typedef union
<> 133:99b5ccf27215 277 {
<> 133:99b5ccf27215 278 struct
<> 133:99b5ccf27215 279 {
<> 133:99b5ccf27215 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 133:99b5ccf27215 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 133:99b5ccf27215 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 133:99b5ccf27215 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 133:99b5ccf27215 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 133:99b5ccf27215 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 133:99b5ccf27215 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 133:99b5ccf27215 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 133:99b5ccf27215 288 } b; /*!< Structure used for bit access */
<> 133:99b5ccf27215 289 uint32_t w; /*!< Type used for word access */
<> 133:99b5ccf27215 290 } xPSR_Type;
<> 133:99b5ccf27215 291
<> 133:99b5ccf27215 292 /* xPSR Register Definitions */
<> 133:99b5ccf27215 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 133:99b5ccf27215 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 133:99b5ccf27215 295
<> 133:99b5ccf27215 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 133:99b5ccf27215 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 133:99b5ccf27215 298
<> 133:99b5ccf27215 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 133:99b5ccf27215 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 133:99b5ccf27215 301
<> 133:99b5ccf27215 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 133:99b5ccf27215 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 133:99b5ccf27215 304
<> 133:99b5ccf27215 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 133:99b5ccf27215 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 133:99b5ccf27215 307
<> 133:99b5ccf27215 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 133:99b5ccf27215 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 133:99b5ccf27215 310
<> 133:99b5ccf27215 311
<> 133:99b5ccf27215 312 /** \brief Union type to access the Control Registers (CONTROL).
<> 133:99b5ccf27215 313 */
<> 133:99b5ccf27215 314 typedef union
<> 133:99b5ccf27215 315 {
<> 133:99b5ccf27215 316 struct
<> 133:99b5ccf27215 317 {
<> 133:99b5ccf27215 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
<> 133:99b5ccf27215 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 133:99b5ccf27215 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 133:99b5ccf27215 321 } b; /*!< Structure used for bit access */
<> 133:99b5ccf27215 322 uint32_t w; /*!< Type used for word access */
<> 133:99b5ccf27215 323 } CONTROL_Type;
<> 133:99b5ccf27215 324
<> 133:99b5ccf27215 325 /* CONTROL Register Definitions */
<> 133:99b5ccf27215 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 133:99b5ccf27215 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 133:99b5ccf27215 328
<> 133:99b5ccf27215 329 /*@} end of group CMSIS_CORE */
<> 133:99b5ccf27215 330
<> 133:99b5ccf27215 331
<> 133:99b5ccf27215 332 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 133:99b5ccf27215 334 \brief Type definitions for the NVIC Registers
<> 133:99b5ccf27215 335 @{
<> 133:99b5ccf27215 336 */
<> 133:99b5ccf27215 337
<> 133:99b5ccf27215 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 133:99b5ccf27215 339 */
<> 133:99b5ccf27215 340 typedef struct
<> 133:99b5ccf27215 341 {
<> 133:99b5ccf27215 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 133:99b5ccf27215 343 uint32_t RESERVED0[31];
<> 133:99b5ccf27215 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 133:99b5ccf27215 345 uint32_t RSERVED1[31];
<> 133:99b5ccf27215 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 133:99b5ccf27215 347 uint32_t RESERVED2[31];
<> 133:99b5ccf27215 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 133:99b5ccf27215 349 uint32_t RESERVED3[31];
<> 133:99b5ccf27215 350 uint32_t RESERVED4[64];
<> 133:99b5ccf27215 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 133:99b5ccf27215 352 } NVIC_Type;
<> 133:99b5ccf27215 353
<> 133:99b5ccf27215 354 /*@} end of group CMSIS_NVIC */
<> 133:99b5ccf27215 355
<> 133:99b5ccf27215 356
<> 133:99b5ccf27215 357 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 358 \defgroup CMSIS_SCB System Control Block (SCB)
<> 133:99b5ccf27215 359 \brief Type definitions for the System Control Block Registers
<> 133:99b5ccf27215 360 @{
<> 133:99b5ccf27215 361 */
<> 133:99b5ccf27215 362
<> 133:99b5ccf27215 363 /** \brief Structure type to access the System Control Block (SCB).
<> 133:99b5ccf27215 364 */
<> 133:99b5ccf27215 365 typedef struct
<> 133:99b5ccf27215 366 {
<> 133:99b5ccf27215 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 133:99b5ccf27215 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 133:99b5ccf27215 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 133:99b5ccf27215 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 133:99b5ccf27215 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 133:99b5ccf27215 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 133:99b5ccf27215 373 uint32_t RESERVED0[1];
<> 133:99b5ccf27215 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 133:99b5ccf27215 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 133:99b5ccf27215 376 uint32_t RESERVED1[154];
<> 133:99b5ccf27215 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
<> 133:99b5ccf27215 378 } SCB_Type;
<> 133:99b5ccf27215 379
<> 133:99b5ccf27215 380 /* SCB CPUID Register Definitions */
<> 133:99b5ccf27215 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 133:99b5ccf27215 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 133:99b5ccf27215 383
<> 133:99b5ccf27215 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 133:99b5ccf27215 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 133:99b5ccf27215 386
<> 133:99b5ccf27215 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 133:99b5ccf27215 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 133:99b5ccf27215 389
<> 133:99b5ccf27215 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 133:99b5ccf27215 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 133:99b5ccf27215 392
<> 133:99b5ccf27215 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 133:99b5ccf27215 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 133:99b5ccf27215 395
<> 133:99b5ccf27215 396 /* SCB Interrupt Control State Register Definitions */
<> 133:99b5ccf27215 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 133:99b5ccf27215 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 133:99b5ccf27215 399
<> 133:99b5ccf27215 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 133:99b5ccf27215 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 133:99b5ccf27215 402
<> 133:99b5ccf27215 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 133:99b5ccf27215 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 133:99b5ccf27215 405
<> 133:99b5ccf27215 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 133:99b5ccf27215 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 133:99b5ccf27215 408
<> 133:99b5ccf27215 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 133:99b5ccf27215 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 133:99b5ccf27215 411
<> 133:99b5ccf27215 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 133:99b5ccf27215 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 133:99b5ccf27215 414
<> 133:99b5ccf27215 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 133:99b5ccf27215 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 133:99b5ccf27215 417
<> 133:99b5ccf27215 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 133:99b5ccf27215 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 133:99b5ccf27215 420
<> 133:99b5ccf27215 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 133:99b5ccf27215 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 133:99b5ccf27215 423
<> 133:99b5ccf27215 424 /* SCB Interrupt Control State Register Definitions */
<> 133:99b5ccf27215 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 133:99b5ccf27215 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 133:99b5ccf27215 427
<> 133:99b5ccf27215 428 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 133:99b5ccf27215 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 133:99b5ccf27215 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 133:99b5ccf27215 431
<> 133:99b5ccf27215 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 133:99b5ccf27215 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 133:99b5ccf27215 434
<> 133:99b5ccf27215 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 133:99b5ccf27215 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 133:99b5ccf27215 437
<> 133:99b5ccf27215 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 133:99b5ccf27215 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 133:99b5ccf27215 440
<> 133:99b5ccf27215 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 133:99b5ccf27215 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 133:99b5ccf27215 443
<> 133:99b5ccf27215 444 /* SCB System Control Register Definitions */
<> 133:99b5ccf27215 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 133:99b5ccf27215 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 133:99b5ccf27215 447
<> 133:99b5ccf27215 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 133:99b5ccf27215 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 133:99b5ccf27215 450
<> 133:99b5ccf27215 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 133:99b5ccf27215 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 133:99b5ccf27215 453
<> 133:99b5ccf27215 454 /* SCB Configuration Control Register Definitions */
<> 133:99b5ccf27215 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 133:99b5ccf27215 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 133:99b5ccf27215 457
<> 133:99b5ccf27215 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 133:99b5ccf27215 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 133:99b5ccf27215 460
<> 133:99b5ccf27215 461 /* SCB System Handler Control and State Register Definitions */
<> 133:99b5ccf27215 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 133:99b5ccf27215 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 133:99b5ccf27215 464
<> 133:99b5ccf27215 465 /*@} end of group CMSIS_SCB */
<> 133:99b5ccf27215 466
<> 133:99b5ccf27215 467
<> 133:99b5ccf27215 468 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<> 133:99b5ccf27215 470 \brief Type definitions for the System Control and ID Register not in the SCB
<> 133:99b5ccf27215 471 @{
<> 133:99b5ccf27215 472 */
<> 133:99b5ccf27215 473
<> 133:99b5ccf27215 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
<> 133:99b5ccf27215 475 */
<> 133:99b5ccf27215 476 typedef struct
<> 133:99b5ccf27215 477 {
<> 133:99b5ccf27215 478 uint32_t RESERVED0[2];
<> 133:99b5ccf27215 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
<> 133:99b5ccf27215 480 } SCnSCB_Type;
<> 133:99b5ccf27215 481
<> 133:99b5ccf27215 482 /* Auxiliary Control Register Definitions */
<> 133:99b5ccf27215 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
<> 133:99b5ccf27215 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
<> 133:99b5ccf27215 485
<> 133:99b5ccf27215 486 /*@} end of group CMSIS_SCnotSCB */
<> 133:99b5ccf27215 487
<> 133:99b5ccf27215 488
<> 133:99b5ccf27215 489 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 133:99b5ccf27215 491 \brief Type definitions for the System Timer Registers.
<> 133:99b5ccf27215 492 @{
<> 133:99b5ccf27215 493 */
<> 133:99b5ccf27215 494
<> 133:99b5ccf27215 495 /** \brief Structure type to access the System Timer (SysTick).
<> 133:99b5ccf27215 496 */
<> 133:99b5ccf27215 497 typedef struct
<> 133:99b5ccf27215 498 {
<> 133:99b5ccf27215 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 133:99b5ccf27215 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 133:99b5ccf27215 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 133:99b5ccf27215 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 133:99b5ccf27215 503 } SysTick_Type;
<> 133:99b5ccf27215 504
<> 133:99b5ccf27215 505 /* SysTick Control / Status Register Definitions */
<> 133:99b5ccf27215 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 133:99b5ccf27215 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 133:99b5ccf27215 508
<> 133:99b5ccf27215 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 133:99b5ccf27215 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 133:99b5ccf27215 511
<> 133:99b5ccf27215 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 133:99b5ccf27215 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 133:99b5ccf27215 514
<> 133:99b5ccf27215 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 133:99b5ccf27215 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 133:99b5ccf27215 517
<> 133:99b5ccf27215 518 /* SysTick Reload Register Definitions */
<> 133:99b5ccf27215 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 133:99b5ccf27215 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 133:99b5ccf27215 521
<> 133:99b5ccf27215 522 /* SysTick Current Register Definitions */
<> 133:99b5ccf27215 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 133:99b5ccf27215 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 133:99b5ccf27215 525
<> 133:99b5ccf27215 526 /* SysTick Calibration Register Definitions */
<> 133:99b5ccf27215 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 133:99b5ccf27215 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 133:99b5ccf27215 529
<> 133:99b5ccf27215 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 133:99b5ccf27215 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 133:99b5ccf27215 532
<> 133:99b5ccf27215 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 133:99b5ccf27215 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 133:99b5ccf27215 535
<> 133:99b5ccf27215 536 /*@} end of group CMSIS_SysTick */
<> 133:99b5ccf27215 537
<> 133:99b5ccf27215 538 #if (__MPU_PRESENT == 1)
<> 133:99b5ccf27215 539 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 133:99b5ccf27215 541 \brief Type definitions for the Memory Protection Unit (MPU)
<> 133:99b5ccf27215 542 @{
<> 133:99b5ccf27215 543 */
<> 133:99b5ccf27215 544
<> 133:99b5ccf27215 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 133:99b5ccf27215 546 */
<> 133:99b5ccf27215 547 typedef struct
<> 133:99b5ccf27215 548 {
<> 133:99b5ccf27215 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 133:99b5ccf27215 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 133:99b5ccf27215 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 133:99b5ccf27215 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 133:99b5ccf27215 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 133:99b5ccf27215 554 } MPU_Type;
<> 133:99b5ccf27215 555
<> 133:99b5ccf27215 556 /* MPU Type Register */
<> 133:99b5ccf27215 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 133:99b5ccf27215 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 133:99b5ccf27215 559
<> 133:99b5ccf27215 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 133:99b5ccf27215 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 133:99b5ccf27215 562
<> 133:99b5ccf27215 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 133:99b5ccf27215 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 133:99b5ccf27215 565
<> 133:99b5ccf27215 566 /* MPU Control Register */
<> 133:99b5ccf27215 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 133:99b5ccf27215 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 133:99b5ccf27215 569
<> 133:99b5ccf27215 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 133:99b5ccf27215 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 133:99b5ccf27215 572
<> 133:99b5ccf27215 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 133:99b5ccf27215 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 133:99b5ccf27215 575
<> 133:99b5ccf27215 576 /* MPU Region Number Register */
<> 133:99b5ccf27215 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 133:99b5ccf27215 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 133:99b5ccf27215 579
<> 133:99b5ccf27215 580 /* MPU Region Base Address Register */
<> 133:99b5ccf27215 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
<> 133:99b5ccf27215 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 133:99b5ccf27215 583
<> 133:99b5ccf27215 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 133:99b5ccf27215 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 133:99b5ccf27215 586
<> 133:99b5ccf27215 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 133:99b5ccf27215 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 133:99b5ccf27215 589
<> 133:99b5ccf27215 590 /* MPU Region Attribute and Size Register */
<> 133:99b5ccf27215 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 133:99b5ccf27215 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 133:99b5ccf27215 593
<> 133:99b5ccf27215 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 133:99b5ccf27215 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 133:99b5ccf27215 596
<> 133:99b5ccf27215 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 133:99b5ccf27215 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 133:99b5ccf27215 599
<> 133:99b5ccf27215 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 133:99b5ccf27215 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 133:99b5ccf27215 602
<> 133:99b5ccf27215 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 133:99b5ccf27215 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 133:99b5ccf27215 605
<> 133:99b5ccf27215 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 133:99b5ccf27215 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 133:99b5ccf27215 608
<> 133:99b5ccf27215 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 133:99b5ccf27215 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 133:99b5ccf27215 611
<> 133:99b5ccf27215 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 133:99b5ccf27215 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 133:99b5ccf27215 614
<> 133:99b5ccf27215 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 133:99b5ccf27215 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 133:99b5ccf27215 617
<> 133:99b5ccf27215 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 133:99b5ccf27215 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 133:99b5ccf27215 620
<> 133:99b5ccf27215 621 /*@} end of group CMSIS_MPU */
<> 133:99b5ccf27215 622 #endif
<> 133:99b5ccf27215 623
<> 133:99b5ccf27215 624
<> 133:99b5ccf27215 625 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 133:99b5ccf27215 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 133:99b5ccf27215 628 are only accessible over DAP and not via processor. Therefore
<> 133:99b5ccf27215 629 they are not covered by the Cortex-M0 header file.
<> 133:99b5ccf27215 630 @{
<> 133:99b5ccf27215 631 */
<> 133:99b5ccf27215 632 /*@} end of group CMSIS_CoreDebug */
<> 133:99b5ccf27215 633
<> 133:99b5ccf27215 634
<> 133:99b5ccf27215 635 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 636 \defgroup CMSIS_core_base Core Definitions
<> 133:99b5ccf27215 637 \brief Definitions for base addresses, unions, and structures.
<> 133:99b5ccf27215 638 @{
<> 133:99b5ccf27215 639 */
<> 133:99b5ccf27215 640
<> 133:99b5ccf27215 641 /* Memory mapping of SC000 Hardware */
<> 133:99b5ccf27215 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 133:99b5ccf27215 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 133:99b5ccf27215 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 133:99b5ccf27215 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 133:99b5ccf27215 646
<> 133:99b5ccf27215 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
<> 133:99b5ccf27215 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 133:99b5ccf27215 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 133:99b5ccf27215 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 133:99b5ccf27215 651
<> 133:99b5ccf27215 652 #if (__MPU_PRESENT == 1)
<> 133:99b5ccf27215 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 133:99b5ccf27215 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 133:99b5ccf27215 655 #endif
<> 133:99b5ccf27215 656
<> 133:99b5ccf27215 657 /*@} */
<> 133:99b5ccf27215 658
<> 133:99b5ccf27215 659
<> 133:99b5ccf27215 660
<> 133:99b5ccf27215 661 /*******************************************************************************
<> 133:99b5ccf27215 662 * Hardware Abstraction Layer
<> 133:99b5ccf27215 663 Core Function Interface contains:
<> 133:99b5ccf27215 664 - Core NVIC Functions
<> 133:99b5ccf27215 665 - Core SysTick Functions
<> 133:99b5ccf27215 666 - Core Register Access Functions
<> 133:99b5ccf27215 667 ******************************************************************************/
<> 133:99b5ccf27215 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 133:99b5ccf27215 669 */
<> 133:99b5ccf27215 670
<> 133:99b5ccf27215 671
<> 133:99b5ccf27215 672
<> 133:99b5ccf27215 673 /* ########################## NVIC functions #################################### */
<> 133:99b5ccf27215 674 /** \ingroup CMSIS_Core_FunctionInterface
<> 133:99b5ccf27215 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 133:99b5ccf27215 676 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 133:99b5ccf27215 677 @{
<> 133:99b5ccf27215 678 */
<> 133:99b5ccf27215 679
<> 133:99b5ccf27215 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 133:99b5ccf27215 681 /* The following MACROS handle generation of the register offset and byte masks */
<> 133:99b5ccf27215 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 133:99b5ccf27215 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 133:99b5ccf27215 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 133:99b5ccf27215 685
<> 133:99b5ccf27215 686
<> 133:99b5ccf27215 687 /** \brief Enable External Interrupt
<> 133:99b5ccf27215 688
<> 133:99b5ccf27215 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 133:99b5ccf27215 690
<> 133:99b5ccf27215 691 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 133:99b5ccf27215 692 */
<> 133:99b5ccf27215 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 133:99b5ccf27215 694 {
<> 133:99b5ccf27215 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 133:99b5ccf27215 696 }
<> 133:99b5ccf27215 697
<> 133:99b5ccf27215 698
<> 133:99b5ccf27215 699 /** \brief Disable External Interrupt
<> 133:99b5ccf27215 700
<> 133:99b5ccf27215 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 133:99b5ccf27215 702
<> 133:99b5ccf27215 703 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 133:99b5ccf27215 704 */
<> 133:99b5ccf27215 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 133:99b5ccf27215 706 {
<> 133:99b5ccf27215 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 133:99b5ccf27215 708 __DSB();
<> 133:99b5ccf27215 709 __ISB();
<> 133:99b5ccf27215 710 }
<> 133:99b5ccf27215 711
<> 133:99b5ccf27215 712
<> 133:99b5ccf27215 713 /** \brief Get Pending Interrupt
<> 133:99b5ccf27215 714
<> 133:99b5ccf27215 715 The function reads the pending register in the NVIC and returns the pending bit
<> 133:99b5ccf27215 716 for the specified interrupt.
<> 133:99b5ccf27215 717
<> 133:99b5ccf27215 718 \param [in] IRQn Interrupt number.
<> 133:99b5ccf27215 719
<> 133:99b5ccf27215 720 \return 0 Interrupt status is not pending.
<> 133:99b5ccf27215 721 \return 1 Interrupt status is pending.
<> 133:99b5ccf27215 722 */
<> 133:99b5ccf27215 723 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 133:99b5ccf27215 724 {
<> 133:99b5ccf27215 725 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 133:99b5ccf27215 726 }
<> 133:99b5ccf27215 727
<> 133:99b5ccf27215 728
<> 133:99b5ccf27215 729 /** \brief Set Pending Interrupt
<> 133:99b5ccf27215 730
<> 133:99b5ccf27215 731 The function sets the pending bit of an external interrupt.
<> 133:99b5ccf27215 732
<> 133:99b5ccf27215 733 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 133:99b5ccf27215 734 */
<> 133:99b5ccf27215 735 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 133:99b5ccf27215 736 {
<> 133:99b5ccf27215 737 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 133:99b5ccf27215 738 }
<> 133:99b5ccf27215 739
<> 133:99b5ccf27215 740
<> 133:99b5ccf27215 741 /** \brief Clear Pending Interrupt
<> 133:99b5ccf27215 742
<> 133:99b5ccf27215 743 The function clears the pending bit of an external interrupt.
<> 133:99b5ccf27215 744
<> 133:99b5ccf27215 745 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 133:99b5ccf27215 746 */
<> 133:99b5ccf27215 747 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 133:99b5ccf27215 748 {
<> 133:99b5ccf27215 749 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 133:99b5ccf27215 750 }
<> 133:99b5ccf27215 751
<> 133:99b5ccf27215 752
<> 133:99b5ccf27215 753 /** \brief Set Interrupt Priority
<> 133:99b5ccf27215 754
<> 133:99b5ccf27215 755 The function sets the priority of an interrupt.
<> 133:99b5ccf27215 756
<> 133:99b5ccf27215 757 \note The priority cannot be set for every core interrupt.
<> 133:99b5ccf27215 758
<> 133:99b5ccf27215 759 \param [in] IRQn Interrupt number.
<> 133:99b5ccf27215 760 \param [in] priority Priority to set.
<> 133:99b5ccf27215 761 */
<> 133:99b5ccf27215 762 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 133:99b5ccf27215 763 {
<> 133:99b5ccf27215 764 if((int32_t)(IRQn) < 0) {
<> 133:99b5ccf27215 765 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 133:99b5ccf27215 766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 133:99b5ccf27215 767 }
<> 133:99b5ccf27215 768 else {
<> 133:99b5ccf27215 769 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 133:99b5ccf27215 770 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 133:99b5ccf27215 771 }
<> 133:99b5ccf27215 772 }
<> 133:99b5ccf27215 773
<> 133:99b5ccf27215 774
<> 133:99b5ccf27215 775 /** \brief Get Interrupt Priority
<> 133:99b5ccf27215 776
<> 133:99b5ccf27215 777 The function reads the priority of an interrupt. The interrupt
<> 133:99b5ccf27215 778 number can be positive to specify an external (device specific)
<> 133:99b5ccf27215 779 interrupt, or negative to specify an internal (core) interrupt.
<> 133:99b5ccf27215 780
<> 133:99b5ccf27215 781
<> 133:99b5ccf27215 782 \param [in] IRQn Interrupt number.
<> 133:99b5ccf27215 783 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 133:99b5ccf27215 784 priority bits of the microcontroller.
<> 133:99b5ccf27215 785 */
<> 133:99b5ccf27215 786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 133:99b5ccf27215 787 {
<> 133:99b5ccf27215 788
<> 133:99b5ccf27215 789 if((int32_t)(IRQn) < 0) {
<> 133:99b5ccf27215 790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 133:99b5ccf27215 791 }
<> 133:99b5ccf27215 792 else {
<> 133:99b5ccf27215 793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 133:99b5ccf27215 794 }
<> 133:99b5ccf27215 795 }
<> 133:99b5ccf27215 796
<> 133:99b5ccf27215 797
<> 133:99b5ccf27215 798 /** \brief System Reset
<> 133:99b5ccf27215 799
<> 133:99b5ccf27215 800 The function initiates a system reset request to reset the MCU.
<> 133:99b5ccf27215 801 */
<> 133:99b5ccf27215 802 __STATIC_INLINE void NVIC_SystemReset(void)
<> 133:99b5ccf27215 803 {
<> 133:99b5ccf27215 804 __DSB(); /* Ensure all outstanding memory accesses included
<> 133:99b5ccf27215 805 buffered write are completed before reset */
<> 133:99b5ccf27215 806 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 133:99b5ccf27215 807 SCB_AIRCR_SYSRESETREQ_Msk);
<> 133:99b5ccf27215 808 __DSB(); /* Ensure completion of memory access */
<> 133:99b5ccf27215 809 while(1) { __NOP(); } /* wait until reset */
<> 133:99b5ccf27215 810 }
<> 133:99b5ccf27215 811
<> 133:99b5ccf27215 812 /*@} end of CMSIS_Core_NVICFunctions */
<> 133:99b5ccf27215 813
<> 133:99b5ccf27215 814
<> 133:99b5ccf27215 815
<> 133:99b5ccf27215 816 /* ################################## SysTick function ############################################ */
<> 133:99b5ccf27215 817 /** \ingroup CMSIS_Core_FunctionInterface
<> 133:99b5ccf27215 818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 133:99b5ccf27215 819 \brief Functions that configure the System.
<> 133:99b5ccf27215 820 @{
<> 133:99b5ccf27215 821 */
<> 133:99b5ccf27215 822
<> 133:99b5ccf27215 823 #if (__Vendor_SysTickConfig == 0)
<> 133:99b5ccf27215 824
<> 133:99b5ccf27215 825 /** \brief System Tick Configuration
<> 133:99b5ccf27215 826
<> 133:99b5ccf27215 827 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 133:99b5ccf27215 828 Counter is in free running mode to generate periodic interrupts.
<> 133:99b5ccf27215 829
<> 133:99b5ccf27215 830 \param [in] ticks Number of ticks between two interrupts.
<> 133:99b5ccf27215 831
<> 133:99b5ccf27215 832 \return 0 Function succeeded.
<> 133:99b5ccf27215 833 \return 1 Function failed.
<> 133:99b5ccf27215 834
<> 133:99b5ccf27215 835 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 133:99b5ccf27215 836 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 133:99b5ccf27215 837 must contain a vendor-specific implementation of this function.
<> 133:99b5ccf27215 838
<> 133:99b5ccf27215 839 */
<> 133:99b5ccf27215 840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 133:99b5ccf27215 841 {
<> 133:99b5ccf27215 842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
<> 133:99b5ccf27215 843
<> 133:99b5ccf27215 844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 133:99b5ccf27215 845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 133:99b5ccf27215 846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 133:99b5ccf27215 847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 133:99b5ccf27215 848 SysTick_CTRL_TICKINT_Msk |
<> 133:99b5ccf27215 849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 133:99b5ccf27215 850 return (0UL); /* Function successful */
<> 133:99b5ccf27215 851 }
<> 133:99b5ccf27215 852
<> 133:99b5ccf27215 853 #endif
<> 133:99b5ccf27215 854
<> 133:99b5ccf27215 855 /*@} end of CMSIS_Core_SysTickFunctions */
<> 133:99b5ccf27215 856
<> 133:99b5ccf27215 857
<> 133:99b5ccf27215 858
<> 133:99b5ccf27215 859
<> 133:99b5ccf27215 860 #ifdef __cplusplus
<> 133:99b5ccf27215 861 }
<> 133:99b5ccf27215 862 #endif
<> 133:99b5ccf27215 863
<> 133:99b5ccf27215 864 #endif /* __CORE_SC000_H_DEPENDANT */
<> 133:99b5ccf27215 865
<> 133:99b5ccf27215 866 #endif /* __CMSIS_GENERIC */