mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_UBLOX_EVK_NINA_B1/core_cmInstr.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
133:99b5ccf27215 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 133:99b5ccf27215 1 /**************************************************************************//**
<> 133:99b5ccf27215 2 * @file core_cmInstr.h
<> 133:99b5ccf27215 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
<> 133:99b5ccf27215 4 * @version V4.10
<> 133:99b5ccf27215 5 * @date 18. March 2015
<> 133:99b5ccf27215 6 *
<> 133:99b5ccf27215 7 * @note
<> 133:99b5ccf27215 8 *
<> 133:99b5ccf27215 9 ******************************************************************************/
<> 133:99b5ccf27215 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 133:99b5ccf27215 11
<> 133:99b5ccf27215 12 All rights reserved.
<> 133:99b5ccf27215 13 Redistribution and use in source and binary forms, with or without
<> 133:99b5ccf27215 14 modification, are permitted provided that the following conditions are met:
<> 133:99b5ccf27215 15 - Redistributions of source code must retain the above copyright
<> 133:99b5ccf27215 16 notice, this list of conditions and the following disclaimer.
<> 133:99b5ccf27215 17 - Redistributions in binary form must reproduce the above copyright
<> 133:99b5ccf27215 18 notice, this list of conditions and the following disclaimer in the
<> 133:99b5ccf27215 19 documentation and/or other materials provided with the distribution.
<> 133:99b5ccf27215 20 - Neither the name of ARM nor the names of its contributors may be used
<> 133:99b5ccf27215 21 to endorse or promote products derived from this software without
<> 133:99b5ccf27215 22 specific prior written permission.
<> 133:99b5ccf27215 23 *
<> 133:99b5ccf27215 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 133:99b5ccf27215 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 133:99b5ccf27215 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 133:99b5ccf27215 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 133:99b5ccf27215 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 133:99b5ccf27215 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 133:99b5ccf27215 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 133:99b5ccf27215 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 133:99b5ccf27215 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 133:99b5ccf27215 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 133:99b5ccf27215 34 POSSIBILITY OF SUCH DAMAGE.
<> 133:99b5ccf27215 35 ---------------------------------------------------------------------------*/
<> 133:99b5ccf27215 36
<> 133:99b5ccf27215 37
<> 133:99b5ccf27215 38 #ifndef __CORE_CMINSTR_H
<> 133:99b5ccf27215 39 #define __CORE_CMINSTR_H
<> 133:99b5ccf27215 40
<> 133:99b5ccf27215 41
<> 133:99b5ccf27215 42 /* ########################## Core Instruction Access ######################### */
<> 133:99b5ccf27215 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
<> 133:99b5ccf27215 44 Access to dedicated instructions
<> 133:99b5ccf27215 45 @{
<> 133:99b5ccf27215 46 */
<> 133:99b5ccf27215 47
<> 133:99b5ccf27215 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 133:99b5ccf27215 49 /* ARM armcc specific functions */
<> 133:99b5ccf27215 50
<> 133:99b5ccf27215 51 #if (__ARMCC_VERSION < 400677)
<> 133:99b5ccf27215 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 133:99b5ccf27215 53 #endif
<> 133:99b5ccf27215 54
<> 133:99b5ccf27215 55
<> 133:99b5ccf27215 56 /** \brief No Operation
<> 133:99b5ccf27215 57
<> 133:99b5ccf27215 58 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 133:99b5ccf27215 59 */
<> 133:99b5ccf27215 60 #define __NOP __nop
<> 133:99b5ccf27215 61
<> 133:99b5ccf27215 62
<> 133:99b5ccf27215 63 /** \brief Wait For Interrupt
<> 133:99b5ccf27215 64
<> 133:99b5ccf27215 65 Wait For Interrupt is a hint instruction that suspends execution
<> 133:99b5ccf27215 66 until one of a number of events occurs.
<> 133:99b5ccf27215 67 */
<> 133:99b5ccf27215 68 #define __WFI __wfi
<> 133:99b5ccf27215 69
<> 133:99b5ccf27215 70
<> 133:99b5ccf27215 71 /** \brief Wait For Event
<> 133:99b5ccf27215 72
<> 133:99b5ccf27215 73 Wait For Event is a hint instruction that permits the processor to enter
<> 133:99b5ccf27215 74 a low-power state until one of a number of events occurs.
<> 133:99b5ccf27215 75 */
<> 133:99b5ccf27215 76 #define __WFE __wfe
<> 133:99b5ccf27215 77
<> 133:99b5ccf27215 78
<> 133:99b5ccf27215 79 /** \brief Send Event
<> 133:99b5ccf27215 80
<> 133:99b5ccf27215 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 133:99b5ccf27215 82 */
<> 133:99b5ccf27215 83 #define __SEV __sev
<> 133:99b5ccf27215 84
<> 133:99b5ccf27215 85
<> 133:99b5ccf27215 86 /** \brief Instruction Synchronization Barrier
<> 133:99b5ccf27215 87
<> 133:99b5ccf27215 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 133:99b5ccf27215 89 so that all instructions following the ISB are fetched from cache or
<> 133:99b5ccf27215 90 memory, after the instruction has been completed.
<> 133:99b5ccf27215 91 */
<> 133:99b5ccf27215 92 #define __ISB() do {\
<> 133:99b5ccf27215 93 __schedule_barrier();\
<> 133:99b5ccf27215 94 __isb(0xF);\
<> 133:99b5ccf27215 95 __schedule_barrier();\
<> 133:99b5ccf27215 96 } while (0)
<> 133:99b5ccf27215 97
<> 133:99b5ccf27215 98 /** \brief Data Synchronization Barrier
<> 133:99b5ccf27215 99
<> 133:99b5ccf27215 100 This function acts as a special kind of Data Memory Barrier.
<> 133:99b5ccf27215 101 It completes when all explicit memory accesses before this instruction complete.
<> 133:99b5ccf27215 102 */
<> 133:99b5ccf27215 103 #define __DSB() do {\
<> 133:99b5ccf27215 104 __schedule_barrier();\
<> 133:99b5ccf27215 105 __dsb(0xF);\
<> 133:99b5ccf27215 106 __schedule_barrier();\
<> 133:99b5ccf27215 107 } while (0)
<> 133:99b5ccf27215 108
<> 133:99b5ccf27215 109 /** \brief Data Memory Barrier
<> 133:99b5ccf27215 110
<> 133:99b5ccf27215 111 This function ensures the apparent order of the explicit memory operations before
<> 133:99b5ccf27215 112 and after the instruction, without ensuring their completion.
<> 133:99b5ccf27215 113 */
<> 133:99b5ccf27215 114 #define __DMB() do {\
<> 133:99b5ccf27215 115 __schedule_barrier();\
<> 133:99b5ccf27215 116 __dmb(0xF);\
<> 133:99b5ccf27215 117 __schedule_barrier();\
<> 133:99b5ccf27215 118 } while (0)
<> 133:99b5ccf27215 119
<> 133:99b5ccf27215 120 /** \brief Reverse byte order (32 bit)
<> 133:99b5ccf27215 121
<> 133:99b5ccf27215 122 This function reverses the byte order in integer value.
<> 133:99b5ccf27215 123
<> 133:99b5ccf27215 124 \param [in] value Value to reverse
<> 133:99b5ccf27215 125 \return Reversed value
<> 133:99b5ccf27215 126 */
<> 133:99b5ccf27215 127 #define __REV __rev
<> 133:99b5ccf27215 128
<> 133:99b5ccf27215 129
<> 133:99b5ccf27215 130 /** \brief Reverse byte order (16 bit)
<> 133:99b5ccf27215 131
<> 133:99b5ccf27215 132 This function reverses the byte order in two unsigned short values.
<> 133:99b5ccf27215 133
<> 133:99b5ccf27215 134 \param [in] value Value to reverse
<> 133:99b5ccf27215 135 \return Reversed value
<> 133:99b5ccf27215 136 */
<> 133:99b5ccf27215 137 #ifndef __NO_EMBEDDED_ASM
<> 133:99b5ccf27215 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
<> 133:99b5ccf27215 139 {
<> 133:99b5ccf27215 140 rev16 r0, r0
<> 133:99b5ccf27215 141 bx lr
<> 133:99b5ccf27215 142 }
<> 133:99b5ccf27215 143 #endif
<> 133:99b5ccf27215 144
<> 133:99b5ccf27215 145 /** \brief Reverse byte order in signed short value
<> 133:99b5ccf27215 146
<> 133:99b5ccf27215 147 This function reverses the byte order in a signed short value with sign extension to integer.
<> 133:99b5ccf27215 148
<> 133:99b5ccf27215 149 \param [in] value Value to reverse
<> 133:99b5ccf27215 150 \return Reversed value
<> 133:99b5ccf27215 151 */
<> 133:99b5ccf27215 152 #ifndef __NO_EMBEDDED_ASM
<> 133:99b5ccf27215 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
<> 133:99b5ccf27215 154 {
<> 133:99b5ccf27215 155 revsh r0, r0
<> 133:99b5ccf27215 156 bx lr
<> 133:99b5ccf27215 157 }
<> 133:99b5ccf27215 158 #endif
<> 133:99b5ccf27215 159
<> 133:99b5ccf27215 160
<> 133:99b5ccf27215 161 /** \brief Rotate Right in unsigned value (32 bit)
<> 133:99b5ccf27215 162
<> 133:99b5ccf27215 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 133:99b5ccf27215 164
<> 133:99b5ccf27215 165 \param [in] value Value to rotate
<> 133:99b5ccf27215 166 \param [in] value Number of Bits to rotate
<> 133:99b5ccf27215 167 \return Rotated value
<> 133:99b5ccf27215 168 */
<> 133:99b5ccf27215 169 #define __ROR __ror
<> 133:99b5ccf27215 170
<> 133:99b5ccf27215 171
<> 133:99b5ccf27215 172 /** \brief Breakpoint
<> 133:99b5ccf27215 173
<> 133:99b5ccf27215 174 This function causes the processor to enter Debug state.
<> 133:99b5ccf27215 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 133:99b5ccf27215 176
<> 133:99b5ccf27215 177 \param [in] value is ignored by the processor.
<> 133:99b5ccf27215 178 If required, a debugger can use it to store additional information about the breakpoint.
<> 133:99b5ccf27215 179 */
<> 133:99b5ccf27215 180 #define __BKPT(value) __breakpoint(value)
<> 133:99b5ccf27215 181
<> 133:99b5ccf27215 182
<> 133:99b5ccf27215 183 /** \brief Reverse bit order of value
<> 133:99b5ccf27215 184
<> 133:99b5ccf27215 185 This function reverses the bit order of the given value.
<> 133:99b5ccf27215 186
<> 133:99b5ccf27215 187 \param [in] value Value to reverse
<> 133:99b5ccf27215 188 \return Reversed value
<> 133:99b5ccf27215 189 */
<> 133:99b5ccf27215 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 133:99b5ccf27215 191 #define __RBIT __rbit
<> 133:99b5ccf27215 192 #else
<> 133:99b5ccf27215 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 133:99b5ccf27215 194 {
<> 133:99b5ccf27215 195 uint32_t result;
<> 133:99b5ccf27215 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 133:99b5ccf27215 197
<> 133:99b5ccf27215 198 result = value; // r will be reversed bits of v; first get LSB of v
<> 133:99b5ccf27215 199 for (value >>= 1; value; value >>= 1)
<> 133:99b5ccf27215 200 {
<> 133:99b5ccf27215 201 result <<= 1;
<> 133:99b5ccf27215 202 result |= value & 1;
<> 133:99b5ccf27215 203 s--;
<> 133:99b5ccf27215 204 }
<> 133:99b5ccf27215 205 result <<= s; // shift when v's highest bits are zero
<> 133:99b5ccf27215 206 return(result);
<> 133:99b5ccf27215 207 }
<> 133:99b5ccf27215 208 #endif
<> 133:99b5ccf27215 209
<> 133:99b5ccf27215 210
<> 133:99b5ccf27215 211 /** \brief Count leading zeros
<> 133:99b5ccf27215 212
<> 133:99b5ccf27215 213 This function counts the number of leading zeros of a data value.
<> 133:99b5ccf27215 214
<> 133:99b5ccf27215 215 \param [in] value Value to count the leading zeros
<> 133:99b5ccf27215 216 \return number of leading zeros in value
<> 133:99b5ccf27215 217 */
<> 133:99b5ccf27215 218 #define __CLZ __clz
<> 133:99b5ccf27215 219
<> 133:99b5ccf27215 220
<> 133:99b5ccf27215 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 133:99b5ccf27215 222
<> 133:99b5ccf27215 223 /** \brief LDR Exclusive (8 bit)
<> 133:99b5ccf27215 224
<> 133:99b5ccf27215 225 This function executes a exclusive LDR instruction for 8 bit value.
<> 133:99b5ccf27215 226
<> 133:99b5ccf27215 227 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 228 \return value of type uint8_t at (*ptr)
<> 133:99b5ccf27215 229 */
<> 133:99b5ccf27215 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
<> 133:99b5ccf27215 231
<> 133:99b5ccf27215 232
<> 133:99b5ccf27215 233 /** \brief LDR Exclusive (16 bit)
<> 133:99b5ccf27215 234
<> 133:99b5ccf27215 235 This function executes a exclusive LDR instruction for 16 bit values.
<> 133:99b5ccf27215 236
<> 133:99b5ccf27215 237 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 238 \return value of type uint16_t at (*ptr)
<> 133:99b5ccf27215 239 */
<> 133:99b5ccf27215 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
<> 133:99b5ccf27215 241
<> 133:99b5ccf27215 242
<> 133:99b5ccf27215 243 /** \brief LDR Exclusive (32 bit)
<> 133:99b5ccf27215 244
<> 133:99b5ccf27215 245 This function executes a exclusive LDR instruction for 32 bit values.
<> 133:99b5ccf27215 246
<> 133:99b5ccf27215 247 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 248 \return value of type uint32_t at (*ptr)
<> 133:99b5ccf27215 249 */
<> 133:99b5ccf27215 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
<> 133:99b5ccf27215 251
<> 133:99b5ccf27215 252
<> 133:99b5ccf27215 253 /** \brief STR Exclusive (8 bit)
<> 133:99b5ccf27215 254
<> 133:99b5ccf27215 255 This function executes a exclusive STR instruction for 8 bit values.
<> 133:99b5ccf27215 256
<> 133:99b5ccf27215 257 \param [in] value Value to store
<> 133:99b5ccf27215 258 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 259 \return 0 Function succeeded
<> 133:99b5ccf27215 260 \return 1 Function failed
<> 133:99b5ccf27215 261 */
<> 133:99b5ccf27215 262 #define __STREXB(value, ptr) __strex(value, ptr)
<> 133:99b5ccf27215 263
<> 133:99b5ccf27215 264
<> 133:99b5ccf27215 265 /** \brief STR Exclusive (16 bit)
<> 133:99b5ccf27215 266
<> 133:99b5ccf27215 267 This function executes a exclusive STR instruction for 16 bit values.
<> 133:99b5ccf27215 268
<> 133:99b5ccf27215 269 \param [in] value Value to store
<> 133:99b5ccf27215 270 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 271 \return 0 Function succeeded
<> 133:99b5ccf27215 272 \return 1 Function failed
<> 133:99b5ccf27215 273 */
<> 133:99b5ccf27215 274 #define __STREXH(value, ptr) __strex(value, ptr)
<> 133:99b5ccf27215 275
<> 133:99b5ccf27215 276
<> 133:99b5ccf27215 277 /** \brief STR Exclusive (32 bit)
<> 133:99b5ccf27215 278
<> 133:99b5ccf27215 279 This function executes a exclusive STR instruction for 32 bit values.
<> 133:99b5ccf27215 280
<> 133:99b5ccf27215 281 \param [in] value Value to store
<> 133:99b5ccf27215 282 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 283 \return 0 Function succeeded
<> 133:99b5ccf27215 284 \return 1 Function failed
<> 133:99b5ccf27215 285 */
<> 133:99b5ccf27215 286 #define __STREXW(value, ptr) __strex(value, ptr)
<> 133:99b5ccf27215 287
<> 133:99b5ccf27215 288
<> 133:99b5ccf27215 289 /** \brief Remove the exclusive lock
<> 133:99b5ccf27215 290
<> 133:99b5ccf27215 291 This function removes the exclusive lock which is created by LDREX.
<> 133:99b5ccf27215 292
<> 133:99b5ccf27215 293 */
<> 133:99b5ccf27215 294 #define __CLREX __clrex
<> 133:99b5ccf27215 295
<> 133:99b5ccf27215 296
<> 133:99b5ccf27215 297 /** \brief Signed Saturate
<> 133:99b5ccf27215 298
<> 133:99b5ccf27215 299 This function saturates a signed value.
<> 133:99b5ccf27215 300
<> 133:99b5ccf27215 301 \param [in] value Value to be saturated
<> 133:99b5ccf27215 302 \param [in] sat Bit position to saturate to (1..32)
<> 133:99b5ccf27215 303 \return Saturated value
<> 133:99b5ccf27215 304 */
<> 133:99b5ccf27215 305 #define __SSAT __ssat
<> 133:99b5ccf27215 306
<> 133:99b5ccf27215 307
<> 133:99b5ccf27215 308 /** \brief Unsigned Saturate
<> 133:99b5ccf27215 309
<> 133:99b5ccf27215 310 This function saturates an unsigned value.
<> 133:99b5ccf27215 311
<> 133:99b5ccf27215 312 \param [in] value Value to be saturated
<> 133:99b5ccf27215 313 \param [in] sat Bit position to saturate to (0..31)
<> 133:99b5ccf27215 314 \return Saturated value
<> 133:99b5ccf27215 315 */
<> 133:99b5ccf27215 316 #define __USAT __usat
<> 133:99b5ccf27215 317
<> 133:99b5ccf27215 318
<> 133:99b5ccf27215 319 /** \brief Rotate Right with Extend (32 bit)
<> 133:99b5ccf27215 320
<> 133:99b5ccf27215 321 This function moves each bit of a bitstring right by one bit.
<> 133:99b5ccf27215 322 The carry input is shifted in at the left end of the bitstring.
<> 133:99b5ccf27215 323
<> 133:99b5ccf27215 324 \param [in] value Value to rotate
<> 133:99b5ccf27215 325 \return Rotated value
<> 133:99b5ccf27215 326 */
<> 133:99b5ccf27215 327 #ifndef __NO_EMBEDDED_ASM
<> 133:99b5ccf27215 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
<> 133:99b5ccf27215 329 {
<> 133:99b5ccf27215 330 rrx r0, r0
<> 133:99b5ccf27215 331 bx lr
<> 133:99b5ccf27215 332 }
<> 133:99b5ccf27215 333 #endif
<> 133:99b5ccf27215 334
<> 133:99b5ccf27215 335
<> 133:99b5ccf27215 336 /** \brief LDRT Unprivileged (8 bit)
<> 133:99b5ccf27215 337
<> 133:99b5ccf27215 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 133:99b5ccf27215 339
<> 133:99b5ccf27215 340 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 341 \return value of type uint8_t at (*ptr)
<> 133:99b5ccf27215 342 */
<> 133:99b5ccf27215 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
<> 133:99b5ccf27215 344
<> 133:99b5ccf27215 345
<> 133:99b5ccf27215 346 /** \brief LDRT Unprivileged (16 bit)
<> 133:99b5ccf27215 347
<> 133:99b5ccf27215 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 133:99b5ccf27215 349
<> 133:99b5ccf27215 350 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 351 \return value of type uint16_t at (*ptr)
<> 133:99b5ccf27215 352 */
<> 133:99b5ccf27215 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
<> 133:99b5ccf27215 354
<> 133:99b5ccf27215 355
<> 133:99b5ccf27215 356 /** \brief LDRT Unprivileged (32 bit)
<> 133:99b5ccf27215 357
<> 133:99b5ccf27215 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 133:99b5ccf27215 359
<> 133:99b5ccf27215 360 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 361 \return value of type uint32_t at (*ptr)
<> 133:99b5ccf27215 362 */
<> 133:99b5ccf27215 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
<> 133:99b5ccf27215 364
<> 133:99b5ccf27215 365
<> 133:99b5ccf27215 366 /** \brief STRT Unprivileged (8 bit)
<> 133:99b5ccf27215 367
<> 133:99b5ccf27215 368 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 133:99b5ccf27215 369
<> 133:99b5ccf27215 370 \param [in] value Value to store
<> 133:99b5ccf27215 371 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 372 */
<> 133:99b5ccf27215 373 #define __STRBT(value, ptr) __strt(value, ptr)
<> 133:99b5ccf27215 374
<> 133:99b5ccf27215 375
<> 133:99b5ccf27215 376 /** \brief STRT Unprivileged (16 bit)
<> 133:99b5ccf27215 377
<> 133:99b5ccf27215 378 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 133:99b5ccf27215 379
<> 133:99b5ccf27215 380 \param [in] value Value to store
<> 133:99b5ccf27215 381 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 382 */
<> 133:99b5ccf27215 383 #define __STRHT(value, ptr) __strt(value, ptr)
<> 133:99b5ccf27215 384
<> 133:99b5ccf27215 385
<> 133:99b5ccf27215 386 /** \brief STRT Unprivileged (32 bit)
<> 133:99b5ccf27215 387
<> 133:99b5ccf27215 388 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 133:99b5ccf27215 389
<> 133:99b5ccf27215 390 \param [in] value Value to store
<> 133:99b5ccf27215 391 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 392 */
<> 133:99b5ccf27215 393 #define __STRT(value, ptr) __strt(value, ptr)
<> 133:99b5ccf27215 394
<> 133:99b5ccf27215 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 133:99b5ccf27215 396
<> 133:99b5ccf27215 397
<> 133:99b5ccf27215 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 133:99b5ccf27215 399 /* GNU gcc specific functions */
<> 133:99b5ccf27215 400
<> 133:99b5ccf27215 401 /* Define macros for porting to both thumb1 and thumb2.
<> 133:99b5ccf27215 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
<> 133:99b5ccf27215 403 * Otherwise, use general registers, specified by constrant "r" */
<> 133:99b5ccf27215 404 #if defined (__thumb__) && !defined (__thumb2__)
<> 133:99b5ccf27215 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
<> 133:99b5ccf27215 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
<> 133:99b5ccf27215 407 #else
<> 133:99b5ccf27215 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
<> 133:99b5ccf27215 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
<> 133:99b5ccf27215 410 #endif
<> 133:99b5ccf27215 411
<> 133:99b5ccf27215 412 /** \brief No Operation
<> 133:99b5ccf27215 413
<> 133:99b5ccf27215 414 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 133:99b5ccf27215 415 */
<> 133:99b5ccf27215 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
<> 133:99b5ccf27215 417 {
<> 133:99b5ccf27215 418 __ASM volatile ("nop");
<> 133:99b5ccf27215 419 }
<> 133:99b5ccf27215 420
<> 133:99b5ccf27215 421
<> 133:99b5ccf27215 422 /** \brief Wait For Interrupt
<> 133:99b5ccf27215 423
<> 133:99b5ccf27215 424 Wait For Interrupt is a hint instruction that suspends execution
<> 133:99b5ccf27215 425 until one of a number of events occurs.
<> 133:99b5ccf27215 426 */
<> 133:99b5ccf27215 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
<> 133:99b5ccf27215 428 {
<> 133:99b5ccf27215 429 __ASM volatile ("wfi");
<> 133:99b5ccf27215 430 }
<> 133:99b5ccf27215 431
<> 133:99b5ccf27215 432
<> 133:99b5ccf27215 433 /** \brief Wait For Event
<> 133:99b5ccf27215 434
<> 133:99b5ccf27215 435 Wait For Event is a hint instruction that permits the processor to enter
<> 133:99b5ccf27215 436 a low-power state until one of a number of events occurs.
<> 133:99b5ccf27215 437 */
<> 133:99b5ccf27215 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
<> 133:99b5ccf27215 439 {
<> 133:99b5ccf27215 440 __ASM volatile ("wfe");
<> 133:99b5ccf27215 441 }
<> 133:99b5ccf27215 442
<> 133:99b5ccf27215 443
<> 133:99b5ccf27215 444 /** \brief Send Event
<> 133:99b5ccf27215 445
<> 133:99b5ccf27215 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 133:99b5ccf27215 447 */
<> 133:99b5ccf27215 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
<> 133:99b5ccf27215 449 {
<> 133:99b5ccf27215 450 __ASM volatile ("sev");
<> 133:99b5ccf27215 451 }
<> 133:99b5ccf27215 452
<> 133:99b5ccf27215 453
<> 133:99b5ccf27215 454 /** \brief Instruction Synchronization Barrier
<> 133:99b5ccf27215 455
<> 133:99b5ccf27215 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 133:99b5ccf27215 457 so that all instructions following the ISB are fetched from cache or
<> 133:99b5ccf27215 458 memory, after the instruction has been completed.
<> 133:99b5ccf27215 459 */
<> 133:99b5ccf27215 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
<> 133:99b5ccf27215 461 {
<> 133:99b5ccf27215 462 __ASM volatile ("isb 0xF":::"memory");
<> 133:99b5ccf27215 463 }
<> 133:99b5ccf27215 464
<> 133:99b5ccf27215 465
<> 133:99b5ccf27215 466 /** \brief Data Synchronization Barrier
<> 133:99b5ccf27215 467
<> 133:99b5ccf27215 468 This function acts as a special kind of Data Memory Barrier.
<> 133:99b5ccf27215 469 It completes when all explicit memory accesses before this instruction complete.
<> 133:99b5ccf27215 470 */
<> 133:99b5ccf27215 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
<> 133:99b5ccf27215 472 {
<> 133:99b5ccf27215 473 __ASM volatile ("dsb 0xF":::"memory");
<> 133:99b5ccf27215 474 }
<> 133:99b5ccf27215 475
<> 133:99b5ccf27215 476
<> 133:99b5ccf27215 477 /** \brief Data Memory Barrier
<> 133:99b5ccf27215 478
<> 133:99b5ccf27215 479 This function ensures the apparent order of the explicit memory operations before
<> 133:99b5ccf27215 480 and after the instruction, without ensuring their completion.
<> 133:99b5ccf27215 481 */
<> 133:99b5ccf27215 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
<> 133:99b5ccf27215 483 {
<> 133:99b5ccf27215 484 __ASM volatile ("dmb 0xF":::"memory");
<> 133:99b5ccf27215 485 }
<> 133:99b5ccf27215 486
<> 133:99b5ccf27215 487
<> 133:99b5ccf27215 488 /** \brief Reverse byte order (32 bit)
<> 133:99b5ccf27215 489
<> 133:99b5ccf27215 490 This function reverses the byte order in integer value.
<> 133:99b5ccf27215 491
<> 133:99b5ccf27215 492 \param [in] value Value to reverse
<> 133:99b5ccf27215 493 \return Reversed value
<> 133:99b5ccf27215 494 */
<> 133:99b5ccf27215 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
<> 133:99b5ccf27215 496 {
<> 133:99b5ccf27215 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
<> 133:99b5ccf27215 498 return __builtin_bswap32(value);
<> 133:99b5ccf27215 499 #else
<> 133:99b5ccf27215 500 uint32_t result;
<> 133:99b5ccf27215 501
<> 133:99b5ccf27215 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 133:99b5ccf27215 503 return(result);
<> 133:99b5ccf27215 504 #endif
<> 133:99b5ccf27215 505 }
<> 133:99b5ccf27215 506
<> 133:99b5ccf27215 507
<> 133:99b5ccf27215 508 /** \brief Reverse byte order (16 bit)
<> 133:99b5ccf27215 509
<> 133:99b5ccf27215 510 This function reverses the byte order in two unsigned short values.
<> 133:99b5ccf27215 511
<> 133:99b5ccf27215 512 \param [in] value Value to reverse
<> 133:99b5ccf27215 513 \return Reversed value
<> 133:99b5ccf27215 514 */
<> 133:99b5ccf27215 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
<> 133:99b5ccf27215 516 {
<> 133:99b5ccf27215 517 uint32_t result;
<> 133:99b5ccf27215 518
<> 133:99b5ccf27215 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 133:99b5ccf27215 520 return(result);
<> 133:99b5ccf27215 521 }
<> 133:99b5ccf27215 522
<> 133:99b5ccf27215 523
<> 133:99b5ccf27215 524 /** \brief Reverse byte order in signed short value
<> 133:99b5ccf27215 525
<> 133:99b5ccf27215 526 This function reverses the byte order in a signed short value with sign extension to integer.
<> 133:99b5ccf27215 527
<> 133:99b5ccf27215 528 \param [in] value Value to reverse
<> 133:99b5ccf27215 529 \return Reversed value
<> 133:99b5ccf27215 530 */
<> 133:99b5ccf27215 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
<> 133:99b5ccf27215 532 {
<> 133:99b5ccf27215 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 133:99b5ccf27215 534 return (short)__builtin_bswap16(value);
<> 133:99b5ccf27215 535 #else
<> 133:99b5ccf27215 536 uint32_t result;
<> 133:99b5ccf27215 537
<> 133:99b5ccf27215 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 133:99b5ccf27215 539 return(result);
<> 133:99b5ccf27215 540 #endif
<> 133:99b5ccf27215 541 }
<> 133:99b5ccf27215 542
<> 133:99b5ccf27215 543
<> 133:99b5ccf27215 544 /** \brief Rotate Right in unsigned value (32 bit)
<> 133:99b5ccf27215 545
<> 133:99b5ccf27215 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 133:99b5ccf27215 547
<> 133:99b5ccf27215 548 \param [in] value Value to rotate
<> 133:99b5ccf27215 549 \param [in] value Number of Bits to rotate
<> 133:99b5ccf27215 550 \return Rotated value
<> 133:99b5ccf27215 551 */
<> 133:99b5ccf27215 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
<> 133:99b5ccf27215 553 {
<> 133:99b5ccf27215 554 return (op1 >> op2) | (op1 << (32 - op2));
<> 133:99b5ccf27215 555 }
<> 133:99b5ccf27215 556
<> 133:99b5ccf27215 557
<> 133:99b5ccf27215 558 /** \brief Breakpoint
<> 133:99b5ccf27215 559
<> 133:99b5ccf27215 560 This function causes the processor to enter Debug state.
<> 133:99b5ccf27215 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 133:99b5ccf27215 562
<> 133:99b5ccf27215 563 \param [in] value is ignored by the processor.
<> 133:99b5ccf27215 564 If required, a debugger can use it to store additional information about the breakpoint.
<> 133:99b5ccf27215 565 */
<> 133:99b5ccf27215 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
<> 133:99b5ccf27215 567
<> 133:99b5ccf27215 568
<> 133:99b5ccf27215 569 /** \brief Reverse bit order of value
<> 133:99b5ccf27215 570
<> 133:99b5ccf27215 571 This function reverses the bit order of the given value.
<> 133:99b5ccf27215 572
<> 133:99b5ccf27215 573 \param [in] value Value to reverse
<> 133:99b5ccf27215 574 \return Reversed value
<> 133:99b5ccf27215 575 */
<> 133:99b5ccf27215 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 133:99b5ccf27215 577 {
<> 133:99b5ccf27215 578 uint32_t result;
<> 133:99b5ccf27215 579
<> 133:99b5ccf27215 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 133:99b5ccf27215 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
<> 133:99b5ccf27215 582 #else
<> 133:99b5ccf27215 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 133:99b5ccf27215 584
<> 133:99b5ccf27215 585 result = value; // r will be reversed bits of v; first get LSB of v
<> 133:99b5ccf27215 586 for (value >>= 1; value; value >>= 1)
<> 133:99b5ccf27215 587 {
<> 133:99b5ccf27215 588 result <<= 1;
<> 133:99b5ccf27215 589 result |= value & 1;
<> 133:99b5ccf27215 590 s--;
<> 133:99b5ccf27215 591 }
<> 133:99b5ccf27215 592 result <<= s; // shift when v's highest bits are zero
<> 133:99b5ccf27215 593 #endif
<> 133:99b5ccf27215 594 return(result);
<> 133:99b5ccf27215 595 }
<> 133:99b5ccf27215 596
<> 133:99b5ccf27215 597
<> 133:99b5ccf27215 598 /** \brief Count leading zeros
<> 133:99b5ccf27215 599
<> 133:99b5ccf27215 600 This function counts the number of leading zeros of a data value.
<> 133:99b5ccf27215 601
<> 133:99b5ccf27215 602 \param [in] value Value to count the leading zeros
<> 133:99b5ccf27215 603 \return number of leading zeros in value
<> 133:99b5ccf27215 604 */
<> 133:99b5ccf27215 605 #define __CLZ __builtin_clz
<> 133:99b5ccf27215 606
<> 133:99b5ccf27215 607
<> 133:99b5ccf27215 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 133:99b5ccf27215 609
<> 133:99b5ccf27215 610 /** \brief LDR Exclusive (8 bit)
<> 133:99b5ccf27215 611
<> 133:99b5ccf27215 612 This function executes a exclusive LDR instruction for 8 bit value.
<> 133:99b5ccf27215 613
<> 133:99b5ccf27215 614 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 615 \return value of type uint8_t at (*ptr)
<> 133:99b5ccf27215 616 */
<> 133:99b5ccf27215 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
<> 133:99b5ccf27215 618 {
<> 133:99b5ccf27215 619 uint32_t result;
<> 133:99b5ccf27215 620
<> 133:99b5ccf27215 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 133:99b5ccf27215 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
<> 133:99b5ccf27215 623 #else
<> 133:99b5ccf27215 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 133:99b5ccf27215 625 accepted by assembler. So has to use following less efficient pattern.
<> 133:99b5ccf27215 626 */
<> 133:99b5ccf27215 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 133:99b5ccf27215 628 #endif
<> 133:99b5ccf27215 629 return ((uint8_t) result); /* Add explicit type cast here */
<> 133:99b5ccf27215 630 }
<> 133:99b5ccf27215 631
<> 133:99b5ccf27215 632
<> 133:99b5ccf27215 633 /** \brief LDR Exclusive (16 bit)
<> 133:99b5ccf27215 634
<> 133:99b5ccf27215 635 This function executes a exclusive LDR instruction for 16 bit values.
<> 133:99b5ccf27215 636
<> 133:99b5ccf27215 637 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 638 \return value of type uint16_t at (*ptr)
<> 133:99b5ccf27215 639 */
<> 133:99b5ccf27215 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
<> 133:99b5ccf27215 641 {
<> 133:99b5ccf27215 642 uint32_t result;
<> 133:99b5ccf27215 643
<> 133:99b5ccf27215 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 133:99b5ccf27215 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
<> 133:99b5ccf27215 646 #else
<> 133:99b5ccf27215 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 133:99b5ccf27215 648 accepted by assembler. So has to use following less efficient pattern.
<> 133:99b5ccf27215 649 */
<> 133:99b5ccf27215 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 133:99b5ccf27215 651 #endif
<> 133:99b5ccf27215 652 return ((uint16_t) result); /* Add explicit type cast here */
<> 133:99b5ccf27215 653 }
<> 133:99b5ccf27215 654
<> 133:99b5ccf27215 655
<> 133:99b5ccf27215 656 /** \brief LDR Exclusive (32 bit)
<> 133:99b5ccf27215 657
<> 133:99b5ccf27215 658 This function executes a exclusive LDR instruction for 32 bit values.
<> 133:99b5ccf27215 659
<> 133:99b5ccf27215 660 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 661 \return value of type uint32_t at (*ptr)
<> 133:99b5ccf27215 662 */
<> 133:99b5ccf27215 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
<> 133:99b5ccf27215 664 {
<> 133:99b5ccf27215 665 uint32_t result;
<> 133:99b5ccf27215 666
<> 133:99b5ccf27215 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
<> 133:99b5ccf27215 668 return(result);
<> 133:99b5ccf27215 669 }
<> 133:99b5ccf27215 670
<> 133:99b5ccf27215 671
<> 133:99b5ccf27215 672 /** \brief STR Exclusive (8 bit)
<> 133:99b5ccf27215 673
<> 133:99b5ccf27215 674 This function executes a exclusive STR instruction for 8 bit values.
<> 133:99b5ccf27215 675
<> 133:99b5ccf27215 676 \param [in] value Value to store
<> 133:99b5ccf27215 677 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 678 \return 0 Function succeeded
<> 133:99b5ccf27215 679 \return 1 Function failed
<> 133:99b5ccf27215 680 */
<> 133:99b5ccf27215 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
<> 133:99b5ccf27215 682 {
<> 133:99b5ccf27215 683 uint32_t result;
<> 133:99b5ccf27215 684
<> 133:99b5ccf27215 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 133:99b5ccf27215 686 return(result);
<> 133:99b5ccf27215 687 }
<> 133:99b5ccf27215 688
<> 133:99b5ccf27215 689
<> 133:99b5ccf27215 690 /** \brief STR Exclusive (16 bit)
<> 133:99b5ccf27215 691
<> 133:99b5ccf27215 692 This function executes a exclusive STR instruction for 16 bit values.
<> 133:99b5ccf27215 693
<> 133:99b5ccf27215 694 \param [in] value Value to store
<> 133:99b5ccf27215 695 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 696 \return 0 Function succeeded
<> 133:99b5ccf27215 697 \return 1 Function failed
<> 133:99b5ccf27215 698 */
<> 133:99b5ccf27215 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
<> 133:99b5ccf27215 700 {
<> 133:99b5ccf27215 701 uint32_t result;
<> 133:99b5ccf27215 702
<> 133:99b5ccf27215 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 133:99b5ccf27215 704 return(result);
<> 133:99b5ccf27215 705 }
<> 133:99b5ccf27215 706
<> 133:99b5ccf27215 707
<> 133:99b5ccf27215 708 /** \brief STR Exclusive (32 bit)
<> 133:99b5ccf27215 709
<> 133:99b5ccf27215 710 This function executes a exclusive STR instruction for 32 bit values.
<> 133:99b5ccf27215 711
<> 133:99b5ccf27215 712 \param [in] value Value to store
<> 133:99b5ccf27215 713 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 714 \return 0 Function succeeded
<> 133:99b5ccf27215 715 \return 1 Function failed
<> 133:99b5ccf27215 716 */
<> 133:99b5ccf27215 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
<> 133:99b5ccf27215 718 {
<> 133:99b5ccf27215 719 uint32_t result;
<> 133:99b5ccf27215 720
<> 133:99b5ccf27215 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
<> 133:99b5ccf27215 722 return(result);
<> 133:99b5ccf27215 723 }
<> 133:99b5ccf27215 724
<> 133:99b5ccf27215 725
<> 133:99b5ccf27215 726 /** \brief Remove the exclusive lock
<> 133:99b5ccf27215 727
<> 133:99b5ccf27215 728 This function removes the exclusive lock which is created by LDREX.
<> 133:99b5ccf27215 729
<> 133:99b5ccf27215 730 */
<> 133:99b5ccf27215 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
<> 133:99b5ccf27215 732 {
<> 133:99b5ccf27215 733 __ASM volatile ("clrex" ::: "memory");
<> 133:99b5ccf27215 734 }
<> 133:99b5ccf27215 735
<> 133:99b5ccf27215 736
<> 133:99b5ccf27215 737 /** \brief Signed Saturate
<> 133:99b5ccf27215 738
<> 133:99b5ccf27215 739 This function saturates a signed value.
<> 133:99b5ccf27215 740
<> 133:99b5ccf27215 741 \param [in] value Value to be saturated
<> 133:99b5ccf27215 742 \param [in] sat Bit position to saturate to (1..32)
<> 133:99b5ccf27215 743 \return Saturated value
<> 133:99b5ccf27215 744 */
<> 133:99b5ccf27215 745 #define __SSAT(ARG1,ARG2) \
<> 133:99b5ccf27215 746 ({ \
<> 133:99b5ccf27215 747 uint32_t __RES, __ARG1 = (ARG1); \
<> 133:99b5ccf27215 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 133:99b5ccf27215 749 __RES; \
<> 133:99b5ccf27215 750 })
<> 133:99b5ccf27215 751
<> 133:99b5ccf27215 752
<> 133:99b5ccf27215 753 /** \brief Unsigned Saturate
<> 133:99b5ccf27215 754
<> 133:99b5ccf27215 755 This function saturates an unsigned value.
<> 133:99b5ccf27215 756
<> 133:99b5ccf27215 757 \param [in] value Value to be saturated
<> 133:99b5ccf27215 758 \param [in] sat Bit position to saturate to (0..31)
<> 133:99b5ccf27215 759 \return Saturated value
<> 133:99b5ccf27215 760 */
<> 133:99b5ccf27215 761 #define __USAT(ARG1,ARG2) \
<> 133:99b5ccf27215 762 ({ \
<> 133:99b5ccf27215 763 uint32_t __RES, __ARG1 = (ARG1); \
<> 133:99b5ccf27215 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 133:99b5ccf27215 765 __RES; \
<> 133:99b5ccf27215 766 })
<> 133:99b5ccf27215 767
<> 133:99b5ccf27215 768
<> 133:99b5ccf27215 769 /** \brief Rotate Right with Extend (32 bit)
<> 133:99b5ccf27215 770
<> 133:99b5ccf27215 771 This function moves each bit of a bitstring right by one bit.
<> 133:99b5ccf27215 772 The carry input is shifted in at the left end of the bitstring.
<> 133:99b5ccf27215 773
<> 133:99b5ccf27215 774 \param [in] value Value to rotate
<> 133:99b5ccf27215 775 \return Rotated value
<> 133:99b5ccf27215 776 */
<> 133:99b5ccf27215 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
<> 133:99b5ccf27215 778 {
<> 133:99b5ccf27215 779 uint32_t result;
<> 133:99b5ccf27215 780
<> 133:99b5ccf27215 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 133:99b5ccf27215 782 return(result);
<> 133:99b5ccf27215 783 }
<> 133:99b5ccf27215 784
<> 133:99b5ccf27215 785
<> 133:99b5ccf27215 786 /** \brief LDRT Unprivileged (8 bit)
<> 133:99b5ccf27215 787
<> 133:99b5ccf27215 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 133:99b5ccf27215 789
<> 133:99b5ccf27215 790 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 791 \return value of type uint8_t at (*ptr)
<> 133:99b5ccf27215 792 */
<> 133:99b5ccf27215 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
<> 133:99b5ccf27215 794 {
<> 133:99b5ccf27215 795 uint32_t result;
<> 133:99b5ccf27215 796
<> 133:99b5ccf27215 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 133:99b5ccf27215 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 133:99b5ccf27215 799 #else
<> 133:99b5ccf27215 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 133:99b5ccf27215 801 accepted by assembler. So has to use following less efficient pattern.
<> 133:99b5ccf27215 802 */
<> 133:99b5ccf27215 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 133:99b5ccf27215 804 #endif
<> 133:99b5ccf27215 805 return ((uint8_t) result); /* Add explicit type cast here */
<> 133:99b5ccf27215 806 }
<> 133:99b5ccf27215 807
<> 133:99b5ccf27215 808
<> 133:99b5ccf27215 809 /** \brief LDRT Unprivileged (16 bit)
<> 133:99b5ccf27215 810
<> 133:99b5ccf27215 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 133:99b5ccf27215 812
<> 133:99b5ccf27215 813 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 814 \return value of type uint16_t at (*ptr)
<> 133:99b5ccf27215 815 */
<> 133:99b5ccf27215 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
<> 133:99b5ccf27215 817 {
<> 133:99b5ccf27215 818 uint32_t result;
<> 133:99b5ccf27215 819
<> 133:99b5ccf27215 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 133:99b5ccf27215 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
<> 133:99b5ccf27215 822 #else
<> 133:99b5ccf27215 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 133:99b5ccf27215 824 accepted by assembler. So has to use following less efficient pattern.
<> 133:99b5ccf27215 825 */
<> 133:99b5ccf27215 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 133:99b5ccf27215 827 #endif
<> 133:99b5ccf27215 828 return ((uint16_t) result); /* Add explicit type cast here */
<> 133:99b5ccf27215 829 }
<> 133:99b5ccf27215 830
<> 133:99b5ccf27215 831
<> 133:99b5ccf27215 832 /** \brief LDRT Unprivileged (32 bit)
<> 133:99b5ccf27215 833
<> 133:99b5ccf27215 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 133:99b5ccf27215 835
<> 133:99b5ccf27215 836 \param [in] ptr Pointer to data
<> 133:99b5ccf27215 837 \return value of type uint32_t at (*ptr)
<> 133:99b5ccf27215 838 */
<> 133:99b5ccf27215 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
<> 133:99b5ccf27215 840 {
<> 133:99b5ccf27215 841 uint32_t result;
<> 133:99b5ccf27215 842
<> 133:99b5ccf27215 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 133:99b5ccf27215 844 return(result);
<> 133:99b5ccf27215 845 }
<> 133:99b5ccf27215 846
<> 133:99b5ccf27215 847
<> 133:99b5ccf27215 848 /** \brief STRT Unprivileged (8 bit)
<> 133:99b5ccf27215 849
<> 133:99b5ccf27215 850 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 133:99b5ccf27215 851
<> 133:99b5ccf27215 852 \param [in] value Value to store
<> 133:99b5ccf27215 853 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 854 */
<> 133:99b5ccf27215 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
<> 133:99b5ccf27215 856 {
<> 133:99b5ccf27215 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 133:99b5ccf27215 858 }
<> 133:99b5ccf27215 859
<> 133:99b5ccf27215 860
<> 133:99b5ccf27215 861 /** \brief STRT Unprivileged (16 bit)
<> 133:99b5ccf27215 862
<> 133:99b5ccf27215 863 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 133:99b5ccf27215 864
<> 133:99b5ccf27215 865 \param [in] value Value to store
<> 133:99b5ccf27215 866 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 867 */
<> 133:99b5ccf27215 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
<> 133:99b5ccf27215 869 {
<> 133:99b5ccf27215 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 133:99b5ccf27215 871 }
<> 133:99b5ccf27215 872
<> 133:99b5ccf27215 873
<> 133:99b5ccf27215 874 /** \brief STRT Unprivileged (32 bit)
<> 133:99b5ccf27215 875
<> 133:99b5ccf27215 876 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 133:99b5ccf27215 877
<> 133:99b5ccf27215 878 \param [in] value Value to store
<> 133:99b5ccf27215 879 \param [in] ptr Pointer to location
<> 133:99b5ccf27215 880 */
<> 133:99b5ccf27215 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
<> 133:99b5ccf27215 882 {
<> 133:99b5ccf27215 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
<> 133:99b5ccf27215 884 }
<> 133:99b5ccf27215 885
<> 133:99b5ccf27215 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 133:99b5ccf27215 887
<> 133:99b5ccf27215 888
<> 133:99b5ccf27215 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 133:99b5ccf27215 890 /* IAR iccarm specific functions */
<> 133:99b5ccf27215 891 #include <cmsis_iar.h>
<> 133:99b5ccf27215 892
<> 133:99b5ccf27215 893
<> 133:99b5ccf27215 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 133:99b5ccf27215 895 /* TI CCS specific functions */
<> 133:99b5ccf27215 896 #include <cmsis_ccs.h>
<> 133:99b5ccf27215 897
<> 133:99b5ccf27215 898
<> 133:99b5ccf27215 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 133:99b5ccf27215 900 /* TASKING carm specific functions */
<> 133:99b5ccf27215 901 /*
<> 133:99b5ccf27215 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 133:99b5ccf27215 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 133:99b5ccf27215 904 * Including the CMSIS ones.
<> 133:99b5ccf27215 905 */
<> 133:99b5ccf27215 906
<> 133:99b5ccf27215 907
<> 133:99b5ccf27215 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 133:99b5ccf27215 909 /* Cosmic specific functions */
<> 133:99b5ccf27215 910 #include <cmsis_csm.h>
<> 133:99b5ccf27215 911
<> 133:99b5ccf27215 912 #endif
<> 133:99b5ccf27215 913
<> 133:99b5ccf27215 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
<> 133:99b5ccf27215 915
<> 133:99b5ccf27215 916 #endif /* __CORE_CMINSTR_H */