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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_UBLOX_EVK_NINA_B1/core_cmFunc.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
133:99b5ccf27215 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 133:99b5ccf27215 1 /**************************************************************************//**
<> 133:99b5ccf27215 2 * @file core_cmFunc.h
<> 133:99b5ccf27215 3 * @brief CMSIS Cortex-M Core Function Access Header File
<> 133:99b5ccf27215 4 * @version V4.10
<> 133:99b5ccf27215 5 * @date 18. March 2015
<> 133:99b5ccf27215 6 *
<> 133:99b5ccf27215 7 * @note
<> 133:99b5ccf27215 8 *
<> 133:99b5ccf27215 9 ******************************************************************************/
<> 133:99b5ccf27215 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 133:99b5ccf27215 11
<> 133:99b5ccf27215 12 All rights reserved.
<> 133:99b5ccf27215 13 Redistribution and use in source and binary forms, with or without
<> 133:99b5ccf27215 14 modification, are permitted provided that the following conditions are met:
<> 133:99b5ccf27215 15 - Redistributions of source code must retain the above copyright
<> 133:99b5ccf27215 16 notice, this list of conditions and the following disclaimer.
<> 133:99b5ccf27215 17 - Redistributions in binary form must reproduce the above copyright
<> 133:99b5ccf27215 18 notice, this list of conditions and the following disclaimer in the
<> 133:99b5ccf27215 19 documentation and/or other materials provided with the distribution.
<> 133:99b5ccf27215 20 - Neither the name of ARM nor the names of its contributors may be used
<> 133:99b5ccf27215 21 to endorse or promote products derived from this software without
<> 133:99b5ccf27215 22 specific prior written permission.
<> 133:99b5ccf27215 23 *
<> 133:99b5ccf27215 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 133:99b5ccf27215 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 133:99b5ccf27215 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 133:99b5ccf27215 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 133:99b5ccf27215 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 133:99b5ccf27215 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 133:99b5ccf27215 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 133:99b5ccf27215 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 133:99b5ccf27215 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 133:99b5ccf27215 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 133:99b5ccf27215 34 POSSIBILITY OF SUCH DAMAGE.
<> 133:99b5ccf27215 35 ---------------------------------------------------------------------------*/
<> 133:99b5ccf27215 36
<> 133:99b5ccf27215 37
<> 133:99b5ccf27215 38 #ifndef __CORE_CMFUNC_H
<> 133:99b5ccf27215 39 #define __CORE_CMFUNC_H
<> 133:99b5ccf27215 40
<> 133:99b5ccf27215 41
<> 133:99b5ccf27215 42 /* ########################### Core Function Access ########################### */
<> 133:99b5ccf27215 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 133:99b5ccf27215 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 133:99b5ccf27215 45 @{
<> 133:99b5ccf27215 46 */
<> 133:99b5ccf27215 47
<> 133:99b5ccf27215 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 133:99b5ccf27215 49 /* ARM armcc specific functions */
<> 133:99b5ccf27215 50
<> 133:99b5ccf27215 51 #if (__ARMCC_VERSION < 400677)
<> 133:99b5ccf27215 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 133:99b5ccf27215 53 #endif
<> 133:99b5ccf27215 54
<> 133:99b5ccf27215 55 /* intrinsic void __enable_irq(); */
<> 133:99b5ccf27215 56 /* intrinsic void __disable_irq(); */
<> 133:99b5ccf27215 57
<> 133:99b5ccf27215 58 /** \brief Get Control Register
<> 133:99b5ccf27215 59
<> 133:99b5ccf27215 60 This function returns the content of the Control Register.
<> 133:99b5ccf27215 61
<> 133:99b5ccf27215 62 \return Control Register value
<> 133:99b5ccf27215 63 */
<> 133:99b5ccf27215 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 133:99b5ccf27215 65 {
<> 133:99b5ccf27215 66 register uint32_t __regControl __ASM("control");
<> 133:99b5ccf27215 67 return(__regControl);
<> 133:99b5ccf27215 68 }
<> 133:99b5ccf27215 69
<> 133:99b5ccf27215 70
<> 133:99b5ccf27215 71 /** \brief Set Control Register
<> 133:99b5ccf27215 72
<> 133:99b5ccf27215 73 This function writes the given value to the Control Register.
<> 133:99b5ccf27215 74
<> 133:99b5ccf27215 75 \param [in] control Control Register value to set
<> 133:99b5ccf27215 76 */
<> 133:99b5ccf27215 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 133:99b5ccf27215 78 {
<> 133:99b5ccf27215 79 register uint32_t __regControl __ASM("control");
<> 133:99b5ccf27215 80 __regControl = control;
<> 133:99b5ccf27215 81 }
<> 133:99b5ccf27215 82
<> 133:99b5ccf27215 83
<> 133:99b5ccf27215 84 /** \brief Get IPSR Register
<> 133:99b5ccf27215 85
<> 133:99b5ccf27215 86 This function returns the content of the IPSR Register.
<> 133:99b5ccf27215 87
<> 133:99b5ccf27215 88 \return IPSR Register value
<> 133:99b5ccf27215 89 */
<> 133:99b5ccf27215 90 __STATIC_INLINE uint32_t __get_IPSR(void)
<> 133:99b5ccf27215 91 {
<> 133:99b5ccf27215 92 register uint32_t __regIPSR __ASM("ipsr");
<> 133:99b5ccf27215 93 return(__regIPSR);
<> 133:99b5ccf27215 94 }
<> 133:99b5ccf27215 95
<> 133:99b5ccf27215 96
<> 133:99b5ccf27215 97 /** \brief Get APSR Register
<> 133:99b5ccf27215 98
<> 133:99b5ccf27215 99 This function returns the content of the APSR Register.
<> 133:99b5ccf27215 100
<> 133:99b5ccf27215 101 \return APSR Register value
<> 133:99b5ccf27215 102 */
<> 133:99b5ccf27215 103 __STATIC_INLINE uint32_t __get_APSR(void)
<> 133:99b5ccf27215 104 {
<> 133:99b5ccf27215 105 register uint32_t __regAPSR __ASM("apsr");
<> 133:99b5ccf27215 106 return(__regAPSR);
<> 133:99b5ccf27215 107 }
<> 133:99b5ccf27215 108
<> 133:99b5ccf27215 109
<> 133:99b5ccf27215 110 /** \brief Get xPSR Register
<> 133:99b5ccf27215 111
<> 133:99b5ccf27215 112 This function returns the content of the xPSR Register.
<> 133:99b5ccf27215 113
<> 133:99b5ccf27215 114 \return xPSR Register value
<> 133:99b5ccf27215 115 */
<> 133:99b5ccf27215 116 __STATIC_INLINE uint32_t __get_xPSR(void)
<> 133:99b5ccf27215 117 {
<> 133:99b5ccf27215 118 register uint32_t __regXPSR __ASM("xpsr");
<> 133:99b5ccf27215 119 return(__regXPSR);
<> 133:99b5ccf27215 120 }
<> 133:99b5ccf27215 121
<> 133:99b5ccf27215 122
<> 133:99b5ccf27215 123 /** \brief Get Process Stack Pointer
<> 133:99b5ccf27215 124
<> 133:99b5ccf27215 125 This function returns the current value of the Process Stack Pointer (PSP).
<> 133:99b5ccf27215 126
<> 133:99b5ccf27215 127 \return PSP Register value
<> 133:99b5ccf27215 128 */
<> 133:99b5ccf27215 129 __STATIC_INLINE uint32_t __get_PSP(void)
<> 133:99b5ccf27215 130 {
<> 133:99b5ccf27215 131 register uint32_t __regProcessStackPointer __ASM("psp");
<> 133:99b5ccf27215 132 return(__regProcessStackPointer);
<> 133:99b5ccf27215 133 }
<> 133:99b5ccf27215 134
<> 133:99b5ccf27215 135
<> 133:99b5ccf27215 136 /** \brief Set Process Stack Pointer
<> 133:99b5ccf27215 137
<> 133:99b5ccf27215 138 This function assigns the given value to the Process Stack Pointer (PSP).
<> 133:99b5ccf27215 139
<> 133:99b5ccf27215 140 \param [in] topOfProcStack Process Stack Pointer value to set
<> 133:99b5ccf27215 141 */
<> 133:99b5ccf27215 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 133:99b5ccf27215 143 {
<> 133:99b5ccf27215 144 register uint32_t __regProcessStackPointer __ASM("psp");
<> 133:99b5ccf27215 145 __regProcessStackPointer = topOfProcStack;
<> 133:99b5ccf27215 146 }
<> 133:99b5ccf27215 147
<> 133:99b5ccf27215 148
<> 133:99b5ccf27215 149 /** \brief Get Main Stack Pointer
<> 133:99b5ccf27215 150
<> 133:99b5ccf27215 151 This function returns the current value of the Main Stack Pointer (MSP).
<> 133:99b5ccf27215 152
<> 133:99b5ccf27215 153 \return MSP Register value
<> 133:99b5ccf27215 154 */
<> 133:99b5ccf27215 155 __STATIC_INLINE uint32_t __get_MSP(void)
<> 133:99b5ccf27215 156 {
<> 133:99b5ccf27215 157 register uint32_t __regMainStackPointer __ASM("msp");
<> 133:99b5ccf27215 158 return(__regMainStackPointer);
<> 133:99b5ccf27215 159 }
<> 133:99b5ccf27215 160
<> 133:99b5ccf27215 161
<> 133:99b5ccf27215 162 /** \brief Set Main Stack Pointer
<> 133:99b5ccf27215 163
<> 133:99b5ccf27215 164 This function assigns the given value to the Main Stack Pointer (MSP).
<> 133:99b5ccf27215 165
<> 133:99b5ccf27215 166 \param [in] topOfMainStack Main Stack Pointer value to set
<> 133:99b5ccf27215 167 */
<> 133:99b5ccf27215 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 133:99b5ccf27215 169 {
<> 133:99b5ccf27215 170 register uint32_t __regMainStackPointer __ASM("msp");
<> 133:99b5ccf27215 171 __regMainStackPointer = topOfMainStack;
<> 133:99b5ccf27215 172 }
<> 133:99b5ccf27215 173
<> 133:99b5ccf27215 174
<> 133:99b5ccf27215 175 /** \brief Get Priority Mask
<> 133:99b5ccf27215 176
<> 133:99b5ccf27215 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 133:99b5ccf27215 178
<> 133:99b5ccf27215 179 \return Priority Mask value
<> 133:99b5ccf27215 180 */
<> 133:99b5ccf27215 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 133:99b5ccf27215 182 {
<> 133:99b5ccf27215 183 register uint32_t __regPriMask __ASM("primask");
<> 133:99b5ccf27215 184 return(__regPriMask);
<> 133:99b5ccf27215 185 }
<> 133:99b5ccf27215 186
<> 133:99b5ccf27215 187
<> 133:99b5ccf27215 188 /** \brief Set Priority Mask
<> 133:99b5ccf27215 189
<> 133:99b5ccf27215 190 This function assigns the given value to the Priority Mask Register.
<> 133:99b5ccf27215 191
<> 133:99b5ccf27215 192 \param [in] priMask Priority Mask
<> 133:99b5ccf27215 193 */
<> 133:99b5ccf27215 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 133:99b5ccf27215 195 {
<> 133:99b5ccf27215 196 register uint32_t __regPriMask __ASM("primask");
<> 133:99b5ccf27215 197 __regPriMask = (priMask);
<> 133:99b5ccf27215 198 }
<> 133:99b5ccf27215 199
<> 133:99b5ccf27215 200
<> 133:99b5ccf27215 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 133:99b5ccf27215 202
<> 133:99b5ccf27215 203 /** \brief Enable FIQ
<> 133:99b5ccf27215 204
<> 133:99b5ccf27215 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 133:99b5ccf27215 206 Can only be executed in Privileged modes.
<> 133:99b5ccf27215 207 */
<> 133:99b5ccf27215 208 #define __enable_fault_irq __enable_fiq
<> 133:99b5ccf27215 209
<> 133:99b5ccf27215 210
<> 133:99b5ccf27215 211 /** \brief Disable FIQ
<> 133:99b5ccf27215 212
<> 133:99b5ccf27215 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 133:99b5ccf27215 214 Can only be executed in Privileged modes.
<> 133:99b5ccf27215 215 */
<> 133:99b5ccf27215 216 #define __disable_fault_irq __disable_fiq
<> 133:99b5ccf27215 217
<> 133:99b5ccf27215 218
<> 133:99b5ccf27215 219 /** \brief Get Base Priority
<> 133:99b5ccf27215 220
<> 133:99b5ccf27215 221 This function returns the current value of the Base Priority register.
<> 133:99b5ccf27215 222
<> 133:99b5ccf27215 223 \return Base Priority register value
<> 133:99b5ccf27215 224 */
<> 133:99b5ccf27215 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 133:99b5ccf27215 226 {
<> 133:99b5ccf27215 227 register uint32_t __regBasePri __ASM("basepri");
<> 133:99b5ccf27215 228 return(__regBasePri);
<> 133:99b5ccf27215 229 }
<> 133:99b5ccf27215 230
<> 133:99b5ccf27215 231
<> 133:99b5ccf27215 232 /** \brief Set Base Priority
<> 133:99b5ccf27215 233
<> 133:99b5ccf27215 234 This function assigns the given value to the Base Priority register.
<> 133:99b5ccf27215 235
<> 133:99b5ccf27215 236 \param [in] basePri Base Priority value to set
<> 133:99b5ccf27215 237 */
<> 133:99b5ccf27215 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
<> 133:99b5ccf27215 239 {
<> 133:99b5ccf27215 240 register uint32_t __regBasePri __ASM("basepri");
<> 133:99b5ccf27215 241 __regBasePri = (basePri & 0xff);
<> 133:99b5ccf27215 242 }
<> 133:99b5ccf27215 243
<> 133:99b5ccf27215 244
<> 133:99b5ccf27215 245 /** \brief Set Base Priority with condition
<> 133:99b5ccf27215 246
<> 133:99b5ccf27215 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 133:99b5ccf27215 248 or the new value increases the BASEPRI priority level.
<> 133:99b5ccf27215 249
<> 133:99b5ccf27215 250 \param [in] basePri Base Priority value to set
<> 133:99b5ccf27215 251 */
<> 133:99b5ccf27215 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
<> 133:99b5ccf27215 253 {
<> 133:99b5ccf27215 254 register uint32_t __regBasePriMax __ASM("basepri_max");
<> 133:99b5ccf27215 255 __regBasePriMax = (basePri & 0xff);
<> 133:99b5ccf27215 256 }
<> 133:99b5ccf27215 257
<> 133:99b5ccf27215 258
<> 133:99b5ccf27215 259 /** \brief Get Fault Mask
<> 133:99b5ccf27215 260
<> 133:99b5ccf27215 261 This function returns the current value of the Fault Mask register.
<> 133:99b5ccf27215 262
<> 133:99b5ccf27215 263 \return Fault Mask register value
<> 133:99b5ccf27215 264 */
<> 133:99b5ccf27215 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 133:99b5ccf27215 266 {
<> 133:99b5ccf27215 267 register uint32_t __regFaultMask __ASM("faultmask");
<> 133:99b5ccf27215 268 return(__regFaultMask);
<> 133:99b5ccf27215 269 }
<> 133:99b5ccf27215 270
<> 133:99b5ccf27215 271
<> 133:99b5ccf27215 272 /** \brief Set Fault Mask
<> 133:99b5ccf27215 273
<> 133:99b5ccf27215 274 This function assigns the given value to the Fault Mask register.
<> 133:99b5ccf27215 275
<> 133:99b5ccf27215 276 \param [in] faultMask Fault Mask value to set
<> 133:99b5ccf27215 277 */
<> 133:99b5ccf27215 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 133:99b5ccf27215 279 {
<> 133:99b5ccf27215 280 register uint32_t __regFaultMask __ASM("faultmask");
<> 133:99b5ccf27215 281 __regFaultMask = (faultMask & (uint32_t)1);
<> 133:99b5ccf27215 282 }
<> 133:99b5ccf27215 283
<> 133:99b5ccf27215 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 133:99b5ccf27215 285
<> 133:99b5ccf27215 286
<> 133:99b5ccf27215 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 133:99b5ccf27215 288
<> 133:99b5ccf27215 289 /** \brief Get FPSCR
<> 133:99b5ccf27215 290
<> 133:99b5ccf27215 291 This function returns the current value of the Floating Point Status/Control register.
<> 133:99b5ccf27215 292
<> 133:99b5ccf27215 293 \return Floating Point Status/Control register value
<> 133:99b5ccf27215 294 */
<> 133:99b5ccf27215 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 133:99b5ccf27215 296 {
<> 133:99b5ccf27215 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 133:99b5ccf27215 298 register uint32_t __regfpscr __ASM("fpscr");
<> 133:99b5ccf27215 299 return(__regfpscr);
<> 133:99b5ccf27215 300 #else
<> 133:99b5ccf27215 301 return(0);
<> 133:99b5ccf27215 302 #endif
<> 133:99b5ccf27215 303 }
<> 133:99b5ccf27215 304
<> 133:99b5ccf27215 305
<> 133:99b5ccf27215 306 /** \brief Set FPSCR
<> 133:99b5ccf27215 307
<> 133:99b5ccf27215 308 This function assigns the given value to the Floating Point Status/Control register.
<> 133:99b5ccf27215 309
<> 133:99b5ccf27215 310 \param [in] fpscr Floating Point Status/Control value to set
<> 133:99b5ccf27215 311 */
<> 133:99b5ccf27215 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 133:99b5ccf27215 313 {
<> 133:99b5ccf27215 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 133:99b5ccf27215 315 register uint32_t __regfpscr __ASM("fpscr");
<> 133:99b5ccf27215 316 __regfpscr = (fpscr);
<> 133:99b5ccf27215 317 #endif
<> 133:99b5ccf27215 318 }
<> 133:99b5ccf27215 319
<> 133:99b5ccf27215 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 133:99b5ccf27215 321
<> 133:99b5ccf27215 322
<> 133:99b5ccf27215 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 133:99b5ccf27215 324 /* GNU gcc specific functions */
<> 133:99b5ccf27215 325
<> 133:99b5ccf27215 326 /** \brief Enable IRQ Interrupts
<> 133:99b5ccf27215 327
<> 133:99b5ccf27215 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
<> 133:99b5ccf27215 329 Can only be executed in Privileged modes.
<> 133:99b5ccf27215 330 */
<> 133:99b5ccf27215 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 133:99b5ccf27215 332 {
<> 133:99b5ccf27215 333 __ASM volatile ("cpsie i" : : : "memory");
<> 133:99b5ccf27215 334 }
<> 133:99b5ccf27215 335
<> 133:99b5ccf27215 336
<> 133:99b5ccf27215 337 /** \brief Disable IRQ Interrupts
<> 133:99b5ccf27215 338
<> 133:99b5ccf27215 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 133:99b5ccf27215 340 Can only be executed in Privileged modes.
<> 133:99b5ccf27215 341 */
<> 133:99b5ccf27215 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
<> 133:99b5ccf27215 343 {
<> 133:99b5ccf27215 344 __ASM volatile ("cpsid i" : : : "memory");
<> 133:99b5ccf27215 345 }
<> 133:99b5ccf27215 346
<> 133:99b5ccf27215 347
<> 133:99b5ccf27215 348 /** \brief Get Control Register
<> 133:99b5ccf27215 349
<> 133:99b5ccf27215 350 This function returns the content of the Control Register.
<> 133:99b5ccf27215 351
<> 133:99b5ccf27215 352 \return Control Register value
<> 133:99b5ccf27215 353 */
<> 133:99b5ccf27215 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 133:99b5ccf27215 355 {
<> 133:99b5ccf27215 356 uint32_t result;
<> 133:99b5ccf27215 357
<> 133:99b5ccf27215 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
<> 133:99b5ccf27215 359 return(result);
<> 133:99b5ccf27215 360 }
<> 133:99b5ccf27215 361
<> 133:99b5ccf27215 362
<> 133:99b5ccf27215 363 /** \brief Set Control Register
<> 133:99b5ccf27215 364
<> 133:99b5ccf27215 365 This function writes the given value to the Control Register.
<> 133:99b5ccf27215 366
<> 133:99b5ccf27215 367 \param [in] control Control Register value to set
<> 133:99b5ccf27215 368 */
<> 133:99b5ccf27215 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 133:99b5ccf27215 370 {
<> 133:99b5ccf27215 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
<> 133:99b5ccf27215 372 }
<> 133:99b5ccf27215 373
<> 133:99b5ccf27215 374
<> 133:99b5ccf27215 375 /** \brief Get IPSR Register
<> 133:99b5ccf27215 376
<> 133:99b5ccf27215 377 This function returns the content of the IPSR Register.
<> 133:99b5ccf27215 378
<> 133:99b5ccf27215 379 \return IPSR Register value
<> 133:99b5ccf27215 380 */
<> 133:99b5ccf27215 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
<> 133:99b5ccf27215 382 {
<> 133:99b5ccf27215 383 uint32_t result;
<> 133:99b5ccf27215 384
<> 133:99b5ccf27215 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
<> 133:99b5ccf27215 386 return(result);
<> 133:99b5ccf27215 387 }
<> 133:99b5ccf27215 388
<> 133:99b5ccf27215 389
<> 133:99b5ccf27215 390 /** \brief Get APSR Register
<> 133:99b5ccf27215 391
<> 133:99b5ccf27215 392 This function returns the content of the APSR Register.
<> 133:99b5ccf27215 393
<> 133:99b5ccf27215 394 \return APSR Register value
<> 133:99b5ccf27215 395 */
<> 133:99b5ccf27215 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 133:99b5ccf27215 397 {
<> 133:99b5ccf27215 398 uint32_t result;
<> 133:99b5ccf27215 399
<> 133:99b5ccf27215 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
<> 133:99b5ccf27215 401 return(result);
<> 133:99b5ccf27215 402 }
<> 133:99b5ccf27215 403
<> 133:99b5ccf27215 404
<> 133:99b5ccf27215 405 /** \brief Get xPSR Register
<> 133:99b5ccf27215 406
<> 133:99b5ccf27215 407 This function returns the content of the xPSR Register.
<> 133:99b5ccf27215 408
<> 133:99b5ccf27215 409 \return xPSR Register value
<> 133:99b5ccf27215 410 */
<> 133:99b5ccf27215 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
<> 133:99b5ccf27215 412 {
<> 133:99b5ccf27215 413 uint32_t result;
<> 133:99b5ccf27215 414
<> 133:99b5ccf27215 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
<> 133:99b5ccf27215 416 return(result);
<> 133:99b5ccf27215 417 }
<> 133:99b5ccf27215 418
<> 133:99b5ccf27215 419
<> 133:99b5ccf27215 420 /** \brief Get Process Stack Pointer
<> 133:99b5ccf27215 421
<> 133:99b5ccf27215 422 This function returns the current value of the Process Stack Pointer (PSP).
<> 133:99b5ccf27215 423
<> 133:99b5ccf27215 424 \return PSP Register value
<> 133:99b5ccf27215 425 */
<> 133:99b5ccf27215 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
<> 133:99b5ccf27215 427 {
<> 133:99b5ccf27215 428 register uint32_t result;
<> 133:99b5ccf27215 429
<> 133:99b5ccf27215 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
<> 133:99b5ccf27215 431 return(result);
<> 133:99b5ccf27215 432 }
<> 133:99b5ccf27215 433
<> 133:99b5ccf27215 434
<> 133:99b5ccf27215 435 /** \brief Set Process Stack Pointer
<> 133:99b5ccf27215 436
<> 133:99b5ccf27215 437 This function assigns the given value to the Process Stack Pointer (PSP).
<> 133:99b5ccf27215 438
<> 133:99b5ccf27215 439 \param [in] topOfProcStack Process Stack Pointer value to set
<> 133:99b5ccf27215 440 */
<> 133:99b5ccf27215 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 133:99b5ccf27215 442 {
<> 133:99b5ccf27215 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
<> 133:99b5ccf27215 444 }
<> 133:99b5ccf27215 445
<> 133:99b5ccf27215 446
<> 133:99b5ccf27215 447 /** \brief Get Main Stack Pointer
<> 133:99b5ccf27215 448
<> 133:99b5ccf27215 449 This function returns the current value of the Main Stack Pointer (MSP).
<> 133:99b5ccf27215 450
<> 133:99b5ccf27215 451 \return MSP Register value
<> 133:99b5ccf27215 452 */
<> 133:99b5ccf27215 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
<> 133:99b5ccf27215 454 {
<> 133:99b5ccf27215 455 register uint32_t result;
<> 133:99b5ccf27215 456
<> 133:99b5ccf27215 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
<> 133:99b5ccf27215 458 return(result);
<> 133:99b5ccf27215 459 }
<> 133:99b5ccf27215 460
<> 133:99b5ccf27215 461
<> 133:99b5ccf27215 462 /** \brief Set Main Stack Pointer
<> 133:99b5ccf27215 463
<> 133:99b5ccf27215 464 This function assigns the given value to the Main Stack Pointer (MSP).
<> 133:99b5ccf27215 465
<> 133:99b5ccf27215 466 \param [in] topOfMainStack Main Stack Pointer value to set
<> 133:99b5ccf27215 467 */
<> 133:99b5ccf27215 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 133:99b5ccf27215 469 {
<> 133:99b5ccf27215 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
<> 133:99b5ccf27215 471 }
<> 133:99b5ccf27215 472
<> 133:99b5ccf27215 473
<> 133:99b5ccf27215 474 /** \brief Get Priority Mask
<> 133:99b5ccf27215 475
<> 133:99b5ccf27215 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 133:99b5ccf27215 477
<> 133:99b5ccf27215 478 \return Priority Mask value
<> 133:99b5ccf27215 479 */
<> 133:99b5ccf27215 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 133:99b5ccf27215 481 {
<> 133:99b5ccf27215 482 uint32_t result;
<> 133:99b5ccf27215 483
<> 133:99b5ccf27215 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
<> 133:99b5ccf27215 485 return(result);
<> 133:99b5ccf27215 486 }
<> 133:99b5ccf27215 487
<> 133:99b5ccf27215 488
<> 133:99b5ccf27215 489 /** \brief Set Priority Mask
<> 133:99b5ccf27215 490
<> 133:99b5ccf27215 491 This function assigns the given value to the Priority Mask Register.
<> 133:99b5ccf27215 492
<> 133:99b5ccf27215 493 \param [in] priMask Priority Mask
<> 133:99b5ccf27215 494 */
<> 133:99b5ccf27215 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 133:99b5ccf27215 496 {
<> 133:99b5ccf27215 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
<> 133:99b5ccf27215 498 }
<> 133:99b5ccf27215 499
<> 133:99b5ccf27215 500
<> 133:99b5ccf27215 501 #if (__CORTEX_M >= 0x03)
<> 133:99b5ccf27215 502
<> 133:99b5ccf27215 503 /** \brief Enable FIQ
<> 133:99b5ccf27215 504
<> 133:99b5ccf27215 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 133:99b5ccf27215 506 Can only be executed in Privileged modes.
<> 133:99b5ccf27215 507 */
<> 133:99b5ccf27215 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
<> 133:99b5ccf27215 509 {
<> 133:99b5ccf27215 510 __ASM volatile ("cpsie f" : : : "memory");
<> 133:99b5ccf27215 511 }
<> 133:99b5ccf27215 512
<> 133:99b5ccf27215 513
<> 133:99b5ccf27215 514 /** \brief Disable FIQ
<> 133:99b5ccf27215 515
<> 133:99b5ccf27215 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 133:99b5ccf27215 517 Can only be executed in Privileged modes.
<> 133:99b5ccf27215 518 */
<> 133:99b5ccf27215 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
<> 133:99b5ccf27215 520 {
<> 133:99b5ccf27215 521 __ASM volatile ("cpsid f" : : : "memory");
<> 133:99b5ccf27215 522 }
<> 133:99b5ccf27215 523
<> 133:99b5ccf27215 524
<> 133:99b5ccf27215 525 /** \brief Get Base Priority
<> 133:99b5ccf27215 526
<> 133:99b5ccf27215 527 This function returns the current value of the Base Priority register.
<> 133:99b5ccf27215 528
<> 133:99b5ccf27215 529 \return Base Priority register value
<> 133:99b5ccf27215 530 */
<> 133:99b5ccf27215 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 133:99b5ccf27215 532 {
<> 133:99b5ccf27215 533 uint32_t result;
<> 133:99b5ccf27215 534
<> 133:99b5ccf27215 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
<> 133:99b5ccf27215 536 return(result);
<> 133:99b5ccf27215 537 }
<> 133:99b5ccf27215 538
<> 133:99b5ccf27215 539
<> 133:99b5ccf27215 540 /** \brief Set Base Priority
<> 133:99b5ccf27215 541
<> 133:99b5ccf27215 542 This function assigns the given value to the Base Priority register.
<> 133:99b5ccf27215 543
<> 133:99b5ccf27215 544 \param [in] basePri Base Priority value to set
<> 133:99b5ccf27215 545 */
<> 133:99b5ccf27215 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
<> 133:99b5ccf27215 547 {
<> 133:99b5ccf27215 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
<> 133:99b5ccf27215 549 }
<> 133:99b5ccf27215 550
<> 133:99b5ccf27215 551
<> 133:99b5ccf27215 552 /** \brief Set Base Priority with condition
<> 133:99b5ccf27215 553
<> 133:99b5ccf27215 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 133:99b5ccf27215 555 or the new value increases the BASEPRI priority level.
<> 133:99b5ccf27215 556
<> 133:99b5ccf27215 557 \param [in] basePri Base Priority value to set
<> 133:99b5ccf27215 558 */
<> 133:99b5ccf27215 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
<> 133:99b5ccf27215 560 {
<> 133:99b5ccf27215 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
<> 133:99b5ccf27215 562 }
<> 133:99b5ccf27215 563
<> 133:99b5ccf27215 564
<> 133:99b5ccf27215 565 /** \brief Get Fault Mask
<> 133:99b5ccf27215 566
<> 133:99b5ccf27215 567 This function returns the current value of the Fault Mask register.
<> 133:99b5ccf27215 568
<> 133:99b5ccf27215 569 \return Fault Mask register value
<> 133:99b5ccf27215 570 */
<> 133:99b5ccf27215 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 133:99b5ccf27215 572 {
<> 133:99b5ccf27215 573 uint32_t result;
<> 133:99b5ccf27215 574
<> 133:99b5ccf27215 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
<> 133:99b5ccf27215 576 return(result);
<> 133:99b5ccf27215 577 }
<> 133:99b5ccf27215 578
<> 133:99b5ccf27215 579
<> 133:99b5ccf27215 580 /** \brief Set Fault Mask
<> 133:99b5ccf27215 581
<> 133:99b5ccf27215 582 This function assigns the given value to the Fault Mask register.
<> 133:99b5ccf27215 583
<> 133:99b5ccf27215 584 \param [in] faultMask Fault Mask value to set
<> 133:99b5ccf27215 585 */
<> 133:99b5ccf27215 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 133:99b5ccf27215 587 {
<> 133:99b5ccf27215 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
<> 133:99b5ccf27215 589 }
<> 133:99b5ccf27215 590
<> 133:99b5ccf27215 591 #endif /* (__CORTEX_M >= 0x03) */
<> 133:99b5ccf27215 592
<> 133:99b5ccf27215 593
<> 133:99b5ccf27215 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 133:99b5ccf27215 595
<> 133:99b5ccf27215 596 /** \brief Get FPSCR
<> 133:99b5ccf27215 597
<> 133:99b5ccf27215 598 This function returns the current value of the Floating Point Status/Control register.
<> 133:99b5ccf27215 599
<> 133:99b5ccf27215 600 \return Floating Point Status/Control register value
<> 133:99b5ccf27215 601 */
<> 133:99b5ccf27215 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 133:99b5ccf27215 603 {
<> 133:99b5ccf27215 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 133:99b5ccf27215 605 uint32_t result;
<> 133:99b5ccf27215 606
<> 133:99b5ccf27215 607 /* Empty asm statement works as a scheduling barrier */
<> 133:99b5ccf27215 608 __ASM volatile ("");
<> 133:99b5ccf27215 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
<> 133:99b5ccf27215 610 __ASM volatile ("");
<> 133:99b5ccf27215 611 return(result);
<> 133:99b5ccf27215 612 #else
<> 133:99b5ccf27215 613 return(0);
<> 133:99b5ccf27215 614 #endif
<> 133:99b5ccf27215 615 }
<> 133:99b5ccf27215 616
<> 133:99b5ccf27215 617
<> 133:99b5ccf27215 618 /** \brief Set FPSCR
<> 133:99b5ccf27215 619
<> 133:99b5ccf27215 620 This function assigns the given value to the Floating Point Status/Control register.
<> 133:99b5ccf27215 621
<> 133:99b5ccf27215 622 \param [in] fpscr Floating Point Status/Control value to set
<> 133:99b5ccf27215 623 */
<> 133:99b5ccf27215 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 133:99b5ccf27215 625 {
<> 133:99b5ccf27215 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 133:99b5ccf27215 627 /* Empty asm statement works as a scheduling barrier */
<> 133:99b5ccf27215 628 __ASM volatile ("");
<> 133:99b5ccf27215 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
<> 133:99b5ccf27215 630 __ASM volatile ("");
<> 133:99b5ccf27215 631 #endif
<> 133:99b5ccf27215 632 }
<> 133:99b5ccf27215 633
<> 133:99b5ccf27215 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 133:99b5ccf27215 635
<> 133:99b5ccf27215 636
<> 133:99b5ccf27215 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 133:99b5ccf27215 638 /* IAR iccarm specific functions */
<> 133:99b5ccf27215 639 #include <cmsis_iar.h>
<> 133:99b5ccf27215 640
<> 133:99b5ccf27215 641
<> 133:99b5ccf27215 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 133:99b5ccf27215 643 /* TI CCS specific functions */
<> 133:99b5ccf27215 644 #include <cmsis_ccs.h>
<> 133:99b5ccf27215 645
<> 133:99b5ccf27215 646
<> 133:99b5ccf27215 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 133:99b5ccf27215 648 /* TASKING carm specific functions */
<> 133:99b5ccf27215 649 /*
<> 133:99b5ccf27215 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 133:99b5ccf27215 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 133:99b5ccf27215 652 * Including the CMSIS ones.
<> 133:99b5ccf27215 653 */
<> 133:99b5ccf27215 654
<> 133:99b5ccf27215 655
<> 133:99b5ccf27215 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 133:99b5ccf27215 657 /* Cosmic specific functions */
<> 133:99b5ccf27215 658 #include <cmsis_csm.h>
<> 133:99b5ccf27215 659
<> 133:99b5ccf27215 660 #endif
<> 133:99b5ccf27215 661
<> 133:99b5ccf27215 662 /*@} end of CMSIS_Core_RegAccFunctions */
<> 133:99b5ccf27215 663
<> 133:99b5ccf27215 664 #endif /* __CORE_CMFUNC_H */