mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_UBLOX_EVK_NINA_B1/core_ca9.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
133:99b5ccf27215 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 133:99b5ccf27215 1 /**************************************************************************//**
<> 133:99b5ccf27215 2 * @file core_ca9.h
<> 133:99b5ccf27215 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 133:99b5ccf27215 4 * @version
<> 133:99b5ccf27215 5 * @date 25 March 2013
<> 133:99b5ccf27215 6 *
<> 133:99b5ccf27215 7 * @note
<> 133:99b5ccf27215 8 *
<> 133:99b5ccf27215 9 ******************************************************************************/
<> 133:99b5ccf27215 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
<> 133:99b5ccf27215 11
<> 133:99b5ccf27215 12 All rights reserved.
<> 133:99b5ccf27215 13 Redistribution and use in source and binary forms, with or without
<> 133:99b5ccf27215 14 modification, are permitted provided that the following conditions are met:
<> 133:99b5ccf27215 15 - Redistributions of source code must retain the above copyright
<> 133:99b5ccf27215 16 notice, this list of conditions and the following disclaimer.
<> 133:99b5ccf27215 17 - Redistributions in binary form must reproduce the above copyright
<> 133:99b5ccf27215 18 notice, this list of conditions and the following disclaimer in the
<> 133:99b5ccf27215 19 documentation and/or other materials provided with the distribution.
<> 133:99b5ccf27215 20 - Neither the name of ARM nor the names of its contributors may be used
<> 133:99b5ccf27215 21 to endorse or promote products derived from this software without
<> 133:99b5ccf27215 22 specific prior written permission.
<> 133:99b5ccf27215 23 *
<> 133:99b5ccf27215 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 133:99b5ccf27215 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 133:99b5ccf27215 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 133:99b5ccf27215 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 133:99b5ccf27215 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 133:99b5ccf27215 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 133:99b5ccf27215 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 133:99b5ccf27215 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 133:99b5ccf27215 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 133:99b5ccf27215 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 133:99b5ccf27215 34 POSSIBILITY OF SUCH DAMAGE.
<> 133:99b5ccf27215 35 ---------------------------------------------------------------------------*/
<> 133:99b5ccf27215 36
<> 133:99b5ccf27215 37
<> 133:99b5ccf27215 38 #if defined ( __ICCARM__ )
<> 133:99b5ccf27215 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 133:99b5ccf27215 40 #endif
<> 133:99b5ccf27215 41
<> 133:99b5ccf27215 42 #ifdef __cplusplus
<> 133:99b5ccf27215 43 extern "C" {
<> 133:99b5ccf27215 44 #endif
<> 133:99b5ccf27215 45
<> 133:99b5ccf27215 46 #ifndef __CORE_CA9_H_GENERIC
<> 133:99b5ccf27215 47 #define __CORE_CA9_H_GENERIC
<> 133:99b5ccf27215 48
<> 133:99b5ccf27215 49
<> 133:99b5ccf27215 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 133:99b5ccf27215 51 CMSIS violates the following MISRA-C:2004 rules:
<> 133:99b5ccf27215 52
<> 133:99b5ccf27215 53 \li Required Rule 8.5, object/function definition in header file.<br>
<> 133:99b5ccf27215 54 Function definitions in header files are used to allow 'inlining'.
<> 133:99b5ccf27215 55
<> 133:99b5ccf27215 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 133:99b5ccf27215 57 Unions are used for effective representation of core registers.
<> 133:99b5ccf27215 58
<> 133:99b5ccf27215 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 133:99b5ccf27215 60 Function-like macros are used to allow more efficient code.
<> 133:99b5ccf27215 61 */
<> 133:99b5ccf27215 62
<> 133:99b5ccf27215 63
<> 133:99b5ccf27215 64 /*******************************************************************************
<> 133:99b5ccf27215 65 * CMSIS definitions
<> 133:99b5ccf27215 66 ******************************************************************************/
<> 133:99b5ccf27215 67 /** \ingroup Cortex_A9
<> 133:99b5ccf27215 68 @{
<> 133:99b5ccf27215 69 */
<> 133:99b5ccf27215 70
<> 133:99b5ccf27215 71 /* CMSIS CA9 definitions */
<> 133:99b5ccf27215 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
<> 133:99b5ccf27215 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
<> 133:99b5ccf27215 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
<> 133:99b5ccf27215 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 133:99b5ccf27215 76
<> 133:99b5ccf27215 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
<> 133:99b5ccf27215 78
<> 133:99b5ccf27215 79
<> 133:99b5ccf27215 80 #if defined ( __CC_ARM )
<> 133:99b5ccf27215 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 133:99b5ccf27215 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 133:99b5ccf27215 83 #define __STATIC_INLINE static __inline
<> 133:99b5ccf27215 84 #define __STATIC_ASM static __asm
<> 133:99b5ccf27215 85
<> 133:99b5ccf27215 86 #elif defined ( __ICCARM__ )
<> 133:99b5ccf27215 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 133:99b5ccf27215 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 133:99b5ccf27215 89 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 90 #define __STATIC_ASM static __asm
<> 133:99b5ccf27215 91
<> 133:99b5ccf27215 92 #include <stdint.h>
<> 133:99b5ccf27215 93 inline uint32_t __get_PSR(void) {
<> 133:99b5ccf27215 94 __ASM("mrs r0, cpsr");
<> 133:99b5ccf27215 95 }
<> 133:99b5ccf27215 96
<> 133:99b5ccf27215 97 #elif defined ( __TMS470__ )
<> 133:99b5ccf27215 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 133:99b5ccf27215 99 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 100 #define __STATIC_ASM static __asm
<> 133:99b5ccf27215 101
<> 133:99b5ccf27215 102 #elif defined ( __GNUC__ )
<> 133:99b5ccf27215 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 133:99b5ccf27215 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 133:99b5ccf27215 105 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 106 #define __STATIC_ASM static __asm
<> 133:99b5ccf27215 107
<> 133:99b5ccf27215 108 #elif defined ( __TASKING__ )
<> 133:99b5ccf27215 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 133:99b5ccf27215 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 133:99b5ccf27215 111 #define __STATIC_INLINE static inline
<> 133:99b5ccf27215 112 #define __STATIC_ASM static __asm
<> 133:99b5ccf27215 113
<> 133:99b5ccf27215 114 #endif
<> 133:99b5ccf27215 115
<> 133:99b5ccf27215 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 133:99b5ccf27215 117 */
<> 133:99b5ccf27215 118 #if defined ( __CC_ARM )
<> 133:99b5ccf27215 119 #if defined __TARGET_FPU_VFP
<> 133:99b5ccf27215 120 #if (__FPU_PRESENT == 1)
<> 133:99b5ccf27215 121 #define __FPU_USED 1
<> 133:99b5ccf27215 122 #else
<> 133:99b5ccf27215 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 124 #define __FPU_USED 0
<> 133:99b5ccf27215 125 #endif
<> 133:99b5ccf27215 126 #else
<> 133:99b5ccf27215 127 #define __FPU_USED 0
<> 133:99b5ccf27215 128 #endif
<> 133:99b5ccf27215 129
<> 133:99b5ccf27215 130 #elif defined ( __ICCARM__ )
<> 133:99b5ccf27215 131 #if defined __ARMVFP__
<> 133:99b5ccf27215 132 #if (__FPU_PRESENT == 1)
<> 133:99b5ccf27215 133 #define __FPU_USED 1
<> 133:99b5ccf27215 134 #else
<> 133:99b5ccf27215 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 136 #define __FPU_USED 0
<> 133:99b5ccf27215 137 #endif
<> 133:99b5ccf27215 138 #else
<> 133:99b5ccf27215 139 #define __FPU_USED 0
<> 133:99b5ccf27215 140 #endif
<> 133:99b5ccf27215 141
<> 133:99b5ccf27215 142 #elif defined ( __TMS470__ )
<> 133:99b5ccf27215 143 #if defined __TI_VFP_SUPPORT__
<> 133:99b5ccf27215 144 #if (__FPU_PRESENT == 1)
<> 133:99b5ccf27215 145 #define __FPU_USED 1
<> 133:99b5ccf27215 146 #else
<> 133:99b5ccf27215 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 148 #define __FPU_USED 0
<> 133:99b5ccf27215 149 #endif
<> 133:99b5ccf27215 150 #else
<> 133:99b5ccf27215 151 #define __FPU_USED 0
<> 133:99b5ccf27215 152 #endif
<> 133:99b5ccf27215 153
<> 133:99b5ccf27215 154 #elif defined ( __GNUC__ )
<> 133:99b5ccf27215 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 133:99b5ccf27215 156 #if (__FPU_PRESENT == 1)
<> 133:99b5ccf27215 157 #define __FPU_USED 1
<> 133:99b5ccf27215 158 #else
<> 133:99b5ccf27215 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 160 #define __FPU_USED 0
<> 133:99b5ccf27215 161 #endif
<> 133:99b5ccf27215 162 #else
<> 133:99b5ccf27215 163 #define __FPU_USED 0
<> 133:99b5ccf27215 164 #endif
<> 133:99b5ccf27215 165
<> 133:99b5ccf27215 166 #elif defined ( __TASKING__ )
<> 133:99b5ccf27215 167 #if defined __FPU_VFP__
<> 133:99b5ccf27215 168 #if (__FPU_PRESENT == 1)
<> 133:99b5ccf27215 169 #define __FPU_USED 1
<> 133:99b5ccf27215 170 #else
<> 133:99b5ccf27215 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 133:99b5ccf27215 172 #define __FPU_USED 0
<> 133:99b5ccf27215 173 #endif
<> 133:99b5ccf27215 174 #else
<> 133:99b5ccf27215 175 #define __FPU_USED 0
<> 133:99b5ccf27215 176 #endif
<> 133:99b5ccf27215 177 #endif
<> 133:99b5ccf27215 178
<> 133:99b5ccf27215 179 #include <stdint.h> /*!< standard types definitions */
<> 133:99b5ccf27215 180 #include "core_caInstr.h" /*!< Core Instruction Access */
<> 133:99b5ccf27215 181 #include "core_caFunc.h" /*!< Core Function Access */
<> 133:99b5ccf27215 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
<> 133:99b5ccf27215 183
<> 133:99b5ccf27215 184 #endif /* __CORE_CA9_H_GENERIC */
<> 133:99b5ccf27215 185
<> 133:99b5ccf27215 186 #ifndef __CMSIS_GENERIC
<> 133:99b5ccf27215 187
<> 133:99b5ccf27215 188 #ifndef __CORE_CA9_H_DEPENDANT
<> 133:99b5ccf27215 189 #define __CORE_CA9_H_DEPENDANT
<> 133:99b5ccf27215 190
<> 133:99b5ccf27215 191 /* check device defines and use defaults */
<> 133:99b5ccf27215 192 #if defined __CHECK_DEVICE_DEFINES
<> 133:99b5ccf27215 193 #ifndef __CA9_REV
<> 133:99b5ccf27215 194 #define __CA9_REV 0x0000
<> 133:99b5ccf27215 195 #warning "__CA9_REV not defined in device header file; using default!"
<> 133:99b5ccf27215 196 #endif
<> 133:99b5ccf27215 197
<> 133:99b5ccf27215 198 #ifndef __FPU_PRESENT
<> 133:99b5ccf27215 199 #define __FPU_PRESENT 1
<> 133:99b5ccf27215 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 133:99b5ccf27215 201 #endif
<> 133:99b5ccf27215 202
<> 133:99b5ccf27215 203 #ifndef __Vendor_SysTickConfig
<> 133:99b5ccf27215 204 #define __Vendor_SysTickConfig 1
<> 133:99b5ccf27215 205 #endif
<> 133:99b5ccf27215 206
<> 133:99b5ccf27215 207 #if __Vendor_SysTickConfig == 0
<> 133:99b5ccf27215 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
<> 133:99b5ccf27215 209 #endif
<> 133:99b5ccf27215 210 #endif
<> 133:99b5ccf27215 211
<> 133:99b5ccf27215 212 /* IO definitions (access restrictions to peripheral registers) */
<> 133:99b5ccf27215 213 /**
<> 133:99b5ccf27215 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 133:99b5ccf27215 215
<> 133:99b5ccf27215 216 <strong>IO Type Qualifiers</strong> are used
<> 133:99b5ccf27215 217 \li to specify the access to peripheral variables.
<> 133:99b5ccf27215 218 \li for automatic generation of peripheral register debug information.
<> 133:99b5ccf27215 219 */
<> 133:99b5ccf27215 220 #ifdef __cplusplus
<> 133:99b5ccf27215 221 #define __I volatile /*!< Defines 'read only' permissions */
<> 133:99b5ccf27215 222 #else
<> 133:99b5ccf27215 223 #define __I volatile const /*!< Defines 'read only' permissions */
<> 133:99b5ccf27215 224 #endif
<> 133:99b5ccf27215 225 #define __O volatile /*!< Defines 'write only' permissions */
<> 133:99b5ccf27215 226 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 133:99b5ccf27215 227
<> 133:99b5ccf27215 228 /*@} end of group Cortex_A9 */
<> 133:99b5ccf27215 229
<> 133:99b5ccf27215 230
<> 133:99b5ccf27215 231 /*******************************************************************************
<> 133:99b5ccf27215 232 * Register Abstraction
<> 133:99b5ccf27215 233 ******************************************************************************/
<> 133:99b5ccf27215 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 133:99b5ccf27215 235 \brief Type definitions and defines for Cortex-A processor based devices.
<> 133:99b5ccf27215 236 */
<> 133:99b5ccf27215 237
<> 133:99b5ccf27215 238 /** \ingroup CMSIS_core_register
<> 133:99b5ccf27215 239 \defgroup CMSIS_CORE Status and Control Registers
<> 133:99b5ccf27215 240 \brief Core Register type definitions.
<> 133:99b5ccf27215 241 @{
<> 133:99b5ccf27215 242 */
<> 133:99b5ccf27215 243
<> 133:99b5ccf27215 244 /** \brief Union type to access the Application Program Status Register (APSR).
<> 133:99b5ccf27215 245 */
<> 133:99b5ccf27215 246 typedef union
<> 133:99b5ccf27215 247 {
<> 133:99b5ccf27215 248 struct
<> 133:99b5ccf27215 249 {
<> 133:99b5ccf27215 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
<> 133:99b5ccf27215 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 133:99b5ccf27215 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
<> 133:99b5ccf27215 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 133:99b5ccf27215 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 133:99b5ccf27215 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 133:99b5ccf27215 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 133:99b5ccf27215 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 133:99b5ccf27215 258 } b; /*!< Structure used for bit access */
<> 133:99b5ccf27215 259 uint32_t w; /*!< Type used for word access */
<> 133:99b5ccf27215 260 } APSR_Type;
<> 133:99b5ccf27215 261
<> 133:99b5ccf27215 262
<> 133:99b5ccf27215 263 /*@} end of group CMSIS_CORE */
<> 133:99b5ccf27215 264
<> 133:99b5ccf27215 265 /*@} end of CMSIS_Core_FPUFunctions */
<> 133:99b5ccf27215 266
<> 133:99b5ccf27215 267
<> 133:99b5ccf27215 268 #endif /* __CORE_CA9_H_GENERIC */
<> 133:99b5ccf27215 269
<> 133:99b5ccf27215 270 #endif /* __CMSIS_GENERIC */
<> 133:99b5ccf27215 271
<> 133:99b5ccf27215 272 #ifdef __cplusplus
<> 133:99b5ccf27215 273 }
<> 133:99b5ccf27215 274
<> 133:99b5ccf27215 275
<> 133:99b5ccf27215 276 #endif