The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
84:0b3ab51c8877
Release 138 of the mbed library

Ports for Upcoming Targets


Fixes and Changes

3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716
3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741
3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780
3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831
3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836
3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840
3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844
3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850
3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860
3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880
3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795
3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828
3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842
3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843
3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879
3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902
3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**************************************************************************//**
bogdanm 84:0b3ab51c8877 2 * @file core_cm4_simd.h
bogdanm 84:0b3ab51c8877 3 * @brief CMSIS Cortex-M4 SIMD Header File
bogdanm 84:0b3ab51c8877 4 * @version V3.20
bogdanm 84:0b3ab51c8877 5 * @date 25. February 2013
bogdanm 84:0b3ab51c8877 6 *
bogdanm 84:0b3ab51c8877 7 * @note
bogdanm 84:0b3ab51c8877 8 *
bogdanm 84:0b3ab51c8877 9 ******************************************************************************/
bogdanm 84:0b3ab51c8877 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 84:0b3ab51c8877 11
bogdanm 84:0b3ab51c8877 12 All rights reserved.
bogdanm 84:0b3ab51c8877 13 Redistribution and use in source and binary forms, with or without
bogdanm 84:0b3ab51c8877 14 modification, are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 - Redistributions of source code must retain the above copyright
bogdanm 84:0b3ab51c8877 16 notice, this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 84:0b3ab51c8877 18 notice, this list of conditions and the following disclaimer in the
bogdanm 84:0b3ab51c8877 19 documentation and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 84:0b3ab51c8877 21 to endorse or promote products derived from this software without
bogdanm 84:0b3ab51c8877 22 specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 84:0b3ab51c8877 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 84:0b3ab51c8877 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 84:0b3ab51c8877 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 84:0b3ab51c8877 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 84:0b3ab51c8877 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 84:0b3ab51c8877 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 84:0b3ab51c8877 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 84:0b3ab51c8877 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 35 ---------------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 36
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 39 extern "C" {
bogdanm 84:0b3ab51c8877 40 #endif
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifndef __CORE_CM4_SIMD_H
bogdanm 84:0b3ab51c8877 43 #define __CORE_CM4_SIMD_H
bogdanm 84:0b3ab51c8877 44
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /*******************************************************************************
bogdanm 84:0b3ab51c8877 47 * Hardware Abstraction Layer
bogdanm 84:0b3ab51c8877 48 ******************************************************************************/
bogdanm 84:0b3ab51c8877 49
bogdanm 84:0b3ab51c8877 50
bogdanm 84:0b3ab51c8877 51 /* ################### Compiler specific Intrinsics ########################### */
bogdanm 84:0b3ab51c8877 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
bogdanm 84:0b3ab51c8877 53 Access to dedicated SIMD instructions
bogdanm 84:0b3ab51c8877 54 @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 84:0b3ab51c8877 58 /* ARM armcc specific functions */
bogdanm 84:0b3ab51c8877 59
bogdanm 84:0b3ab51c8877 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 61 #define __SADD8 __sadd8
bogdanm 84:0b3ab51c8877 62 #define __QADD8 __qadd8
bogdanm 84:0b3ab51c8877 63 #define __SHADD8 __shadd8
bogdanm 84:0b3ab51c8877 64 #define __UADD8 __uadd8
bogdanm 84:0b3ab51c8877 65 #define __UQADD8 __uqadd8
bogdanm 84:0b3ab51c8877 66 #define __UHADD8 __uhadd8
bogdanm 84:0b3ab51c8877 67 #define __SSUB8 __ssub8
bogdanm 84:0b3ab51c8877 68 #define __QSUB8 __qsub8
bogdanm 84:0b3ab51c8877 69 #define __SHSUB8 __shsub8
bogdanm 84:0b3ab51c8877 70 #define __USUB8 __usub8
bogdanm 84:0b3ab51c8877 71 #define __UQSUB8 __uqsub8
bogdanm 84:0b3ab51c8877 72 #define __UHSUB8 __uhsub8
bogdanm 84:0b3ab51c8877 73 #define __SADD16 __sadd16
bogdanm 84:0b3ab51c8877 74 #define __QADD16 __qadd16
bogdanm 84:0b3ab51c8877 75 #define __SHADD16 __shadd16
bogdanm 84:0b3ab51c8877 76 #define __UADD16 __uadd16
bogdanm 84:0b3ab51c8877 77 #define __UQADD16 __uqadd16
bogdanm 84:0b3ab51c8877 78 #define __UHADD16 __uhadd16
bogdanm 84:0b3ab51c8877 79 #define __SSUB16 __ssub16
bogdanm 84:0b3ab51c8877 80 #define __QSUB16 __qsub16
bogdanm 84:0b3ab51c8877 81 #define __SHSUB16 __shsub16
bogdanm 84:0b3ab51c8877 82 #define __USUB16 __usub16
bogdanm 84:0b3ab51c8877 83 #define __UQSUB16 __uqsub16
bogdanm 84:0b3ab51c8877 84 #define __UHSUB16 __uhsub16
bogdanm 84:0b3ab51c8877 85 #define __SASX __sasx
bogdanm 84:0b3ab51c8877 86 #define __QASX __qasx
bogdanm 84:0b3ab51c8877 87 #define __SHASX __shasx
bogdanm 84:0b3ab51c8877 88 #define __UASX __uasx
bogdanm 84:0b3ab51c8877 89 #define __UQASX __uqasx
bogdanm 84:0b3ab51c8877 90 #define __UHASX __uhasx
bogdanm 84:0b3ab51c8877 91 #define __SSAX __ssax
bogdanm 84:0b3ab51c8877 92 #define __QSAX __qsax
bogdanm 84:0b3ab51c8877 93 #define __SHSAX __shsax
bogdanm 84:0b3ab51c8877 94 #define __USAX __usax
bogdanm 84:0b3ab51c8877 95 #define __UQSAX __uqsax
bogdanm 84:0b3ab51c8877 96 #define __UHSAX __uhsax
bogdanm 84:0b3ab51c8877 97 #define __USAD8 __usad8
bogdanm 84:0b3ab51c8877 98 #define __USADA8 __usada8
bogdanm 84:0b3ab51c8877 99 #define __SSAT16 __ssat16
bogdanm 84:0b3ab51c8877 100 #define __USAT16 __usat16
bogdanm 84:0b3ab51c8877 101 #define __UXTB16 __uxtb16
bogdanm 84:0b3ab51c8877 102 #define __UXTAB16 __uxtab16
bogdanm 84:0b3ab51c8877 103 #define __SXTB16 __sxtb16
bogdanm 84:0b3ab51c8877 104 #define __SXTAB16 __sxtab16
bogdanm 84:0b3ab51c8877 105 #define __SMUAD __smuad
bogdanm 84:0b3ab51c8877 106 #define __SMUADX __smuadx
bogdanm 84:0b3ab51c8877 107 #define __SMLAD __smlad
bogdanm 84:0b3ab51c8877 108 #define __SMLADX __smladx
bogdanm 84:0b3ab51c8877 109 #define __SMLALD __smlald
bogdanm 84:0b3ab51c8877 110 #define __SMLALDX __smlaldx
bogdanm 84:0b3ab51c8877 111 #define __SMUSD __smusd
bogdanm 84:0b3ab51c8877 112 #define __SMUSDX __smusdx
bogdanm 84:0b3ab51c8877 113 #define __SMLSD __smlsd
bogdanm 84:0b3ab51c8877 114 #define __SMLSDX __smlsdx
bogdanm 84:0b3ab51c8877 115 #define __SMLSLD __smlsld
bogdanm 84:0b3ab51c8877 116 #define __SMLSLDX __smlsldx
bogdanm 84:0b3ab51c8877 117 #define __SEL __sel
bogdanm 84:0b3ab51c8877 118 #define __QADD __qadd
bogdanm 84:0b3ab51c8877 119 #define __QSUB __qsub
bogdanm 84:0b3ab51c8877 120
bogdanm 84:0b3ab51c8877 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
bogdanm 84:0b3ab51c8877 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
bogdanm 84:0b3ab51c8877 123
bogdanm 84:0b3ab51c8877 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
bogdanm 84:0b3ab51c8877 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
bogdanm 84:0b3ab51c8877 126
bogdanm 84:0b3ab51c8877 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
bogdanm 84:0b3ab51c8877 128 ((int64_t)(ARG3) << 32) ) >> 32))
bogdanm 84:0b3ab51c8877 129
bogdanm 84:0b3ab51c8877 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 131
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133
bogdanm 84:0b3ab51c8877 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
bogdanm 84:0b3ab51c8877 135 /* IAR iccarm specific functions */
bogdanm 84:0b3ab51c8877 136
bogdanm 84:0b3ab51c8877 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 138 #include <cmsis_iar.h>
bogdanm 84:0b3ab51c8877 139
bogdanm 84:0b3ab51c8877 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 141
bogdanm 84:0b3ab51c8877 142
bogdanm 84:0b3ab51c8877 143
bogdanm 84:0b3ab51c8877 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
bogdanm 84:0b3ab51c8877 145 /* TI CCS specific functions */
bogdanm 84:0b3ab51c8877 146
bogdanm 84:0b3ab51c8877 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 148 #include <cmsis_ccs.h>
bogdanm 84:0b3ab51c8877 149
bogdanm 84:0b3ab51c8877 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 151
bogdanm 84:0b3ab51c8877 152
bogdanm 84:0b3ab51c8877 153
bogdanm 84:0b3ab51c8877 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
bogdanm 84:0b3ab51c8877 155 /* GNU gcc specific functions */
bogdanm 84:0b3ab51c8877 156
bogdanm 84:0b3ab51c8877 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 159 {
bogdanm 84:0b3ab51c8877 160 uint32_t result;
bogdanm 84:0b3ab51c8877 161
bogdanm 84:0b3ab51c8877 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 163 return(result);
bogdanm 84:0b3ab51c8877 164 }
bogdanm 84:0b3ab51c8877 165
bogdanm 84:0b3ab51c8877 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 167 {
bogdanm 84:0b3ab51c8877 168 uint32_t result;
bogdanm 84:0b3ab51c8877 169
bogdanm 84:0b3ab51c8877 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 171 return(result);
bogdanm 84:0b3ab51c8877 172 }
bogdanm 84:0b3ab51c8877 173
bogdanm 84:0b3ab51c8877 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 175 {
bogdanm 84:0b3ab51c8877 176 uint32_t result;
bogdanm 84:0b3ab51c8877 177
bogdanm 84:0b3ab51c8877 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 179 return(result);
bogdanm 84:0b3ab51c8877 180 }
bogdanm 84:0b3ab51c8877 181
bogdanm 84:0b3ab51c8877 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 183 {
bogdanm 84:0b3ab51c8877 184 uint32_t result;
bogdanm 84:0b3ab51c8877 185
bogdanm 84:0b3ab51c8877 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 187 return(result);
bogdanm 84:0b3ab51c8877 188 }
bogdanm 84:0b3ab51c8877 189
bogdanm 84:0b3ab51c8877 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 191 {
bogdanm 84:0b3ab51c8877 192 uint32_t result;
bogdanm 84:0b3ab51c8877 193
bogdanm 84:0b3ab51c8877 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 195 return(result);
bogdanm 84:0b3ab51c8877 196 }
bogdanm 84:0b3ab51c8877 197
bogdanm 84:0b3ab51c8877 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 199 {
bogdanm 84:0b3ab51c8877 200 uint32_t result;
bogdanm 84:0b3ab51c8877 201
bogdanm 84:0b3ab51c8877 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 203 return(result);
bogdanm 84:0b3ab51c8877 204 }
bogdanm 84:0b3ab51c8877 205
bogdanm 84:0b3ab51c8877 206
bogdanm 84:0b3ab51c8877 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 208 {
bogdanm 84:0b3ab51c8877 209 uint32_t result;
bogdanm 84:0b3ab51c8877 210
bogdanm 84:0b3ab51c8877 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 212 return(result);
bogdanm 84:0b3ab51c8877 213 }
bogdanm 84:0b3ab51c8877 214
bogdanm 84:0b3ab51c8877 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 216 {
bogdanm 84:0b3ab51c8877 217 uint32_t result;
bogdanm 84:0b3ab51c8877 218
bogdanm 84:0b3ab51c8877 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 220 return(result);
bogdanm 84:0b3ab51c8877 221 }
bogdanm 84:0b3ab51c8877 222
bogdanm 84:0b3ab51c8877 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 224 {
bogdanm 84:0b3ab51c8877 225 uint32_t result;
bogdanm 84:0b3ab51c8877 226
bogdanm 84:0b3ab51c8877 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 228 return(result);
bogdanm 84:0b3ab51c8877 229 }
bogdanm 84:0b3ab51c8877 230
bogdanm 84:0b3ab51c8877 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 232 {
bogdanm 84:0b3ab51c8877 233 uint32_t result;
bogdanm 84:0b3ab51c8877 234
bogdanm 84:0b3ab51c8877 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 236 return(result);
bogdanm 84:0b3ab51c8877 237 }
bogdanm 84:0b3ab51c8877 238
bogdanm 84:0b3ab51c8877 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 240 {
bogdanm 84:0b3ab51c8877 241 uint32_t result;
bogdanm 84:0b3ab51c8877 242
bogdanm 84:0b3ab51c8877 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 244 return(result);
bogdanm 84:0b3ab51c8877 245 }
bogdanm 84:0b3ab51c8877 246
bogdanm 84:0b3ab51c8877 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 248 {
bogdanm 84:0b3ab51c8877 249 uint32_t result;
bogdanm 84:0b3ab51c8877 250
bogdanm 84:0b3ab51c8877 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 252 return(result);
bogdanm 84:0b3ab51c8877 253 }
bogdanm 84:0b3ab51c8877 254
bogdanm 84:0b3ab51c8877 255
bogdanm 84:0b3ab51c8877 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 257 {
bogdanm 84:0b3ab51c8877 258 uint32_t result;
bogdanm 84:0b3ab51c8877 259
bogdanm 84:0b3ab51c8877 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 261 return(result);
bogdanm 84:0b3ab51c8877 262 }
bogdanm 84:0b3ab51c8877 263
bogdanm 84:0b3ab51c8877 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 265 {
bogdanm 84:0b3ab51c8877 266 uint32_t result;
bogdanm 84:0b3ab51c8877 267
bogdanm 84:0b3ab51c8877 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 269 return(result);
bogdanm 84:0b3ab51c8877 270 }
bogdanm 84:0b3ab51c8877 271
bogdanm 84:0b3ab51c8877 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 273 {
bogdanm 84:0b3ab51c8877 274 uint32_t result;
bogdanm 84:0b3ab51c8877 275
bogdanm 84:0b3ab51c8877 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 277 return(result);
bogdanm 84:0b3ab51c8877 278 }
bogdanm 84:0b3ab51c8877 279
bogdanm 84:0b3ab51c8877 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 281 {
bogdanm 84:0b3ab51c8877 282 uint32_t result;
bogdanm 84:0b3ab51c8877 283
bogdanm 84:0b3ab51c8877 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 285 return(result);
bogdanm 84:0b3ab51c8877 286 }
bogdanm 84:0b3ab51c8877 287
bogdanm 84:0b3ab51c8877 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 289 {
bogdanm 84:0b3ab51c8877 290 uint32_t result;
bogdanm 84:0b3ab51c8877 291
bogdanm 84:0b3ab51c8877 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 293 return(result);
bogdanm 84:0b3ab51c8877 294 }
bogdanm 84:0b3ab51c8877 295
bogdanm 84:0b3ab51c8877 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 297 {
bogdanm 84:0b3ab51c8877 298 uint32_t result;
bogdanm 84:0b3ab51c8877 299
bogdanm 84:0b3ab51c8877 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 301 return(result);
bogdanm 84:0b3ab51c8877 302 }
bogdanm 84:0b3ab51c8877 303
bogdanm 84:0b3ab51c8877 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 305 {
bogdanm 84:0b3ab51c8877 306 uint32_t result;
bogdanm 84:0b3ab51c8877 307
bogdanm 84:0b3ab51c8877 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 309 return(result);
bogdanm 84:0b3ab51c8877 310 }
bogdanm 84:0b3ab51c8877 311
bogdanm 84:0b3ab51c8877 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 313 {
bogdanm 84:0b3ab51c8877 314 uint32_t result;
bogdanm 84:0b3ab51c8877 315
bogdanm 84:0b3ab51c8877 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 317 return(result);
bogdanm 84:0b3ab51c8877 318 }
bogdanm 84:0b3ab51c8877 319
bogdanm 84:0b3ab51c8877 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 321 {
bogdanm 84:0b3ab51c8877 322 uint32_t result;
bogdanm 84:0b3ab51c8877 323
bogdanm 84:0b3ab51c8877 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 325 return(result);
bogdanm 84:0b3ab51c8877 326 }
bogdanm 84:0b3ab51c8877 327
bogdanm 84:0b3ab51c8877 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 329 {
bogdanm 84:0b3ab51c8877 330 uint32_t result;
bogdanm 84:0b3ab51c8877 331
bogdanm 84:0b3ab51c8877 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 333 return(result);
bogdanm 84:0b3ab51c8877 334 }
bogdanm 84:0b3ab51c8877 335
bogdanm 84:0b3ab51c8877 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 337 {
bogdanm 84:0b3ab51c8877 338 uint32_t result;
bogdanm 84:0b3ab51c8877 339
bogdanm 84:0b3ab51c8877 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 341 return(result);
bogdanm 84:0b3ab51c8877 342 }
bogdanm 84:0b3ab51c8877 343
bogdanm 84:0b3ab51c8877 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 345 {
bogdanm 84:0b3ab51c8877 346 uint32_t result;
bogdanm 84:0b3ab51c8877 347
bogdanm 84:0b3ab51c8877 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 349 return(result);
bogdanm 84:0b3ab51c8877 350 }
bogdanm 84:0b3ab51c8877 351
bogdanm 84:0b3ab51c8877 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 353 {
bogdanm 84:0b3ab51c8877 354 uint32_t result;
bogdanm 84:0b3ab51c8877 355
bogdanm 84:0b3ab51c8877 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 357 return(result);
bogdanm 84:0b3ab51c8877 358 }
bogdanm 84:0b3ab51c8877 359
bogdanm 84:0b3ab51c8877 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 361 {
bogdanm 84:0b3ab51c8877 362 uint32_t result;
bogdanm 84:0b3ab51c8877 363
bogdanm 84:0b3ab51c8877 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 365 return(result);
bogdanm 84:0b3ab51c8877 366 }
bogdanm 84:0b3ab51c8877 367
bogdanm 84:0b3ab51c8877 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 369 {
bogdanm 84:0b3ab51c8877 370 uint32_t result;
bogdanm 84:0b3ab51c8877 371
bogdanm 84:0b3ab51c8877 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 373 return(result);
bogdanm 84:0b3ab51c8877 374 }
bogdanm 84:0b3ab51c8877 375
bogdanm 84:0b3ab51c8877 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 377 {
bogdanm 84:0b3ab51c8877 378 uint32_t result;
bogdanm 84:0b3ab51c8877 379
bogdanm 84:0b3ab51c8877 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 381 return(result);
bogdanm 84:0b3ab51c8877 382 }
bogdanm 84:0b3ab51c8877 383
bogdanm 84:0b3ab51c8877 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 385 {
bogdanm 84:0b3ab51c8877 386 uint32_t result;
bogdanm 84:0b3ab51c8877 387
bogdanm 84:0b3ab51c8877 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 389 return(result);
bogdanm 84:0b3ab51c8877 390 }
bogdanm 84:0b3ab51c8877 391
bogdanm 84:0b3ab51c8877 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 393 {
bogdanm 84:0b3ab51c8877 394 uint32_t result;
bogdanm 84:0b3ab51c8877 395
bogdanm 84:0b3ab51c8877 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 397 return(result);
bogdanm 84:0b3ab51c8877 398 }
bogdanm 84:0b3ab51c8877 399
bogdanm 84:0b3ab51c8877 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 401 {
bogdanm 84:0b3ab51c8877 402 uint32_t result;
bogdanm 84:0b3ab51c8877 403
bogdanm 84:0b3ab51c8877 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 405 return(result);
bogdanm 84:0b3ab51c8877 406 }
bogdanm 84:0b3ab51c8877 407
bogdanm 84:0b3ab51c8877 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 409 {
bogdanm 84:0b3ab51c8877 410 uint32_t result;
bogdanm 84:0b3ab51c8877 411
bogdanm 84:0b3ab51c8877 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 413 return(result);
bogdanm 84:0b3ab51c8877 414 }
bogdanm 84:0b3ab51c8877 415
bogdanm 84:0b3ab51c8877 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 417 {
bogdanm 84:0b3ab51c8877 418 uint32_t result;
bogdanm 84:0b3ab51c8877 419
bogdanm 84:0b3ab51c8877 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 421 return(result);
bogdanm 84:0b3ab51c8877 422 }
bogdanm 84:0b3ab51c8877 423
bogdanm 84:0b3ab51c8877 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 425 {
bogdanm 84:0b3ab51c8877 426 uint32_t result;
bogdanm 84:0b3ab51c8877 427
bogdanm 84:0b3ab51c8877 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 429 return(result);
bogdanm 84:0b3ab51c8877 430 }
bogdanm 84:0b3ab51c8877 431
bogdanm 84:0b3ab51c8877 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 433 {
bogdanm 84:0b3ab51c8877 434 uint32_t result;
bogdanm 84:0b3ab51c8877 435
bogdanm 84:0b3ab51c8877 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 437 return(result);
bogdanm 84:0b3ab51c8877 438 }
bogdanm 84:0b3ab51c8877 439
bogdanm 84:0b3ab51c8877 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 441 {
bogdanm 84:0b3ab51c8877 442 uint32_t result;
bogdanm 84:0b3ab51c8877 443
bogdanm 84:0b3ab51c8877 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 445 return(result);
bogdanm 84:0b3ab51c8877 446 }
bogdanm 84:0b3ab51c8877 447
bogdanm 84:0b3ab51c8877 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 449 {
bogdanm 84:0b3ab51c8877 450 uint32_t result;
bogdanm 84:0b3ab51c8877 451
bogdanm 84:0b3ab51c8877 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 453 return(result);
bogdanm 84:0b3ab51c8877 454 }
bogdanm 84:0b3ab51c8877 455
bogdanm 84:0b3ab51c8877 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 84:0b3ab51c8877 457 {
bogdanm 84:0b3ab51c8877 458 uint32_t result;
bogdanm 84:0b3ab51c8877 459
bogdanm 84:0b3ab51c8877 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 84:0b3ab51c8877 461 return(result);
bogdanm 84:0b3ab51c8877 462 }
bogdanm 84:0b3ab51c8877 463
bogdanm 84:0b3ab51c8877 464 #define __SSAT16(ARG1,ARG2) \
bogdanm 84:0b3ab51c8877 465 ({ \
bogdanm 84:0b3ab51c8877 466 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 84:0b3ab51c8877 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 84:0b3ab51c8877 468 __RES; \
bogdanm 84:0b3ab51c8877 469 })
bogdanm 84:0b3ab51c8877 470
bogdanm 84:0b3ab51c8877 471 #define __USAT16(ARG1,ARG2) \
bogdanm 84:0b3ab51c8877 472 ({ \
bogdanm 84:0b3ab51c8877 473 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 84:0b3ab51c8877 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 84:0b3ab51c8877 475 __RES; \
bogdanm 84:0b3ab51c8877 476 })
bogdanm 84:0b3ab51c8877 477
bogdanm 84:0b3ab51c8877 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
bogdanm 84:0b3ab51c8877 479 {
bogdanm 84:0b3ab51c8877 480 uint32_t result;
bogdanm 84:0b3ab51c8877 481
bogdanm 84:0b3ab51c8877 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
bogdanm 84:0b3ab51c8877 483 return(result);
bogdanm 84:0b3ab51c8877 484 }
bogdanm 84:0b3ab51c8877 485
bogdanm 84:0b3ab51c8877 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 487 {
bogdanm 84:0b3ab51c8877 488 uint32_t result;
bogdanm 84:0b3ab51c8877 489
bogdanm 84:0b3ab51c8877 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 491 return(result);
bogdanm 84:0b3ab51c8877 492 }
bogdanm 84:0b3ab51c8877 493
bogdanm 84:0b3ab51c8877 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
bogdanm 84:0b3ab51c8877 495 {
bogdanm 84:0b3ab51c8877 496 uint32_t result;
bogdanm 84:0b3ab51c8877 497
bogdanm 84:0b3ab51c8877 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
bogdanm 84:0b3ab51c8877 499 return(result);
bogdanm 84:0b3ab51c8877 500 }
bogdanm 84:0b3ab51c8877 501
bogdanm 84:0b3ab51c8877 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 503 {
bogdanm 84:0b3ab51c8877 504 uint32_t result;
bogdanm 84:0b3ab51c8877 505
bogdanm 84:0b3ab51c8877 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 507 return(result);
bogdanm 84:0b3ab51c8877 508 }
bogdanm 84:0b3ab51c8877 509
bogdanm 84:0b3ab51c8877 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 511 {
bogdanm 84:0b3ab51c8877 512 uint32_t result;
bogdanm 84:0b3ab51c8877 513
bogdanm 84:0b3ab51c8877 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 515 return(result);
bogdanm 84:0b3ab51c8877 516 }
bogdanm 84:0b3ab51c8877 517
bogdanm 84:0b3ab51c8877 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 519 {
bogdanm 84:0b3ab51c8877 520 uint32_t result;
bogdanm 84:0b3ab51c8877 521
bogdanm 84:0b3ab51c8877 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 523 return(result);
bogdanm 84:0b3ab51c8877 524 }
bogdanm 84:0b3ab51c8877 525
bogdanm 84:0b3ab51c8877 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 84:0b3ab51c8877 527 {
bogdanm 84:0b3ab51c8877 528 uint32_t result;
bogdanm 84:0b3ab51c8877 529
bogdanm 84:0b3ab51c8877 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 84:0b3ab51c8877 531 return(result);
bogdanm 84:0b3ab51c8877 532 }
bogdanm 84:0b3ab51c8877 533
bogdanm 84:0b3ab51c8877 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 84:0b3ab51c8877 535 {
bogdanm 84:0b3ab51c8877 536 uint32_t result;
bogdanm 84:0b3ab51c8877 537
bogdanm 84:0b3ab51c8877 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 84:0b3ab51c8877 539 return(result);
bogdanm 84:0b3ab51c8877 540 }
bogdanm 84:0b3ab51c8877 541
bogdanm 84:0b3ab51c8877 542 #define __SMLALD(ARG1,ARG2,ARG3) \
bogdanm 84:0b3ab51c8877 543 ({ \
bogdanm 84:0b3ab51c8877 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
bogdanm 84:0b3ab51c8877 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 84:0b3ab51c8877 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 84:0b3ab51c8877 547 })
bogdanm 84:0b3ab51c8877 548
bogdanm 84:0b3ab51c8877 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
bogdanm 84:0b3ab51c8877 550 ({ \
bogdanm 84:0b3ab51c8877 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
bogdanm 84:0b3ab51c8877 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 84:0b3ab51c8877 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 84:0b3ab51c8877 554 })
bogdanm 84:0b3ab51c8877 555
bogdanm 84:0b3ab51c8877 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 557 {
bogdanm 84:0b3ab51c8877 558 uint32_t result;
bogdanm 84:0b3ab51c8877 559
bogdanm 84:0b3ab51c8877 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 561 return(result);
bogdanm 84:0b3ab51c8877 562 }
bogdanm 84:0b3ab51c8877 563
bogdanm 84:0b3ab51c8877 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 565 {
bogdanm 84:0b3ab51c8877 566 uint32_t result;
bogdanm 84:0b3ab51c8877 567
bogdanm 84:0b3ab51c8877 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 569 return(result);
bogdanm 84:0b3ab51c8877 570 }
bogdanm 84:0b3ab51c8877 571
bogdanm 84:0b3ab51c8877 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 84:0b3ab51c8877 573 {
bogdanm 84:0b3ab51c8877 574 uint32_t result;
bogdanm 84:0b3ab51c8877 575
bogdanm 84:0b3ab51c8877 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 84:0b3ab51c8877 577 return(result);
bogdanm 84:0b3ab51c8877 578 }
bogdanm 84:0b3ab51c8877 579
bogdanm 84:0b3ab51c8877 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 84:0b3ab51c8877 581 {
bogdanm 84:0b3ab51c8877 582 uint32_t result;
bogdanm 84:0b3ab51c8877 583
bogdanm 84:0b3ab51c8877 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 84:0b3ab51c8877 585 return(result);
bogdanm 84:0b3ab51c8877 586 }
bogdanm 84:0b3ab51c8877 587
bogdanm 84:0b3ab51c8877 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
bogdanm 84:0b3ab51c8877 589 ({ \
bogdanm 84:0b3ab51c8877 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
bogdanm 84:0b3ab51c8877 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 84:0b3ab51c8877 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 84:0b3ab51c8877 593 })
bogdanm 84:0b3ab51c8877 594
bogdanm 84:0b3ab51c8877 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
bogdanm 84:0b3ab51c8877 596 ({ \
bogdanm 84:0b3ab51c8877 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
bogdanm 84:0b3ab51c8877 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 84:0b3ab51c8877 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 84:0b3ab51c8877 600 })
bogdanm 84:0b3ab51c8877 601
bogdanm 84:0b3ab51c8877 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 603 {
bogdanm 84:0b3ab51c8877 604 uint32_t result;
bogdanm 84:0b3ab51c8877 605
bogdanm 84:0b3ab51c8877 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 607 return(result);
bogdanm 84:0b3ab51c8877 608 }
bogdanm 84:0b3ab51c8877 609
bogdanm 84:0b3ab51c8877 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 611 {
bogdanm 84:0b3ab51c8877 612 uint32_t result;
bogdanm 84:0b3ab51c8877 613
bogdanm 84:0b3ab51c8877 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 615 return(result);
bogdanm 84:0b3ab51c8877 616 }
bogdanm 84:0b3ab51c8877 617
bogdanm 84:0b3ab51c8877 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
bogdanm 84:0b3ab51c8877 619 {
bogdanm 84:0b3ab51c8877 620 uint32_t result;
bogdanm 84:0b3ab51c8877 621
bogdanm 84:0b3ab51c8877 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 84:0b3ab51c8877 623 return(result);
bogdanm 84:0b3ab51c8877 624 }
bogdanm 84:0b3ab51c8877 625
bogdanm 84:0b3ab51c8877 626 #define __PKHBT(ARG1,ARG2,ARG3) \
bogdanm 84:0b3ab51c8877 627 ({ \
bogdanm 84:0b3ab51c8877 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
bogdanm 84:0b3ab51c8877 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
bogdanm 84:0b3ab51c8877 630 __RES; \
bogdanm 84:0b3ab51c8877 631 })
bogdanm 84:0b3ab51c8877 632
bogdanm 84:0b3ab51c8877 633 #define __PKHTB(ARG1,ARG2,ARG3) \
bogdanm 84:0b3ab51c8877 634 ({ \
bogdanm 84:0b3ab51c8877 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
bogdanm 84:0b3ab51c8877 636 if (ARG3 == 0) \
bogdanm 84:0b3ab51c8877 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
bogdanm 84:0b3ab51c8877 638 else \
bogdanm 84:0b3ab51c8877 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
bogdanm 84:0b3ab51c8877 640 __RES; \
bogdanm 84:0b3ab51c8877 641 })
bogdanm 84:0b3ab51c8877 642
bogdanm 84:0b3ab51c8877 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
bogdanm 84:0b3ab51c8877 644 {
bogdanm 84:0b3ab51c8877 645 int32_t result;
bogdanm 84:0b3ab51c8877 646
bogdanm 84:0b3ab51c8877 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
bogdanm 84:0b3ab51c8877 648 return(result);
bogdanm 84:0b3ab51c8877 649 }
bogdanm 84:0b3ab51c8877 650
bogdanm 84:0b3ab51c8877 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 652
bogdanm 84:0b3ab51c8877 653
bogdanm 84:0b3ab51c8877 654
bogdanm 84:0b3ab51c8877 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
bogdanm 84:0b3ab51c8877 656 /* TASKING carm specific functions */
bogdanm 84:0b3ab51c8877 657
bogdanm 84:0b3ab51c8877 658
bogdanm 84:0b3ab51c8877 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 660 /* not yet supported */
bogdanm 84:0b3ab51c8877 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 84:0b3ab51c8877 662
bogdanm 84:0b3ab51c8877 663
bogdanm 84:0b3ab51c8877 664 #endif
bogdanm 84:0b3ab51c8877 665
bogdanm 84:0b3ab51c8877 666 /*@} end of group CMSIS_SIMD_intrinsics */
bogdanm 84:0b3ab51c8877 667
bogdanm 84:0b3ab51c8877 668
bogdanm 84:0b3ab51c8877 669 #endif /* __CORE_CM4_SIMD_H */
bogdanm 84:0b3ab51c8877 670
bogdanm 84:0b3ab51c8877 671 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 672 }
bogdanm 84:0b3ab51c8877 673 #endif