mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L053R8/core_cm0plus.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**************************************************************************//**
bogdanm 84:0b3ab51c8877 2 * @file core_cm0plus.h
bogdanm 84:0b3ab51c8877 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 84:0b3ab51c8877 6 *
bogdanm 84:0b3ab51c8877 7 * @note
bogdanm 84:0b3ab51c8877 8 *
bogdanm 84:0b3ab51c8877 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 84:0b3ab51c8877 11
bogdanm 84:0b3ab51c8877 12 All rights reserved.
bogdanm 84:0b3ab51c8877 13 Redistribution and use in source and binary forms, with or without
bogdanm 84:0b3ab51c8877 14 modification, are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 - Redistributions of source code must retain the above copyright
bogdanm 84:0b3ab51c8877 16 notice, this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 84:0b3ab51c8877 18 notice, this list of conditions and the following disclaimer in the
bogdanm 84:0b3ab51c8877 19 documentation and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 84:0b3ab51c8877 21 to endorse or promote products derived from this software without
bogdanm 84:0b3ab51c8877 22 specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 84:0b3ab51c8877 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 84:0b3ab51c8877 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 84:0b3ab51c8877 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 84:0b3ab51c8877 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 84:0b3ab51c8877 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 84:0b3ab51c8877 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 84:0b3ab51c8877 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 84:0b3ab51c8877 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 35 ---------------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 36
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 #if defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 84:0b3ab51c8877 40 #endif
bogdanm 84:0b3ab51c8877 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 84:0b3ab51c8877 45 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 46 extern "C" {
bogdanm 84:0b3ab51c8877 47 #endif
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 84:0b3ab51c8877 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 84:0b3ab51c8877 51
bogdanm 84:0b3ab51c8877 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 84:0b3ab51c8877 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 84:0b3ab51c8877 54
bogdanm 84:0b3ab51c8877 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 84:0b3ab51c8877 56 Unions are used for effective representation of core registers.
bogdanm 84:0b3ab51c8877 57
bogdanm 84:0b3ab51c8877 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 84:0b3ab51c8877 59 Function-like macros are used to allow more efficient code.
bogdanm 84:0b3ab51c8877 60 */
bogdanm 84:0b3ab51c8877 61
bogdanm 84:0b3ab51c8877 62
bogdanm 84:0b3ab51c8877 63 /*******************************************************************************
bogdanm 84:0b3ab51c8877 64 * CMSIS definitions
bogdanm 84:0b3ab51c8877 65 ******************************************************************************/
bogdanm 84:0b3ab51c8877 66 /** \ingroup Cortex-M0+
bogdanm 84:0b3ab51c8877 67 @{
bogdanm 84:0b3ab51c8877 68 */
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 84:0b3ab51c8877 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 84:0b3ab51c8877 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 84:0b3ab51c8877 75
bogdanm 84:0b3ab51c8877 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 84:0b3ab51c8877 77
bogdanm 84:0b3ab51c8877 78
bogdanm 84:0b3ab51c8877 79 #if defined ( __CC_ARM )
bogdanm 84:0b3ab51c8877 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 84:0b3ab51c8877 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 84:0b3ab51c8877 82 #define __STATIC_INLINE static __inline
bogdanm 84:0b3ab51c8877 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 84:0b3ab51c8877 89 #elif defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 84:0b3ab51c8877 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 84:0b3ab51c8877 92 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 84:0b3ab51c8877 96 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 #elif defined ( __TASKING__ )
bogdanm 84:0b3ab51c8877 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 84:0b3ab51c8877 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 84:0b3ab51c8877 101 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 84:0b3ab51c8877 109 #endif
bogdanm 84:0b3ab51c8877 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 84:0b3ab51c8877 113 */
bogdanm 84:0b3ab51c8877 114 #define __FPU_USED 0
bogdanm 84:0b3ab51c8877 115
bogdanm 84:0b3ab51c8877 116 #if defined ( __CC_ARM )
bogdanm 84:0b3ab51c8877 117 #if defined __TARGET_FPU_VFP
bogdanm 84:0b3ab51c8877 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 119 #endif
bogdanm 84:0b3ab51c8877 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 84:0b3ab51c8877 126 #elif defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 127 #if defined __ARMVFP__
bogdanm 84:0b3ab51c8877 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 129 #endif
bogdanm 84:0b3ab51c8877 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 84:0b3ab51c8877 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 134 #endif
bogdanm 84:0b3ab51c8877 135
bogdanm 84:0b3ab51c8877 136 #elif defined ( __TASKING__ )
bogdanm 84:0b3ab51c8877 137 #if defined __FPU_VFP__
bogdanm 84:0b3ab51c8877 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 84:0b3ab51c8877 145 #endif
bogdanm 84:0b3ab51c8877 146
bogdanm 84:0b3ab51c8877 147 #include <stdint.h> /* standard types definitions */
bogdanm 84:0b3ab51c8877 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 84:0b3ab51c8877 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 84:0b3ab51c8877 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 84:0b3ab51c8877 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 84:0b3ab51c8877 156
bogdanm 84:0b3ab51c8877 157 #ifndef __CMSIS_GENERIC
bogdanm 84:0b3ab51c8877 158
bogdanm 84:0b3ab51c8877 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 84:0b3ab51c8877 160 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 84:0b3ab51c8877 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 84:0b3ab51c8877 166 /* check device defines and use defaults */
bogdanm 84:0b3ab51c8877 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 84:0b3ab51c8877 168 #ifndef __CM0PLUS_REV
bogdanm 84:0b3ab51c8877 169 #define __CM0PLUS_REV 0x0000
bogdanm 84:0b3ab51c8877 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 171 #endif
bogdanm 84:0b3ab51c8877 172
bogdanm 84:0b3ab51c8877 173 #ifndef __MPU_PRESENT
bogdanm 84:0b3ab51c8877 174 #define __MPU_PRESENT 0
bogdanm 84:0b3ab51c8877 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 176 #endif
bogdanm 84:0b3ab51c8877 177
bogdanm 84:0b3ab51c8877 178 #ifndef __VTOR_PRESENT
bogdanm 84:0b3ab51c8877 179 #define __VTOR_PRESENT 0
bogdanm 84:0b3ab51c8877 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 181 #endif
bogdanm 84:0b3ab51c8877 182
bogdanm 84:0b3ab51c8877 183 #ifndef __NVIC_PRIO_BITS
bogdanm 84:0b3ab51c8877 184 #define __NVIC_PRIO_BITS 2
bogdanm 84:0b3ab51c8877 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 186 #endif
bogdanm 84:0b3ab51c8877 187
bogdanm 84:0b3ab51c8877 188 #ifndef __Vendor_SysTickConfig
bogdanm 84:0b3ab51c8877 189 #define __Vendor_SysTickConfig 0
bogdanm 84:0b3ab51c8877 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 191 #endif
bogdanm 84:0b3ab51c8877 192 #endif
bogdanm 84:0b3ab51c8877 193
bogdanm 84:0b3ab51c8877 194 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 84:0b3ab51c8877 195 /**
bogdanm 84:0b3ab51c8877 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 84:0b3ab51c8877 197
bogdanm 84:0b3ab51c8877 198 <strong>IO Type Qualifiers</strong> are used
bogdanm 84:0b3ab51c8877 199 \li to specify the access to peripheral variables.
bogdanm 84:0b3ab51c8877 200 \li for automatic generation of peripheral register debug information.
bogdanm 84:0b3ab51c8877 201 */
bogdanm 84:0b3ab51c8877 202 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 203 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 84:0b3ab51c8877 204 #else
bogdanm 84:0b3ab51c8877 205 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 84:0b3ab51c8877 206 #endif
bogdanm 84:0b3ab51c8877 207 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 84:0b3ab51c8877 208 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 84:0b3ab51c8877 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
bogdanm 84:0b3ab51c8877 218 /*@} end of group Cortex-M0+ */
bogdanm 84:0b3ab51c8877 219
bogdanm 84:0b3ab51c8877 220
bogdanm 84:0b3ab51c8877 221
bogdanm 84:0b3ab51c8877 222 /*******************************************************************************
bogdanm 84:0b3ab51c8877 223 * Register Abstraction
bogdanm 84:0b3ab51c8877 224 Core Register contain:
bogdanm 84:0b3ab51c8877 225 - Core Register
bogdanm 84:0b3ab51c8877 226 - Core NVIC Register
bogdanm 84:0b3ab51c8877 227 - Core SCB Register
bogdanm 84:0b3ab51c8877 228 - Core SysTick Register
bogdanm 84:0b3ab51c8877 229 - Core MPU Register
bogdanm 84:0b3ab51c8877 230 ******************************************************************************/
bogdanm 84:0b3ab51c8877 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 84:0b3ab51c8877 232 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 84:0b3ab51c8877 233 */
bogdanm 84:0b3ab51c8877 234
bogdanm 84:0b3ab51c8877 235 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 236 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 84:0b3ab51c8877 237 \brief Core Register type definitions.
bogdanm 84:0b3ab51c8877 238 @{
bogdanm 84:0b3ab51c8877 239 */
bogdanm 84:0b3ab51c8877 240
bogdanm 84:0b3ab51c8877 241 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 84:0b3ab51c8877 242 */
bogdanm 84:0b3ab51c8877 243 typedef union
bogdanm 84:0b3ab51c8877 244 {
bogdanm 84:0b3ab51c8877 245 struct
bogdanm 84:0b3ab51c8877 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 84:0b3ab51c8877 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 84:0b3ab51c8877 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 84:0b3ab51c8877 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 84:0b3ab51c8877 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 84:0b3ab51c8877 252 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 253 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 254 } APSR_Type;
bogdanm 84:0b3ab51c8877 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
bogdanm 84:0b3ab51c8877 269
bogdanm 84:0b3ab51c8877 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 84:0b3ab51c8877 271 */
bogdanm 84:0b3ab51c8877 272 typedef union
bogdanm 84:0b3ab51c8877 273 {
bogdanm 84:0b3ab51c8877 274 struct
bogdanm 84:0b3ab51c8877 275 {
bogdanm 84:0b3ab51c8877 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 84:0b3ab51c8877 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 84:0b3ab51c8877 278 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 279 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 280 } IPSR_Type;
bogdanm 84:0b3ab51c8877 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
bogdanm 84:0b3ab51c8877 286
bogdanm 84:0b3ab51c8877 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 84:0b3ab51c8877 288 */
bogdanm 84:0b3ab51c8877 289 typedef union
bogdanm 84:0b3ab51c8877 290 {
bogdanm 84:0b3ab51c8877 291 struct
bogdanm 84:0b3ab51c8877 292 {
bogdanm 84:0b3ab51c8877 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 84:0b3ab51c8877 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 84:0b3ab51c8877 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 84:0b3ab51c8877 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 84:0b3ab51c8877 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 84:0b3ab51c8877 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 84:0b3ab51c8877 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 84:0b3ab51c8877 301 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 302 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 303 } xPSR_Type;
bogdanm 84:0b3ab51c8877 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
bogdanm 84:0b3ab51c8877 324
bogdanm 84:0b3ab51c8877 325 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 84:0b3ab51c8877 326 */
bogdanm 84:0b3ab51c8877 327 typedef union
bogdanm 84:0b3ab51c8877 328 {
bogdanm 84:0b3ab51c8877 329 struct
bogdanm 84:0b3ab51c8877 330 {
bogdanm 84:0b3ab51c8877 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 84:0b3ab51c8877 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 84:0b3ab51c8877 334 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 335 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 336 } CONTROL_Type;
bogdanm 84:0b3ab51c8877 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
bogdanm 84:0b3ab51c8877 345 /*@} end of group CMSIS_CORE */
bogdanm 84:0b3ab51c8877 346
bogdanm 84:0b3ab51c8877 347
bogdanm 84:0b3ab51c8877 348 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 84:0b3ab51c8877 350 \brief Type definitions for the NVIC Registers
bogdanm 84:0b3ab51c8877 351 @{
bogdanm 84:0b3ab51c8877 352 */
bogdanm 84:0b3ab51c8877 353
bogdanm 84:0b3ab51c8877 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 84:0b3ab51c8877 355 */
bogdanm 84:0b3ab51c8877 356 typedef struct
bogdanm 84:0b3ab51c8877 357 {
bogdanm 84:0b3ab51c8877 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 84:0b3ab51c8877 359 uint32_t RESERVED0[31];
bogdanm 84:0b3ab51c8877 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 84:0b3ab51c8877 361 uint32_t RSERVED1[31];
bogdanm 84:0b3ab51c8877 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 84:0b3ab51c8877 363 uint32_t RESERVED2[31];
bogdanm 84:0b3ab51c8877 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 84:0b3ab51c8877 365 uint32_t RESERVED3[31];
bogdanm 84:0b3ab51c8877 366 uint32_t RESERVED4[64];
bogdanm 84:0b3ab51c8877 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 84:0b3ab51c8877 368 } NVIC_Type;
bogdanm 84:0b3ab51c8877 369
bogdanm 84:0b3ab51c8877 370 /*@} end of group CMSIS_NVIC */
bogdanm 84:0b3ab51c8877 371
bogdanm 84:0b3ab51c8877 372
bogdanm 84:0b3ab51c8877 373 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 374 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 84:0b3ab51c8877 375 \brief Type definitions for the System Control Block Registers
bogdanm 84:0b3ab51c8877 376 @{
bogdanm 84:0b3ab51c8877 377 */
bogdanm 84:0b3ab51c8877 378
bogdanm 84:0b3ab51c8877 379 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 84:0b3ab51c8877 380 */
bogdanm 84:0b3ab51c8877 381 typedef struct
bogdanm 84:0b3ab51c8877 382 {
bogdanm 84:0b3ab51c8877 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 84:0b3ab51c8877 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 84:0b3ab51c8877 385 #if (__VTOR_PRESENT == 1)
bogdanm 84:0b3ab51c8877 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 84:0b3ab51c8877 387 #else
bogdanm 84:0b3ab51c8877 388 uint32_t RESERVED0;
bogdanm 84:0b3ab51c8877 389 #endif
bogdanm 84:0b3ab51c8877 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 84:0b3ab51c8877 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 84:0b3ab51c8877 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 84:0b3ab51c8877 393 uint32_t RESERVED1;
bogdanm 84:0b3ab51c8877 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 84:0b3ab51c8877 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 84:0b3ab51c8877 396 } SCB_Type;
bogdanm 84:0b3ab51c8877 397
bogdanm 84:0b3ab51c8877 398 /* SCB CPUID Register Definitions */
bogdanm 84:0b3ab51c8877 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 84:0b3ab51c8877 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 84:0b3ab51c8877 401
bogdanm 84:0b3ab51c8877 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 84:0b3ab51c8877 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 84:0b3ab51c8877 404
bogdanm 84:0b3ab51c8877 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 84:0b3ab51c8877 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 84:0b3ab51c8877 407
bogdanm 84:0b3ab51c8877 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 84:0b3ab51c8877 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 84:0b3ab51c8877 410
bogdanm 84:0b3ab51c8877 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 84:0b3ab51c8877 413
bogdanm 84:0b3ab51c8877 414 /* SCB Interrupt Control State Register Definitions */
bogdanm 84:0b3ab51c8877 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 84:0b3ab51c8877 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 84:0b3ab51c8877 417
bogdanm 84:0b3ab51c8877 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 84:0b3ab51c8877 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 84:0b3ab51c8877 420
bogdanm 84:0b3ab51c8877 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 84:0b3ab51c8877 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 84:0b3ab51c8877 423
bogdanm 84:0b3ab51c8877 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 84:0b3ab51c8877 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 84:0b3ab51c8877 426
bogdanm 84:0b3ab51c8877 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 84:0b3ab51c8877 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 84:0b3ab51c8877 429
bogdanm 84:0b3ab51c8877 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 84:0b3ab51c8877 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 84:0b3ab51c8877 432
bogdanm 84:0b3ab51c8877 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 84:0b3ab51c8877 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 84:0b3ab51c8877 435
bogdanm 84:0b3ab51c8877 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 84:0b3ab51c8877 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 84:0b3ab51c8877 438
bogdanm 84:0b3ab51c8877 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 84:0b3ab51c8877 441
bogdanm 84:0b3ab51c8877 442 #if (__VTOR_PRESENT == 1)
bogdanm 84:0b3ab51c8877 443 /* SCB Interrupt Control State Register Definitions */
bogdanm 84:0b3ab51c8877 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 84:0b3ab51c8877 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 84:0b3ab51c8877 446 #endif
bogdanm 84:0b3ab51c8877 447
bogdanm 84:0b3ab51c8877 448 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 84:0b3ab51c8877 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 84:0b3ab51c8877 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 84:0b3ab51c8877 451
bogdanm 84:0b3ab51c8877 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 84:0b3ab51c8877 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 84:0b3ab51c8877 454
bogdanm 84:0b3ab51c8877 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 84:0b3ab51c8877 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 84:0b3ab51c8877 457
bogdanm 84:0b3ab51c8877 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 84:0b3ab51c8877 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 84:0b3ab51c8877 460
bogdanm 84:0b3ab51c8877 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 84:0b3ab51c8877 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 84:0b3ab51c8877 463
bogdanm 84:0b3ab51c8877 464 /* SCB System Control Register Definitions */
bogdanm 84:0b3ab51c8877 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 84:0b3ab51c8877 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 84:0b3ab51c8877 467
bogdanm 84:0b3ab51c8877 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 84:0b3ab51c8877 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 84:0b3ab51c8877 470
bogdanm 84:0b3ab51c8877 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 84:0b3ab51c8877 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 84:0b3ab51c8877 473
bogdanm 84:0b3ab51c8877 474 /* SCB Configuration Control Register Definitions */
bogdanm 84:0b3ab51c8877 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 84:0b3ab51c8877 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 84:0b3ab51c8877 477
bogdanm 84:0b3ab51c8877 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 84:0b3ab51c8877 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 84:0b3ab51c8877 480
bogdanm 84:0b3ab51c8877 481 /* SCB System Handler Control and State Register Definitions */
bogdanm 84:0b3ab51c8877 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 84:0b3ab51c8877 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 84:0b3ab51c8877 484
bogdanm 84:0b3ab51c8877 485 /*@} end of group CMSIS_SCB */
bogdanm 84:0b3ab51c8877 486
bogdanm 84:0b3ab51c8877 487
bogdanm 84:0b3ab51c8877 488 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 84:0b3ab51c8877 490 \brief Type definitions for the System Timer Registers.
bogdanm 84:0b3ab51c8877 491 @{
bogdanm 84:0b3ab51c8877 492 */
bogdanm 84:0b3ab51c8877 493
bogdanm 84:0b3ab51c8877 494 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 84:0b3ab51c8877 495 */
bogdanm 84:0b3ab51c8877 496 typedef struct
bogdanm 84:0b3ab51c8877 497 {
bogdanm 84:0b3ab51c8877 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 84:0b3ab51c8877 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 84:0b3ab51c8877 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 84:0b3ab51c8877 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 84:0b3ab51c8877 502 } SysTick_Type;
bogdanm 84:0b3ab51c8877 503
bogdanm 84:0b3ab51c8877 504 /* SysTick Control / Status Register Definitions */
bogdanm 84:0b3ab51c8877 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 84:0b3ab51c8877 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 84:0b3ab51c8877 507
bogdanm 84:0b3ab51c8877 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 84:0b3ab51c8877 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 84:0b3ab51c8877 510
bogdanm 84:0b3ab51c8877 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 84:0b3ab51c8877 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 84:0b3ab51c8877 513
bogdanm 84:0b3ab51c8877 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 84:0b3ab51c8877 516
bogdanm 84:0b3ab51c8877 517 /* SysTick Reload Register Definitions */
bogdanm 84:0b3ab51c8877 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 84:0b3ab51c8877 520
bogdanm 84:0b3ab51c8877 521 /* SysTick Current Register Definitions */
bogdanm 84:0b3ab51c8877 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 84:0b3ab51c8877 524
bogdanm 84:0b3ab51c8877 525 /* SysTick Calibration Register Definitions */
bogdanm 84:0b3ab51c8877 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 84:0b3ab51c8877 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 84:0b3ab51c8877 528
bogdanm 84:0b3ab51c8877 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 84:0b3ab51c8877 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 84:0b3ab51c8877 531
bogdanm 84:0b3ab51c8877 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 84:0b3ab51c8877 534
bogdanm 84:0b3ab51c8877 535 /*@} end of group CMSIS_SysTick */
bogdanm 84:0b3ab51c8877 536
bogdanm 84:0b3ab51c8877 537 #if (__MPU_PRESENT == 1)
bogdanm 84:0b3ab51c8877 538 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 84:0b3ab51c8877 540 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 84:0b3ab51c8877 541 @{
bogdanm 84:0b3ab51c8877 542 */
bogdanm 84:0b3ab51c8877 543
bogdanm 84:0b3ab51c8877 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 84:0b3ab51c8877 545 */
bogdanm 84:0b3ab51c8877 546 typedef struct
bogdanm 84:0b3ab51c8877 547 {
bogdanm 84:0b3ab51c8877 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 84:0b3ab51c8877 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 84:0b3ab51c8877 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 84:0b3ab51c8877 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 84:0b3ab51c8877 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 84:0b3ab51c8877 553 } MPU_Type;
bogdanm 84:0b3ab51c8877 554
bogdanm 84:0b3ab51c8877 555 /* MPU Type Register */
bogdanm 84:0b3ab51c8877 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 84:0b3ab51c8877 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 84:0b3ab51c8877 558
bogdanm 84:0b3ab51c8877 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 84:0b3ab51c8877 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 84:0b3ab51c8877 561
bogdanm 84:0b3ab51c8877 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 84:0b3ab51c8877 564
bogdanm 84:0b3ab51c8877 565 /* MPU Control Register */
bogdanm 84:0b3ab51c8877 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 84:0b3ab51c8877 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 84:0b3ab51c8877 568
bogdanm 84:0b3ab51c8877 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 84:0b3ab51c8877 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 84:0b3ab51c8877 571
bogdanm 84:0b3ab51c8877 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
bogdanm 84:0b3ab51c8877 574
bogdanm 84:0b3ab51c8877 575 /* MPU Region Number Register */
bogdanm 84:0b3ab51c8877 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
bogdanm 84:0b3ab51c8877 578
bogdanm 84:0b3ab51c8877 579 /* MPU Region Base Address Register */
bogdanm 84:0b3ab51c8877 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 84:0b3ab51c8877 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 84:0b3ab51c8877 582
bogdanm 84:0b3ab51c8877 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 84:0b3ab51c8877 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 84:0b3ab51c8877 585
bogdanm 84:0b3ab51c8877 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
bogdanm 84:0b3ab51c8877 588
bogdanm 84:0b3ab51c8877 589 /* MPU Region Attribute and Size Register */
bogdanm 84:0b3ab51c8877 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 84:0b3ab51c8877 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 84:0b3ab51c8877 592
bogdanm 84:0b3ab51c8877 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 84:0b3ab51c8877 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 84:0b3ab51c8877 595
bogdanm 84:0b3ab51c8877 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 84:0b3ab51c8877 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 84:0b3ab51c8877 598
bogdanm 84:0b3ab51c8877 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 84:0b3ab51c8877 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 84:0b3ab51c8877 601
bogdanm 84:0b3ab51c8877 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 84:0b3ab51c8877 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 84:0b3ab51c8877 604
bogdanm 84:0b3ab51c8877 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 84:0b3ab51c8877 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 84:0b3ab51c8877 607
bogdanm 84:0b3ab51c8877 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 84:0b3ab51c8877 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 84:0b3ab51c8877 610
bogdanm 84:0b3ab51c8877 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 84:0b3ab51c8877 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 84:0b3ab51c8877 613
bogdanm 84:0b3ab51c8877 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 84:0b3ab51c8877 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 84:0b3ab51c8877 616
bogdanm 84:0b3ab51c8877 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 84:0b3ab51c8877 619
bogdanm 84:0b3ab51c8877 620 /*@} end of group CMSIS_MPU */
bogdanm 84:0b3ab51c8877 621 #endif
bogdanm 84:0b3ab51c8877 622
bogdanm 84:0b3ab51c8877 623
bogdanm 84:0b3ab51c8877 624 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 84:0b3ab51c8877 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 84:0b3ab51c8877 627 are only accessible over DAP and not via processor. Therefore
bogdanm 84:0b3ab51c8877 628 they are not covered by the Cortex-M0 header file.
bogdanm 84:0b3ab51c8877 629 @{
bogdanm 84:0b3ab51c8877 630 */
bogdanm 84:0b3ab51c8877 631 /*@} end of group CMSIS_CoreDebug */
bogdanm 84:0b3ab51c8877 632
bogdanm 84:0b3ab51c8877 633
bogdanm 84:0b3ab51c8877 634 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 635 \defgroup CMSIS_core_base Core Definitions
bogdanm 84:0b3ab51c8877 636 \brief Definitions for base addresses, unions, and structures.
bogdanm 84:0b3ab51c8877 637 @{
bogdanm 84:0b3ab51c8877 638 */
bogdanm 84:0b3ab51c8877 639
bogdanm 84:0b3ab51c8877 640 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 84:0b3ab51c8877 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 84:0b3ab51c8877 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 84:0b3ab51c8877 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 84:0b3ab51c8877 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 84:0b3ab51c8877 645
bogdanm 84:0b3ab51c8877 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 84:0b3ab51c8877 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 84:0b3ab51c8877 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 84:0b3ab51c8877 649
bogdanm 84:0b3ab51c8877 650 #if (__MPU_PRESENT == 1)
bogdanm 84:0b3ab51c8877 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 84:0b3ab51c8877 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 84:0b3ab51c8877 653 #endif
bogdanm 84:0b3ab51c8877 654
bogdanm 84:0b3ab51c8877 655 /*@} */
bogdanm 84:0b3ab51c8877 656
bogdanm 84:0b3ab51c8877 657
bogdanm 84:0b3ab51c8877 658
bogdanm 84:0b3ab51c8877 659 /*******************************************************************************
bogdanm 84:0b3ab51c8877 660 * Hardware Abstraction Layer
bogdanm 84:0b3ab51c8877 661 Core Function Interface contains:
bogdanm 84:0b3ab51c8877 662 - Core NVIC Functions
bogdanm 84:0b3ab51c8877 663 - Core SysTick Functions
bogdanm 84:0b3ab51c8877 664 - Core Register Access Functions
bogdanm 84:0b3ab51c8877 665 ******************************************************************************/
bogdanm 84:0b3ab51c8877 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 84:0b3ab51c8877 667 */
bogdanm 84:0b3ab51c8877 668
bogdanm 84:0b3ab51c8877 669
bogdanm 84:0b3ab51c8877 670
bogdanm 84:0b3ab51c8877 671 /* ########################## NVIC functions #################################### */
bogdanm 84:0b3ab51c8877 672 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 84:0b3ab51c8877 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 84:0b3ab51c8877 674 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 84:0b3ab51c8877 675 @{
bogdanm 84:0b3ab51c8877 676 */
bogdanm 84:0b3ab51c8877 677
bogdanm 84:0b3ab51c8877 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 84:0b3ab51c8877 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 84:0b3ab51c8877 683
bogdanm 84:0b3ab51c8877 684
bogdanm 84:0b3ab51c8877 685 /** \brief Enable External Interrupt
bogdanm 84:0b3ab51c8877 686
bogdanm 84:0b3ab51c8877 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 84:0b3ab51c8877 688
bogdanm 84:0b3ab51c8877 689 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 690 */
bogdanm 84:0b3ab51c8877 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 84:0b3ab51c8877 694 }
bogdanm 84:0b3ab51c8877 695
bogdanm 84:0b3ab51c8877 696
bogdanm 84:0b3ab51c8877 697 /** \brief Disable External Interrupt
bogdanm 84:0b3ab51c8877 698
bogdanm 84:0b3ab51c8877 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 84:0b3ab51c8877 700
bogdanm 84:0b3ab51c8877 701 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 702 */
bogdanm 84:0b3ab51c8877 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
bogdanm 84:0b3ab51c8877 708 }
bogdanm 84:0b3ab51c8877 709
bogdanm 84:0b3ab51c8877 710
bogdanm 84:0b3ab51c8877 711 /** \brief Get Pending Interrupt
bogdanm 84:0b3ab51c8877 712
bogdanm 84:0b3ab51c8877 713 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 84:0b3ab51c8877 714 for the specified interrupt.
bogdanm 84:0b3ab51c8877 715
bogdanm 84:0b3ab51c8877 716 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 717
bogdanm 84:0b3ab51c8877 718 \return 0 Interrupt status is not pending.
bogdanm 84:0b3ab51c8877 719 \return 1 Interrupt status is pending.
bogdanm 84:0b3ab51c8877 720 */
bogdanm 84:0b3ab51c8877 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 84:0b3ab51c8877 724 }
bogdanm 84:0b3ab51c8877 725
bogdanm 84:0b3ab51c8877 726
bogdanm 84:0b3ab51c8877 727 /** \brief Set Pending Interrupt
bogdanm 84:0b3ab51c8877 728
bogdanm 84:0b3ab51c8877 729 The function sets the pending bit of an external interrupt.
bogdanm 84:0b3ab51c8877 730
bogdanm 84:0b3ab51c8877 731 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 732 */
bogdanm 84:0b3ab51c8877 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 84:0b3ab51c8877 736 }
bogdanm 84:0b3ab51c8877 737
bogdanm 84:0b3ab51c8877 738
bogdanm 84:0b3ab51c8877 739 /** \brief Clear Pending Interrupt
bogdanm 84:0b3ab51c8877 740
bogdanm 84:0b3ab51c8877 741 The function clears the pending bit of an external interrupt.
bogdanm 84:0b3ab51c8877 742
bogdanm 84:0b3ab51c8877 743 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 744 */
bogdanm 84:0b3ab51c8877 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 84:0b3ab51c8877 748 }
bogdanm 84:0b3ab51c8877 749
bogdanm 84:0b3ab51c8877 750
bogdanm 84:0b3ab51c8877 751 /** \brief Set Interrupt Priority
bogdanm 84:0b3ab51c8877 752
bogdanm 84:0b3ab51c8877 753 The function sets the priority of an interrupt.
bogdanm 84:0b3ab51c8877 754
bogdanm 84:0b3ab51c8877 755 \note The priority cannot be set for every core interrupt.
bogdanm 84:0b3ab51c8877 756
bogdanm 84:0b3ab51c8877 757 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 758 \param [in] priority Priority to set.
bogdanm 84:0b3ab51c8877 759 */
bogdanm 84:0b3ab51c8877 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 84:0b3ab51c8877 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
bogdanm 84:0b3ab51c8877 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
bogdanm 84:0b3ab51c8877 770 }
bogdanm 84:0b3ab51c8877 771
bogdanm 84:0b3ab51c8877 772
bogdanm 84:0b3ab51c8877 773 /** \brief Get Interrupt Priority
bogdanm 84:0b3ab51c8877 774
bogdanm 84:0b3ab51c8877 775 The function reads the priority of an interrupt. The interrupt
bogdanm 84:0b3ab51c8877 776 number can be positive to specify an external (device specific)
bogdanm 84:0b3ab51c8877 777 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 84:0b3ab51c8877 778
bogdanm 84:0b3ab51c8877 779
bogdanm 84:0b3ab51c8877 780 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 781 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 84:0b3ab51c8877 782 priority bits of the microcontroller.
bogdanm 84:0b3ab51c8877 783 */
bogdanm 84:0b3ab51c8877 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 785 {
bogdanm 84:0b3ab51c8877 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
bogdanm 84:0b3ab51c8877 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
bogdanm 84:0b3ab51c8877 793 }
bogdanm 84:0b3ab51c8877 794
bogdanm 84:0b3ab51c8877 795
bogdanm 84:0b3ab51c8877 796 /** \brief System Reset
bogdanm 84:0b3ab51c8877 797
bogdanm 84:0b3ab51c8877 798 The function initiates a system reset request to reset the MCU.
bogdanm 84:0b3ab51c8877 799 */
bogdanm 84:0b3ab51c8877 800 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 84:0b3ab51c8877 801 {
bogdanm 84:0b3ab51c8877 802 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 84:0b3ab51c8877 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 84:0b3ab51c8877 805 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 84:0b3ab51c8877 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
bogdanm 84:0b3ab51c8877 808 }
bogdanm 84:0b3ab51c8877 809
bogdanm 84:0b3ab51c8877 810 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 84:0b3ab51c8877 811
bogdanm 84:0b3ab51c8877 812
bogdanm 84:0b3ab51c8877 813
bogdanm 84:0b3ab51c8877 814 /* ################################## SysTick function ############################################ */
bogdanm 84:0b3ab51c8877 815 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 84:0b3ab51c8877 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 84:0b3ab51c8877 817 \brief Functions that configure the System.
bogdanm 84:0b3ab51c8877 818 @{
bogdanm 84:0b3ab51c8877 819 */
bogdanm 84:0b3ab51c8877 820
bogdanm 84:0b3ab51c8877 821 #if (__Vendor_SysTickConfig == 0)
bogdanm 84:0b3ab51c8877 822
bogdanm 84:0b3ab51c8877 823 /** \brief System Tick Configuration
bogdanm 84:0b3ab51c8877 824
bogdanm 84:0b3ab51c8877 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 84:0b3ab51c8877 826 Counter is in free running mode to generate periodic interrupts.
bogdanm 84:0b3ab51c8877 827
bogdanm 84:0b3ab51c8877 828 \param [in] ticks Number of ticks between two interrupts.
bogdanm 84:0b3ab51c8877 829
bogdanm 84:0b3ab51c8877 830 \return 0 Function succeeded.
bogdanm 84:0b3ab51c8877 831 \return 1 Function failed.
bogdanm 84:0b3ab51c8877 832
bogdanm 84:0b3ab51c8877 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 84:0b3ab51c8877 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 84:0b3ab51c8877 835 must contain a vendor-specific implementation of this function.
bogdanm 84:0b3ab51c8877 836
bogdanm 84:0b3ab51c8877 837 */
bogdanm 84:0b3ab51c8877 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 84:0b3ab51c8877 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
bogdanm 84:0b3ab51c8877 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 84:0b3ab51c8877 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 84:0b3ab51c8877 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
bogdanm 84:0b3ab51c8877 849 }
bogdanm 84:0b3ab51c8877 850
bogdanm 84:0b3ab51c8877 851 #endif
bogdanm 84:0b3ab51c8877 852
bogdanm 84:0b3ab51c8877 853 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 84:0b3ab51c8877 854
bogdanm 84:0b3ab51c8877 855
bogdanm 84:0b3ab51c8877 856
bogdanm 84:0b3ab51c8877 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
bogdanm 84:0b3ab51c8877 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 84:0b3ab51c8877 863
bogdanm 84:0b3ab51c8877 864 #endif /* __CMSIS_GENERIC */