mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F756ZG/core_cm0plus.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file core_cm0plus.h
<> 128:9bcdf88f62b0 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
<> 128:9bcdf88f62b0 4 * @version V4.10
<> 128:9bcdf88f62b0 5 * @date 18. March 2015
<> 128:9bcdf88f62b0 6 *
<> 128:9bcdf88f62b0 7 * @note
<> 128:9bcdf88f62b0 8 *
<> 128:9bcdf88f62b0 9 ******************************************************************************/
<> 128:9bcdf88f62b0 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 128:9bcdf88f62b0 11
<> 128:9bcdf88f62b0 12 All rights reserved.
<> 128:9bcdf88f62b0 13 Redistribution and use in source and binary forms, with or without
<> 128:9bcdf88f62b0 14 modification, are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 - Redistributions of source code must retain the above copyright
<> 128:9bcdf88f62b0 16 notice, this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 - Redistributions in binary form must reproduce the above copyright
<> 128:9bcdf88f62b0 18 notice, this list of conditions and the following disclaimer in the
<> 128:9bcdf88f62b0 19 documentation and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 - Neither the name of ARM nor the names of its contributors may be used
<> 128:9bcdf88f62b0 21 to endorse or promote products derived from this software without
<> 128:9bcdf88f62b0 22 specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 128:9bcdf88f62b0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 128:9bcdf88f62b0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 128:9bcdf88f62b0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 128:9bcdf88f62b0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 128:9bcdf88f62b0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 128:9bcdf88f62b0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 128:9bcdf88f62b0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 128:9bcdf88f62b0 34 POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 35 ---------------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 #if defined ( __ICCARM__ )
<> 128:9bcdf88f62b0 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 128:9bcdf88f62b0 40 #endif
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifndef __CORE_CM0PLUS_H_GENERIC
<> 128:9bcdf88f62b0 43 #define __CORE_CM0PLUS_H_GENERIC
<> 128:9bcdf88f62b0 44
<> 128:9bcdf88f62b0 45 #ifdef __cplusplus
<> 128:9bcdf88f62b0 46 extern "C" {
<> 128:9bcdf88f62b0 47 #endif
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 128:9bcdf88f62b0 50 CMSIS violates the following MISRA-C:2004 rules:
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 128:9bcdf88f62b0 53 Function definitions in header files are used to allow 'inlining'.
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 128:9bcdf88f62b0 56 Unions are used for effective representation of core registers.
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 128:9bcdf88f62b0 59 Function-like macros are used to allow more efficient code.
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /*******************************************************************************
<> 128:9bcdf88f62b0 64 * CMSIS definitions
<> 128:9bcdf88f62b0 65 ******************************************************************************/
<> 128:9bcdf88f62b0 66 /** \ingroup Cortex-M0+
<> 128:9bcdf88f62b0 67 @{
<> 128:9bcdf88f62b0 68 */
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 /* CMSIS CM0P definitions */
<> 128:9bcdf88f62b0 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 128:9bcdf88f62b0 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 128:9bcdf88f62b0 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
<> 128:9bcdf88f62b0 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
<> 128:9bcdf88f62b0 77
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 #if defined ( __CC_ARM )
<> 128:9bcdf88f62b0 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 128:9bcdf88f62b0 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 128:9bcdf88f62b0 82 #define __STATIC_INLINE static __inline
<> 128:9bcdf88f62b0 83
<> 128:9bcdf88f62b0 84 #elif defined ( __GNUC__ )
<> 128:9bcdf88f62b0 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 128:9bcdf88f62b0 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 128:9bcdf88f62b0 87 #define __STATIC_INLINE static inline
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 #elif defined ( __ICCARM__ )
<> 128:9bcdf88f62b0 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 128:9bcdf88f62b0 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 128:9bcdf88f62b0 92 #define __STATIC_INLINE static inline
<> 128:9bcdf88f62b0 93
<> 128:9bcdf88f62b0 94 #elif defined ( __TMS470__ )
<> 128:9bcdf88f62b0 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 128:9bcdf88f62b0 96 #define __STATIC_INLINE static inline
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 #elif defined ( __TASKING__ )
<> 128:9bcdf88f62b0 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 128:9bcdf88f62b0 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 128:9bcdf88f62b0 101 #define __STATIC_INLINE static inline
<> 128:9bcdf88f62b0 102
<> 128:9bcdf88f62b0 103 #elif defined ( __CSMC__ )
<> 128:9bcdf88f62b0 104 #define __packed
<> 128:9bcdf88f62b0 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 128:9bcdf88f62b0 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 128:9bcdf88f62b0 107 #define __STATIC_INLINE static inline
<> 128:9bcdf88f62b0 108
<> 128:9bcdf88f62b0 109 #endif
<> 128:9bcdf88f62b0 110
<> 128:9bcdf88f62b0 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 128:9bcdf88f62b0 112 This core does not support an FPU at all
<> 128:9bcdf88f62b0 113 */
<> 128:9bcdf88f62b0 114 #define __FPU_USED 0
<> 128:9bcdf88f62b0 115
<> 128:9bcdf88f62b0 116 #if defined ( __CC_ARM )
<> 128:9bcdf88f62b0 117 #if defined __TARGET_FPU_VFP
<> 128:9bcdf88f62b0 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 128:9bcdf88f62b0 119 #endif
<> 128:9bcdf88f62b0 120
<> 128:9bcdf88f62b0 121 #elif defined ( __GNUC__ )
<> 128:9bcdf88f62b0 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 128:9bcdf88f62b0 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 128:9bcdf88f62b0 124 #endif
<> 128:9bcdf88f62b0 125
<> 128:9bcdf88f62b0 126 #elif defined ( __ICCARM__ )
<> 128:9bcdf88f62b0 127 #if defined __ARMVFP__
<> 128:9bcdf88f62b0 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 128:9bcdf88f62b0 129 #endif
<> 128:9bcdf88f62b0 130
<> 128:9bcdf88f62b0 131 #elif defined ( __TMS470__ )
<> 128:9bcdf88f62b0 132 #if defined __TI__VFP_SUPPORT____
<> 128:9bcdf88f62b0 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 128:9bcdf88f62b0 134 #endif
<> 128:9bcdf88f62b0 135
<> 128:9bcdf88f62b0 136 #elif defined ( __TASKING__ )
<> 128:9bcdf88f62b0 137 #if defined __FPU_VFP__
<> 128:9bcdf88f62b0 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 128:9bcdf88f62b0 139 #endif
<> 128:9bcdf88f62b0 140
<> 128:9bcdf88f62b0 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 128:9bcdf88f62b0 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 128:9bcdf88f62b0 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 128:9bcdf88f62b0 144 #endif
<> 128:9bcdf88f62b0 145 #endif
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 #include <stdint.h> /* standard types definitions */
<> 128:9bcdf88f62b0 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 128:9bcdf88f62b0 149 #include <core_cmFunc.h> /* Core Function Access */
<> 128:9bcdf88f62b0 150
<> 128:9bcdf88f62b0 151 #ifdef __cplusplus
<> 128:9bcdf88f62b0 152 }
<> 128:9bcdf88f62b0 153 #endif
<> 128:9bcdf88f62b0 154
<> 128:9bcdf88f62b0 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
<> 128:9bcdf88f62b0 156
<> 128:9bcdf88f62b0 157 #ifndef __CMSIS_GENERIC
<> 128:9bcdf88f62b0 158
<> 128:9bcdf88f62b0 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
<> 128:9bcdf88f62b0 160 #define __CORE_CM0PLUS_H_DEPENDANT
<> 128:9bcdf88f62b0 161
<> 128:9bcdf88f62b0 162 #ifdef __cplusplus
<> 128:9bcdf88f62b0 163 extern "C" {
<> 128:9bcdf88f62b0 164 #endif
<> 128:9bcdf88f62b0 165
<> 128:9bcdf88f62b0 166 /* check device defines and use defaults */
<> 128:9bcdf88f62b0 167 #if defined __CHECK_DEVICE_DEFINES
<> 128:9bcdf88f62b0 168 #ifndef __CM0PLUS_REV
<> 128:9bcdf88f62b0 169 #define __CM0PLUS_REV 0x0000
<> 128:9bcdf88f62b0 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
<> 128:9bcdf88f62b0 171 #endif
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 #ifndef __MPU_PRESENT
<> 128:9bcdf88f62b0 174 #define __MPU_PRESENT 0
<> 128:9bcdf88f62b0 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 128:9bcdf88f62b0 176 #endif
<> 128:9bcdf88f62b0 177
<> 128:9bcdf88f62b0 178 #ifndef __VTOR_PRESENT
<> 128:9bcdf88f62b0 179 #define __VTOR_PRESENT 0
<> 128:9bcdf88f62b0 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
<> 128:9bcdf88f62b0 181 #endif
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 #ifndef __NVIC_PRIO_BITS
<> 128:9bcdf88f62b0 184 #define __NVIC_PRIO_BITS 2
<> 128:9bcdf88f62b0 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 128:9bcdf88f62b0 186 #endif
<> 128:9bcdf88f62b0 187
<> 128:9bcdf88f62b0 188 #ifndef __Vendor_SysTickConfig
<> 128:9bcdf88f62b0 189 #define __Vendor_SysTickConfig 0
<> 128:9bcdf88f62b0 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 128:9bcdf88f62b0 191 #endif
<> 128:9bcdf88f62b0 192 #endif
<> 128:9bcdf88f62b0 193
<> 128:9bcdf88f62b0 194 /* IO definitions (access restrictions to peripheral registers) */
<> 128:9bcdf88f62b0 195 /**
<> 128:9bcdf88f62b0 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 128:9bcdf88f62b0 197
<> 128:9bcdf88f62b0 198 <strong>IO Type Qualifiers</strong> are used
<> 128:9bcdf88f62b0 199 \li to specify the access to peripheral variables.
<> 128:9bcdf88f62b0 200 \li for automatic generation of peripheral register debug information.
<> 128:9bcdf88f62b0 201 */
<> 128:9bcdf88f62b0 202 #ifdef __cplusplus
<> 128:9bcdf88f62b0 203 #define __I volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #else
<> 128:9bcdf88f62b0 205 #define __I volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 206 #endif
<> 128:9bcdf88f62b0 207 #define __O volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 208 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
<> 128:9bcdf88f62b0 218 /*@} end of group Cortex-M0+ */
<> 128:9bcdf88f62b0 219
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221
<> 128:9bcdf88f62b0 222 /*******************************************************************************
<> 128:9bcdf88f62b0 223 * Register Abstraction
<> 128:9bcdf88f62b0 224 Core Register contain:
<> 128:9bcdf88f62b0 225 - Core Register
<> 128:9bcdf88f62b0 226 - Core NVIC Register
<> 128:9bcdf88f62b0 227 - Core SCB Register
<> 128:9bcdf88f62b0 228 - Core SysTick Register
<> 128:9bcdf88f62b0 229 - Core MPU Register
<> 128:9bcdf88f62b0 230 ******************************************************************************/
<> 128:9bcdf88f62b0 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 128:9bcdf88f62b0 232 \brief Type definitions and defines for Cortex-M processor based devices.
<> 128:9bcdf88f62b0 233 */
<> 128:9bcdf88f62b0 234
<> 128:9bcdf88f62b0 235 /** \ingroup CMSIS_core_register
<> 128:9bcdf88f62b0 236 \defgroup CMSIS_CORE Status and Control Registers
<> 128:9bcdf88f62b0 237 \brief Core Register type definitions.
<> 128:9bcdf88f62b0 238 @{
<> 128:9bcdf88f62b0 239 */
<> 128:9bcdf88f62b0 240
<> 128:9bcdf88f62b0 241 /** \brief Union type to access the Application Program Status Register (APSR).
<> 128:9bcdf88f62b0 242 */
<> 128:9bcdf88f62b0 243 typedef union
<> 128:9bcdf88f62b0 244 {
<> 128:9bcdf88f62b0 245 struct
<> 128:9bcdf88f62b0 246 {
<> 128:9bcdf88f62b0 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 128:9bcdf88f62b0 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 128:9bcdf88f62b0 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 128:9bcdf88f62b0 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 128:9bcdf88f62b0 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 128:9bcdf88f62b0 252 } b; /*!< Structure used for bit access */
<> 128:9bcdf88f62b0 253 uint32_t w; /*!< Type used for word access */
<> 128:9bcdf88f62b0 254 } APSR_Type;
<> 128:9bcdf88f62b0 255
<> 128:9bcdf88f62b0 256 /* APSR Register Definitions */
<> 128:9bcdf88f62b0 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 128:9bcdf88f62b0 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 128:9bcdf88f62b0 259
<> 128:9bcdf88f62b0 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 128:9bcdf88f62b0 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 128:9bcdf88f62b0 262
<> 128:9bcdf88f62b0 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 128:9bcdf88f62b0 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 128:9bcdf88f62b0 265
<> 128:9bcdf88f62b0 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 128:9bcdf88f62b0 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 128:9bcdf88f62b0 268
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 128:9bcdf88f62b0 271 */
<> 128:9bcdf88f62b0 272 typedef union
<> 128:9bcdf88f62b0 273 {
<> 128:9bcdf88f62b0 274 struct
<> 128:9bcdf88f62b0 275 {
<> 128:9bcdf88f62b0 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 128:9bcdf88f62b0 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 128:9bcdf88f62b0 278 } b; /*!< Structure used for bit access */
<> 128:9bcdf88f62b0 279 uint32_t w; /*!< Type used for word access */
<> 128:9bcdf88f62b0 280 } IPSR_Type;
<> 128:9bcdf88f62b0 281
<> 128:9bcdf88f62b0 282 /* IPSR Register Definitions */
<> 128:9bcdf88f62b0 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 128:9bcdf88f62b0 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 128:9bcdf88f62b0 285
<> 128:9bcdf88f62b0 286
<> 128:9bcdf88f62b0 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 128:9bcdf88f62b0 288 */
<> 128:9bcdf88f62b0 289 typedef union
<> 128:9bcdf88f62b0 290 {
<> 128:9bcdf88f62b0 291 struct
<> 128:9bcdf88f62b0 292 {
<> 128:9bcdf88f62b0 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 128:9bcdf88f62b0 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 128:9bcdf88f62b0 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 128:9bcdf88f62b0 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 128:9bcdf88f62b0 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 128:9bcdf88f62b0 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 128:9bcdf88f62b0 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 128:9bcdf88f62b0 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 128:9bcdf88f62b0 301 } b; /*!< Structure used for bit access */
<> 128:9bcdf88f62b0 302 uint32_t w; /*!< Type used for word access */
<> 128:9bcdf88f62b0 303 } xPSR_Type;
<> 128:9bcdf88f62b0 304
<> 128:9bcdf88f62b0 305 /* xPSR Register Definitions */
<> 128:9bcdf88f62b0 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 128:9bcdf88f62b0 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 128:9bcdf88f62b0 308
<> 128:9bcdf88f62b0 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 128:9bcdf88f62b0 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 128:9bcdf88f62b0 311
<> 128:9bcdf88f62b0 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 128:9bcdf88f62b0 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 128:9bcdf88f62b0 314
<> 128:9bcdf88f62b0 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 128:9bcdf88f62b0 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 128:9bcdf88f62b0 317
<> 128:9bcdf88f62b0 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 128:9bcdf88f62b0 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 128:9bcdf88f62b0 320
<> 128:9bcdf88f62b0 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 128:9bcdf88f62b0 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 128:9bcdf88f62b0 323
<> 128:9bcdf88f62b0 324
<> 128:9bcdf88f62b0 325 /** \brief Union type to access the Control Registers (CONTROL).
<> 128:9bcdf88f62b0 326 */
<> 128:9bcdf88f62b0 327 typedef union
<> 128:9bcdf88f62b0 328 {
<> 128:9bcdf88f62b0 329 struct
<> 128:9bcdf88f62b0 330 {
<> 128:9bcdf88f62b0 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 128:9bcdf88f62b0 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 128:9bcdf88f62b0 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 128:9bcdf88f62b0 334 } b; /*!< Structure used for bit access */
<> 128:9bcdf88f62b0 335 uint32_t w; /*!< Type used for word access */
<> 128:9bcdf88f62b0 336 } CONTROL_Type;
<> 128:9bcdf88f62b0 337
<> 128:9bcdf88f62b0 338 /* CONTROL Register Definitions */
<> 128:9bcdf88f62b0 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 128:9bcdf88f62b0 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 128:9bcdf88f62b0 341
<> 128:9bcdf88f62b0 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 128:9bcdf88f62b0 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 128:9bcdf88f62b0 344
<> 128:9bcdf88f62b0 345 /*@} end of group CMSIS_CORE */
<> 128:9bcdf88f62b0 346
<> 128:9bcdf88f62b0 347
<> 128:9bcdf88f62b0 348 /** \ingroup CMSIS_core_register
<> 128:9bcdf88f62b0 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 128:9bcdf88f62b0 350 \brief Type definitions for the NVIC Registers
<> 128:9bcdf88f62b0 351 @{
<> 128:9bcdf88f62b0 352 */
<> 128:9bcdf88f62b0 353
<> 128:9bcdf88f62b0 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 128:9bcdf88f62b0 355 */
<> 128:9bcdf88f62b0 356 typedef struct
<> 128:9bcdf88f62b0 357 {
<> 128:9bcdf88f62b0 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 128:9bcdf88f62b0 359 uint32_t RESERVED0[31];
<> 128:9bcdf88f62b0 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 128:9bcdf88f62b0 361 uint32_t RSERVED1[31];
<> 128:9bcdf88f62b0 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 128:9bcdf88f62b0 363 uint32_t RESERVED2[31];
<> 128:9bcdf88f62b0 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 128:9bcdf88f62b0 365 uint32_t RESERVED3[31];
<> 128:9bcdf88f62b0 366 uint32_t RESERVED4[64];
<> 128:9bcdf88f62b0 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 128:9bcdf88f62b0 368 } NVIC_Type;
<> 128:9bcdf88f62b0 369
<> 128:9bcdf88f62b0 370 /*@} end of group CMSIS_NVIC */
<> 128:9bcdf88f62b0 371
<> 128:9bcdf88f62b0 372
<> 128:9bcdf88f62b0 373 /** \ingroup CMSIS_core_register
<> 128:9bcdf88f62b0 374 \defgroup CMSIS_SCB System Control Block (SCB)
<> 128:9bcdf88f62b0 375 \brief Type definitions for the System Control Block Registers
<> 128:9bcdf88f62b0 376 @{
<> 128:9bcdf88f62b0 377 */
<> 128:9bcdf88f62b0 378
<> 128:9bcdf88f62b0 379 /** \brief Structure type to access the System Control Block (SCB).
<> 128:9bcdf88f62b0 380 */
<> 128:9bcdf88f62b0 381 typedef struct
<> 128:9bcdf88f62b0 382 {
<> 128:9bcdf88f62b0 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 128:9bcdf88f62b0 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 128:9bcdf88f62b0 385 #if (__VTOR_PRESENT == 1)
<> 128:9bcdf88f62b0 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 128:9bcdf88f62b0 387 #else
<> 128:9bcdf88f62b0 388 uint32_t RESERVED0;
<> 128:9bcdf88f62b0 389 #endif
<> 128:9bcdf88f62b0 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 128:9bcdf88f62b0 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 128:9bcdf88f62b0 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 128:9bcdf88f62b0 393 uint32_t RESERVED1;
<> 128:9bcdf88f62b0 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 128:9bcdf88f62b0 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 128:9bcdf88f62b0 396 } SCB_Type;
<> 128:9bcdf88f62b0 397
<> 128:9bcdf88f62b0 398 /* SCB CPUID Register Definitions */
<> 128:9bcdf88f62b0 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 128:9bcdf88f62b0 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 128:9bcdf88f62b0 401
<> 128:9bcdf88f62b0 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 128:9bcdf88f62b0 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 128:9bcdf88f62b0 404
<> 128:9bcdf88f62b0 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 128:9bcdf88f62b0 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 128:9bcdf88f62b0 407
<> 128:9bcdf88f62b0 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 128:9bcdf88f62b0 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 128:9bcdf88f62b0 410
<> 128:9bcdf88f62b0 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 128:9bcdf88f62b0 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 128:9bcdf88f62b0 413
<> 128:9bcdf88f62b0 414 /* SCB Interrupt Control State Register Definitions */
<> 128:9bcdf88f62b0 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 128:9bcdf88f62b0 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 128:9bcdf88f62b0 417
<> 128:9bcdf88f62b0 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 128:9bcdf88f62b0 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 128:9bcdf88f62b0 420
<> 128:9bcdf88f62b0 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 128:9bcdf88f62b0 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 128:9bcdf88f62b0 423
<> 128:9bcdf88f62b0 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 128:9bcdf88f62b0 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 128:9bcdf88f62b0 426
<> 128:9bcdf88f62b0 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 128:9bcdf88f62b0 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 128:9bcdf88f62b0 429
<> 128:9bcdf88f62b0 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 128:9bcdf88f62b0 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 128:9bcdf88f62b0 432
<> 128:9bcdf88f62b0 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 128:9bcdf88f62b0 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 128:9bcdf88f62b0 435
<> 128:9bcdf88f62b0 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 128:9bcdf88f62b0 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 128:9bcdf88f62b0 438
<> 128:9bcdf88f62b0 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 128:9bcdf88f62b0 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 128:9bcdf88f62b0 441
<> 128:9bcdf88f62b0 442 #if (__VTOR_PRESENT == 1)
<> 128:9bcdf88f62b0 443 /* SCB Interrupt Control State Register Definitions */
<> 128:9bcdf88f62b0 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
<> 128:9bcdf88f62b0 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 128:9bcdf88f62b0 446 #endif
<> 128:9bcdf88f62b0 447
<> 128:9bcdf88f62b0 448 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 128:9bcdf88f62b0 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 128:9bcdf88f62b0 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 128:9bcdf88f62b0 451
<> 128:9bcdf88f62b0 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 128:9bcdf88f62b0 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 128:9bcdf88f62b0 454
<> 128:9bcdf88f62b0 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 128:9bcdf88f62b0 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 128:9bcdf88f62b0 457
<> 128:9bcdf88f62b0 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 128:9bcdf88f62b0 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 128:9bcdf88f62b0 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 128:9bcdf88f62b0 463
<> 128:9bcdf88f62b0 464 /* SCB System Control Register Definitions */
<> 128:9bcdf88f62b0 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 128:9bcdf88f62b0 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 128:9bcdf88f62b0 467
<> 128:9bcdf88f62b0 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 128:9bcdf88f62b0 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 128:9bcdf88f62b0 470
<> 128:9bcdf88f62b0 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 128:9bcdf88f62b0 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 128:9bcdf88f62b0 473
<> 128:9bcdf88f62b0 474 /* SCB Configuration Control Register Definitions */
<> 128:9bcdf88f62b0 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 128:9bcdf88f62b0 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 128:9bcdf88f62b0 477
<> 128:9bcdf88f62b0 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 128:9bcdf88f62b0 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 128:9bcdf88f62b0 480
<> 128:9bcdf88f62b0 481 /* SCB System Handler Control and State Register Definitions */
<> 128:9bcdf88f62b0 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 128:9bcdf88f62b0 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 128:9bcdf88f62b0 484
<> 128:9bcdf88f62b0 485 /*@} end of group CMSIS_SCB */
<> 128:9bcdf88f62b0 486
<> 128:9bcdf88f62b0 487
<> 128:9bcdf88f62b0 488 /** \ingroup CMSIS_core_register
<> 128:9bcdf88f62b0 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 128:9bcdf88f62b0 490 \brief Type definitions for the System Timer Registers.
<> 128:9bcdf88f62b0 491 @{
<> 128:9bcdf88f62b0 492 */
<> 128:9bcdf88f62b0 493
<> 128:9bcdf88f62b0 494 /** \brief Structure type to access the System Timer (SysTick).
<> 128:9bcdf88f62b0 495 */
<> 128:9bcdf88f62b0 496 typedef struct
<> 128:9bcdf88f62b0 497 {
<> 128:9bcdf88f62b0 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 128:9bcdf88f62b0 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 128:9bcdf88f62b0 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 128:9bcdf88f62b0 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 128:9bcdf88f62b0 502 } SysTick_Type;
<> 128:9bcdf88f62b0 503
<> 128:9bcdf88f62b0 504 /* SysTick Control / Status Register Definitions */
<> 128:9bcdf88f62b0 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 128:9bcdf88f62b0 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 128:9bcdf88f62b0 507
<> 128:9bcdf88f62b0 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 128:9bcdf88f62b0 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 128:9bcdf88f62b0 510
<> 128:9bcdf88f62b0 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 128:9bcdf88f62b0 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 128:9bcdf88f62b0 513
<> 128:9bcdf88f62b0 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 128:9bcdf88f62b0 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 128:9bcdf88f62b0 516
<> 128:9bcdf88f62b0 517 /* SysTick Reload Register Definitions */
<> 128:9bcdf88f62b0 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 128:9bcdf88f62b0 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 128:9bcdf88f62b0 520
<> 128:9bcdf88f62b0 521 /* SysTick Current Register Definitions */
<> 128:9bcdf88f62b0 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 128:9bcdf88f62b0 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 128:9bcdf88f62b0 524
<> 128:9bcdf88f62b0 525 /* SysTick Calibration Register Definitions */
<> 128:9bcdf88f62b0 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 128:9bcdf88f62b0 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 128:9bcdf88f62b0 528
<> 128:9bcdf88f62b0 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 128:9bcdf88f62b0 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 128:9bcdf88f62b0 531
<> 128:9bcdf88f62b0 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 128:9bcdf88f62b0 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 128:9bcdf88f62b0 534
<> 128:9bcdf88f62b0 535 /*@} end of group CMSIS_SysTick */
<> 128:9bcdf88f62b0 536
<> 128:9bcdf88f62b0 537 #if (__MPU_PRESENT == 1)
<> 128:9bcdf88f62b0 538 /** \ingroup CMSIS_core_register
<> 128:9bcdf88f62b0 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 128:9bcdf88f62b0 540 \brief Type definitions for the Memory Protection Unit (MPU)
<> 128:9bcdf88f62b0 541 @{
<> 128:9bcdf88f62b0 542 */
<> 128:9bcdf88f62b0 543
<> 128:9bcdf88f62b0 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 128:9bcdf88f62b0 545 */
<> 128:9bcdf88f62b0 546 typedef struct
<> 128:9bcdf88f62b0 547 {
<> 128:9bcdf88f62b0 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 128:9bcdf88f62b0 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 128:9bcdf88f62b0 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 128:9bcdf88f62b0 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 128:9bcdf88f62b0 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 128:9bcdf88f62b0 553 } MPU_Type;
<> 128:9bcdf88f62b0 554
<> 128:9bcdf88f62b0 555 /* MPU Type Register */
<> 128:9bcdf88f62b0 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 128:9bcdf88f62b0 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 128:9bcdf88f62b0 558
<> 128:9bcdf88f62b0 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 128:9bcdf88f62b0 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 128:9bcdf88f62b0 561
<> 128:9bcdf88f62b0 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 128:9bcdf88f62b0 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 /* MPU Control Register */
<> 128:9bcdf88f62b0 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 128:9bcdf88f62b0 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 128:9bcdf88f62b0 568
<> 128:9bcdf88f62b0 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 128:9bcdf88f62b0 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 128:9bcdf88f62b0 571
<> 128:9bcdf88f62b0 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 128:9bcdf88f62b0 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 128:9bcdf88f62b0 574
<> 128:9bcdf88f62b0 575 /* MPU Region Number Register */
<> 128:9bcdf88f62b0 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 128:9bcdf88f62b0 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 128:9bcdf88f62b0 578
<> 128:9bcdf88f62b0 579 /* MPU Region Base Address Register */
<> 128:9bcdf88f62b0 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
<> 128:9bcdf88f62b0 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 128:9bcdf88f62b0 582
<> 128:9bcdf88f62b0 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 128:9bcdf88f62b0 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 128:9bcdf88f62b0 585
<> 128:9bcdf88f62b0 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 128:9bcdf88f62b0 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 128:9bcdf88f62b0 588
<> 128:9bcdf88f62b0 589 /* MPU Region Attribute and Size Register */
<> 128:9bcdf88f62b0 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 128:9bcdf88f62b0 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 128:9bcdf88f62b0 592
<> 128:9bcdf88f62b0 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 128:9bcdf88f62b0 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 128:9bcdf88f62b0 595
<> 128:9bcdf88f62b0 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 128:9bcdf88f62b0 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 128:9bcdf88f62b0 598
<> 128:9bcdf88f62b0 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 128:9bcdf88f62b0 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 128:9bcdf88f62b0 601
<> 128:9bcdf88f62b0 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 128:9bcdf88f62b0 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 128:9bcdf88f62b0 604
<> 128:9bcdf88f62b0 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 128:9bcdf88f62b0 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 128:9bcdf88f62b0 607
<> 128:9bcdf88f62b0 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 128:9bcdf88f62b0 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 128:9bcdf88f62b0 610
<> 128:9bcdf88f62b0 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 128:9bcdf88f62b0 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 128:9bcdf88f62b0 613
<> 128:9bcdf88f62b0 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 128:9bcdf88f62b0 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 128:9bcdf88f62b0 616
<> 128:9bcdf88f62b0 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 128:9bcdf88f62b0 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 128:9bcdf88f62b0 619
<> 128:9bcdf88f62b0 620 /*@} end of group CMSIS_MPU */
<> 128:9bcdf88f62b0 621 #endif
<> 128:9bcdf88f62b0 622
<> 128:9bcdf88f62b0 623
<> 128:9bcdf88f62b0 624 /** \ingroup CMSIS_core_register
<> 128:9bcdf88f62b0 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 128:9bcdf88f62b0 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 128:9bcdf88f62b0 627 are only accessible over DAP and not via processor. Therefore
<> 128:9bcdf88f62b0 628 they are not covered by the Cortex-M0 header file.
<> 128:9bcdf88f62b0 629 @{
<> 128:9bcdf88f62b0 630 */
<> 128:9bcdf88f62b0 631 /*@} end of group CMSIS_CoreDebug */
<> 128:9bcdf88f62b0 632
<> 128:9bcdf88f62b0 633
<> 128:9bcdf88f62b0 634 /** \ingroup CMSIS_core_register
<> 128:9bcdf88f62b0 635 \defgroup CMSIS_core_base Core Definitions
<> 128:9bcdf88f62b0 636 \brief Definitions for base addresses, unions, and structures.
<> 128:9bcdf88f62b0 637 @{
<> 128:9bcdf88f62b0 638 */
<> 128:9bcdf88f62b0 639
<> 128:9bcdf88f62b0 640 /* Memory mapping of Cortex-M0+ Hardware */
<> 128:9bcdf88f62b0 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 128:9bcdf88f62b0 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 128:9bcdf88f62b0 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 128:9bcdf88f62b0 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 128:9bcdf88f62b0 645
<> 128:9bcdf88f62b0 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 128:9bcdf88f62b0 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 128:9bcdf88f62b0 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 128:9bcdf88f62b0 649
<> 128:9bcdf88f62b0 650 #if (__MPU_PRESENT == 1)
<> 128:9bcdf88f62b0 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 128:9bcdf88f62b0 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 128:9bcdf88f62b0 653 #endif
<> 128:9bcdf88f62b0 654
<> 128:9bcdf88f62b0 655 /*@} */
<> 128:9bcdf88f62b0 656
<> 128:9bcdf88f62b0 657
<> 128:9bcdf88f62b0 658
<> 128:9bcdf88f62b0 659 /*******************************************************************************
<> 128:9bcdf88f62b0 660 * Hardware Abstraction Layer
<> 128:9bcdf88f62b0 661 Core Function Interface contains:
<> 128:9bcdf88f62b0 662 - Core NVIC Functions
<> 128:9bcdf88f62b0 663 - Core SysTick Functions
<> 128:9bcdf88f62b0 664 - Core Register Access Functions
<> 128:9bcdf88f62b0 665 ******************************************************************************/
<> 128:9bcdf88f62b0 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 128:9bcdf88f62b0 667 */
<> 128:9bcdf88f62b0 668
<> 128:9bcdf88f62b0 669
<> 128:9bcdf88f62b0 670
<> 128:9bcdf88f62b0 671 /* ########################## NVIC functions #################################### */
<> 128:9bcdf88f62b0 672 /** \ingroup CMSIS_Core_FunctionInterface
<> 128:9bcdf88f62b0 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 128:9bcdf88f62b0 674 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 128:9bcdf88f62b0 675 @{
<> 128:9bcdf88f62b0 676 */
<> 128:9bcdf88f62b0 677
<> 128:9bcdf88f62b0 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 128:9bcdf88f62b0 679 /* The following MACROS handle generation of the register offset and byte masks */
<> 128:9bcdf88f62b0 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 128:9bcdf88f62b0 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 128:9bcdf88f62b0 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 128:9bcdf88f62b0 683
<> 128:9bcdf88f62b0 684
<> 128:9bcdf88f62b0 685 /** \brief Enable External Interrupt
<> 128:9bcdf88f62b0 686
<> 128:9bcdf88f62b0 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 128:9bcdf88f62b0 688
<> 128:9bcdf88f62b0 689 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 128:9bcdf88f62b0 690 */
<> 128:9bcdf88f62b0 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 128:9bcdf88f62b0 692 {
<> 128:9bcdf88f62b0 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 128:9bcdf88f62b0 694 }
<> 128:9bcdf88f62b0 695
<> 128:9bcdf88f62b0 696
<> 128:9bcdf88f62b0 697 /** \brief Disable External Interrupt
<> 128:9bcdf88f62b0 698
<> 128:9bcdf88f62b0 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 128:9bcdf88f62b0 700
<> 128:9bcdf88f62b0 701 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 128:9bcdf88f62b0 702 */
<> 128:9bcdf88f62b0 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 128:9bcdf88f62b0 704 {
<> 128:9bcdf88f62b0 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
<> 128:9bcdf88f62b0 708 }
<> 128:9bcdf88f62b0 709
<> 128:9bcdf88f62b0 710
<> 128:9bcdf88f62b0 711 /** \brief Get Pending Interrupt
<> 128:9bcdf88f62b0 712
<> 128:9bcdf88f62b0 713 The function reads the pending register in the NVIC and returns the pending bit
<> 128:9bcdf88f62b0 714 for the specified interrupt.
<> 128:9bcdf88f62b0 715
<> 128:9bcdf88f62b0 716 \param [in] IRQn Interrupt number.
<> 128:9bcdf88f62b0 717
<> 128:9bcdf88f62b0 718 \return 0 Interrupt status is not pending.
<> 128:9bcdf88f62b0 719 \return 1 Interrupt status is pending.
<> 128:9bcdf88f62b0 720 */
<> 128:9bcdf88f62b0 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 128:9bcdf88f62b0 722 {
<> 128:9bcdf88f62b0 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 128:9bcdf88f62b0 724 }
<> 128:9bcdf88f62b0 725
<> 128:9bcdf88f62b0 726
<> 128:9bcdf88f62b0 727 /** \brief Set Pending Interrupt
<> 128:9bcdf88f62b0 728
<> 128:9bcdf88f62b0 729 The function sets the pending bit of an external interrupt.
<> 128:9bcdf88f62b0 730
<> 128:9bcdf88f62b0 731 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 128:9bcdf88f62b0 732 */
<> 128:9bcdf88f62b0 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 128:9bcdf88f62b0 734 {
<> 128:9bcdf88f62b0 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 128:9bcdf88f62b0 736 }
<> 128:9bcdf88f62b0 737
<> 128:9bcdf88f62b0 738
<> 128:9bcdf88f62b0 739 /** \brief Clear Pending Interrupt
<> 128:9bcdf88f62b0 740
<> 128:9bcdf88f62b0 741 The function clears the pending bit of an external interrupt.
<> 128:9bcdf88f62b0 742
<> 128:9bcdf88f62b0 743 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 128:9bcdf88f62b0 744 */
<> 128:9bcdf88f62b0 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 128:9bcdf88f62b0 746 {
<> 128:9bcdf88f62b0 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 128:9bcdf88f62b0 748 }
<> 128:9bcdf88f62b0 749
<> 128:9bcdf88f62b0 750
<> 128:9bcdf88f62b0 751 /** \brief Set Interrupt Priority
<> 128:9bcdf88f62b0 752
<> 128:9bcdf88f62b0 753 The function sets the priority of an interrupt.
<> 128:9bcdf88f62b0 754
<> 128:9bcdf88f62b0 755 \note The priority cannot be set for every core interrupt.
<> 128:9bcdf88f62b0 756
<> 128:9bcdf88f62b0 757 \param [in] IRQn Interrupt number.
<> 128:9bcdf88f62b0 758 \param [in] priority Priority to set.
<> 128:9bcdf88f62b0 759 */
<> 128:9bcdf88f62b0 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 128:9bcdf88f62b0 761 {
<> 128:9bcdf88f62b0 762 if((int32_t)(IRQn) < 0) {
<> 128:9bcdf88f62b0 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 128:9bcdf88f62b0 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 128:9bcdf88f62b0 765 }
<> 128:9bcdf88f62b0 766 else {
<> 128:9bcdf88f62b0 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 128:9bcdf88f62b0 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 128:9bcdf88f62b0 769 }
<> 128:9bcdf88f62b0 770 }
<> 128:9bcdf88f62b0 771
<> 128:9bcdf88f62b0 772
<> 128:9bcdf88f62b0 773 /** \brief Get Interrupt Priority
<> 128:9bcdf88f62b0 774
<> 128:9bcdf88f62b0 775 The function reads the priority of an interrupt. The interrupt
<> 128:9bcdf88f62b0 776 number can be positive to specify an external (device specific)
<> 128:9bcdf88f62b0 777 interrupt, or negative to specify an internal (core) interrupt.
<> 128:9bcdf88f62b0 778
<> 128:9bcdf88f62b0 779
<> 128:9bcdf88f62b0 780 \param [in] IRQn Interrupt number.
<> 128:9bcdf88f62b0 781 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 128:9bcdf88f62b0 782 priority bits of the microcontroller.
<> 128:9bcdf88f62b0 783 */
<> 128:9bcdf88f62b0 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 128:9bcdf88f62b0 785 {
<> 128:9bcdf88f62b0 786
<> 128:9bcdf88f62b0 787 if((int32_t)(IRQn) < 0) {
<> 128:9bcdf88f62b0 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 128:9bcdf88f62b0 789 }
<> 128:9bcdf88f62b0 790 else {
<> 128:9bcdf88f62b0 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 128:9bcdf88f62b0 792 }
<> 128:9bcdf88f62b0 793 }
<> 128:9bcdf88f62b0 794
<> 128:9bcdf88f62b0 795
<> 128:9bcdf88f62b0 796 /** \brief System Reset
<> 128:9bcdf88f62b0 797
<> 128:9bcdf88f62b0 798 The function initiates a system reset request to reset the MCU.
<> 128:9bcdf88f62b0 799 */
<> 128:9bcdf88f62b0 800 __STATIC_INLINE void NVIC_SystemReset(void)
<> 128:9bcdf88f62b0 801 {
<> 128:9bcdf88f62b0 802 __DSB(); /* Ensure all outstanding memory accesses included
<> 128:9bcdf88f62b0 803 buffered write are completed before reset */
<> 128:9bcdf88f62b0 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 128:9bcdf88f62b0 805 SCB_AIRCR_SYSRESETREQ_Msk);
<> 128:9bcdf88f62b0 806 __DSB(); /* Ensure completion of memory access */
<> 128:9bcdf88f62b0 807 while(1) { __NOP(); } /* wait until reset */
<> 128:9bcdf88f62b0 808 }
<> 128:9bcdf88f62b0 809
<> 128:9bcdf88f62b0 810 /*@} end of CMSIS_Core_NVICFunctions */
<> 128:9bcdf88f62b0 811
<> 128:9bcdf88f62b0 812
<> 128:9bcdf88f62b0 813
<> 128:9bcdf88f62b0 814 /* ################################## SysTick function ############################################ */
<> 128:9bcdf88f62b0 815 /** \ingroup CMSIS_Core_FunctionInterface
<> 128:9bcdf88f62b0 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 128:9bcdf88f62b0 817 \brief Functions that configure the System.
<> 128:9bcdf88f62b0 818 @{
<> 128:9bcdf88f62b0 819 */
<> 128:9bcdf88f62b0 820
<> 128:9bcdf88f62b0 821 #if (__Vendor_SysTickConfig == 0)
<> 128:9bcdf88f62b0 822
<> 128:9bcdf88f62b0 823 /** \brief System Tick Configuration
<> 128:9bcdf88f62b0 824
<> 128:9bcdf88f62b0 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 128:9bcdf88f62b0 826 Counter is in free running mode to generate periodic interrupts.
<> 128:9bcdf88f62b0 827
<> 128:9bcdf88f62b0 828 \param [in] ticks Number of ticks between two interrupts.
<> 128:9bcdf88f62b0 829
<> 128:9bcdf88f62b0 830 \return 0 Function succeeded.
<> 128:9bcdf88f62b0 831 \return 1 Function failed.
<> 128:9bcdf88f62b0 832
<> 128:9bcdf88f62b0 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 128:9bcdf88f62b0 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 128:9bcdf88f62b0 835 must contain a vendor-specific implementation of this function.
<> 128:9bcdf88f62b0 836
<> 128:9bcdf88f62b0 837 */
<> 128:9bcdf88f62b0 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 128:9bcdf88f62b0 839 {
<> 128:9bcdf88f62b0 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
<> 128:9bcdf88f62b0 841
<> 128:9bcdf88f62b0 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 128:9bcdf88f62b0 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 128:9bcdf88f62b0 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 128:9bcdf88f62b0 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 128:9bcdf88f62b0 846 SysTick_CTRL_TICKINT_Msk |
<> 128:9bcdf88f62b0 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 128:9bcdf88f62b0 848 return (0UL); /* Function successful */
<> 128:9bcdf88f62b0 849 }
<> 128:9bcdf88f62b0 850
<> 128:9bcdf88f62b0 851 #endif
<> 128:9bcdf88f62b0 852
<> 128:9bcdf88f62b0 853 /*@} end of CMSIS_Core_SysTickFunctions */
<> 128:9bcdf88f62b0 854
<> 128:9bcdf88f62b0 855
<> 128:9bcdf88f62b0 856
<> 128:9bcdf88f62b0 857
<> 128:9bcdf88f62b0 858 #ifdef __cplusplus
<> 128:9bcdf88f62b0 859 }
<> 128:9bcdf88f62b0 860 #endif
<> 128:9bcdf88f62b0 861
<> 128:9bcdf88f62b0 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
<> 128:9bcdf88f62b0 863
<> 128:9bcdf88f62b0 864 #endif /* __CMSIS_GENERIC */