mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F746ZG/core_cm0.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 115:87f2f5183dfb 1 /**************************************************************************//**
Kojto 115:87f2f5183dfb 2 * @file core_cm0.h
Kojto 115:87f2f5183dfb 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 115:87f2f5183dfb 4 * @version V4.10
Kojto 115:87f2f5183dfb 5 * @date 18. March 2015
Kojto 115:87f2f5183dfb 6 *
Kojto 115:87f2f5183dfb 7 * @note
Kojto 115:87f2f5183dfb 8 *
Kojto 115:87f2f5183dfb 9 ******************************************************************************/
Kojto 115:87f2f5183dfb 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 115:87f2f5183dfb 11
Kojto 115:87f2f5183dfb 12 All rights reserved.
Kojto 115:87f2f5183dfb 13 Redistribution and use in source and binary forms, with or without
Kojto 115:87f2f5183dfb 14 modification, are permitted provided that the following conditions are met:
Kojto 115:87f2f5183dfb 15 - Redistributions of source code must retain the above copyright
Kojto 115:87f2f5183dfb 16 notice, this list of conditions and the following disclaimer.
Kojto 115:87f2f5183dfb 17 - Redistributions in binary form must reproduce the above copyright
Kojto 115:87f2f5183dfb 18 notice, this list of conditions and the following disclaimer in the
Kojto 115:87f2f5183dfb 19 documentation and/or other materials provided with the distribution.
Kojto 115:87f2f5183dfb 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 115:87f2f5183dfb 21 to endorse or promote products derived from this software without
Kojto 115:87f2f5183dfb 22 specific prior written permission.
Kojto 115:87f2f5183dfb 23 *
Kojto 115:87f2f5183dfb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 115:87f2f5183dfb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 115:87f2f5183dfb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 115:87f2f5183dfb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 115:87f2f5183dfb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 115:87f2f5183dfb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 115:87f2f5183dfb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 115:87f2f5183dfb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 115:87f2f5183dfb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 115:87f2f5183dfb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 115:87f2f5183dfb 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 115:87f2f5183dfb 35 ---------------------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 36
Kojto 115:87f2f5183dfb 37
Kojto 115:87f2f5183dfb 38 #if defined ( __ICCARM__ )
Kojto 115:87f2f5183dfb 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 115:87f2f5183dfb 40 #endif
Kojto 115:87f2f5183dfb 41
Kojto 115:87f2f5183dfb 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 115:87f2f5183dfb 43 #define __CORE_CM0_H_GENERIC
Kojto 115:87f2f5183dfb 44
Kojto 115:87f2f5183dfb 45 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 46 extern "C" {
Kojto 115:87f2f5183dfb 47 #endif
Kojto 115:87f2f5183dfb 48
Kojto 115:87f2f5183dfb 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 115:87f2f5183dfb 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 115:87f2f5183dfb 51
Kojto 115:87f2f5183dfb 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 115:87f2f5183dfb 53 Function definitions in header files are used to allow 'inlining'.
Kojto 115:87f2f5183dfb 54
Kojto 115:87f2f5183dfb 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 115:87f2f5183dfb 56 Unions are used for effective representation of core registers.
Kojto 115:87f2f5183dfb 57
Kojto 115:87f2f5183dfb 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 115:87f2f5183dfb 59 Function-like macros are used to allow more efficient code.
Kojto 115:87f2f5183dfb 60 */
Kojto 115:87f2f5183dfb 61
Kojto 115:87f2f5183dfb 62
Kojto 115:87f2f5183dfb 63 /*******************************************************************************
Kojto 115:87f2f5183dfb 64 * CMSIS definitions
Kojto 115:87f2f5183dfb 65 ******************************************************************************/
Kojto 115:87f2f5183dfb 66 /** \ingroup Cortex_M0
Kojto 115:87f2f5183dfb 67 @{
Kojto 115:87f2f5183dfb 68 */
Kojto 115:87f2f5183dfb 69
Kojto 115:87f2f5183dfb 70 /* CMSIS CM0 definitions */
Kojto 115:87f2f5183dfb 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 115:87f2f5183dfb 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 115:87f2f5183dfb 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 115:87f2f5183dfb 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 115:87f2f5183dfb 75
Kojto 115:87f2f5183dfb 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 115:87f2f5183dfb 77
Kojto 115:87f2f5183dfb 78
Kojto 115:87f2f5183dfb 79 #if defined ( __CC_ARM )
Kojto 115:87f2f5183dfb 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 115:87f2f5183dfb 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 115:87f2f5183dfb 82 #define __STATIC_INLINE static __inline
Kojto 115:87f2f5183dfb 83
Kojto 115:87f2f5183dfb 84 #elif defined ( __GNUC__ )
Kojto 115:87f2f5183dfb 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 115:87f2f5183dfb 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 115:87f2f5183dfb 87 #define __STATIC_INLINE static inline
Kojto 115:87f2f5183dfb 88
Kojto 115:87f2f5183dfb 89 #elif defined ( __ICCARM__ )
Kojto 115:87f2f5183dfb 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 115:87f2f5183dfb 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 115:87f2f5183dfb 92 #define __STATIC_INLINE static inline
Kojto 115:87f2f5183dfb 93
Kojto 115:87f2f5183dfb 94 #elif defined ( __TMS470__ )
Kojto 115:87f2f5183dfb 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 115:87f2f5183dfb 96 #define __STATIC_INLINE static inline
Kojto 115:87f2f5183dfb 97
Kojto 115:87f2f5183dfb 98 #elif defined ( __TASKING__ )
Kojto 115:87f2f5183dfb 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 115:87f2f5183dfb 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 115:87f2f5183dfb 101 #define __STATIC_INLINE static inline
Kojto 115:87f2f5183dfb 102
Kojto 115:87f2f5183dfb 103 #elif defined ( __CSMC__ )
Kojto 115:87f2f5183dfb 104 #define __packed
Kojto 115:87f2f5183dfb 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 115:87f2f5183dfb 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 115:87f2f5183dfb 107 #define __STATIC_INLINE static inline
Kojto 115:87f2f5183dfb 108
Kojto 115:87f2f5183dfb 109 #endif
Kojto 115:87f2f5183dfb 110
Kojto 115:87f2f5183dfb 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 115:87f2f5183dfb 112 This core does not support an FPU at all
Kojto 115:87f2f5183dfb 113 */
Kojto 115:87f2f5183dfb 114 #define __FPU_USED 0
Kojto 115:87f2f5183dfb 115
Kojto 115:87f2f5183dfb 116 #if defined ( __CC_ARM )
Kojto 115:87f2f5183dfb 117 #if defined __TARGET_FPU_VFP
Kojto 115:87f2f5183dfb 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 115:87f2f5183dfb 119 #endif
Kojto 115:87f2f5183dfb 120
Kojto 115:87f2f5183dfb 121 #elif defined ( __GNUC__ )
Kojto 115:87f2f5183dfb 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 115:87f2f5183dfb 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 115:87f2f5183dfb 124 #endif
Kojto 115:87f2f5183dfb 125
Kojto 115:87f2f5183dfb 126 #elif defined ( __ICCARM__ )
Kojto 115:87f2f5183dfb 127 #if defined __ARMVFP__
Kojto 115:87f2f5183dfb 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 115:87f2f5183dfb 129 #endif
Kojto 115:87f2f5183dfb 130
Kojto 115:87f2f5183dfb 131 #elif defined ( __TMS470__ )
Kojto 115:87f2f5183dfb 132 #if defined __TI__VFP_SUPPORT____
Kojto 115:87f2f5183dfb 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 115:87f2f5183dfb 134 #endif
Kojto 115:87f2f5183dfb 135
Kojto 115:87f2f5183dfb 136 #elif defined ( __TASKING__ )
Kojto 115:87f2f5183dfb 137 #if defined __FPU_VFP__
Kojto 115:87f2f5183dfb 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 115:87f2f5183dfb 139 #endif
Kojto 115:87f2f5183dfb 140
Kojto 115:87f2f5183dfb 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 115:87f2f5183dfb 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 115:87f2f5183dfb 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 115:87f2f5183dfb 144 #endif
Kojto 115:87f2f5183dfb 145 #endif
Kojto 115:87f2f5183dfb 146
Kojto 115:87f2f5183dfb 147 #include <stdint.h> /* standard types definitions */
Kojto 115:87f2f5183dfb 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 115:87f2f5183dfb 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 115:87f2f5183dfb 150
Kojto 115:87f2f5183dfb 151 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 152 }
Kojto 115:87f2f5183dfb 153 #endif
Kojto 115:87f2f5183dfb 154
Kojto 115:87f2f5183dfb 155 #endif /* __CORE_CM0_H_GENERIC */
Kojto 115:87f2f5183dfb 156
Kojto 115:87f2f5183dfb 157 #ifndef __CMSIS_GENERIC
Kojto 115:87f2f5183dfb 158
Kojto 115:87f2f5183dfb 159 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 115:87f2f5183dfb 160 #define __CORE_CM0_H_DEPENDANT
Kojto 115:87f2f5183dfb 161
Kojto 115:87f2f5183dfb 162 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 163 extern "C" {
Kojto 115:87f2f5183dfb 164 #endif
Kojto 115:87f2f5183dfb 165
Kojto 115:87f2f5183dfb 166 /* check device defines and use defaults */
Kojto 115:87f2f5183dfb 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 115:87f2f5183dfb 168 #ifndef __CM0_REV
Kojto 115:87f2f5183dfb 169 #define __CM0_REV 0x0000
Kojto 115:87f2f5183dfb 170 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 115:87f2f5183dfb 171 #endif
Kojto 115:87f2f5183dfb 172
Kojto 115:87f2f5183dfb 173 #ifndef __NVIC_PRIO_BITS
Kojto 115:87f2f5183dfb 174 #define __NVIC_PRIO_BITS 2
Kojto 115:87f2f5183dfb 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 115:87f2f5183dfb 176 #endif
Kojto 115:87f2f5183dfb 177
Kojto 115:87f2f5183dfb 178 #ifndef __Vendor_SysTickConfig
Kojto 115:87f2f5183dfb 179 #define __Vendor_SysTickConfig 0
Kojto 115:87f2f5183dfb 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 115:87f2f5183dfb 181 #endif
Kojto 115:87f2f5183dfb 182 #endif
Kojto 115:87f2f5183dfb 183
Kojto 115:87f2f5183dfb 184 /* IO definitions (access restrictions to peripheral registers) */
Kojto 115:87f2f5183dfb 185 /**
Kojto 115:87f2f5183dfb 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 115:87f2f5183dfb 187
Kojto 115:87f2f5183dfb 188 <strong>IO Type Qualifiers</strong> are used
Kojto 115:87f2f5183dfb 189 \li to specify the access to peripheral variables.
Kojto 115:87f2f5183dfb 190 \li for automatic generation of peripheral register debug information.
Kojto 115:87f2f5183dfb 191 */
Kojto 115:87f2f5183dfb 192 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 193 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 115:87f2f5183dfb 194 #else
Kojto 115:87f2f5183dfb 195 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 115:87f2f5183dfb 196 #endif
Kojto 115:87f2f5183dfb 197 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 115:87f2f5183dfb 198 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 115:87f2f5183dfb 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
Kojto 115:87f2f5183dfb 208 /*@} end of group Cortex_M0 */
Kojto 115:87f2f5183dfb 209
Kojto 115:87f2f5183dfb 210
Kojto 115:87f2f5183dfb 211
Kojto 115:87f2f5183dfb 212 /*******************************************************************************
Kojto 115:87f2f5183dfb 213 * Register Abstraction
Kojto 115:87f2f5183dfb 214 Core Register contain:
Kojto 115:87f2f5183dfb 215 - Core Register
Kojto 115:87f2f5183dfb 216 - Core NVIC Register
Kojto 115:87f2f5183dfb 217 - Core SCB Register
Kojto 115:87f2f5183dfb 218 - Core SysTick Register
Kojto 115:87f2f5183dfb 219 ******************************************************************************/
Kojto 115:87f2f5183dfb 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 115:87f2f5183dfb 221 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 115:87f2f5183dfb 222 */
Kojto 115:87f2f5183dfb 223
Kojto 115:87f2f5183dfb 224 /** \ingroup CMSIS_core_register
Kojto 115:87f2f5183dfb 225 \defgroup CMSIS_CORE Status and Control Registers
Kojto 115:87f2f5183dfb 226 \brief Core Register type definitions.
Kojto 115:87f2f5183dfb 227 @{
Kojto 115:87f2f5183dfb 228 */
Kojto 115:87f2f5183dfb 229
Kojto 115:87f2f5183dfb 230 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 115:87f2f5183dfb 231 */
Kojto 115:87f2f5183dfb 232 typedef union
Kojto 115:87f2f5183dfb 233 {
Kojto 115:87f2f5183dfb 234 struct
Kojto 115:87f2f5183dfb 235 {
Kojto 115:87f2f5183dfb 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 115:87f2f5183dfb 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 115:87f2f5183dfb 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 115:87f2f5183dfb 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 115:87f2f5183dfb 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 115:87f2f5183dfb 241 } b; /*!< Structure used for bit access */
Kojto 115:87f2f5183dfb 242 uint32_t w; /*!< Type used for word access */
Kojto 115:87f2f5183dfb 243 } APSR_Type;
Kojto 115:87f2f5183dfb 244
Kojto 115:87f2f5183dfb 245 /* APSR Register Definitions */
Kojto 115:87f2f5183dfb 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 115:87f2f5183dfb 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 115:87f2f5183dfb 248
Kojto 115:87f2f5183dfb 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 115:87f2f5183dfb 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 115:87f2f5183dfb 251
Kojto 115:87f2f5183dfb 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 115:87f2f5183dfb 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 115:87f2f5183dfb 254
Kojto 115:87f2f5183dfb 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 115:87f2f5183dfb 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 115:87f2f5183dfb 257
Kojto 115:87f2f5183dfb 258
Kojto 115:87f2f5183dfb 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 115:87f2f5183dfb 260 */
Kojto 115:87f2f5183dfb 261 typedef union
Kojto 115:87f2f5183dfb 262 {
Kojto 115:87f2f5183dfb 263 struct
Kojto 115:87f2f5183dfb 264 {
Kojto 115:87f2f5183dfb 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 115:87f2f5183dfb 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 115:87f2f5183dfb 267 } b; /*!< Structure used for bit access */
Kojto 115:87f2f5183dfb 268 uint32_t w; /*!< Type used for word access */
Kojto 115:87f2f5183dfb 269 } IPSR_Type;
Kojto 115:87f2f5183dfb 270
Kojto 115:87f2f5183dfb 271 /* IPSR Register Definitions */
Kojto 115:87f2f5183dfb 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 115:87f2f5183dfb 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 115:87f2f5183dfb 274
Kojto 115:87f2f5183dfb 275
Kojto 115:87f2f5183dfb 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 115:87f2f5183dfb 277 */
Kojto 115:87f2f5183dfb 278 typedef union
Kojto 115:87f2f5183dfb 279 {
Kojto 115:87f2f5183dfb 280 struct
Kojto 115:87f2f5183dfb 281 {
Kojto 115:87f2f5183dfb 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 115:87f2f5183dfb 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 115:87f2f5183dfb 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 115:87f2f5183dfb 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 115:87f2f5183dfb 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 115:87f2f5183dfb 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 115:87f2f5183dfb 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 115:87f2f5183dfb 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 115:87f2f5183dfb 290 } b; /*!< Structure used for bit access */
Kojto 115:87f2f5183dfb 291 uint32_t w; /*!< Type used for word access */
Kojto 115:87f2f5183dfb 292 } xPSR_Type;
Kojto 115:87f2f5183dfb 293
Kojto 115:87f2f5183dfb 294 /* xPSR Register Definitions */
Kojto 115:87f2f5183dfb 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 115:87f2f5183dfb 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 115:87f2f5183dfb 297
Kojto 115:87f2f5183dfb 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 115:87f2f5183dfb 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 115:87f2f5183dfb 300
Kojto 115:87f2f5183dfb 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 115:87f2f5183dfb 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 115:87f2f5183dfb 303
Kojto 115:87f2f5183dfb 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 115:87f2f5183dfb 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 115:87f2f5183dfb 306
Kojto 115:87f2f5183dfb 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 115:87f2f5183dfb 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 115:87f2f5183dfb 309
Kojto 115:87f2f5183dfb 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 115:87f2f5183dfb 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 115:87f2f5183dfb 312
Kojto 115:87f2f5183dfb 313
Kojto 115:87f2f5183dfb 314 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 115:87f2f5183dfb 315 */
Kojto 115:87f2f5183dfb 316 typedef union
Kojto 115:87f2f5183dfb 317 {
Kojto 115:87f2f5183dfb 318 struct
Kojto 115:87f2f5183dfb 319 {
Kojto 115:87f2f5183dfb 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Kojto 115:87f2f5183dfb 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 115:87f2f5183dfb 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 115:87f2f5183dfb 323 } b; /*!< Structure used for bit access */
Kojto 115:87f2f5183dfb 324 uint32_t w; /*!< Type used for word access */
Kojto 115:87f2f5183dfb 325 } CONTROL_Type;
Kojto 115:87f2f5183dfb 326
Kojto 115:87f2f5183dfb 327 /* CONTROL Register Definitions */
Kojto 115:87f2f5183dfb 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 115:87f2f5183dfb 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 115:87f2f5183dfb 330
Kojto 115:87f2f5183dfb 331 /*@} end of group CMSIS_CORE */
Kojto 115:87f2f5183dfb 332
Kojto 115:87f2f5183dfb 333
Kojto 115:87f2f5183dfb 334 /** \ingroup CMSIS_core_register
Kojto 115:87f2f5183dfb 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 115:87f2f5183dfb 336 \brief Type definitions for the NVIC Registers
Kojto 115:87f2f5183dfb 337 @{
Kojto 115:87f2f5183dfb 338 */
Kojto 115:87f2f5183dfb 339
Kojto 115:87f2f5183dfb 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 115:87f2f5183dfb 341 */
Kojto 115:87f2f5183dfb 342 typedef struct
Kojto 115:87f2f5183dfb 343 {
Kojto 115:87f2f5183dfb 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 115:87f2f5183dfb 345 uint32_t RESERVED0[31];
Kojto 115:87f2f5183dfb 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 115:87f2f5183dfb 347 uint32_t RSERVED1[31];
Kojto 115:87f2f5183dfb 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 115:87f2f5183dfb 349 uint32_t RESERVED2[31];
Kojto 115:87f2f5183dfb 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 115:87f2f5183dfb 351 uint32_t RESERVED3[31];
Kojto 115:87f2f5183dfb 352 uint32_t RESERVED4[64];
Kojto 115:87f2f5183dfb 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 115:87f2f5183dfb 354 } NVIC_Type;
Kojto 115:87f2f5183dfb 355
Kojto 115:87f2f5183dfb 356 /*@} end of group CMSIS_NVIC */
Kojto 115:87f2f5183dfb 357
Kojto 115:87f2f5183dfb 358
Kojto 115:87f2f5183dfb 359 /** \ingroup CMSIS_core_register
Kojto 115:87f2f5183dfb 360 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 115:87f2f5183dfb 361 \brief Type definitions for the System Control Block Registers
Kojto 115:87f2f5183dfb 362 @{
Kojto 115:87f2f5183dfb 363 */
Kojto 115:87f2f5183dfb 364
Kojto 115:87f2f5183dfb 365 /** \brief Structure type to access the System Control Block (SCB).
Kojto 115:87f2f5183dfb 366 */
Kojto 115:87f2f5183dfb 367 typedef struct
Kojto 115:87f2f5183dfb 368 {
Kojto 115:87f2f5183dfb 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 115:87f2f5183dfb 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 115:87f2f5183dfb 371 uint32_t RESERVED0;
Kojto 115:87f2f5183dfb 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 115:87f2f5183dfb 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 115:87f2f5183dfb 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 115:87f2f5183dfb 375 uint32_t RESERVED1;
Kojto 115:87f2f5183dfb 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 115:87f2f5183dfb 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 115:87f2f5183dfb 378 } SCB_Type;
Kojto 115:87f2f5183dfb 379
Kojto 115:87f2f5183dfb 380 /* SCB CPUID Register Definitions */
Kojto 115:87f2f5183dfb 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 115:87f2f5183dfb 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 115:87f2f5183dfb 383
Kojto 115:87f2f5183dfb 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 115:87f2f5183dfb 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 115:87f2f5183dfb 386
Kojto 115:87f2f5183dfb 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 115:87f2f5183dfb 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 115:87f2f5183dfb 389
Kojto 115:87f2f5183dfb 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 115:87f2f5183dfb 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 115:87f2f5183dfb 392
Kojto 115:87f2f5183dfb 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 115:87f2f5183dfb 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 115:87f2f5183dfb 395
Kojto 115:87f2f5183dfb 396 /* SCB Interrupt Control State Register Definitions */
Kojto 115:87f2f5183dfb 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 115:87f2f5183dfb 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 115:87f2f5183dfb 399
Kojto 115:87f2f5183dfb 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 115:87f2f5183dfb 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 115:87f2f5183dfb 402
Kojto 115:87f2f5183dfb 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 115:87f2f5183dfb 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 115:87f2f5183dfb 405
Kojto 115:87f2f5183dfb 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 115:87f2f5183dfb 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 115:87f2f5183dfb 408
Kojto 115:87f2f5183dfb 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 115:87f2f5183dfb 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 115:87f2f5183dfb 411
Kojto 115:87f2f5183dfb 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 115:87f2f5183dfb 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 115:87f2f5183dfb 414
Kojto 115:87f2f5183dfb 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 115:87f2f5183dfb 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 115:87f2f5183dfb 417
Kojto 115:87f2f5183dfb 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 115:87f2f5183dfb 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 115:87f2f5183dfb 420
Kojto 115:87f2f5183dfb 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 115:87f2f5183dfb 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 115:87f2f5183dfb 423
Kojto 115:87f2f5183dfb 424 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 115:87f2f5183dfb 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 115:87f2f5183dfb 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 115:87f2f5183dfb 427
Kojto 115:87f2f5183dfb 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 115:87f2f5183dfb 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 115:87f2f5183dfb 430
Kojto 115:87f2f5183dfb 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 115:87f2f5183dfb 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 115:87f2f5183dfb 433
Kojto 115:87f2f5183dfb 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 115:87f2f5183dfb 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 115:87f2f5183dfb 436
Kojto 115:87f2f5183dfb 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 115:87f2f5183dfb 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 115:87f2f5183dfb 439
Kojto 115:87f2f5183dfb 440 /* SCB System Control Register Definitions */
Kojto 115:87f2f5183dfb 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 115:87f2f5183dfb 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 115:87f2f5183dfb 443
Kojto 115:87f2f5183dfb 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 115:87f2f5183dfb 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 115:87f2f5183dfb 446
Kojto 115:87f2f5183dfb 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 115:87f2f5183dfb 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 115:87f2f5183dfb 449
Kojto 115:87f2f5183dfb 450 /* SCB Configuration Control Register Definitions */
Kojto 115:87f2f5183dfb 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 115:87f2f5183dfb 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 115:87f2f5183dfb 453
Kojto 115:87f2f5183dfb 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 115:87f2f5183dfb 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 115:87f2f5183dfb 456
Kojto 115:87f2f5183dfb 457 /* SCB System Handler Control and State Register Definitions */
Kojto 115:87f2f5183dfb 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 115:87f2f5183dfb 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 115:87f2f5183dfb 460
Kojto 115:87f2f5183dfb 461 /*@} end of group CMSIS_SCB */
Kojto 115:87f2f5183dfb 462
Kojto 115:87f2f5183dfb 463
Kojto 115:87f2f5183dfb 464 /** \ingroup CMSIS_core_register
Kojto 115:87f2f5183dfb 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 115:87f2f5183dfb 466 \brief Type definitions for the System Timer Registers.
Kojto 115:87f2f5183dfb 467 @{
Kojto 115:87f2f5183dfb 468 */
Kojto 115:87f2f5183dfb 469
Kojto 115:87f2f5183dfb 470 /** \brief Structure type to access the System Timer (SysTick).
Kojto 115:87f2f5183dfb 471 */
Kojto 115:87f2f5183dfb 472 typedef struct
Kojto 115:87f2f5183dfb 473 {
Kojto 115:87f2f5183dfb 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 115:87f2f5183dfb 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 115:87f2f5183dfb 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 115:87f2f5183dfb 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 115:87f2f5183dfb 478 } SysTick_Type;
Kojto 115:87f2f5183dfb 479
Kojto 115:87f2f5183dfb 480 /* SysTick Control / Status Register Definitions */
Kojto 115:87f2f5183dfb 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 115:87f2f5183dfb 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 115:87f2f5183dfb 483
Kojto 115:87f2f5183dfb 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 115:87f2f5183dfb 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 115:87f2f5183dfb 486
Kojto 115:87f2f5183dfb 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 115:87f2f5183dfb 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 115:87f2f5183dfb 489
Kojto 115:87f2f5183dfb 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 115:87f2f5183dfb 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 115:87f2f5183dfb 492
Kojto 115:87f2f5183dfb 493 /* SysTick Reload Register Definitions */
Kojto 115:87f2f5183dfb 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 115:87f2f5183dfb 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 115:87f2f5183dfb 496
Kojto 115:87f2f5183dfb 497 /* SysTick Current Register Definitions */
Kojto 115:87f2f5183dfb 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 115:87f2f5183dfb 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 115:87f2f5183dfb 500
Kojto 115:87f2f5183dfb 501 /* SysTick Calibration Register Definitions */
Kojto 115:87f2f5183dfb 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 115:87f2f5183dfb 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 115:87f2f5183dfb 504
Kojto 115:87f2f5183dfb 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 115:87f2f5183dfb 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 115:87f2f5183dfb 507
Kojto 115:87f2f5183dfb 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 115:87f2f5183dfb 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 115:87f2f5183dfb 510
Kojto 115:87f2f5183dfb 511 /*@} end of group CMSIS_SysTick */
Kojto 115:87f2f5183dfb 512
Kojto 115:87f2f5183dfb 513
Kojto 115:87f2f5183dfb 514 /** \ingroup CMSIS_core_register
Kojto 115:87f2f5183dfb 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 115:87f2f5183dfb 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 115:87f2f5183dfb 517 are only accessible over DAP and not via processor. Therefore
Kojto 115:87f2f5183dfb 518 they are not covered by the Cortex-M0 header file.
Kojto 115:87f2f5183dfb 519 @{
Kojto 115:87f2f5183dfb 520 */
Kojto 115:87f2f5183dfb 521 /*@} end of group CMSIS_CoreDebug */
Kojto 115:87f2f5183dfb 522
Kojto 115:87f2f5183dfb 523
Kojto 115:87f2f5183dfb 524 /** \ingroup CMSIS_core_register
Kojto 115:87f2f5183dfb 525 \defgroup CMSIS_core_base Core Definitions
Kojto 115:87f2f5183dfb 526 \brief Definitions for base addresses, unions, and structures.
Kojto 115:87f2f5183dfb 527 @{
Kojto 115:87f2f5183dfb 528 */
Kojto 115:87f2f5183dfb 529
Kojto 115:87f2f5183dfb 530 /* Memory mapping of Cortex-M0 Hardware */
Kojto 115:87f2f5183dfb 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 115:87f2f5183dfb 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 115:87f2f5183dfb 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 115:87f2f5183dfb 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 115:87f2f5183dfb 535
Kojto 115:87f2f5183dfb 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 115:87f2f5183dfb 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 115:87f2f5183dfb 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 115:87f2f5183dfb 539
Kojto 115:87f2f5183dfb 540
Kojto 115:87f2f5183dfb 541 /*@} */
Kojto 115:87f2f5183dfb 542
Kojto 115:87f2f5183dfb 543
Kojto 115:87f2f5183dfb 544
Kojto 115:87f2f5183dfb 545 /*******************************************************************************
Kojto 115:87f2f5183dfb 546 * Hardware Abstraction Layer
Kojto 115:87f2f5183dfb 547 Core Function Interface contains:
Kojto 115:87f2f5183dfb 548 - Core NVIC Functions
Kojto 115:87f2f5183dfb 549 - Core SysTick Functions
Kojto 115:87f2f5183dfb 550 - Core Register Access Functions
Kojto 115:87f2f5183dfb 551 ******************************************************************************/
Kojto 115:87f2f5183dfb 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 115:87f2f5183dfb 553 */
Kojto 115:87f2f5183dfb 554
Kojto 115:87f2f5183dfb 555
Kojto 115:87f2f5183dfb 556
Kojto 115:87f2f5183dfb 557 /* ########################## NVIC functions #################################### */
Kojto 115:87f2f5183dfb 558 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 115:87f2f5183dfb 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 115:87f2f5183dfb 560 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 115:87f2f5183dfb 561 @{
Kojto 115:87f2f5183dfb 562 */
Kojto 115:87f2f5183dfb 563
Kojto 115:87f2f5183dfb 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 115:87f2f5183dfb 565 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 115:87f2f5183dfb 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 115:87f2f5183dfb 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 115:87f2f5183dfb 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 115:87f2f5183dfb 569
Kojto 115:87f2f5183dfb 570
Kojto 115:87f2f5183dfb 571 /** \brief Enable External Interrupt
Kojto 115:87f2f5183dfb 572
Kojto 115:87f2f5183dfb 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 115:87f2f5183dfb 576 */
Kojto 115:87f2f5183dfb 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 115:87f2f5183dfb 578 {
Kojto 115:87f2f5183dfb 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 115:87f2f5183dfb 580 }
Kojto 115:87f2f5183dfb 581
Kojto 115:87f2f5183dfb 582
Kojto 115:87f2f5183dfb 583 /** \brief Disable External Interrupt
Kojto 115:87f2f5183dfb 584
Kojto 115:87f2f5183dfb 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 115:87f2f5183dfb 586
Kojto 115:87f2f5183dfb 587 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 115:87f2f5183dfb 588 */
Kojto 115:87f2f5183dfb 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 115:87f2f5183dfb 590 {
Kojto 115:87f2f5183dfb 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
Kojto 115:87f2f5183dfb 594 }
Kojto 115:87f2f5183dfb 595
Kojto 115:87f2f5183dfb 596
Kojto 115:87f2f5183dfb 597 /** \brief Get Pending Interrupt
Kojto 115:87f2f5183dfb 598
Kojto 115:87f2f5183dfb 599 The function reads the pending register in the NVIC and returns the pending bit
Kojto 115:87f2f5183dfb 600 for the specified interrupt.
Kojto 115:87f2f5183dfb 601
Kojto 115:87f2f5183dfb 602 \param [in] IRQn Interrupt number.
Kojto 115:87f2f5183dfb 603
Kojto 115:87f2f5183dfb 604 \return 0 Interrupt status is not pending.
Kojto 115:87f2f5183dfb 605 \return 1 Interrupt status is pending.
Kojto 115:87f2f5183dfb 606 */
Kojto 115:87f2f5183dfb 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 115:87f2f5183dfb 608 {
Kojto 115:87f2f5183dfb 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612
Kojto 115:87f2f5183dfb 613 /** \brief Set Pending Interrupt
Kojto 115:87f2f5183dfb 614
Kojto 115:87f2f5183dfb 615 The function sets the pending bit of an external interrupt.
Kojto 115:87f2f5183dfb 616
Kojto 115:87f2f5183dfb 617 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 115:87f2f5183dfb 618 */
Kojto 115:87f2f5183dfb 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 115:87f2f5183dfb 620 {
Kojto 115:87f2f5183dfb 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 115:87f2f5183dfb 622 }
Kojto 115:87f2f5183dfb 623
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Clear Pending Interrupt
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 The function clears the pending bit of an external interrupt.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 115:87f2f5183dfb 632 {
Kojto 115:87f2f5183dfb 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 115:87f2f5183dfb 634 }
Kojto 115:87f2f5183dfb 635
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set Interrupt Priority
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 The function sets the priority of an interrupt.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \note The priority cannot be set for every core interrupt.
Kojto 115:87f2f5183dfb 642
Kojto 115:87f2f5183dfb 643 \param [in] IRQn Interrupt number.
Kojto 115:87f2f5183dfb 644 \param [in] priority Priority to set.
Kojto 115:87f2f5183dfb 645 */
Kojto 115:87f2f5183dfb 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 115:87f2f5183dfb 647 {
Kojto 115:87f2f5183dfb 648 if((int32_t)(IRQn) < 0) {
Kojto 115:87f2f5183dfb 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 115:87f2f5183dfb 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 115:87f2f5183dfb 651 }
Kojto 115:87f2f5183dfb 652 else {
Kojto 115:87f2f5183dfb 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 115:87f2f5183dfb 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 115:87f2f5183dfb 655 }
Kojto 115:87f2f5183dfb 656 }
Kojto 115:87f2f5183dfb 657
Kojto 115:87f2f5183dfb 658
Kojto 115:87f2f5183dfb 659 /** \brief Get Interrupt Priority
Kojto 115:87f2f5183dfb 660
Kojto 115:87f2f5183dfb 661 The function reads the priority of an interrupt. The interrupt
Kojto 115:87f2f5183dfb 662 number can be positive to specify an external (device specific)
Kojto 115:87f2f5183dfb 663 interrupt, or negative to specify an internal (core) interrupt.
Kojto 115:87f2f5183dfb 664
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \param [in] IRQn Interrupt number.
Kojto 115:87f2f5183dfb 667 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 115:87f2f5183dfb 668 priority bits of the microcontroller.
Kojto 115:87f2f5183dfb 669 */
Kojto 115:87f2f5183dfb 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 115:87f2f5183dfb 671 {
Kojto 115:87f2f5183dfb 672
Kojto 115:87f2f5183dfb 673 if((int32_t)(IRQn) < 0) {
Kojto 115:87f2f5183dfb 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 115:87f2f5183dfb 675 }
Kojto 115:87f2f5183dfb 676 else {
Kojto 115:87f2f5183dfb 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 115:87f2f5183dfb 678 }
Kojto 115:87f2f5183dfb 679 }
Kojto 115:87f2f5183dfb 680
Kojto 115:87f2f5183dfb 681
Kojto 115:87f2f5183dfb 682 /** \brief System Reset
Kojto 115:87f2f5183dfb 683
Kojto 115:87f2f5183dfb 684 The function initiates a system reset request to reset the MCU.
Kojto 115:87f2f5183dfb 685 */
Kojto 115:87f2f5183dfb 686 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 115:87f2f5183dfb 687 {
Kojto 115:87f2f5183dfb 688 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 115:87f2f5183dfb 689 buffered write are completed before reset */
Kojto 115:87f2f5183dfb 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 115:87f2f5183dfb 691 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 115:87f2f5183dfb 692 __DSB(); /* Ensure completion of memory access */
Kojto 115:87f2f5183dfb 693 while(1) { __NOP(); } /* wait until reset */
Kojto 115:87f2f5183dfb 694 }
Kojto 115:87f2f5183dfb 695
Kojto 115:87f2f5183dfb 696 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 115:87f2f5183dfb 697
Kojto 115:87f2f5183dfb 698
Kojto 115:87f2f5183dfb 699
Kojto 115:87f2f5183dfb 700 /* ################################## SysTick function ############################################ */
Kojto 115:87f2f5183dfb 701 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 115:87f2f5183dfb 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 115:87f2f5183dfb 703 \brief Functions that configure the System.
Kojto 115:87f2f5183dfb 704 @{
Kojto 115:87f2f5183dfb 705 */
Kojto 115:87f2f5183dfb 706
Kojto 115:87f2f5183dfb 707 #if (__Vendor_SysTickConfig == 0)
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 /** \brief System Tick Configuration
Kojto 115:87f2f5183dfb 710
Kojto 115:87f2f5183dfb 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 115:87f2f5183dfb 712 Counter is in free running mode to generate periodic interrupts.
Kojto 115:87f2f5183dfb 713
Kojto 115:87f2f5183dfb 714 \param [in] ticks Number of ticks between two interrupts.
Kojto 115:87f2f5183dfb 715
Kojto 115:87f2f5183dfb 716 \return 0 Function succeeded.
Kojto 115:87f2f5183dfb 717 \return 1 Function failed.
Kojto 115:87f2f5183dfb 718
Kojto 115:87f2f5183dfb 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 115:87f2f5183dfb 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 115:87f2f5183dfb 721 must contain a vendor-specific implementation of this function.
Kojto 115:87f2f5183dfb 722
Kojto 115:87f2f5183dfb 723 */
Kojto 115:87f2f5183dfb 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 115:87f2f5183dfb 725 {
Kojto 115:87f2f5183dfb 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 115:87f2f5183dfb 727
Kojto 115:87f2f5183dfb 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 115:87f2f5183dfb 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 115:87f2f5183dfb 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 115:87f2f5183dfb 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 115:87f2f5183dfb 732 SysTick_CTRL_TICKINT_Msk |
Kojto 115:87f2f5183dfb 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 115:87f2f5183dfb 734 return (0UL); /* Function successful */
Kojto 115:87f2f5183dfb 735 }
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 #endif
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 115:87f2f5183dfb 740
Kojto 115:87f2f5183dfb 741
Kojto 115:87f2f5183dfb 742
Kojto 115:87f2f5183dfb 743
Kojto 115:87f2f5183dfb 744 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 745 }
Kojto 115:87f2f5183dfb 746 #endif
Kojto 115:87f2f5183dfb 747
Kojto 115:87f2f5183dfb 748 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 115:87f2f5183dfb 749
Kojto 115:87f2f5183dfb 750 #endif /* __CMSIS_GENERIC */