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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F746ZG/core_caFunc.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
130:d75b3fe1f5cb 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 115:87f2f5183dfb 1 /**************************************************************************//**
Kojto 115:87f2f5183dfb 2 * @file core_caFunc.h
Kojto 115:87f2f5183dfb 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 115:87f2f5183dfb 4 * @version V3.10
Kojto 115:87f2f5183dfb 5 * @date 30 Oct 2013
Kojto 115:87f2f5183dfb 6 *
Kojto 115:87f2f5183dfb 7 * @note
Kojto 115:87f2f5183dfb 8 *
Kojto 115:87f2f5183dfb 9 ******************************************************************************/
Kojto 115:87f2f5183dfb 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 115:87f2f5183dfb 11
Kojto 115:87f2f5183dfb 12 All rights reserved.
Kojto 115:87f2f5183dfb 13 Redistribution and use in source and binary forms, with or without
Kojto 115:87f2f5183dfb 14 modification, are permitted provided that the following conditions are met:
Kojto 115:87f2f5183dfb 15 - Redistributions of source code must retain the above copyright
Kojto 115:87f2f5183dfb 16 notice, this list of conditions and the following disclaimer.
Kojto 115:87f2f5183dfb 17 - Redistributions in binary form must reproduce the above copyright
Kojto 115:87f2f5183dfb 18 notice, this list of conditions and the following disclaimer in the
Kojto 115:87f2f5183dfb 19 documentation and/or other materials provided with the distribution.
Kojto 115:87f2f5183dfb 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 115:87f2f5183dfb 21 to endorse or promote products derived from this software without
Kojto 115:87f2f5183dfb 22 specific prior written permission.
Kojto 115:87f2f5183dfb 23 *
Kojto 115:87f2f5183dfb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 115:87f2f5183dfb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 115:87f2f5183dfb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 115:87f2f5183dfb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 115:87f2f5183dfb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 115:87f2f5183dfb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 115:87f2f5183dfb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 115:87f2f5183dfb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 115:87f2f5183dfb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 115:87f2f5183dfb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 115:87f2f5183dfb 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 115:87f2f5183dfb 35 ---------------------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 36
Kojto 115:87f2f5183dfb 37
Kojto 115:87f2f5183dfb 38 #ifndef __CORE_CAFUNC_H__
Kojto 115:87f2f5183dfb 39 #define __CORE_CAFUNC_H__
Kojto 115:87f2f5183dfb 40
Kojto 115:87f2f5183dfb 41
Kojto 115:87f2f5183dfb 42 /* ########################### Core Function Access ########################### */
Kojto 115:87f2f5183dfb 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 115:87f2f5183dfb 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 115:87f2f5183dfb 45 @{
Kojto 115:87f2f5183dfb 46 */
Kojto 115:87f2f5183dfb 47
Kojto 115:87f2f5183dfb 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 115:87f2f5183dfb 49 /* ARM armcc specific functions */
Kojto 115:87f2f5183dfb 50
Kojto 115:87f2f5183dfb 51 #if (__ARMCC_VERSION < 400677)
Kojto 115:87f2f5183dfb 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 115:87f2f5183dfb 53 #endif
Kojto 115:87f2f5183dfb 54
Kojto 115:87f2f5183dfb 55 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 56 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 57 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 58 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 59 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 60 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 61 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 62 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 63 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 64
Kojto 115:87f2f5183dfb 65 /** \brief Get APSR Register
Kojto 115:87f2f5183dfb 66
Kojto 115:87f2f5183dfb 67 This function returns the content of the APSR Register.
Kojto 115:87f2f5183dfb 68
Kojto 115:87f2f5183dfb 69 \return APSR Register value
Kojto 115:87f2f5183dfb 70 */
Kojto 115:87f2f5183dfb 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 115:87f2f5183dfb 72 {
Kojto 115:87f2f5183dfb 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 115:87f2f5183dfb 74 return(__regAPSR);
Kojto 115:87f2f5183dfb 75 }
Kojto 115:87f2f5183dfb 76
Kojto 115:87f2f5183dfb 77
Kojto 115:87f2f5183dfb 78 /** \brief Get CPSR Register
Kojto 115:87f2f5183dfb 79
Kojto 115:87f2f5183dfb 80 This function returns the content of the CPSR Register.
Kojto 115:87f2f5183dfb 81
Kojto 115:87f2f5183dfb 82 \return CPSR Register value
Kojto 115:87f2f5183dfb 83 */
Kojto 115:87f2f5183dfb 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 115:87f2f5183dfb 85 {
Kojto 115:87f2f5183dfb 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 115:87f2f5183dfb 87 return(__regCPSR);
Kojto 115:87f2f5183dfb 88 }
Kojto 115:87f2f5183dfb 89
Kojto 115:87f2f5183dfb 90 /** \brief Set Stack Pointer
Kojto 115:87f2f5183dfb 91
Kojto 115:87f2f5183dfb 92 This function assigns the given value to the current stack pointer.
Kojto 115:87f2f5183dfb 93
Kojto 115:87f2f5183dfb 94 \param [in] topOfStack Stack Pointer value to set
Kojto 115:87f2f5183dfb 95 */
Kojto 115:87f2f5183dfb 96 register uint32_t __regSP __ASM("sp");
Kojto 115:87f2f5183dfb 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 115:87f2f5183dfb 98 {
Kojto 115:87f2f5183dfb 99 __regSP = topOfStack;
Kojto 115:87f2f5183dfb 100 }
Kojto 115:87f2f5183dfb 101
Kojto 115:87f2f5183dfb 102
Kojto 115:87f2f5183dfb 103 /** \brief Get link register
Kojto 115:87f2f5183dfb 104
Kojto 115:87f2f5183dfb 105 This function returns the value of the link register
Kojto 115:87f2f5183dfb 106
Kojto 115:87f2f5183dfb 107 \return Value of link register
Kojto 115:87f2f5183dfb 108 */
Kojto 115:87f2f5183dfb 109 register uint32_t __reglr __ASM("lr");
Kojto 115:87f2f5183dfb 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 115:87f2f5183dfb 111 {
Kojto 115:87f2f5183dfb 112 return(__reglr);
Kojto 115:87f2f5183dfb 113 }
Kojto 115:87f2f5183dfb 114
Kojto 115:87f2f5183dfb 115 /** \brief Set link register
Kojto 115:87f2f5183dfb 116
Kojto 115:87f2f5183dfb 117 This function sets the value of the link register
Kojto 115:87f2f5183dfb 118
Kojto 115:87f2f5183dfb 119 \param [in] lr LR value to set
Kojto 115:87f2f5183dfb 120 */
Kojto 115:87f2f5183dfb 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 115:87f2f5183dfb 122 {
Kojto 115:87f2f5183dfb 123 __reglr = lr;
Kojto 115:87f2f5183dfb 124 }
Kojto 115:87f2f5183dfb 125
Kojto 115:87f2f5183dfb 126 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 127
Kojto 115:87f2f5183dfb 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 129
Kojto 115:87f2f5183dfb 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 131 */
Kojto 115:87f2f5183dfb 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 115:87f2f5183dfb 133 {
Kojto 115:87f2f5183dfb 134 ARM
Kojto 115:87f2f5183dfb 135 PRESERVE8
Kojto 115:87f2f5183dfb 136
Kojto 115:87f2f5183dfb 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 115:87f2f5183dfb 138 MRS R1, CPSR
Kojto 115:87f2f5183dfb 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 115:87f2f5183dfb 140 MOV SP, R0
Kojto 115:87f2f5183dfb 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 115:87f2f5183dfb 142 ISB
Kojto 115:87f2f5183dfb 143 BX LR
Kojto 115:87f2f5183dfb 144
Kojto 115:87f2f5183dfb 145 }
Kojto 115:87f2f5183dfb 146
Kojto 115:87f2f5183dfb 147 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 148
Kojto 115:87f2f5183dfb 149 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 150 */
Kojto 115:87f2f5183dfb 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 115:87f2f5183dfb 152 {
Kojto 115:87f2f5183dfb 153 ARM
Kojto 115:87f2f5183dfb 154
Kojto 115:87f2f5183dfb 155 CPS #MODE_USR
Kojto 115:87f2f5183dfb 156 BX LR
Kojto 115:87f2f5183dfb 157 }
Kojto 115:87f2f5183dfb 158
Kojto 115:87f2f5183dfb 159
Kojto 115:87f2f5183dfb 160 /** \brief Enable FIQ
Kojto 115:87f2f5183dfb 161
Kojto 115:87f2f5183dfb 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 115:87f2f5183dfb 163 Can only be executed in Privileged modes.
Kojto 115:87f2f5183dfb 164 */
Kojto 115:87f2f5183dfb 165 #define __enable_fault_irq __enable_fiq
Kojto 115:87f2f5183dfb 166
Kojto 115:87f2f5183dfb 167
Kojto 115:87f2f5183dfb 168 /** \brief Disable FIQ
Kojto 115:87f2f5183dfb 169
Kojto 115:87f2f5183dfb 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 115:87f2f5183dfb 171 Can only be executed in Privileged modes.
Kojto 115:87f2f5183dfb 172 */
Kojto 115:87f2f5183dfb 173 #define __disable_fault_irq __disable_fiq
Kojto 115:87f2f5183dfb 174
Kojto 115:87f2f5183dfb 175
Kojto 115:87f2f5183dfb 176 /** \brief Get FPSCR
Kojto 115:87f2f5183dfb 177
Kojto 115:87f2f5183dfb 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 115:87f2f5183dfb 179
Kojto 115:87f2f5183dfb 180 \return Floating Point Status/Control register value
Kojto 115:87f2f5183dfb 181 */
Kojto 115:87f2f5183dfb 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 115:87f2f5183dfb 183 {
Kojto 115:87f2f5183dfb 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 115:87f2f5183dfb 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 115:87f2f5183dfb 186 return(__regfpscr);
Kojto 115:87f2f5183dfb 187 #else
Kojto 115:87f2f5183dfb 188 return(0);
Kojto 115:87f2f5183dfb 189 #endif
Kojto 115:87f2f5183dfb 190 }
Kojto 115:87f2f5183dfb 191
Kojto 115:87f2f5183dfb 192
Kojto 115:87f2f5183dfb 193 /** \brief Set FPSCR
Kojto 115:87f2f5183dfb 194
Kojto 115:87f2f5183dfb 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 115:87f2f5183dfb 196
Kojto 115:87f2f5183dfb 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 115:87f2f5183dfb 198 */
Kojto 115:87f2f5183dfb 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 115:87f2f5183dfb 200 {
Kojto 115:87f2f5183dfb 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 115:87f2f5183dfb 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 115:87f2f5183dfb 203 __regfpscr = (fpscr);
Kojto 115:87f2f5183dfb 204 #endif
Kojto 115:87f2f5183dfb 205 }
Kojto 115:87f2f5183dfb 206
Kojto 115:87f2f5183dfb 207 /** \brief Get FPEXC
Kojto 115:87f2f5183dfb 208
Kojto 115:87f2f5183dfb 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 115:87f2f5183dfb 210
Kojto 115:87f2f5183dfb 211 \return Floating Point Exception Control register value
Kojto 115:87f2f5183dfb 212 */
Kojto 115:87f2f5183dfb 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 115:87f2f5183dfb 214 {
Kojto 115:87f2f5183dfb 215 #if (__FPU_PRESENT == 1)
Kojto 115:87f2f5183dfb 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 115:87f2f5183dfb 217 return(__regfpexc);
Kojto 115:87f2f5183dfb 218 #else
Kojto 115:87f2f5183dfb 219 return(0);
Kojto 115:87f2f5183dfb 220 #endif
Kojto 115:87f2f5183dfb 221 }
Kojto 115:87f2f5183dfb 222
Kojto 115:87f2f5183dfb 223
Kojto 115:87f2f5183dfb 224 /** \brief Set FPEXC
Kojto 115:87f2f5183dfb 225
Kojto 115:87f2f5183dfb 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 115:87f2f5183dfb 227
Kojto 115:87f2f5183dfb 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 115:87f2f5183dfb 229 */
Kojto 115:87f2f5183dfb 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 115:87f2f5183dfb 231 {
Kojto 115:87f2f5183dfb 232 #if (__FPU_PRESENT == 1)
Kojto 115:87f2f5183dfb 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 115:87f2f5183dfb 234 __regfpexc = (fpexc);
Kojto 115:87f2f5183dfb 235 #endif
Kojto 115:87f2f5183dfb 236 }
Kojto 115:87f2f5183dfb 237
Kojto 115:87f2f5183dfb 238 /** \brief Get CPACR
Kojto 115:87f2f5183dfb 239
Kojto 115:87f2f5183dfb 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 115:87f2f5183dfb 241
Kojto 115:87f2f5183dfb 242 \return Coprocessor Access Control register value
Kojto 115:87f2f5183dfb 243 */
Kojto 115:87f2f5183dfb 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 115:87f2f5183dfb 245 {
Kojto 115:87f2f5183dfb 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 115:87f2f5183dfb 247 return __regCPACR;
Kojto 115:87f2f5183dfb 248 }
Kojto 115:87f2f5183dfb 249
Kojto 115:87f2f5183dfb 250 /** \brief Set CPACR
Kojto 115:87f2f5183dfb 251
Kojto 115:87f2f5183dfb 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 115:87f2f5183dfb 253
Kojto 115:87f2f5183dfb 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 115:87f2f5183dfb 255 */
Kojto 115:87f2f5183dfb 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 115:87f2f5183dfb 257 {
Kojto 115:87f2f5183dfb 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 115:87f2f5183dfb 259 __regCPACR = cpacr;
Kojto 115:87f2f5183dfb 260 __ISB();
Kojto 115:87f2f5183dfb 261 }
Kojto 115:87f2f5183dfb 262
Kojto 115:87f2f5183dfb 263 /** \brief Get CBAR
Kojto 115:87f2f5183dfb 264
Kojto 115:87f2f5183dfb 265 This function returns the value of the Configuration Base Address register.
Kojto 115:87f2f5183dfb 266
Kojto 115:87f2f5183dfb 267 \return Configuration Base Address register value
Kojto 115:87f2f5183dfb 268 */
Kojto 115:87f2f5183dfb 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 115:87f2f5183dfb 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 115:87f2f5183dfb 271 return(__regCBAR);
Kojto 115:87f2f5183dfb 272 }
Kojto 115:87f2f5183dfb 273
Kojto 115:87f2f5183dfb 274 /** \brief Get TTBR0
Kojto 115:87f2f5183dfb 275
Kojto 115:87f2f5183dfb 276 This function returns the value of the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 277
Kojto 115:87f2f5183dfb 278 \return Translation Table Base Register 0 value
Kojto 115:87f2f5183dfb 279 */
Kojto 115:87f2f5183dfb 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 115:87f2f5183dfb 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 115:87f2f5183dfb 282 return(__regTTBR0);
Kojto 115:87f2f5183dfb 283 }
Kojto 115:87f2f5183dfb 284
Kojto 115:87f2f5183dfb 285 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 286
Kojto 115:87f2f5183dfb 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 288
Kojto 115:87f2f5183dfb 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 290 */
Kojto 115:87f2f5183dfb 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 115:87f2f5183dfb 293 __regTTBR0 = ttbr0;
Kojto 115:87f2f5183dfb 294 __ISB();
Kojto 115:87f2f5183dfb 295 }
Kojto 115:87f2f5183dfb 296
Kojto 115:87f2f5183dfb 297 /** \brief Get DACR
Kojto 115:87f2f5183dfb 298
Kojto 115:87f2f5183dfb 299 This function returns the value of the Domain Access Control Register.
Kojto 115:87f2f5183dfb 300
Kojto 115:87f2f5183dfb 301 \return Domain Access Control Register value
Kojto 115:87f2f5183dfb 302 */
Kojto 115:87f2f5183dfb 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 115:87f2f5183dfb 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 115:87f2f5183dfb 305 return(__regDACR);
Kojto 115:87f2f5183dfb 306 }
Kojto 115:87f2f5183dfb 307
Kojto 115:87f2f5183dfb 308 /** \brief Set DACR
Kojto 115:87f2f5183dfb 309
Kojto 115:87f2f5183dfb 310 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 311
Kojto 115:87f2f5183dfb 312 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 313 */
Kojto 115:87f2f5183dfb 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 115:87f2f5183dfb 316 __regDACR = dacr;
Kojto 115:87f2f5183dfb 317 __ISB();
Kojto 115:87f2f5183dfb 318 }
Kojto 115:87f2f5183dfb 319
Kojto 115:87f2f5183dfb 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 321
Kojto 115:87f2f5183dfb 322 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 323
Kojto 115:87f2f5183dfb 324 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 325
Kojto 115:87f2f5183dfb 326 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 327 */
Kojto 115:87f2f5183dfb 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 115:87f2f5183dfb 329 {
Kojto 115:87f2f5183dfb 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 115:87f2f5183dfb 331 __regSCTLR = sctlr;
Kojto 115:87f2f5183dfb 332 }
Kojto 115:87f2f5183dfb 333
Kojto 115:87f2f5183dfb 334 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 335
Kojto 115:87f2f5183dfb 336 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 337
Kojto 115:87f2f5183dfb 338 \return System Control Register value
Kojto 115:87f2f5183dfb 339 */
Kojto 115:87f2f5183dfb 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 115:87f2f5183dfb 342 return(__regSCTLR);
Kojto 115:87f2f5183dfb 343 }
Kojto 115:87f2f5183dfb 344
Kojto 115:87f2f5183dfb 345 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 346
Kojto 115:87f2f5183dfb 347 Enable Caches
Kojto 115:87f2f5183dfb 348 */
Kojto 115:87f2f5183dfb 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 350 // Set I bit 12 to enable I Cache
Kojto 115:87f2f5183dfb 351 // Set C bit 2 to enable D Cache
Kojto 115:87f2f5183dfb 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 353 }
Kojto 115:87f2f5183dfb 354
Kojto 115:87f2f5183dfb 355 /** \brief Disable Caches
Kojto 115:87f2f5183dfb 356
Kojto 115:87f2f5183dfb 357 Disable Caches
Kojto 115:87f2f5183dfb 358 */
Kojto 115:87f2f5183dfb 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 115:87f2f5183dfb 360 // Clear I bit 12 to disable I Cache
Kojto 115:87f2f5183dfb 361 // Clear C bit 2 to disable D Cache
Kojto 115:87f2f5183dfb 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 115:87f2f5183dfb 363 __ISB();
Kojto 115:87f2f5183dfb 364 }
Kojto 115:87f2f5183dfb 365
Kojto 115:87f2f5183dfb 366 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 367
Kojto 115:87f2f5183dfb 368 Enable BTAC
Kojto 115:87f2f5183dfb 369 */
Kojto 115:87f2f5183dfb 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 371 // Set Z bit 11 to enable branch prediction
Kojto 115:87f2f5183dfb 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 373 __ISB();
Kojto 115:87f2f5183dfb 374 }
Kojto 115:87f2f5183dfb 375
Kojto 115:87f2f5183dfb 376 /** \brief Disable BTAC
Kojto 115:87f2f5183dfb 377
Kojto 115:87f2f5183dfb 378 Disable BTAC
Kojto 115:87f2f5183dfb 379 */
Kojto 115:87f2f5183dfb 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 115:87f2f5183dfb 381 // Clear Z bit 11 to disable branch prediction
Kojto 115:87f2f5183dfb 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 115:87f2f5183dfb 383 }
Kojto 115:87f2f5183dfb 384
Kojto 115:87f2f5183dfb 385
Kojto 115:87f2f5183dfb 386 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 387
Kojto 115:87f2f5183dfb 388 Enable MMU
Kojto 115:87f2f5183dfb 389 */
Kojto 115:87f2f5183dfb 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 391 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 392 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 395 __ISB();
Kojto 115:87f2f5183dfb 396 }
Kojto 115:87f2f5183dfb 397
Kojto 115:87f2f5183dfb 398 /** \brief Disable MMU
Kojto 115:87f2f5183dfb 399
Kojto 115:87f2f5183dfb 400 Disable MMU
Kojto 115:87f2f5183dfb 401 */
Kojto 115:87f2f5183dfb 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 115:87f2f5183dfb 403 // Clear M bit 0 to disable the MMU
Kojto 115:87f2f5183dfb 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 115:87f2f5183dfb 405 __ISB();
Kojto 115:87f2f5183dfb 406 }
Kojto 115:87f2f5183dfb 407
Kojto 115:87f2f5183dfb 408 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 409 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 410
Kojto 115:87f2f5183dfb 411 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 412 */
Kojto 115:87f2f5183dfb 413
Kojto 115:87f2f5183dfb 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 115:87f2f5183dfb 416 __TLBIALL = 0;
Kojto 115:87f2f5183dfb 417 __DSB();
Kojto 115:87f2f5183dfb 418 __ISB();
Kojto 115:87f2f5183dfb 419 }
Kojto 115:87f2f5183dfb 420
Kojto 115:87f2f5183dfb 421 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 422 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 423
Kojto 115:87f2f5183dfb 424 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 425 */
Kojto 115:87f2f5183dfb 426
Kojto 115:87f2f5183dfb 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 115:87f2f5183dfb 429 __BPIALL = 0;
Kojto 115:87f2f5183dfb 430 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 432 }
Kojto 115:87f2f5183dfb 433
Kojto 115:87f2f5183dfb 434
Kojto 115:87f2f5183dfb 435 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 436
Kojto 115:87f2f5183dfb 437 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 438
Kojto 115:87f2f5183dfb 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 440 */
Kojto 115:87f2f5183dfb 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 115:87f2f5183dfb 443 __ICIALLU = 0;
Kojto 115:87f2f5183dfb 444 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 446 }
Kojto 115:87f2f5183dfb 447
Kojto 115:87f2f5183dfb 448 /** \brief Clean D$ by MVA
Kojto 115:87f2f5183dfb 449
Kojto 115:87f2f5183dfb 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 115:87f2f5183dfb 451 */
Kojto 115:87f2f5183dfb 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 115:87f2f5183dfb 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 115:87f2f5183dfb 454 __DCCMVAC = (uint32_t)va;
Kojto 115:87f2f5183dfb 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 115:87f2f5183dfb 456 }
Kojto 115:87f2f5183dfb 457
Kojto 115:87f2f5183dfb 458 /** \brief Invalidate D$ by MVA
Kojto 115:87f2f5183dfb 459
Kojto 115:87f2f5183dfb 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 115:87f2f5183dfb 461 */
Kojto 115:87f2f5183dfb 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 115:87f2f5183dfb 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 115:87f2f5183dfb 464 __DCIMVAC = (uint32_t)va;
Kojto 115:87f2f5183dfb 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 115:87f2f5183dfb 466 }
Kojto 115:87f2f5183dfb 467
Kojto 115:87f2f5183dfb 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 115:87f2f5183dfb 469
Kojto 115:87f2f5183dfb 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 115:87f2f5183dfb 471 */
Kojto 115:87f2f5183dfb 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 115:87f2f5183dfb 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 115:87f2f5183dfb 474 __DCCIMVAC = (uint32_t)va;
Kojto 115:87f2f5183dfb 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 115:87f2f5183dfb 476 }
Kojto 115:87f2f5183dfb 477
Kojto 115:87f2f5183dfb 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 115:87f2f5183dfb 479
Kojto 115:87f2f5183dfb 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 115:87f2f5183dfb 481 */
Kojto 115:87f2f5183dfb 482 #pragma push
Kojto 115:87f2f5183dfb 483 #pragma arm
Kojto 115:87f2f5183dfb 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 485 ARM
Kojto 115:87f2f5183dfb 486
Kojto 115:87f2f5183dfb 487 PUSH {R4-R11}
Kojto 115:87f2f5183dfb 488
Kojto 115:87f2f5183dfb 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 115:87f2f5183dfb 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 115:87f2f5183dfb 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 115:87f2f5183dfb 492 BEQ Finished // If 0, no need to clean
Kojto 115:87f2f5183dfb 493
Kojto 115:87f2f5183dfb 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 498 CMP R1, #2
Kojto 115:87f2f5183dfb 499 BLT Skip // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 500
Kojto 115:87f2f5183dfb 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 504 AND R2, R1, #7 // Extract the line length field
Kojto 115:87f2f5183dfb 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 506 LDR R4, =0x3FF
Kojto 115:87f2f5183dfb 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 509 LDR R7, =0x7FFF
Kojto 115:87f2f5183dfb 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 511
Kojto 115:87f2f5183dfb 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 513
Kojto 115:87f2f5183dfb 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 115:87f2f5183dfb 516 CMP R0, #0
Kojto 115:87f2f5183dfb 517 BNE Dccsw
Kojto 115:87f2f5183dfb 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 519 B cont
Kojto 115:87f2f5183dfb 520 Dccsw CMP R0, #1
Kojto 115:87f2f5183dfb 521 BNE Dccisw
Kojto 115:87f2f5183dfb 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 523 B cont
Kojto 115:87f2f5183dfb 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 115:87f2f5183dfb 526 BGE Loop3
Kojto 115:87f2f5183dfb 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 115:87f2f5183dfb 528 BGE Loop2
Kojto 115:87f2f5183dfb 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 115:87f2f5183dfb 530 CMP R3, R10
Kojto 115:87f2f5183dfb 531 BGT Loop1
Kojto 115:87f2f5183dfb 532
Kojto 115:87f2f5183dfb 533 Finished
Kojto 115:87f2f5183dfb 534 DSB
Kojto 115:87f2f5183dfb 535 POP {R4-R11}
Kojto 115:87f2f5183dfb 536 BX lr
Kojto 115:87f2f5183dfb 537
Kojto 115:87f2f5183dfb 538 }
Kojto 115:87f2f5183dfb 539 #pragma pop
Kojto 115:87f2f5183dfb 540
Kojto 115:87f2f5183dfb 541
Kojto 115:87f2f5183dfb 542 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 543
Kojto 115:87f2f5183dfb 544 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 545 */
Kojto 115:87f2f5183dfb 546
Kojto 115:87f2f5183dfb 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 548 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 549 }
Kojto 115:87f2f5183dfb 550
Kojto 115:87f2f5183dfb 551 /** \brief Clean the whole D$
Kojto 115:87f2f5183dfb 552
Kojto 115:87f2f5183dfb 553 DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 554 */
Kojto 115:87f2f5183dfb 555
Kojto 115:87f2f5183dfb 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 115:87f2f5183dfb 557 __v7_all_cache(1);
Kojto 115:87f2f5183dfb 558 }
Kojto 115:87f2f5183dfb 559
Kojto 115:87f2f5183dfb 560 /** \brief Clean and invalidate the whole D$
Kojto 115:87f2f5183dfb 561
Kojto 115:87f2f5183dfb 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 563 */
Kojto 115:87f2f5183dfb 564
Kojto 115:87f2f5183dfb 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 566 __v7_all_cache(2);
Kojto 115:87f2f5183dfb 567 }
Kojto 115:87f2f5183dfb 568
Kojto 115:87f2f5183dfb 569 #include "core_ca_mmu.h"
Kojto 115:87f2f5183dfb 570
Kojto 115:87f2f5183dfb 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 115:87f2f5183dfb 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
<> 130:d75b3fe1f5cb 814 /** \brief Clean the whole D$
<> 130:d75b3fe1f5cb 815
<> 130:d75b3fe1f5cb 816 DCCSW. Clean by Set/Way
<> 130:d75b3fe1f5cb 817 */
<> 130:d75b3fe1f5cb 818
<> 130:d75b3fe1f5cb 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 130:d75b3fe1f5cb 820 __v7_all_cache(1);
<> 130:d75b3fe1f5cb 821 }
<> 130:d75b3fe1f5cb 822
<> 130:d75b3fe1f5cb 823 /** \brief Clean and invalidate the whole D$
<> 130:d75b3fe1f5cb 824
<> 130:d75b3fe1f5cb 825 DCCISW. Clean and Invalidate by Set/Way
<> 130:d75b3fe1f5cb 826 */
<> 130:d75b3fe1f5cb 827
<> 130:d75b3fe1f5cb 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 130:d75b3fe1f5cb 829 __v7_all_cache(2);
<> 130:d75b3fe1f5cb 830 }
Kojto 121:6c34061e7c34 831 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 832
Kojto 121:6c34061e7c34 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 834 */
Kojto 121:6c34061e7c34 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 837 __DMB();
Kojto 121:6c34061e7c34 838 }
Kojto 121:6c34061e7c34 839
Kojto 115:87f2f5183dfb 840 #include "core_ca_mmu.h"
Kojto 115:87f2f5183dfb 841
Kojto 115:87f2f5183dfb 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 115:87f2f5183dfb 843 /* GNU gcc specific functions */
Kojto 115:87f2f5183dfb 844
Kojto 115:87f2f5183dfb 845 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 846 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 847 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 848 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 849 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 850 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 851 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 852 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 853 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 854
Kojto 115:87f2f5183dfb 855
Kojto 115:87f2f5183dfb 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 115:87f2f5183dfb 857 {
Kojto 115:87f2f5183dfb 858 __ASM volatile ("cpsie i");
Kojto 115:87f2f5183dfb 859 }
Kojto 115:87f2f5183dfb 860
Kojto 115:87f2f5183dfb 861 /** \brief Disable IRQ Interrupts
Kojto 115:87f2f5183dfb 862
Kojto 115:87f2f5183dfb 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 115:87f2f5183dfb 864 Can only be executed in Privileged modes.
Kojto 115:87f2f5183dfb 865 */
Kojto 115:87f2f5183dfb 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 115:87f2f5183dfb 867 {
Kojto 115:87f2f5183dfb 868 uint32_t result;
Kojto 115:87f2f5183dfb 869
Kojto 115:87f2f5183dfb 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 115:87f2f5183dfb 871 __ASM volatile ("cpsid i");
Kojto 115:87f2f5183dfb 872 return(result & 0x80);
Kojto 115:87f2f5183dfb 873 }
Kojto 115:87f2f5183dfb 874
Kojto 115:87f2f5183dfb 875
Kojto 115:87f2f5183dfb 876 /** \brief Get APSR Register
Kojto 115:87f2f5183dfb 877
Kojto 115:87f2f5183dfb 878 This function returns the content of the APSR Register.
Kojto 115:87f2f5183dfb 879
Kojto 115:87f2f5183dfb 880 \return APSR Register value
Kojto 115:87f2f5183dfb 881 */
Kojto 115:87f2f5183dfb 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 115:87f2f5183dfb 883 {
Kojto 115:87f2f5183dfb 884 #if 1
Kojto 115:87f2f5183dfb 885 register uint32_t __regAPSR;
Kojto 115:87f2f5183dfb 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 115:87f2f5183dfb 887 #else
Kojto 115:87f2f5183dfb 888 register uint32_t __regAPSR __ASM("apsr");
Kojto 115:87f2f5183dfb 889 #endif
Kojto 115:87f2f5183dfb 890 return(__regAPSR);
Kojto 115:87f2f5183dfb 891 }
Kojto 115:87f2f5183dfb 892
Kojto 115:87f2f5183dfb 893
Kojto 115:87f2f5183dfb 894 /** \brief Get CPSR Register
Kojto 115:87f2f5183dfb 895
Kojto 115:87f2f5183dfb 896 This function returns the content of the CPSR Register.
Kojto 115:87f2f5183dfb 897
Kojto 115:87f2f5183dfb 898 \return CPSR Register value
Kojto 115:87f2f5183dfb 899 */
Kojto 115:87f2f5183dfb 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 115:87f2f5183dfb 901 {
Kojto 115:87f2f5183dfb 902 #if 1
Kojto 115:87f2f5183dfb 903 register uint32_t __regCPSR;
Kojto 115:87f2f5183dfb 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 115:87f2f5183dfb 905 #else
Kojto 115:87f2f5183dfb 906 register uint32_t __regCPSR __ASM("cpsr");
Kojto 115:87f2f5183dfb 907 #endif
Kojto 115:87f2f5183dfb 908 return(__regCPSR);
Kojto 115:87f2f5183dfb 909 }
Kojto 115:87f2f5183dfb 910
Kojto 115:87f2f5183dfb 911 #if 0
Kojto 115:87f2f5183dfb 912 /** \brief Set Stack Pointer
Kojto 115:87f2f5183dfb 913
Kojto 115:87f2f5183dfb 914 This function assigns the given value to the current stack pointer.
Kojto 115:87f2f5183dfb 915
Kojto 115:87f2f5183dfb 916 \param [in] topOfStack Stack Pointer value to set
Kojto 115:87f2f5183dfb 917 */
Kojto 115:87f2f5183dfb 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 115:87f2f5183dfb 919 {
Kojto 115:87f2f5183dfb 920 register uint32_t __regSP __ASM("sp");
Kojto 115:87f2f5183dfb 921 __regSP = topOfStack;
Kojto 115:87f2f5183dfb 922 }
Kojto 115:87f2f5183dfb 923 #endif
Kojto 115:87f2f5183dfb 924
Kojto 115:87f2f5183dfb 925 /** \brief Get link register
Kojto 115:87f2f5183dfb 926
Kojto 115:87f2f5183dfb 927 This function returns the value of the link register
Kojto 115:87f2f5183dfb 928
Kojto 115:87f2f5183dfb 929 \return Value of link register
Kojto 115:87f2f5183dfb 930 */
Kojto 115:87f2f5183dfb 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 115:87f2f5183dfb 932 {
Kojto 115:87f2f5183dfb 933 register uint32_t __reglr __ASM("lr");
Kojto 115:87f2f5183dfb 934 return(__reglr);
Kojto 115:87f2f5183dfb 935 }
Kojto 115:87f2f5183dfb 936
Kojto 115:87f2f5183dfb 937 #if 0
Kojto 115:87f2f5183dfb 938 /** \brief Set link register
Kojto 115:87f2f5183dfb 939
Kojto 115:87f2f5183dfb 940 This function sets the value of the link register
Kojto 115:87f2f5183dfb 941
Kojto 115:87f2f5183dfb 942 \param [in] lr LR value to set
Kojto 115:87f2f5183dfb 943 */
Kojto 115:87f2f5183dfb 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 115:87f2f5183dfb 945 {
Kojto 115:87f2f5183dfb 946 register uint32_t __reglr __ASM("lr");
Kojto 115:87f2f5183dfb 947 __reglr = lr;
Kojto 115:87f2f5183dfb 948 }
Kojto 115:87f2f5183dfb 949 #endif
Kojto 115:87f2f5183dfb 950
Kojto 115:87f2f5183dfb 951 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 952
Kojto 115:87f2f5183dfb 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 954
Kojto 115:87f2f5183dfb 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 956 */
Kojto 115:87f2f5183dfb 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 115:87f2f5183dfb 958 {
Kojto 115:87f2f5183dfb 959 __asm__ volatile (
Kojto 115:87f2f5183dfb 960 ".ARM;"
Kojto 115:87f2f5183dfb 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 115:87f2f5183dfb 962
Kojto 115:87f2f5183dfb 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 115:87f2f5183dfb 964 "MRS R1, CPSR;"
Kojto 115:87f2f5183dfb 965 "CPS %0;" /* ;no effect in USR mode */
Kojto 115:87f2f5183dfb 966 "MOV SP, R0;"
Kojto 115:87f2f5183dfb 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 115:87f2f5183dfb 968 "ISB;"
Kojto 115:87f2f5183dfb 969 //"BX LR;"
Kojto 115:87f2f5183dfb 970 :
Kojto 115:87f2f5183dfb 971 : "i"(MODE_SYS)
Kojto 115:87f2f5183dfb 972 : "r0", "r1");
Kojto 115:87f2f5183dfb 973 return;
Kojto 115:87f2f5183dfb 974 }
Kojto 115:87f2f5183dfb 975
Kojto 115:87f2f5183dfb 976 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 977
Kojto 115:87f2f5183dfb 978 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 979 */
Kojto 115:87f2f5183dfb 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 115:87f2f5183dfb 981 {
Kojto 115:87f2f5183dfb 982 __asm__ volatile (
Kojto 115:87f2f5183dfb 983 ".ARM;"
Kojto 115:87f2f5183dfb 984
Kojto 115:87f2f5183dfb 985 "CPS %0;"
Kojto 115:87f2f5183dfb 986 //"BX LR;"
Kojto 115:87f2f5183dfb 987 :
Kojto 115:87f2f5183dfb 988 : "i"(MODE_USR)
Kojto 115:87f2f5183dfb 989 : );
Kojto 115:87f2f5183dfb 990 return;
Kojto 115:87f2f5183dfb 991 }
Kojto 115:87f2f5183dfb 992
Kojto 115:87f2f5183dfb 993
Kojto 115:87f2f5183dfb 994 /** \brief Enable FIQ
Kojto 115:87f2f5183dfb 995
Kojto 115:87f2f5183dfb 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 115:87f2f5183dfb 997 Can only be executed in Privileged modes.
Kojto 115:87f2f5183dfb 998 */
Kojto 115:87f2f5183dfb 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 115:87f2f5183dfb 1000
Kojto 115:87f2f5183dfb 1001
Kojto 115:87f2f5183dfb 1002 /** \brief Disable FIQ
Kojto 115:87f2f5183dfb 1003
Kojto 115:87f2f5183dfb 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 115:87f2f5183dfb 1005 Can only be executed in Privileged modes.
Kojto 115:87f2f5183dfb 1006 */
Kojto 115:87f2f5183dfb 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 115:87f2f5183dfb 1008
Kojto 115:87f2f5183dfb 1009
Kojto 115:87f2f5183dfb 1010 /** \brief Get FPSCR
Kojto 115:87f2f5183dfb 1011
Kojto 115:87f2f5183dfb 1012 This function returns the current value of the Floating Point Status/Control register.
Kojto 115:87f2f5183dfb 1013
Kojto 115:87f2f5183dfb 1014 \return Floating Point Status/Control register value
Kojto 115:87f2f5183dfb 1015 */
Kojto 115:87f2f5183dfb 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 115:87f2f5183dfb 1017 {
Kojto 115:87f2f5183dfb 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 115:87f2f5183dfb 1019 #if 1
Kojto 115:87f2f5183dfb 1020 uint32_t result;
Kojto 115:87f2f5183dfb 1021
Kojto 115:87f2f5183dfb 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 115:87f2f5183dfb 1023 return (result);
Kojto 115:87f2f5183dfb 1024 #else
Kojto 115:87f2f5183dfb 1025 register uint32_t __regfpscr __ASM("fpscr");
Kojto 115:87f2f5183dfb 1026 return(__regfpscr);
Kojto 115:87f2f5183dfb 1027 #endif
Kojto 115:87f2f5183dfb 1028 #else
Kojto 115:87f2f5183dfb 1029 return(0);
Kojto 115:87f2f5183dfb 1030 #endif
Kojto 115:87f2f5183dfb 1031 }
Kojto 115:87f2f5183dfb 1032
Kojto 115:87f2f5183dfb 1033
Kojto 115:87f2f5183dfb 1034 /** \brief Set FPSCR
Kojto 115:87f2f5183dfb 1035
Kojto 115:87f2f5183dfb 1036 This function assigns the given value to the Floating Point Status/Control register.
Kojto 115:87f2f5183dfb 1037
Kojto 115:87f2f5183dfb 1038 \param [in] fpscr Floating Point Status/Control value to set
Kojto 115:87f2f5183dfb 1039 */
Kojto 115:87f2f5183dfb 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 115:87f2f5183dfb 1041 {
Kojto 115:87f2f5183dfb 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 115:87f2f5183dfb 1043 #if 1
Kojto 115:87f2f5183dfb 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 115:87f2f5183dfb 1045 #else
Kojto 115:87f2f5183dfb 1046 register uint32_t __regfpscr __ASM("fpscr");
Kojto 115:87f2f5183dfb 1047 __regfpscr = (fpscr);
Kojto 115:87f2f5183dfb 1048 #endif
Kojto 115:87f2f5183dfb 1049 #endif
Kojto 115:87f2f5183dfb 1050 }
Kojto 115:87f2f5183dfb 1051
Kojto 115:87f2f5183dfb 1052 /** \brief Get FPEXC
Kojto 115:87f2f5183dfb 1053
Kojto 115:87f2f5183dfb 1054 This function returns the current value of the Floating Point Exception Control register.
Kojto 115:87f2f5183dfb 1055
Kojto 115:87f2f5183dfb 1056 \return Floating Point Exception Control register value
Kojto 115:87f2f5183dfb 1057 */
Kojto 115:87f2f5183dfb 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 115:87f2f5183dfb 1059 {
Kojto 115:87f2f5183dfb 1060 #if (__FPU_PRESENT == 1)
Kojto 115:87f2f5183dfb 1061 #if 1
Kojto 115:87f2f5183dfb 1062 uint32_t result;
Kojto 115:87f2f5183dfb 1063
Kojto 115:87f2f5183dfb 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 115:87f2f5183dfb 1065 return (result);
Kojto 115:87f2f5183dfb 1066 #else
Kojto 115:87f2f5183dfb 1067 register uint32_t __regfpexc __ASM("fpexc");
Kojto 115:87f2f5183dfb 1068 return(__regfpexc);
Kojto 115:87f2f5183dfb 1069 #endif
Kojto 115:87f2f5183dfb 1070 #else
Kojto 115:87f2f5183dfb 1071 return(0);
Kojto 115:87f2f5183dfb 1072 #endif
Kojto 115:87f2f5183dfb 1073 }
Kojto 115:87f2f5183dfb 1074
Kojto 115:87f2f5183dfb 1075
Kojto 115:87f2f5183dfb 1076 /** \brief Set FPEXC
Kojto 115:87f2f5183dfb 1077
Kojto 115:87f2f5183dfb 1078 This function assigns the given value to the Floating Point Exception Control register.
Kojto 115:87f2f5183dfb 1079
Kojto 115:87f2f5183dfb 1080 \param [in] fpscr Floating Point Exception Control value to set
Kojto 115:87f2f5183dfb 1081 */
Kojto 115:87f2f5183dfb 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 115:87f2f5183dfb 1083 {
Kojto 115:87f2f5183dfb 1084 #if (__FPU_PRESENT == 1)
Kojto 115:87f2f5183dfb 1085 #if 1
Kojto 115:87f2f5183dfb 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 115:87f2f5183dfb 1087 #else
Kojto 115:87f2f5183dfb 1088 register uint32_t __regfpexc __ASM("fpexc");
Kojto 115:87f2f5183dfb 1089 __regfpexc = (fpexc);
Kojto 115:87f2f5183dfb 1090 #endif
Kojto 115:87f2f5183dfb 1091 #endif
Kojto 115:87f2f5183dfb 1092 }
Kojto 115:87f2f5183dfb 1093
Kojto 115:87f2f5183dfb 1094 /** \brief Get CPACR
Kojto 115:87f2f5183dfb 1095
Kojto 115:87f2f5183dfb 1096 This function returns the current value of the Coprocessor Access Control register.
Kojto 115:87f2f5183dfb 1097
Kojto 115:87f2f5183dfb 1098 \return Coprocessor Access Control register value
Kojto 115:87f2f5183dfb 1099 */
Kojto 115:87f2f5183dfb 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 115:87f2f5183dfb 1101 {
Kojto 115:87f2f5183dfb 1102 #if 1
Kojto 115:87f2f5183dfb 1103 register uint32_t __regCPACR;
Kojto 115:87f2f5183dfb 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 115:87f2f5183dfb 1105 #else
Kojto 115:87f2f5183dfb 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 115:87f2f5183dfb 1107 #endif
Kojto 115:87f2f5183dfb 1108 return __regCPACR;
Kojto 115:87f2f5183dfb 1109 }
Kojto 115:87f2f5183dfb 1110
Kojto 115:87f2f5183dfb 1111 /** \brief Set CPACR
Kojto 115:87f2f5183dfb 1112
Kojto 115:87f2f5183dfb 1113 This function assigns the given value to the Coprocessor Access Control register.
Kojto 115:87f2f5183dfb 1114
Kojto 115:87f2f5183dfb 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 115:87f2f5183dfb 1116 */
Kojto 115:87f2f5183dfb 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 115:87f2f5183dfb 1118 {
Kojto 115:87f2f5183dfb 1119 #if 1
Kojto 115:87f2f5183dfb 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 115:87f2f5183dfb 1121 #else
Kojto 115:87f2f5183dfb 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 115:87f2f5183dfb 1123 __regCPACR = cpacr;
Kojto 115:87f2f5183dfb 1124 #endif
Kojto 115:87f2f5183dfb 1125 __ISB();
Kojto 115:87f2f5183dfb 1126 }
Kojto 115:87f2f5183dfb 1127
Kojto 115:87f2f5183dfb 1128 /** \brief Get CBAR
Kojto 115:87f2f5183dfb 1129
Kojto 115:87f2f5183dfb 1130 This function returns the value of the Configuration Base Address register.
Kojto 115:87f2f5183dfb 1131
Kojto 115:87f2f5183dfb 1132 \return Configuration Base Address register value
Kojto 115:87f2f5183dfb 1133 */
Kojto 115:87f2f5183dfb 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 115:87f2f5183dfb 1135 #if 1
Kojto 115:87f2f5183dfb 1136 register uint32_t __regCBAR;
Kojto 115:87f2f5183dfb 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 115:87f2f5183dfb 1138 #else
Kojto 115:87f2f5183dfb 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 115:87f2f5183dfb 1140 #endif
Kojto 115:87f2f5183dfb 1141 return(__regCBAR);
Kojto 115:87f2f5183dfb 1142 }
Kojto 115:87f2f5183dfb 1143
Kojto 115:87f2f5183dfb 1144 /** \brief Get TTBR0
Kojto 115:87f2f5183dfb 1145
Kojto 115:87f2f5183dfb 1146 This function returns the value of the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 1147
Kojto 115:87f2f5183dfb 1148 \return Translation Table Base Register 0 value
Kojto 115:87f2f5183dfb 1149 */
Kojto 115:87f2f5183dfb 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 115:87f2f5183dfb 1151 #if 1
Kojto 115:87f2f5183dfb 1152 register uint32_t __regTTBR0;
Kojto 115:87f2f5183dfb 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 115:87f2f5183dfb 1154 #else
Kojto 115:87f2f5183dfb 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 115:87f2f5183dfb 1156 #endif
Kojto 115:87f2f5183dfb 1157 return(__regTTBR0);
Kojto 115:87f2f5183dfb 1158 }
Kojto 115:87f2f5183dfb 1159
Kojto 115:87f2f5183dfb 1160 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 1161
Kojto 115:87f2f5183dfb 1162 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 1163
Kojto 115:87f2f5183dfb 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 1165 */
Kojto 115:87f2f5183dfb 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 1167 #if 1
Kojto 115:87f2f5183dfb 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 115:87f2f5183dfb 1169 #else
Kojto 115:87f2f5183dfb 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 115:87f2f5183dfb 1171 __regTTBR0 = ttbr0;
Kojto 115:87f2f5183dfb 1172 #endif
Kojto 115:87f2f5183dfb 1173 __ISB();
Kojto 115:87f2f5183dfb 1174 }
Kojto 115:87f2f5183dfb 1175
Kojto 115:87f2f5183dfb 1176 /** \brief Get DACR
Kojto 115:87f2f5183dfb 1177
Kojto 115:87f2f5183dfb 1178 This function returns the value of the Domain Access Control Register.
Kojto 115:87f2f5183dfb 1179
Kojto 115:87f2f5183dfb 1180 \return Domain Access Control Register value
Kojto 115:87f2f5183dfb 1181 */
Kojto 115:87f2f5183dfb 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 115:87f2f5183dfb 1183 #if 1
Kojto 115:87f2f5183dfb 1184 register uint32_t __regDACR;
Kojto 115:87f2f5183dfb 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 115:87f2f5183dfb 1186 #else
Kojto 115:87f2f5183dfb 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 115:87f2f5183dfb 1188 #endif
Kojto 115:87f2f5183dfb 1189 return(__regDACR);
Kojto 115:87f2f5183dfb 1190 }
Kojto 115:87f2f5183dfb 1191
Kojto 115:87f2f5183dfb 1192 /** \brief Set DACR
Kojto 115:87f2f5183dfb 1193
Kojto 115:87f2f5183dfb 1194 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 1195
Kojto 115:87f2f5183dfb 1196 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 1197 */
Kojto 115:87f2f5183dfb 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 1199 #if 1
Kojto 115:87f2f5183dfb 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 115:87f2f5183dfb 1201 #else
Kojto 115:87f2f5183dfb 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 115:87f2f5183dfb 1203 __regDACR = dacr;
Kojto 115:87f2f5183dfb 1204 #endif
Kojto 115:87f2f5183dfb 1205 __ISB();
Kojto 115:87f2f5183dfb 1206 }
Kojto 115:87f2f5183dfb 1207
Kojto 115:87f2f5183dfb 1208 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 1209
Kojto 115:87f2f5183dfb 1210 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 1211
Kojto 115:87f2f5183dfb 1212 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 1213
Kojto 115:87f2f5183dfb 1214 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 1215 */
Kojto 115:87f2f5183dfb 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 115:87f2f5183dfb 1217 {
Kojto 115:87f2f5183dfb 1218 #if 1
Kojto 115:87f2f5183dfb 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 115:87f2f5183dfb 1220 #else
Kojto 115:87f2f5183dfb 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 115:87f2f5183dfb 1222 __regSCTLR = sctlr;
Kojto 115:87f2f5183dfb 1223 #endif
Kojto 115:87f2f5183dfb 1224 }
Kojto 115:87f2f5183dfb 1225
Kojto 115:87f2f5183dfb 1226 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 1227
Kojto 115:87f2f5183dfb 1228 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 1229
Kojto 115:87f2f5183dfb 1230 \return System Control Register value
Kojto 115:87f2f5183dfb 1231 */
Kojto 115:87f2f5183dfb 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 1233 #if 1
Kojto 115:87f2f5183dfb 1234 register uint32_t __regSCTLR;
Kojto 115:87f2f5183dfb 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 115:87f2f5183dfb 1236 #else
Kojto 115:87f2f5183dfb 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 115:87f2f5183dfb 1238 #endif
Kojto 115:87f2f5183dfb 1239 return(__regSCTLR);
Kojto 115:87f2f5183dfb 1240 }
Kojto 115:87f2f5183dfb 1241
Kojto 115:87f2f5183dfb 1242 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 1243
Kojto 115:87f2f5183dfb 1244 Enable Caches
Kojto 115:87f2f5183dfb 1245 */
Kojto 115:87f2f5183dfb 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 1247 // Set I bit 12 to enable I Cache
Kojto 115:87f2f5183dfb 1248 // Set C bit 2 to enable D Cache
Kojto 115:87f2f5183dfb 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 1250 }
Kojto 115:87f2f5183dfb 1251
Kojto 115:87f2f5183dfb 1252 /** \brief Disable Caches
Kojto 115:87f2f5183dfb 1253
Kojto 115:87f2f5183dfb 1254 Disable Caches
Kojto 115:87f2f5183dfb 1255 */
Kojto 115:87f2f5183dfb 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 115:87f2f5183dfb 1257 // Clear I bit 12 to disable I Cache
Kojto 115:87f2f5183dfb 1258 // Clear C bit 2 to disable D Cache
Kojto 115:87f2f5183dfb 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 115:87f2f5183dfb 1260 __ISB();
Kojto 115:87f2f5183dfb 1261 }
Kojto 115:87f2f5183dfb 1262
Kojto 115:87f2f5183dfb 1263 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 1264
Kojto 115:87f2f5183dfb 1265 Enable BTAC
Kojto 115:87f2f5183dfb 1266 */
Kojto 115:87f2f5183dfb 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 1268 // Set Z bit 11 to enable branch prediction
Kojto 115:87f2f5183dfb 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 1270 __ISB();
Kojto 115:87f2f5183dfb 1271 }
Kojto 115:87f2f5183dfb 1272
Kojto 115:87f2f5183dfb 1273 /** \brief Disable BTAC
Kojto 115:87f2f5183dfb 1274
Kojto 115:87f2f5183dfb 1275 Disable BTAC
Kojto 115:87f2f5183dfb 1276 */
Kojto 115:87f2f5183dfb 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 115:87f2f5183dfb 1278 // Clear Z bit 11 to disable branch prediction
Kojto 115:87f2f5183dfb 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 115:87f2f5183dfb 1280 }
Kojto 115:87f2f5183dfb 1281
Kojto 115:87f2f5183dfb 1282
Kojto 115:87f2f5183dfb 1283 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 1284
Kojto 115:87f2f5183dfb 1285 Enable MMU
Kojto 115:87f2f5183dfb 1286 */
Kojto 115:87f2f5183dfb 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 1288 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 1289 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 1292 __ISB();
Kojto 115:87f2f5183dfb 1293 }
Kojto 115:87f2f5183dfb 1294
Kojto 115:87f2f5183dfb 1295 /** \brief Disable MMU
Kojto 115:87f2f5183dfb 1296
Kojto 115:87f2f5183dfb 1297 Disable MMU
Kojto 115:87f2f5183dfb 1298 */
Kojto 115:87f2f5183dfb 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 115:87f2f5183dfb 1300 // Clear M bit 0 to disable the MMU
Kojto 115:87f2f5183dfb 1301 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 115:87f2f5183dfb 1302 __ISB();
Kojto 115:87f2f5183dfb 1303 }
Kojto 115:87f2f5183dfb 1304
Kojto 115:87f2f5183dfb 1305 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 1306 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 1307
Kojto 115:87f2f5183dfb 1308 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 1309 */
Kojto 115:87f2f5183dfb 1310
Kojto 115:87f2f5183dfb 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 1312 #if 1
Kojto 115:87f2f5183dfb 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 115:87f2f5183dfb 1314 #else
Kojto 115:87f2f5183dfb 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 115:87f2f5183dfb 1316 __TLBIALL = 0;
Kojto 115:87f2f5183dfb 1317 #endif
Kojto 115:87f2f5183dfb 1318 __DSB();
Kojto 115:87f2f5183dfb 1319 __ISB();
Kojto 115:87f2f5183dfb 1320 }
Kojto 115:87f2f5183dfb 1321
Kojto 115:87f2f5183dfb 1322 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 1323 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 1324
Kojto 115:87f2f5183dfb 1325 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 1326 */
Kojto 115:87f2f5183dfb 1327
Kojto 115:87f2f5183dfb 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 1329 #if 1
Kojto 115:87f2f5183dfb 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 115:87f2f5183dfb 1331 #else
Kojto 115:87f2f5183dfb 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 115:87f2f5183dfb 1333 __BPIALL = 0;
Kojto 115:87f2f5183dfb 1334 #endif
Kojto 115:87f2f5183dfb 1335 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 1336 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 1337 }
Kojto 115:87f2f5183dfb 1338
Kojto 115:87f2f5183dfb 1339
Kojto 115:87f2f5183dfb 1340 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 1341
Kojto 115:87f2f5183dfb 1342 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 1343
Kojto 115:87f2f5183dfb 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 1345 */
Kojto 115:87f2f5183dfb 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 1347 #if 1
Kojto 115:87f2f5183dfb 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 115:87f2f5183dfb 1349 #else
Kojto 115:87f2f5183dfb 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 115:87f2f5183dfb 1351 __ICIALLU = 0;
Kojto 115:87f2f5183dfb 1352 #endif
Kojto 115:87f2f5183dfb 1353 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 1355 }
Kojto 115:87f2f5183dfb 1356
Kojto 115:87f2f5183dfb 1357 /** \brief Clean D$ by MVA
Kojto 115:87f2f5183dfb 1358
Kojto 115:87f2f5183dfb 1359 DCCMVAC. Data cache clean by MVA to PoC
Kojto 115:87f2f5183dfb 1360 */
Kojto 115:87f2f5183dfb 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 115:87f2f5183dfb 1362 #if 1
Kojto 115:87f2f5183dfb 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 115:87f2f5183dfb 1364 #else
Kojto 115:87f2f5183dfb 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 115:87f2f5183dfb 1366 __DCCMVAC = (uint32_t)va;
Kojto 115:87f2f5183dfb 1367 #endif
Kojto 115:87f2f5183dfb 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 115:87f2f5183dfb 1369 }
Kojto 115:87f2f5183dfb 1370
Kojto 115:87f2f5183dfb 1371 /** \brief Invalidate D$ by MVA
Kojto 115:87f2f5183dfb 1372
Kojto 115:87f2f5183dfb 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 115:87f2f5183dfb 1374 */
Kojto 115:87f2f5183dfb 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 115:87f2f5183dfb 1376 #if 1
Kojto 115:87f2f5183dfb 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 115:87f2f5183dfb 1378 #else
Kojto 115:87f2f5183dfb 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 115:87f2f5183dfb 1380 __DCIMVAC = (uint32_t)va;
Kojto 115:87f2f5183dfb 1381 #endif
Kojto 115:87f2f5183dfb 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 115:87f2f5183dfb 1383 }
Kojto 115:87f2f5183dfb 1384
Kojto 115:87f2f5183dfb 1385 /** \brief Clean and Invalidate D$ by MVA
Kojto 115:87f2f5183dfb 1386
Kojto 115:87f2f5183dfb 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 115:87f2f5183dfb 1388 */
Kojto 115:87f2f5183dfb 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 115:87f2f5183dfb 1390 #if 1
Kojto 115:87f2f5183dfb 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 115:87f2f5183dfb 1392 #else
Kojto 115:87f2f5183dfb 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 115:87f2f5183dfb 1394 __DCCIMVAC = (uint32_t)va;
Kojto 115:87f2f5183dfb 1395 #endif
Kojto 115:87f2f5183dfb 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 115:87f2f5183dfb 1397 }
Kojto 115:87f2f5183dfb 1398
Kojto 115:87f2f5183dfb 1399 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 115:87f2f5183dfb 1400
Kojto 115:87f2f5183dfb 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 115:87f2f5183dfb 1402 */
Kojto 115:87f2f5183dfb 1403 extern void __v7_all_cache(uint32_t op);
Kojto 115:87f2f5183dfb 1404
Kojto 115:87f2f5183dfb 1405
Kojto 115:87f2f5183dfb 1406 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 1407
Kojto 115:87f2f5183dfb 1408 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 1409 */
Kojto 115:87f2f5183dfb 1410
Kojto 115:87f2f5183dfb 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 1412 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 1413 }
Kojto 115:87f2f5183dfb 1414
Kojto 115:87f2f5183dfb 1415 /** \brief Clean the whole D$
Kojto 115:87f2f5183dfb 1416
Kojto 115:87f2f5183dfb 1417 DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 1418 */
Kojto 115:87f2f5183dfb 1419
Kojto 115:87f2f5183dfb 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 115:87f2f5183dfb 1421 __v7_all_cache(1);
Kojto 115:87f2f5183dfb 1422 }
Kojto 115:87f2f5183dfb 1423
Kojto 115:87f2f5183dfb 1424 /** \brief Clean and invalidate the whole D$
Kojto 115:87f2f5183dfb 1425
Kojto 115:87f2f5183dfb 1426 DCCISW. Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 1427 */
Kojto 115:87f2f5183dfb 1428
Kojto 115:87f2f5183dfb 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 1430 __v7_all_cache(2);
Kojto 115:87f2f5183dfb 1431 }
Kojto 115:87f2f5183dfb 1432
Kojto 115:87f2f5183dfb 1433 #include "core_ca_mmu.h"
Kojto 115:87f2f5183dfb 1434
Kojto 115:87f2f5183dfb 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 115:87f2f5183dfb 1436
Kojto 115:87f2f5183dfb 1437 #error TASKING Compiler support not implemented for Cortex-A
Kojto 115:87f2f5183dfb 1438
Kojto 115:87f2f5183dfb 1439 #endif
Kojto 115:87f2f5183dfb 1440
Kojto 115:87f2f5183dfb 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 115:87f2f5183dfb 1442
Kojto 115:87f2f5183dfb 1443
Kojto 115:87f2f5183dfb 1444 #endif /* __CORE_CAFUNC_H__ */