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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F303ZE/core_sc000.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**************************************************************************//**
AnnaBridge 126:abea610beb85 2 * @file core_sc000.h
AnnaBridge 126:abea610beb85 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
AnnaBridge 126:abea610beb85 4 * @version V4.10
AnnaBridge 126:abea610beb85 5 * @date 18. March 2015
AnnaBridge 126:abea610beb85 6 *
AnnaBridge 126:abea610beb85 7 * @note
AnnaBridge 126:abea610beb85 8 *
AnnaBridge 126:abea610beb85 9 ******************************************************************************/
AnnaBridge 126:abea610beb85 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge 126:abea610beb85 11
AnnaBridge 126:abea610beb85 12 All rights reserved.
AnnaBridge 126:abea610beb85 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 126:abea610beb85 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 - Redistributions of source code must retain the above copyright
AnnaBridge 126:abea610beb85 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 126:abea610beb85 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 126:abea610beb85 19 documentation and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 126:abea610beb85 21 to endorse or promote products derived from this software without
AnnaBridge 126:abea610beb85 22 specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 126:abea610beb85 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 126:abea610beb85 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 126:abea610beb85 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 126:abea610beb85 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 126:abea610beb85 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 126:abea610beb85 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 126:abea610beb85 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 126:abea610beb85 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 35 ---------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 36
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 #if defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 126:abea610beb85 40 #endif
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 #ifndef __CORE_SC000_H_GENERIC
AnnaBridge 126:abea610beb85 43 #define __CORE_SC000_H_GENERIC
AnnaBridge 126:abea610beb85 44
AnnaBridge 126:abea610beb85 45 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 46 extern "C" {
AnnaBridge 126:abea610beb85 47 #endif
AnnaBridge 126:abea610beb85 48
AnnaBridge 126:abea610beb85 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 126:abea610beb85 50 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 126:abea610beb85 51
AnnaBridge 126:abea610beb85 52 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 126:abea610beb85 53 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 126:abea610beb85 54
AnnaBridge 126:abea610beb85 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 126:abea610beb85 56 Unions are used for effective representation of core registers.
AnnaBridge 126:abea610beb85 57
AnnaBridge 126:abea610beb85 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 126:abea610beb85 59 Function-like macros are used to allow more efficient code.
AnnaBridge 126:abea610beb85 60 */
AnnaBridge 126:abea610beb85 61
AnnaBridge 126:abea610beb85 62
AnnaBridge 126:abea610beb85 63 /*******************************************************************************
AnnaBridge 126:abea610beb85 64 * CMSIS definitions
AnnaBridge 126:abea610beb85 65 ******************************************************************************/
AnnaBridge 126:abea610beb85 66 /** \ingroup SC000
AnnaBridge 126:abea610beb85 67 @{
AnnaBridge 126:abea610beb85 68 */
AnnaBridge 126:abea610beb85 69
AnnaBridge 126:abea610beb85 70 /* CMSIS SC000 definitions */
AnnaBridge 126:abea610beb85 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 126:abea610beb85 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 126:abea610beb85 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 126:abea610beb85 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 126:abea610beb85 75
AnnaBridge 126:abea610beb85 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
AnnaBridge 126:abea610beb85 77
AnnaBridge 126:abea610beb85 78
AnnaBridge 126:abea610beb85 79 #if defined ( __CC_ARM )
AnnaBridge 126:abea610beb85 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 126:abea610beb85 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 126:abea610beb85 82 #define __STATIC_INLINE static __inline
AnnaBridge 126:abea610beb85 83
AnnaBridge 126:abea610beb85 84 #elif defined ( __GNUC__ )
AnnaBridge 126:abea610beb85 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 126:abea610beb85 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 126:abea610beb85 87 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 88
AnnaBridge 126:abea610beb85 89 #elif defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 126:abea610beb85 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 126:abea610beb85 92 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 93
AnnaBridge 126:abea610beb85 94 #elif defined ( __TMS470__ )
AnnaBridge 126:abea610beb85 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 126:abea610beb85 96 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 97
AnnaBridge 126:abea610beb85 98 #elif defined ( __TASKING__ )
AnnaBridge 126:abea610beb85 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 126:abea610beb85 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 126:abea610beb85 101 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 102
AnnaBridge 126:abea610beb85 103 #elif defined ( __CSMC__ )
AnnaBridge 126:abea610beb85 104 #define __packed
AnnaBridge 126:abea610beb85 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
AnnaBridge 126:abea610beb85 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
AnnaBridge 126:abea610beb85 107 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 108
AnnaBridge 126:abea610beb85 109 #endif
AnnaBridge 126:abea610beb85 110
AnnaBridge 126:abea610beb85 111 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 126:abea610beb85 112 This core does not support an FPU at all
AnnaBridge 126:abea610beb85 113 */
AnnaBridge 126:abea610beb85 114 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 115
AnnaBridge 126:abea610beb85 116 #if defined ( __CC_ARM )
AnnaBridge 126:abea610beb85 117 #if defined __TARGET_FPU_VFP
AnnaBridge 126:abea610beb85 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 119 #endif
AnnaBridge 126:abea610beb85 120
AnnaBridge 126:abea610beb85 121 #elif defined ( __GNUC__ )
AnnaBridge 126:abea610beb85 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 126:abea610beb85 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 124 #endif
AnnaBridge 126:abea610beb85 125
AnnaBridge 126:abea610beb85 126 #elif defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 127 #if defined __ARMVFP__
AnnaBridge 126:abea610beb85 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 129 #endif
AnnaBridge 126:abea610beb85 130
AnnaBridge 126:abea610beb85 131 #elif defined ( __TMS470__ )
AnnaBridge 126:abea610beb85 132 #if defined __TI__VFP_SUPPORT____
AnnaBridge 126:abea610beb85 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 134 #endif
AnnaBridge 126:abea610beb85 135
AnnaBridge 126:abea610beb85 136 #elif defined ( __TASKING__ )
AnnaBridge 126:abea610beb85 137 #if defined __FPU_VFP__
AnnaBridge 126:abea610beb85 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 139 #endif
AnnaBridge 126:abea610beb85 140
AnnaBridge 126:abea610beb85 141 #elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge 126:abea610beb85 142 #if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge 126:abea610beb85 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 144 #endif
AnnaBridge 126:abea610beb85 145 #endif
AnnaBridge 126:abea610beb85 146
AnnaBridge 126:abea610beb85 147 #include <stdint.h> /* standard types definitions */
AnnaBridge 126:abea610beb85 148 #include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge 126:abea610beb85 149 #include <core_cmFunc.h> /* Core Function Access */
AnnaBridge 126:abea610beb85 150
AnnaBridge 126:abea610beb85 151 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 152 }
AnnaBridge 126:abea610beb85 153 #endif
AnnaBridge 126:abea610beb85 154
AnnaBridge 126:abea610beb85 155 #endif /* __CORE_SC000_H_GENERIC */
AnnaBridge 126:abea610beb85 156
AnnaBridge 126:abea610beb85 157 #ifndef __CMSIS_GENERIC
AnnaBridge 126:abea610beb85 158
AnnaBridge 126:abea610beb85 159 #ifndef __CORE_SC000_H_DEPENDANT
AnnaBridge 126:abea610beb85 160 #define __CORE_SC000_H_DEPENDANT
AnnaBridge 126:abea610beb85 161
AnnaBridge 126:abea610beb85 162 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 163 extern "C" {
AnnaBridge 126:abea610beb85 164 #endif
AnnaBridge 126:abea610beb85 165
AnnaBridge 126:abea610beb85 166 /* check device defines and use defaults */
AnnaBridge 126:abea610beb85 167 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 126:abea610beb85 168 #ifndef __SC000_REV
AnnaBridge 126:abea610beb85 169 #define __SC000_REV 0x0000
AnnaBridge 126:abea610beb85 170 #warning "__SC000_REV not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 171 #endif
AnnaBridge 126:abea610beb85 172
AnnaBridge 126:abea610beb85 173 #ifndef __MPU_PRESENT
AnnaBridge 126:abea610beb85 174 #define __MPU_PRESENT 0
AnnaBridge 126:abea610beb85 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 176 #endif
AnnaBridge 126:abea610beb85 177
AnnaBridge 126:abea610beb85 178 #ifndef __NVIC_PRIO_BITS
AnnaBridge 126:abea610beb85 179 #define __NVIC_PRIO_BITS 2
AnnaBridge 126:abea610beb85 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 181 #endif
AnnaBridge 126:abea610beb85 182
AnnaBridge 126:abea610beb85 183 #ifndef __Vendor_SysTickConfig
AnnaBridge 126:abea610beb85 184 #define __Vendor_SysTickConfig 0
AnnaBridge 126:abea610beb85 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 186 #endif
AnnaBridge 126:abea610beb85 187 #endif
AnnaBridge 126:abea610beb85 188
AnnaBridge 126:abea610beb85 189 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 126:abea610beb85 190 /**
AnnaBridge 126:abea610beb85 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 126:abea610beb85 192
AnnaBridge 126:abea610beb85 193 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 126:abea610beb85 194 \li to specify the access to peripheral variables.
AnnaBridge 126:abea610beb85 195 \li for automatic generation of peripheral register debug information.
AnnaBridge 126:abea610beb85 196 */
AnnaBridge 126:abea610beb85 197 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 198 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 126:abea610beb85 199 #else
AnnaBridge 126:abea610beb85 200 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 126:abea610beb85 201 #endif
AnnaBridge 126:abea610beb85 202 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 126:abea610beb85 203 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 126:abea610beb85 204
AnnaBridge 126:abea610beb85 205 /*@} end of group SC000 */
AnnaBridge 126:abea610beb85 206
AnnaBridge 126:abea610beb85 207
AnnaBridge 126:abea610beb85 208
AnnaBridge 126:abea610beb85 209 /*******************************************************************************
AnnaBridge 126:abea610beb85 210 * Register Abstraction
AnnaBridge 126:abea610beb85 211 Core Register contain:
AnnaBridge 126:abea610beb85 212 - Core Register
AnnaBridge 126:abea610beb85 213 - Core NVIC Register
AnnaBridge 126:abea610beb85 214 - Core SCB Register
AnnaBridge 126:abea610beb85 215 - Core SysTick Register
AnnaBridge 126:abea610beb85 216 - Core MPU Register
AnnaBridge 126:abea610beb85 217 ******************************************************************************/
AnnaBridge 126:abea610beb85 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 126:abea610beb85 219 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 126:abea610beb85 220 */
AnnaBridge 126:abea610beb85 221
AnnaBridge 126:abea610beb85 222 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 223 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 126:abea610beb85 224 \brief Core Register type definitions.
AnnaBridge 126:abea610beb85 225 @{
AnnaBridge 126:abea610beb85 226 */
AnnaBridge 126:abea610beb85 227
AnnaBridge 126:abea610beb85 228 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 126:abea610beb85 229 */
AnnaBridge 126:abea610beb85 230 typedef union
AnnaBridge 126:abea610beb85 231 {
AnnaBridge 126:abea610beb85 232 struct
AnnaBridge 126:abea610beb85 233 {
AnnaBridge 126:abea610beb85 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 126:abea610beb85 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 126:abea610beb85 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 126:abea610beb85 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 126:abea610beb85 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 126:abea610beb85 239 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 240 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 241 } APSR_Type;
AnnaBridge 126:abea610beb85 242
AnnaBridge 126:abea610beb85 243 /* APSR Register Definitions */
AnnaBridge 126:abea610beb85 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
AnnaBridge 126:abea610beb85 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 126:abea610beb85 246
AnnaBridge 126:abea610beb85 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
AnnaBridge 126:abea610beb85 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 126:abea610beb85 249
AnnaBridge 126:abea610beb85 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
AnnaBridge 126:abea610beb85 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 126:abea610beb85 252
AnnaBridge 126:abea610beb85 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
AnnaBridge 126:abea610beb85 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 126:abea610beb85 255
AnnaBridge 126:abea610beb85 256
AnnaBridge 126:abea610beb85 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 126:abea610beb85 258 */
AnnaBridge 126:abea610beb85 259 typedef union
AnnaBridge 126:abea610beb85 260 {
AnnaBridge 126:abea610beb85 261 struct
AnnaBridge 126:abea610beb85 262 {
AnnaBridge 126:abea610beb85 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 126:abea610beb85 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 126:abea610beb85 265 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 266 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 267 } IPSR_Type;
AnnaBridge 126:abea610beb85 268
AnnaBridge 126:abea610beb85 269 /* IPSR Register Definitions */
AnnaBridge 126:abea610beb85 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
AnnaBridge 126:abea610beb85 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 126:abea610beb85 272
AnnaBridge 126:abea610beb85 273
AnnaBridge 126:abea610beb85 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 126:abea610beb85 275 */
AnnaBridge 126:abea610beb85 276 typedef union
AnnaBridge 126:abea610beb85 277 {
AnnaBridge 126:abea610beb85 278 struct
AnnaBridge 126:abea610beb85 279 {
AnnaBridge 126:abea610beb85 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 126:abea610beb85 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 126:abea610beb85 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 126:abea610beb85 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 126:abea610beb85 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 126:abea610beb85 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 126:abea610beb85 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 126:abea610beb85 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 126:abea610beb85 288 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 289 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 290 } xPSR_Type;
AnnaBridge 126:abea610beb85 291
AnnaBridge 126:abea610beb85 292 /* xPSR Register Definitions */
AnnaBridge 126:abea610beb85 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
AnnaBridge 126:abea610beb85 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 126:abea610beb85 295
AnnaBridge 126:abea610beb85 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
AnnaBridge 126:abea610beb85 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 126:abea610beb85 298
AnnaBridge 126:abea610beb85 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
AnnaBridge 126:abea610beb85 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 126:abea610beb85 301
AnnaBridge 126:abea610beb85 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
AnnaBridge 126:abea610beb85 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 126:abea610beb85 304
AnnaBridge 126:abea610beb85 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
AnnaBridge 126:abea610beb85 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 126:abea610beb85 307
AnnaBridge 126:abea610beb85 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
AnnaBridge 126:abea610beb85 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 126:abea610beb85 310
AnnaBridge 126:abea610beb85 311
AnnaBridge 126:abea610beb85 312 /** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 126:abea610beb85 313 */
AnnaBridge 126:abea610beb85 314 typedef union
AnnaBridge 126:abea610beb85 315 {
AnnaBridge 126:abea610beb85 316 struct
AnnaBridge 126:abea610beb85 317 {
AnnaBridge 126:abea610beb85 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 126:abea610beb85 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 126:abea610beb85 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 126:abea610beb85 321 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 322 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 323 } CONTROL_Type;
AnnaBridge 126:abea610beb85 324
AnnaBridge 126:abea610beb85 325 /* CONTROL Register Definitions */
AnnaBridge 126:abea610beb85 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
AnnaBridge 126:abea610beb85 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 126:abea610beb85 328
AnnaBridge 126:abea610beb85 329 /*@} end of group CMSIS_CORE */
AnnaBridge 126:abea610beb85 330
AnnaBridge 126:abea610beb85 331
AnnaBridge 126:abea610beb85 332 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 126:abea610beb85 334 \brief Type definitions for the NVIC Registers
AnnaBridge 126:abea610beb85 335 @{
AnnaBridge 126:abea610beb85 336 */
AnnaBridge 126:abea610beb85 337
AnnaBridge 126:abea610beb85 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 126:abea610beb85 339 */
AnnaBridge 126:abea610beb85 340 typedef struct
AnnaBridge 126:abea610beb85 341 {
AnnaBridge 126:abea610beb85 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 126:abea610beb85 343 uint32_t RESERVED0[31];
AnnaBridge 126:abea610beb85 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 126:abea610beb85 345 uint32_t RSERVED1[31];
AnnaBridge 126:abea610beb85 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 126:abea610beb85 347 uint32_t RESERVED2[31];
AnnaBridge 126:abea610beb85 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 126:abea610beb85 349 uint32_t RESERVED3[31];
AnnaBridge 126:abea610beb85 350 uint32_t RESERVED4[64];
AnnaBridge 126:abea610beb85 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 126:abea610beb85 352 } NVIC_Type;
AnnaBridge 126:abea610beb85 353
AnnaBridge 126:abea610beb85 354 /*@} end of group CMSIS_NVIC */
AnnaBridge 126:abea610beb85 355
AnnaBridge 126:abea610beb85 356
AnnaBridge 126:abea610beb85 357 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 358 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 126:abea610beb85 359 \brief Type definitions for the System Control Block Registers
AnnaBridge 126:abea610beb85 360 @{
AnnaBridge 126:abea610beb85 361 */
AnnaBridge 126:abea610beb85 362
AnnaBridge 126:abea610beb85 363 /** \brief Structure type to access the System Control Block (SCB).
AnnaBridge 126:abea610beb85 364 */
AnnaBridge 126:abea610beb85 365 typedef struct
AnnaBridge 126:abea610beb85 366 {
AnnaBridge 126:abea610beb85 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 126:abea610beb85 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 126:abea610beb85 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 126:abea610beb85 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 126:abea610beb85 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 126:abea610beb85 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 126:abea610beb85 373 uint32_t RESERVED0[1];
AnnaBridge 126:abea610beb85 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 126:abea610beb85 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 126:abea610beb85 376 uint32_t RESERVED1[154];
AnnaBridge 126:abea610beb85 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 126:abea610beb85 378 } SCB_Type;
AnnaBridge 126:abea610beb85 379
AnnaBridge 126:abea610beb85 380 /* SCB CPUID Register Definitions */
AnnaBridge 126:abea610beb85 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 126:abea610beb85 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 126:abea610beb85 383
AnnaBridge 126:abea610beb85 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
AnnaBridge 126:abea610beb85 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 126:abea610beb85 386
AnnaBridge 126:abea610beb85 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 126:abea610beb85 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 126:abea610beb85 389
AnnaBridge 126:abea610beb85 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
AnnaBridge 126:abea610beb85 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 126:abea610beb85 392
AnnaBridge 126:abea610beb85 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
AnnaBridge 126:abea610beb85 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 126:abea610beb85 395
AnnaBridge 126:abea610beb85 396 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 126:abea610beb85 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 126:abea610beb85 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 126:abea610beb85 399
AnnaBridge 126:abea610beb85 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 126:abea610beb85 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 126:abea610beb85 402
AnnaBridge 126:abea610beb85 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 126:abea610beb85 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 126:abea610beb85 405
AnnaBridge 126:abea610beb85 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 126:abea610beb85 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 126:abea610beb85 408
AnnaBridge 126:abea610beb85 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 126:abea610beb85 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 126:abea610beb85 411
AnnaBridge 126:abea610beb85 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 126:abea610beb85 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 126:abea610beb85 414
AnnaBridge 126:abea610beb85 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 126:abea610beb85 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 126:abea610beb85 417
AnnaBridge 126:abea610beb85 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 126:abea610beb85 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 126:abea610beb85 420
AnnaBridge 126:abea610beb85 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 126:abea610beb85 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 126:abea610beb85 423
AnnaBridge 126:abea610beb85 424 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 126:abea610beb85 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 126:abea610beb85 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 126:abea610beb85 427
AnnaBridge 126:abea610beb85 428 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 126:abea610beb85 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 126:abea610beb85 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 126:abea610beb85 431
AnnaBridge 126:abea610beb85 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 126:abea610beb85 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 126:abea610beb85 434
AnnaBridge 126:abea610beb85 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 126:abea610beb85 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 126:abea610beb85 437
AnnaBridge 126:abea610beb85 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 126:abea610beb85 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 126:abea610beb85 440
AnnaBridge 126:abea610beb85 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 126:abea610beb85 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 126:abea610beb85 443
AnnaBridge 126:abea610beb85 444 /* SCB System Control Register Definitions */
AnnaBridge 126:abea610beb85 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 126:abea610beb85 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 126:abea610beb85 447
AnnaBridge 126:abea610beb85 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 126:abea610beb85 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 126:abea610beb85 450
AnnaBridge 126:abea610beb85 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 126:abea610beb85 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 126:abea610beb85 453
AnnaBridge 126:abea610beb85 454 /* SCB Configuration Control Register Definitions */
AnnaBridge 126:abea610beb85 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
AnnaBridge 126:abea610beb85 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 126:abea610beb85 457
AnnaBridge 126:abea610beb85 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 126:abea610beb85 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 126:abea610beb85 460
AnnaBridge 126:abea610beb85 461 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 126:abea610beb85 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 126:abea610beb85 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 126:abea610beb85 464
AnnaBridge 126:abea610beb85 465 /*@} end of group CMSIS_SCB */
AnnaBridge 126:abea610beb85 466
AnnaBridge 126:abea610beb85 467
AnnaBridge 126:abea610beb85 468 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 126:abea610beb85 470 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 126:abea610beb85 471 @{
AnnaBridge 126:abea610beb85 472 */
AnnaBridge 126:abea610beb85 473
AnnaBridge 126:abea610beb85 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 126:abea610beb85 475 */
AnnaBridge 126:abea610beb85 476 typedef struct
AnnaBridge 126:abea610beb85 477 {
AnnaBridge 126:abea610beb85 478 uint32_t RESERVED0[2];
AnnaBridge 126:abea610beb85 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 126:abea610beb85 480 } SCnSCB_Type;
AnnaBridge 126:abea610beb85 481
AnnaBridge 126:abea610beb85 482 /* Auxiliary Control Register Definitions */
AnnaBridge 126:abea610beb85 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
AnnaBridge 126:abea610beb85 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
AnnaBridge 126:abea610beb85 485
AnnaBridge 126:abea610beb85 486 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 126:abea610beb85 487
AnnaBridge 126:abea610beb85 488
AnnaBridge 126:abea610beb85 489 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 126:abea610beb85 491 \brief Type definitions for the System Timer Registers.
AnnaBridge 126:abea610beb85 492 @{
AnnaBridge 126:abea610beb85 493 */
AnnaBridge 126:abea610beb85 494
AnnaBridge 126:abea610beb85 495 /** \brief Structure type to access the System Timer (SysTick).
AnnaBridge 126:abea610beb85 496 */
AnnaBridge 126:abea610beb85 497 typedef struct
AnnaBridge 126:abea610beb85 498 {
AnnaBridge 126:abea610beb85 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 126:abea610beb85 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 126:abea610beb85 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 126:abea610beb85 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 126:abea610beb85 503 } SysTick_Type;
AnnaBridge 126:abea610beb85 504
AnnaBridge 126:abea610beb85 505 /* SysTick Control / Status Register Definitions */
AnnaBridge 126:abea610beb85 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 126:abea610beb85 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 126:abea610beb85 508
AnnaBridge 126:abea610beb85 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 126:abea610beb85 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 126:abea610beb85 511
AnnaBridge 126:abea610beb85 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 126:abea610beb85 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 126:abea610beb85 514
AnnaBridge 126:abea610beb85 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 126:abea610beb85 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 126:abea610beb85 517
AnnaBridge 126:abea610beb85 518 /* SysTick Reload Register Definitions */
AnnaBridge 126:abea610beb85 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 126:abea610beb85 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 126:abea610beb85 521
AnnaBridge 126:abea610beb85 522 /* SysTick Current Register Definitions */
AnnaBridge 126:abea610beb85 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
AnnaBridge 126:abea610beb85 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 126:abea610beb85 525
AnnaBridge 126:abea610beb85 526 /* SysTick Calibration Register Definitions */
AnnaBridge 126:abea610beb85 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
AnnaBridge 126:abea610beb85 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 126:abea610beb85 529
AnnaBridge 126:abea610beb85 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
AnnaBridge 126:abea610beb85 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 126:abea610beb85 532
AnnaBridge 126:abea610beb85 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
AnnaBridge 126:abea610beb85 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 126:abea610beb85 535
AnnaBridge 126:abea610beb85 536 /*@} end of group CMSIS_SysTick */
AnnaBridge 126:abea610beb85 537
AnnaBridge 126:abea610beb85 538 #if (__MPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 539 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 126:abea610beb85 541 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 126:abea610beb85 542 @{
AnnaBridge 126:abea610beb85 543 */
AnnaBridge 126:abea610beb85 544
AnnaBridge 126:abea610beb85 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 126:abea610beb85 546 */
AnnaBridge 126:abea610beb85 547 typedef struct
AnnaBridge 126:abea610beb85 548 {
AnnaBridge 126:abea610beb85 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 126:abea610beb85 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 126:abea610beb85 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 126:abea610beb85 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 126:abea610beb85 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 554 } MPU_Type;
AnnaBridge 126:abea610beb85 555
AnnaBridge 126:abea610beb85 556 /* MPU Type Register */
AnnaBridge 126:abea610beb85 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
AnnaBridge 126:abea610beb85 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 126:abea610beb85 559
AnnaBridge 126:abea610beb85 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
AnnaBridge 126:abea610beb85 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 126:abea610beb85 562
AnnaBridge 126:abea610beb85 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 126:abea610beb85 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 126:abea610beb85 565
AnnaBridge 126:abea610beb85 566 /* MPU Control Register */
AnnaBridge 126:abea610beb85 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 126:abea610beb85 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 126:abea610beb85 569
AnnaBridge 126:abea610beb85 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 126:abea610beb85 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 126:abea610beb85 572
AnnaBridge 126:abea610beb85 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
AnnaBridge 126:abea610beb85 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 126:abea610beb85 575
AnnaBridge 126:abea610beb85 576 /* MPU Region Number Register */
AnnaBridge 126:abea610beb85 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
AnnaBridge 126:abea610beb85 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 126:abea610beb85 579
AnnaBridge 126:abea610beb85 580 /* MPU Region Base Address Register */
AnnaBridge 126:abea610beb85 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
AnnaBridge 126:abea610beb85 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 126:abea610beb85 583
AnnaBridge 126:abea610beb85 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
AnnaBridge 126:abea610beb85 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 126:abea610beb85 586
AnnaBridge 126:abea610beb85 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
AnnaBridge 126:abea610beb85 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 126:abea610beb85 589
AnnaBridge 126:abea610beb85 590 /* MPU Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 126:abea610beb85 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 126:abea610beb85 593
AnnaBridge 126:abea610beb85 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 126:abea610beb85 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 126:abea610beb85 596
AnnaBridge 126:abea610beb85 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 126:abea610beb85 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 126:abea610beb85 599
AnnaBridge 126:abea610beb85 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 126:abea610beb85 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 126:abea610beb85 602
AnnaBridge 126:abea610beb85 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 126:abea610beb85 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 126:abea610beb85 605
AnnaBridge 126:abea610beb85 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 126:abea610beb85 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 126:abea610beb85 608
AnnaBridge 126:abea610beb85 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 126:abea610beb85 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 126:abea610beb85 611
AnnaBridge 126:abea610beb85 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 126:abea610beb85 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 126:abea610beb85 614
AnnaBridge 126:abea610beb85 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
AnnaBridge 126:abea610beb85 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 126:abea610beb85 617
AnnaBridge 126:abea610beb85 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
AnnaBridge 126:abea610beb85 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 126:abea610beb85 620
AnnaBridge 126:abea610beb85 621 /*@} end of group CMSIS_MPU */
AnnaBridge 126:abea610beb85 622 #endif
AnnaBridge 126:abea610beb85 623
AnnaBridge 126:abea610beb85 624
AnnaBridge 126:abea610beb85 625 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 126:abea610beb85 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
AnnaBridge 126:abea610beb85 628 are only accessible over DAP and not via processor. Therefore
AnnaBridge 126:abea610beb85 629 they are not covered by the Cortex-M0 header file.
AnnaBridge 126:abea610beb85 630 @{
AnnaBridge 126:abea610beb85 631 */
AnnaBridge 126:abea610beb85 632 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 126:abea610beb85 633
AnnaBridge 126:abea610beb85 634
AnnaBridge 126:abea610beb85 635 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 636 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 126:abea610beb85 637 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 126:abea610beb85 638 @{
AnnaBridge 126:abea610beb85 639 */
AnnaBridge 126:abea610beb85 640
AnnaBridge 126:abea610beb85 641 /* Memory mapping of SC000 Hardware */
AnnaBridge 126:abea610beb85 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 126:abea610beb85 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 126:abea610beb85 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 126:abea610beb85 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 126:abea610beb85 646
AnnaBridge 126:abea610beb85 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 126:abea610beb85 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 126:abea610beb85 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 126:abea610beb85 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 126:abea610beb85 651
AnnaBridge 126:abea610beb85 652 #if (__MPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 126:abea610beb85 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 126:abea610beb85 655 #endif
AnnaBridge 126:abea610beb85 656
AnnaBridge 126:abea610beb85 657 /*@} */
AnnaBridge 126:abea610beb85 658
AnnaBridge 126:abea610beb85 659
AnnaBridge 126:abea610beb85 660
AnnaBridge 126:abea610beb85 661 /*******************************************************************************
AnnaBridge 126:abea610beb85 662 * Hardware Abstraction Layer
AnnaBridge 126:abea610beb85 663 Core Function Interface contains:
AnnaBridge 126:abea610beb85 664 - Core NVIC Functions
AnnaBridge 126:abea610beb85 665 - Core SysTick Functions
AnnaBridge 126:abea610beb85 666 - Core Register Access Functions
AnnaBridge 126:abea610beb85 667 ******************************************************************************/
AnnaBridge 126:abea610beb85 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 126:abea610beb85 669 */
AnnaBridge 126:abea610beb85 670
AnnaBridge 126:abea610beb85 671
AnnaBridge 126:abea610beb85 672
AnnaBridge 126:abea610beb85 673 /* ########################## NVIC functions #################################### */
AnnaBridge 126:abea610beb85 674 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 126:abea610beb85 676 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 126:abea610beb85 677 @{
AnnaBridge 126:abea610beb85 678 */
AnnaBridge 126:abea610beb85 679
AnnaBridge 126:abea610beb85 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 126:abea610beb85 681 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 126:abea610beb85 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 126:abea610beb85 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 126:abea610beb85 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 126:abea610beb85 685
AnnaBridge 126:abea610beb85 686
AnnaBridge 126:abea610beb85 687 /** \brief Enable External Interrupt
AnnaBridge 126:abea610beb85 688
AnnaBridge 126:abea610beb85 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 126:abea610beb85 690
AnnaBridge 126:abea610beb85 691 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 692 */
AnnaBridge 126:abea610beb85 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 694 {
AnnaBridge 126:abea610beb85 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 696 }
AnnaBridge 126:abea610beb85 697
AnnaBridge 126:abea610beb85 698
AnnaBridge 126:abea610beb85 699 /** \brief Disable External Interrupt
AnnaBridge 126:abea610beb85 700
AnnaBridge 126:abea610beb85 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 126:abea610beb85 702
AnnaBridge 126:abea610beb85 703 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 704 */
AnnaBridge 126:abea610beb85 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 706 {
AnnaBridge 126:abea610beb85 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 708 __DSB();
<> 131:faff56e089b2 709 __ISB();
AnnaBridge 126:abea610beb85 710 }
AnnaBridge 126:abea610beb85 711
AnnaBridge 126:abea610beb85 712
AnnaBridge 126:abea610beb85 713 /** \brief Get Pending Interrupt
AnnaBridge 126:abea610beb85 714
AnnaBridge 126:abea610beb85 715 The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge 126:abea610beb85 716 for the specified interrupt.
AnnaBridge 126:abea610beb85 717
AnnaBridge 126:abea610beb85 718 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 719
AnnaBridge 126:abea610beb85 720 \return 0 Interrupt status is not pending.
AnnaBridge 126:abea610beb85 721 \return 1 Interrupt status is pending.
AnnaBridge 126:abea610beb85 722 */
AnnaBridge 126:abea610beb85 723 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 724 {
AnnaBridge 126:abea610beb85 725 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 126:abea610beb85 726 }
AnnaBridge 126:abea610beb85 727
AnnaBridge 126:abea610beb85 728
AnnaBridge 126:abea610beb85 729 /** \brief Set Pending Interrupt
AnnaBridge 126:abea610beb85 730
AnnaBridge 126:abea610beb85 731 The function sets the pending bit of an external interrupt.
AnnaBridge 126:abea610beb85 732
AnnaBridge 126:abea610beb85 733 \param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 734 */
AnnaBridge 126:abea610beb85 735 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 736 {
AnnaBridge 126:abea610beb85 737 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 738 }
AnnaBridge 126:abea610beb85 739
AnnaBridge 126:abea610beb85 740
AnnaBridge 126:abea610beb85 741 /** \brief Clear Pending Interrupt
AnnaBridge 126:abea610beb85 742
AnnaBridge 126:abea610beb85 743 The function clears the pending bit of an external interrupt.
AnnaBridge 126:abea610beb85 744
AnnaBridge 126:abea610beb85 745 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 746 */
AnnaBridge 126:abea610beb85 747 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 748 {
AnnaBridge 126:abea610beb85 749 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 750 }
AnnaBridge 126:abea610beb85 751
AnnaBridge 126:abea610beb85 752
AnnaBridge 126:abea610beb85 753 /** \brief Set Interrupt Priority
AnnaBridge 126:abea610beb85 754
AnnaBridge 126:abea610beb85 755 The function sets the priority of an interrupt.
AnnaBridge 126:abea610beb85 756
AnnaBridge 126:abea610beb85 757 \note The priority cannot be set for every core interrupt.
AnnaBridge 126:abea610beb85 758
AnnaBridge 126:abea610beb85 759 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 760 \param [in] priority Priority to set.
AnnaBridge 126:abea610beb85 761 */
AnnaBridge 126:abea610beb85 762 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 126:abea610beb85 763 {
AnnaBridge 126:abea610beb85 764 if((int32_t)(IRQn) < 0) {
AnnaBridge 126:abea610beb85 765 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 126:abea610beb85 766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 126:abea610beb85 767 }
AnnaBridge 126:abea610beb85 768 else {
AnnaBridge 126:abea610beb85 769 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 126:abea610beb85 770 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 126:abea610beb85 771 }
AnnaBridge 126:abea610beb85 772 }
AnnaBridge 126:abea610beb85 773
AnnaBridge 126:abea610beb85 774
AnnaBridge 126:abea610beb85 775 /** \brief Get Interrupt Priority
AnnaBridge 126:abea610beb85 776
AnnaBridge 126:abea610beb85 777 The function reads the priority of an interrupt. The interrupt
AnnaBridge 126:abea610beb85 778 number can be positive to specify an external (device specific)
AnnaBridge 126:abea610beb85 779 interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge 126:abea610beb85 780
AnnaBridge 126:abea610beb85 781
AnnaBridge 126:abea610beb85 782 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 783 \return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge 126:abea610beb85 784 priority bits of the microcontroller.
AnnaBridge 126:abea610beb85 785 */
AnnaBridge 126:abea610beb85 786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 787 {
AnnaBridge 126:abea610beb85 788
AnnaBridge 126:abea610beb85 789 if((int32_t)(IRQn) < 0) {
AnnaBridge 126:abea610beb85 790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 126:abea610beb85 791 }
AnnaBridge 126:abea610beb85 792 else {
AnnaBridge 126:abea610beb85 793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 126:abea610beb85 794 }
AnnaBridge 126:abea610beb85 795 }
AnnaBridge 126:abea610beb85 796
AnnaBridge 126:abea610beb85 797
AnnaBridge 126:abea610beb85 798 /** \brief System Reset
AnnaBridge 126:abea610beb85 799
AnnaBridge 126:abea610beb85 800 The function initiates a system reset request to reset the MCU.
AnnaBridge 126:abea610beb85 801 */
AnnaBridge 126:abea610beb85 802 __STATIC_INLINE void NVIC_SystemReset(void)
AnnaBridge 126:abea610beb85 803 {
AnnaBridge 126:abea610beb85 804 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 126:abea610beb85 805 buffered write are completed before reset */
AnnaBridge 126:abea610beb85 806 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 126:abea610beb85 807 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 126:abea610beb85 808 __DSB(); /* Ensure completion of memory access */
AnnaBridge 126:abea610beb85 809 while(1) { __NOP(); } /* wait until reset */
AnnaBridge 126:abea610beb85 810 }
AnnaBridge 126:abea610beb85 811
AnnaBridge 126:abea610beb85 812 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 126:abea610beb85 813
AnnaBridge 126:abea610beb85 814
AnnaBridge 126:abea610beb85 815
AnnaBridge 126:abea610beb85 816 /* ################################## SysTick function ############################################ */
AnnaBridge 126:abea610beb85 817 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 126:abea610beb85 819 \brief Functions that configure the System.
AnnaBridge 126:abea610beb85 820 @{
AnnaBridge 126:abea610beb85 821 */
AnnaBridge 126:abea610beb85 822
AnnaBridge 126:abea610beb85 823 #if (__Vendor_SysTickConfig == 0)
AnnaBridge 126:abea610beb85 824
AnnaBridge 126:abea610beb85 825 /** \brief System Tick Configuration
AnnaBridge 126:abea610beb85 826
AnnaBridge 126:abea610beb85 827 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 126:abea610beb85 828 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 126:abea610beb85 829
AnnaBridge 126:abea610beb85 830 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 126:abea610beb85 831
AnnaBridge 126:abea610beb85 832 \return 0 Function succeeded.
AnnaBridge 126:abea610beb85 833 \return 1 Function failed.
AnnaBridge 126:abea610beb85 834
AnnaBridge 126:abea610beb85 835 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 126:abea610beb85 836 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 126:abea610beb85 837 must contain a vendor-specific implementation of this function.
AnnaBridge 126:abea610beb85 838
AnnaBridge 126:abea610beb85 839 */
AnnaBridge 126:abea610beb85 840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 126:abea610beb85 841 {
AnnaBridge 126:abea610beb85 842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
AnnaBridge 126:abea610beb85 843
AnnaBridge 126:abea610beb85 844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 126:abea610beb85 845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 126:abea610beb85 846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 126:abea610beb85 847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 126:abea610beb85 848 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 126:abea610beb85 849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 126:abea610beb85 850 return (0UL); /* Function successful */
AnnaBridge 126:abea610beb85 851 }
AnnaBridge 126:abea610beb85 852
AnnaBridge 126:abea610beb85 853 #endif
AnnaBridge 126:abea610beb85 854
AnnaBridge 126:abea610beb85 855 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 126:abea610beb85 856
AnnaBridge 126:abea610beb85 857
AnnaBridge 126:abea610beb85 858
AnnaBridge 126:abea610beb85 859
AnnaBridge 126:abea610beb85 860 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 861 }
AnnaBridge 126:abea610beb85 862 #endif
AnnaBridge 126:abea610beb85 863
AnnaBridge 126:abea610beb85 864 #endif /* __CORE_SC000_H_DEPENDANT */
AnnaBridge 126:abea610beb85 865
AnnaBridge 126:abea610beb85 866 #endif /* __CMSIS_GENERIC */