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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F303ZE/TARGET_STM/PinNamesTypes.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /* mbed Microcontroller Library
<> 135:176b8275d35d 2 *******************************************************************************
<> 135:176b8275d35d 3 * Copyright (c) 2016, STMicroelectronics
<> 135:176b8275d35d 4 * All rights reserved.
<> 135:176b8275d35d 5 *
<> 135:176b8275d35d 6 * Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 7 * modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 135:176b8275d35d 10 * this list of conditions and the following disclaimer.
<> 135:176b8275d35d 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 135:176b8275d35d 12 * this list of conditions and the following disclaimer in the documentation
<> 135:176b8275d35d 13 * and/or other materials provided with the distribution.
<> 135:176b8275d35d 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 135:176b8275d35d 15 * may be used to endorse or promote products derived from this software
<> 135:176b8275d35d 16 * without specific prior written permission.
<> 135:176b8275d35d 17 *
<> 135:176b8275d35d 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 135:176b8275d35d 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 135:176b8275d35d 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 135:176b8275d35d 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 135:176b8275d35d 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 135:176b8275d35d 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 135:176b8275d35d 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 135:176b8275d35d 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 28 *******************************************************************************
<> 135:176b8275d35d 29 */
<> 135:176b8275d35d 30 #ifndef MBED_PINNAMESTYPES_H
<> 135:176b8275d35d 31 #define MBED_PINNAMESTYPES_H
<> 135:176b8275d35d 32
<> 135:176b8275d35d 33 #include "cmsis.h"
<> 135:176b8275d35d 34
<> 135:176b8275d35d 35 #ifdef __cplusplus
<> 135:176b8275d35d 36 extern "C" {
<> 135:176b8275d35d 37 #endif
<> 135:176b8275d35d 38
<> 138:093f2bd7b9eb 39 /* STM PIN data as used in pin_function is coded on 32 bits as below
<> 138:093f2bd7b9eb 40 * [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog
<> 138:093f2bd7b9eb 41 * [3] Output Push-Pull / Open Drain (as in OTYPER reg)
<> 138:093f2bd7b9eb 42 * [5:4] as in PUPDR reg: No Pull, Pull-up, Pull-Donc
<> 138:093f2bd7b9eb 43 * [7:6] Reserved for speed config (as in OSPEEDR), but not used yet
<> 138:093f2bd7b9eb 44 * [11:8] Alternate Num (as in AFRL/AFRG reg)
<> 138:093f2bd7b9eb 45 * [16:12] Channel (Analog/Timer specific)
<> 138:093f2bd7b9eb 46 * [17] Inverted (Analog/Timer specific)
<> 138:093f2bd7b9eb 47 * [18] Analog ADC control - Only valid for specific families
<> 138:093f2bd7b9eb 48 * [32:19] Reserved
<> 138:093f2bd7b9eb 49 */
<> 138:093f2bd7b9eb 50
<> 138:093f2bd7b9eb 51 #define STM_PIN_FUNCTION_MASK 0x07
<> 138:093f2bd7b9eb 52 #define STM_PIN_FUNCTION_SHIFT 0
<> 138:093f2bd7b9eb 53 #define STM_PIN_FUNCTION_BITS (STM_PIN_FUNCTION_MASK << STM_PIN_FUNCTION_SHIFT)
<> 138:093f2bd7b9eb 54
<> 138:093f2bd7b9eb 55 #define STM_PIN_OD_MASK 0x01
<> 138:093f2bd7b9eb 56 #define STM_PIN_OD_SHIFT 3
<> 138:093f2bd7b9eb 57 #define STM_PIN_OD_BITS (STM_PIN_OD_MASK << STM_PIN_OD_SHIFT)
<> 135:176b8275d35d 58
<> 138:093f2bd7b9eb 59 #define STM_PIN_PUPD_MASK 0x03
<> 138:093f2bd7b9eb 60 #define STM_PIN_PUPD_SHIFT 4
<> 138:093f2bd7b9eb 61 #define STM_PIN_PUPD_BITS (STM_PIN_PUPD_MASK << STM_PIN_PUPD_SHIFT)
<> 138:093f2bd7b9eb 62
<> 138:093f2bd7b9eb 63 #define STM_PIN_SPEED_MASK 0x03
<> 138:093f2bd7b9eb 64 #define STM_PIN_SPEED_SHIFT 6
<> 138:093f2bd7b9eb 65 #define STM_PIN_SPEED_BITS (STM_PIN_SPEED_MASK << STM_PIN_SPEED_SHIFT)
<> 138:093f2bd7b9eb 66
<> 138:093f2bd7b9eb 67 #define STM_PIN_AFNUM_MASK 0x0F
<> 138:093f2bd7b9eb 68 #define STM_PIN_AFNUM_SHIFT 8
<> 138:093f2bd7b9eb 69 #define STM_PIN_AFNUM_BITS (STM_PIN_AFNUM_MASK << STM_PIN_AFNUM_SHIFT)
<> 135:176b8275d35d 70
<> 138:093f2bd7b9eb 71 #define STM_PIN_CHAN_MASK 0x1F
<> 138:093f2bd7b9eb 72 #define STM_PIN_CHAN_SHIFT 12
<> 138:093f2bd7b9eb 73 #define STM_PIN_CHANNEL_BIT (STM_PIN_CHAN_MASK << STM_PIN_CHAN_SHIFT)
<> 138:093f2bd7b9eb 74
<> 138:093f2bd7b9eb 75 #define STM_PIN_INV_MASK 0x01
<> 138:093f2bd7b9eb 76 #define STM_PIN_INV_SHIFT 17
<> 138:093f2bd7b9eb 77 #define STM_PIN_INV_BIT (STM_PIN_INV_MASK << STM_PIN_INV_SHIFT)
<> 138:093f2bd7b9eb 78
<> 138:093f2bd7b9eb 79 #define STM_PIN_AN_CTRL_MASK 0x01
<> 138:093f2bd7b9eb 80 #define STM_PIN_AN_CTRL_SHIFT 18
<> 138:093f2bd7b9eb 81 #define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT)
<> 135:176b8275d35d 82
<> 138:093f2bd7b9eb 83 #define STM_PIN_FUNCTION(X) (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK)
<> 138:093f2bd7b9eb 84 #define STM_PIN_OD(X) (((X) >> STM_PIN_OD_SHIFT) & STM_PIN_OD_MASK)
<> 138:093f2bd7b9eb 85 #define STM_PIN_PUPD(X) (((X) >> STM_PIN_PUPD_SHIFT) & STM_PIN_PUPD_MASK)
<> 138:093f2bd7b9eb 86 #define STM_PIN_SPEED(X) (((X) >> STM_PIN_SPEED_SHIFT) & STM_PIN_SPEED_MASK)
<> 138:093f2bd7b9eb 87 #define STM_PIN_AFNUM(X) (((X) >> STM_PIN_AFNUM_SHIFT) & STM_PIN_AFNUM_MASK)
<> 138:093f2bd7b9eb 88 #define STM_PIN_CHANNEL(X) (((X) >> STM_PIN_CHAN_SHIFT) & STM_PIN_CHAN_MASK)
<> 138:093f2bd7b9eb 89 #define STM_PIN_INVERTED(X) (((X) >> STM_PIN_INV_SHIFT) & STM_PIN_INV_MASK)
<> 138:093f2bd7b9eb 90 #define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK)
<> 138:093f2bd7b9eb 91
<> 138:093f2bd7b9eb 92 #define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\
<> 138:093f2bd7b9eb 93 ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
<> 138:093f2bd7b9eb 94 ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT))
<> 138:093f2bd7b9eb 95
<> 138:093f2bd7b9eb 96 #define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \
<> 138:093f2bd7b9eb 97 ((int)(FUNC_OD) |\
<> 138:093f2bd7b9eb 98 ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
<> 138:093f2bd7b9eb 99 ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
<> 138:093f2bd7b9eb 100 ((CHAN & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
<> 138:093f2bd7b9eb 101 ((INV & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
<> 138:093f2bd7b9eb 102
<> 138:093f2bd7b9eb 103 /*
<> 138:093f2bd7b9eb 104 * MACROS to support the legacy definition of PIN formats
<> 138:093f2bd7b9eb 105 * The STM_MODE_ defines contain the function and the Push-pull/OpenDrain
<> 138:093f2bd7b9eb 106 * configuration (legacy inheritance).
<> 138:093f2bd7b9eb 107 */
<> 138:093f2bd7b9eb 108 #define STM_PIN_DATA(FUNC_OD, PUPD, AFNUM) \
<> 138:093f2bd7b9eb 109 STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM)
<> 138:093f2bd7b9eb 110 #define STM_PIN_DATA_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED) \
<> 138:093f2bd7b9eb 111 STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED)
<> 138:093f2bd7b9eb 112
<> 138:093f2bd7b9eb 113 typedef enum {
<> 138:093f2bd7b9eb 114 STM_PIN_INPUT = 0,
<> 138:093f2bd7b9eb 115 STM_PIN_OUTPUT = 1,
<> 138:093f2bd7b9eb 116 STM_PIN_ALTERNATE = 2,
<> 138:093f2bd7b9eb 117 STM_PIN_ANALOG = 3,
<> 138:093f2bd7b9eb 118 } StmPinFunction;
<> 138:093f2bd7b9eb 119
<> 138:093f2bd7b9eb 120 #define STM_MODE_INPUT (STM_PIN_INPUT)
<> 138:093f2bd7b9eb 121 #define STM_MODE_OUTPUT_PP (STM_PIN_OUTPUT)
<> 138:093f2bd7b9eb 122 #define STM_MODE_OUTPUT_OD (STM_PIN_OUTPUT | STM_PIN_OD_BITS)
<> 138:093f2bd7b9eb 123 #define STM_MODE_AF_PP (STM_PIN_ALTERNATE)
<> 138:093f2bd7b9eb 124 #define STM_MODE_AF_OD (STM_PIN_ALTERNATE | STM_PIN_OD_BITS)
<> 138:093f2bd7b9eb 125 #define STM_MODE_ANALOG (STM_PIN_ANALOG)
<> 138:093f2bd7b9eb 126 #define STM_MODE_ANALOG_ADC_CONTROL (STM_PIN_ANALOG | STM_PIN_ANALOG_CONTROL_BIT)
<> 135:176b8275d35d 127
<> 135:176b8275d35d 128 // High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
<> 135:176b8275d35d 129 // Low nibble = pin number
<> 135:176b8275d35d 130 #define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
<> 135:176b8275d35d 131 #define STM_PIN(X) ((uint32_t)(X) & 0xF)
<> 135:176b8275d35d 132
<> 138:093f2bd7b9eb 133 /* Defines to be used by application */
<> 135:176b8275d35d 134 typedef enum {
<> 138:093f2bd7b9eb 135 PIN_INPUT = 0,
<> 135:176b8275d35d 136 PIN_OUTPUT
<> 135:176b8275d35d 137 } PinDirection;
<> 135:176b8275d35d 138
<> 135:176b8275d35d 139 typedef enum {
<> 138:093f2bd7b9eb 140 PullNone = 0,
<> 138:093f2bd7b9eb 141 PullUp = 1,
<> 138:093f2bd7b9eb 142 PullDown = 2,
<> 138:093f2bd7b9eb 143 OpenDrainPullUp = 3,
<> 138:093f2bd7b9eb 144 OpenDrainNoPull = 4,
<> 138:093f2bd7b9eb 145 OpenDrainPullDown = 5,
<> 138:093f2bd7b9eb 146 PushPullNoPull = PullNone,
<> 138:093f2bd7b9eb 147 PushPullPullUp = PullUp,
<> 138:093f2bd7b9eb 148 PushPullPullDown = PullDown,
<> 138:093f2bd7b9eb 149 OpenDrain = OpenDrainPullUp,
<> 138:093f2bd7b9eb 150 PullDefault = PullNone
<> 135:176b8275d35d 151 } PinMode;
<> 135:176b8275d35d 152
<> 135:176b8275d35d 153 #ifdef __cplusplus
<> 135:176b8275d35d 154 }
<> 135:176b8275d35d 155 #endif
<> 135:176b8275d35d 156
<> 135:176b8275d35d 157 #endif
<> 138:093f2bd7b9eb 158