mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_cmSimd.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**************************************************************************//**
<> 135:176b8275d35d 2 * @file core_cmSimd.h
<> 135:176b8275d35d 3 * @brief CMSIS Cortex-M SIMD Header File
<> 135:176b8275d35d 4 * @version V4.10
<> 135:176b8275d35d 5 * @date 18. March 2015
<> 135:176b8275d35d 6 *
<> 135:176b8275d35d 7 * @note
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 ******************************************************************************/
<> 135:176b8275d35d 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 135:176b8275d35d 11
<> 135:176b8275d35d 12 All rights reserved.
<> 135:176b8275d35d 13 Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 specific prior written permission.
<> 135:176b8275d35d 23 *
<> 135:176b8275d35d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37
<> 135:176b8275d35d 38 #if defined ( __ICCARM__ )
<> 135:176b8275d35d 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 135:176b8275d35d 40 #endif
<> 135:176b8275d35d 41
<> 135:176b8275d35d 42 #ifndef __CORE_CMSIMD_H
<> 135:176b8275d35d 43 #define __CORE_CMSIMD_H
<> 135:176b8275d35d 44
<> 135:176b8275d35d 45 #ifdef __cplusplus
<> 135:176b8275d35d 46 extern "C" {
<> 135:176b8275d35d 47 #endif
<> 135:176b8275d35d 48
<> 135:176b8275d35d 49
<> 135:176b8275d35d 50 /*******************************************************************************
<> 135:176b8275d35d 51 * Hardware Abstraction Layer
<> 135:176b8275d35d 52 ******************************************************************************/
<> 135:176b8275d35d 53
<> 135:176b8275d35d 54
<> 135:176b8275d35d 55 /* ################### Compiler specific Intrinsics ########################### */
<> 135:176b8275d35d 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
<> 135:176b8275d35d 57 Access to dedicated SIMD instructions
<> 135:176b8275d35d 58 @{
<> 135:176b8275d35d 59 */
<> 135:176b8275d35d 60
<> 135:176b8275d35d 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 135:176b8275d35d 62 /* ARM armcc specific functions */
<> 135:176b8275d35d 63 #define __SADD8 __sadd8
<> 135:176b8275d35d 64 #define __QADD8 __qadd8
<> 135:176b8275d35d 65 #define __SHADD8 __shadd8
<> 135:176b8275d35d 66 #define __UADD8 __uadd8
<> 135:176b8275d35d 67 #define __UQADD8 __uqadd8
<> 135:176b8275d35d 68 #define __UHADD8 __uhadd8
<> 135:176b8275d35d 69 #define __SSUB8 __ssub8
<> 135:176b8275d35d 70 #define __QSUB8 __qsub8
<> 135:176b8275d35d 71 #define __SHSUB8 __shsub8
<> 135:176b8275d35d 72 #define __USUB8 __usub8
<> 135:176b8275d35d 73 #define __UQSUB8 __uqsub8
<> 135:176b8275d35d 74 #define __UHSUB8 __uhsub8
<> 135:176b8275d35d 75 #define __SADD16 __sadd16
<> 135:176b8275d35d 76 #define __QADD16 __qadd16
<> 135:176b8275d35d 77 #define __SHADD16 __shadd16
<> 135:176b8275d35d 78 #define __UADD16 __uadd16
<> 135:176b8275d35d 79 #define __UQADD16 __uqadd16
<> 135:176b8275d35d 80 #define __UHADD16 __uhadd16
<> 135:176b8275d35d 81 #define __SSUB16 __ssub16
<> 135:176b8275d35d 82 #define __QSUB16 __qsub16
<> 135:176b8275d35d 83 #define __SHSUB16 __shsub16
<> 135:176b8275d35d 84 #define __USUB16 __usub16
<> 135:176b8275d35d 85 #define __UQSUB16 __uqsub16
<> 135:176b8275d35d 86 #define __UHSUB16 __uhsub16
<> 135:176b8275d35d 87 #define __SASX __sasx
<> 135:176b8275d35d 88 #define __QASX __qasx
<> 135:176b8275d35d 89 #define __SHASX __shasx
<> 135:176b8275d35d 90 #define __UASX __uasx
<> 135:176b8275d35d 91 #define __UQASX __uqasx
<> 135:176b8275d35d 92 #define __UHASX __uhasx
<> 135:176b8275d35d 93 #define __SSAX __ssax
<> 135:176b8275d35d 94 #define __QSAX __qsax
<> 135:176b8275d35d 95 #define __SHSAX __shsax
<> 135:176b8275d35d 96 #define __USAX __usax
<> 135:176b8275d35d 97 #define __UQSAX __uqsax
<> 135:176b8275d35d 98 #define __UHSAX __uhsax
<> 135:176b8275d35d 99 #define __USAD8 __usad8
<> 135:176b8275d35d 100 #define __USADA8 __usada8
<> 135:176b8275d35d 101 #define __SSAT16 __ssat16
<> 135:176b8275d35d 102 #define __USAT16 __usat16
<> 135:176b8275d35d 103 #define __UXTB16 __uxtb16
<> 135:176b8275d35d 104 #define __UXTAB16 __uxtab16
<> 135:176b8275d35d 105 #define __SXTB16 __sxtb16
<> 135:176b8275d35d 106 #define __SXTAB16 __sxtab16
<> 135:176b8275d35d 107 #define __SMUAD __smuad
<> 135:176b8275d35d 108 #define __SMUADX __smuadx
<> 135:176b8275d35d 109 #define __SMLAD __smlad
<> 135:176b8275d35d 110 #define __SMLADX __smladx
<> 135:176b8275d35d 111 #define __SMLALD __smlald
<> 135:176b8275d35d 112 #define __SMLALDX __smlaldx
<> 135:176b8275d35d 113 #define __SMUSD __smusd
<> 135:176b8275d35d 114 #define __SMUSDX __smusdx
<> 135:176b8275d35d 115 #define __SMLSD __smlsd
<> 135:176b8275d35d 116 #define __SMLSDX __smlsdx
<> 135:176b8275d35d 117 #define __SMLSLD __smlsld
<> 135:176b8275d35d 118 #define __SMLSLDX __smlsldx
<> 135:176b8275d35d 119 #define __SEL __sel
<> 135:176b8275d35d 120 #define __QADD __qadd
<> 135:176b8275d35d 121 #define __QSUB __qsub
<> 135:176b8275d35d 122
<> 135:176b8275d35d 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
<> 135:176b8275d35d 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
<> 135:176b8275d35d 125
<> 135:176b8275d35d 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
<> 135:176b8275d35d 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
<> 135:176b8275d35d 128
<> 135:176b8275d35d 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
<> 135:176b8275d35d 130 ((int64_t)(ARG3) << 32) ) >> 32))
<> 135:176b8275d35d 131
<> 135:176b8275d35d 132
<> 135:176b8275d35d 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 135:176b8275d35d 134 /* GNU gcc specific functions */
<> 135:176b8275d35d 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 136 {
<> 135:176b8275d35d 137 uint32_t result;
<> 135:176b8275d35d 138
<> 135:176b8275d35d 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 140 return(result);
<> 135:176b8275d35d 141 }
<> 135:176b8275d35d 142
<> 135:176b8275d35d 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 144 {
<> 135:176b8275d35d 145 uint32_t result;
<> 135:176b8275d35d 146
<> 135:176b8275d35d 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 148 return(result);
<> 135:176b8275d35d 149 }
<> 135:176b8275d35d 150
<> 135:176b8275d35d 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 152 {
<> 135:176b8275d35d 153 uint32_t result;
<> 135:176b8275d35d 154
<> 135:176b8275d35d 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 156 return(result);
<> 135:176b8275d35d 157 }
<> 135:176b8275d35d 158
<> 135:176b8275d35d 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 160 {
<> 135:176b8275d35d 161 uint32_t result;
<> 135:176b8275d35d 162
<> 135:176b8275d35d 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 164 return(result);
<> 135:176b8275d35d 165 }
<> 135:176b8275d35d 166
<> 135:176b8275d35d 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 168 {
<> 135:176b8275d35d 169 uint32_t result;
<> 135:176b8275d35d 170
<> 135:176b8275d35d 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 172 return(result);
<> 135:176b8275d35d 173 }
<> 135:176b8275d35d 174
<> 135:176b8275d35d 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 176 {
<> 135:176b8275d35d 177 uint32_t result;
<> 135:176b8275d35d 178
<> 135:176b8275d35d 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 180 return(result);
<> 135:176b8275d35d 181 }
<> 135:176b8275d35d 182
<> 135:176b8275d35d 183
<> 135:176b8275d35d 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 185 {
<> 135:176b8275d35d 186 uint32_t result;
<> 135:176b8275d35d 187
<> 135:176b8275d35d 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 189 return(result);
<> 135:176b8275d35d 190 }
<> 135:176b8275d35d 191
<> 135:176b8275d35d 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 193 {
<> 135:176b8275d35d 194 uint32_t result;
<> 135:176b8275d35d 195
<> 135:176b8275d35d 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 197 return(result);
<> 135:176b8275d35d 198 }
<> 135:176b8275d35d 199
<> 135:176b8275d35d 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 201 {
<> 135:176b8275d35d 202 uint32_t result;
<> 135:176b8275d35d 203
<> 135:176b8275d35d 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 205 return(result);
<> 135:176b8275d35d 206 }
<> 135:176b8275d35d 207
<> 135:176b8275d35d 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 209 {
<> 135:176b8275d35d 210 uint32_t result;
<> 135:176b8275d35d 211
<> 135:176b8275d35d 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 213 return(result);
<> 135:176b8275d35d 214 }
<> 135:176b8275d35d 215
<> 135:176b8275d35d 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 217 {
<> 135:176b8275d35d 218 uint32_t result;
<> 135:176b8275d35d 219
<> 135:176b8275d35d 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 221 return(result);
<> 135:176b8275d35d 222 }
<> 135:176b8275d35d 223
<> 135:176b8275d35d 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 225 {
<> 135:176b8275d35d 226 uint32_t result;
<> 135:176b8275d35d 227
<> 135:176b8275d35d 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 229 return(result);
<> 135:176b8275d35d 230 }
<> 135:176b8275d35d 231
<> 135:176b8275d35d 232
<> 135:176b8275d35d 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 234 {
<> 135:176b8275d35d 235 uint32_t result;
<> 135:176b8275d35d 236
<> 135:176b8275d35d 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 238 return(result);
<> 135:176b8275d35d 239 }
<> 135:176b8275d35d 240
<> 135:176b8275d35d 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 242 {
<> 135:176b8275d35d 243 uint32_t result;
<> 135:176b8275d35d 244
<> 135:176b8275d35d 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 246 return(result);
<> 135:176b8275d35d 247 }
<> 135:176b8275d35d 248
<> 135:176b8275d35d 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 250 {
<> 135:176b8275d35d 251 uint32_t result;
<> 135:176b8275d35d 252
<> 135:176b8275d35d 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 254 return(result);
<> 135:176b8275d35d 255 }
<> 135:176b8275d35d 256
<> 135:176b8275d35d 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 258 {
<> 135:176b8275d35d 259 uint32_t result;
<> 135:176b8275d35d 260
<> 135:176b8275d35d 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 262 return(result);
<> 135:176b8275d35d 263 }
<> 135:176b8275d35d 264
<> 135:176b8275d35d 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 266 {
<> 135:176b8275d35d 267 uint32_t result;
<> 135:176b8275d35d 268
<> 135:176b8275d35d 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 270 return(result);
<> 135:176b8275d35d 271 }
<> 135:176b8275d35d 272
<> 135:176b8275d35d 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 274 {
<> 135:176b8275d35d 275 uint32_t result;
<> 135:176b8275d35d 276
<> 135:176b8275d35d 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 278 return(result);
<> 135:176b8275d35d 279 }
<> 135:176b8275d35d 280
<> 135:176b8275d35d 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 282 {
<> 135:176b8275d35d 283 uint32_t result;
<> 135:176b8275d35d 284
<> 135:176b8275d35d 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 286 return(result);
<> 135:176b8275d35d 287 }
<> 135:176b8275d35d 288
<> 135:176b8275d35d 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 290 {
<> 135:176b8275d35d 291 uint32_t result;
<> 135:176b8275d35d 292
<> 135:176b8275d35d 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 294 return(result);
<> 135:176b8275d35d 295 }
<> 135:176b8275d35d 296
<> 135:176b8275d35d 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 298 {
<> 135:176b8275d35d 299 uint32_t result;
<> 135:176b8275d35d 300
<> 135:176b8275d35d 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 302 return(result);
<> 135:176b8275d35d 303 }
<> 135:176b8275d35d 304
<> 135:176b8275d35d 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 306 {
<> 135:176b8275d35d 307 uint32_t result;
<> 135:176b8275d35d 308
<> 135:176b8275d35d 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 310 return(result);
<> 135:176b8275d35d 311 }
<> 135:176b8275d35d 312
<> 135:176b8275d35d 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 314 {
<> 135:176b8275d35d 315 uint32_t result;
<> 135:176b8275d35d 316
<> 135:176b8275d35d 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 318 return(result);
<> 135:176b8275d35d 319 }
<> 135:176b8275d35d 320
<> 135:176b8275d35d 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 322 {
<> 135:176b8275d35d 323 uint32_t result;
<> 135:176b8275d35d 324
<> 135:176b8275d35d 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 326 return(result);
<> 135:176b8275d35d 327 }
<> 135:176b8275d35d 328
<> 135:176b8275d35d 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 330 {
<> 135:176b8275d35d 331 uint32_t result;
<> 135:176b8275d35d 332
<> 135:176b8275d35d 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 334 return(result);
<> 135:176b8275d35d 335 }
<> 135:176b8275d35d 336
<> 135:176b8275d35d 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 338 {
<> 135:176b8275d35d 339 uint32_t result;
<> 135:176b8275d35d 340
<> 135:176b8275d35d 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 342 return(result);
<> 135:176b8275d35d 343 }
<> 135:176b8275d35d 344
<> 135:176b8275d35d 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 346 {
<> 135:176b8275d35d 347 uint32_t result;
<> 135:176b8275d35d 348
<> 135:176b8275d35d 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 350 return(result);
<> 135:176b8275d35d 351 }
<> 135:176b8275d35d 352
<> 135:176b8275d35d 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 354 {
<> 135:176b8275d35d 355 uint32_t result;
<> 135:176b8275d35d 356
<> 135:176b8275d35d 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 358 return(result);
<> 135:176b8275d35d 359 }
<> 135:176b8275d35d 360
<> 135:176b8275d35d 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 362 {
<> 135:176b8275d35d 363 uint32_t result;
<> 135:176b8275d35d 364
<> 135:176b8275d35d 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 366 return(result);
<> 135:176b8275d35d 367 }
<> 135:176b8275d35d 368
<> 135:176b8275d35d 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 370 {
<> 135:176b8275d35d 371 uint32_t result;
<> 135:176b8275d35d 372
<> 135:176b8275d35d 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 374 return(result);
<> 135:176b8275d35d 375 }
<> 135:176b8275d35d 376
<> 135:176b8275d35d 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 378 {
<> 135:176b8275d35d 379 uint32_t result;
<> 135:176b8275d35d 380
<> 135:176b8275d35d 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 382 return(result);
<> 135:176b8275d35d 383 }
<> 135:176b8275d35d 384
<> 135:176b8275d35d 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 386 {
<> 135:176b8275d35d 387 uint32_t result;
<> 135:176b8275d35d 388
<> 135:176b8275d35d 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 390 return(result);
<> 135:176b8275d35d 391 }
<> 135:176b8275d35d 392
<> 135:176b8275d35d 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 394 {
<> 135:176b8275d35d 395 uint32_t result;
<> 135:176b8275d35d 396
<> 135:176b8275d35d 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 398 return(result);
<> 135:176b8275d35d 399 }
<> 135:176b8275d35d 400
<> 135:176b8275d35d 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 402 {
<> 135:176b8275d35d 403 uint32_t result;
<> 135:176b8275d35d 404
<> 135:176b8275d35d 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 406 return(result);
<> 135:176b8275d35d 407 }
<> 135:176b8275d35d 408
<> 135:176b8275d35d 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 410 {
<> 135:176b8275d35d 411 uint32_t result;
<> 135:176b8275d35d 412
<> 135:176b8275d35d 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 414 return(result);
<> 135:176b8275d35d 415 }
<> 135:176b8275d35d 416
<> 135:176b8275d35d 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 418 {
<> 135:176b8275d35d 419 uint32_t result;
<> 135:176b8275d35d 420
<> 135:176b8275d35d 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 422 return(result);
<> 135:176b8275d35d 423 }
<> 135:176b8275d35d 424
<> 135:176b8275d35d 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 426 {
<> 135:176b8275d35d 427 uint32_t result;
<> 135:176b8275d35d 428
<> 135:176b8275d35d 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 430 return(result);
<> 135:176b8275d35d 431 }
<> 135:176b8275d35d 432
<> 135:176b8275d35d 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 434 {
<> 135:176b8275d35d 435 uint32_t result;
<> 135:176b8275d35d 436
<> 135:176b8275d35d 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 438 return(result);
<> 135:176b8275d35d 439 }
<> 135:176b8275d35d 440
<> 135:176b8275d35d 441 #define __SSAT16(ARG1,ARG2) \
<> 135:176b8275d35d 442 ({ \
<> 135:176b8275d35d 443 uint32_t __RES, __ARG1 = (ARG1); \
<> 135:176b8275d35d 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 135:176b8275d35d 445 __RES; \
<> 135:176b8275d35d 446 })
<> 135:176b8275d35d 447
<> 135:176b8275d35d 448 #define __USAT16(ARG1,ARG2) \
<> 135:176b8275d35d 449 ({ \
<> 135:176b8275d35d 450 uint32_t __RES, __ARG1 = (ARG1); \
<> 135:176b8275d35d 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 135:176b8275d35d 452 __RES; \
<> 135:176b8275d35d 453 })
<> 135:176b8275d35d 454
<> 135:176b8275d35d 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
<> 135:176b8275d35d 456 {
<> 135:176b8275d35d 457 uint32_t result;
<> 135:176b8275d35d 458
<> 135:176b8275d35d 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 135:176b8275d35d 460 return(result);
<> 135:176b8275d35d 461 }
<> 135:176b8275d35d 462
<> 135:176b8275d35d 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 464 {
<> 135:176b8275d35d 465 uint32_t result;
<> 135:176b8275d35d 466
<> 135:176b8275d35d 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 468 return(result);
<> 135:176b8275d35d 469 }
<> 135:176b8275d35d 470
<> 135:176b8275d35d 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
<> 135:176b8275d35d 472 {
<> 135:176b8275d35d 473 uint32_t result;
<> 135:176b8275d35d 474
<> 135:176b8275d35d 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 135:176b8275d35d 476 return(result);
<> 135:176b8275d35d 477 }
<> 135:176b8275d35d 478
<> 135:176b8275d35d 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 480 {
<> 135:176b8275d35d 481 uint32_t result;
<> 135:176b8275d35d 482
<> 135:176b8275d35d 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 484 return(result);
<> 135:176b8275d35d 485 }
<> 135:176b8275d35d 486
<> 135:176b8275d35d 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 488 {
<> 135:176b8275d35d 489 uint32_t result;
<> 135:176b8275d35d 490
<> 135:176b8275d35d 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 492 return(result);
<> 135:176b8275d35d 493 }
<> 135:176b8275d35d 494
<> 135:176b8275d35d 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 496 {
<> 135:176b8275d35d 497 uint32_t result;
<> 135:176b8275d35d 498
<> 135:176b8275d35d 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 500 return(result);
<> 135:176b8275d35d 501 }
<> 135:176b8275d35d 502
<> 135:176b8275d35d 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 504 {
<> 135:176b8275d35d 505 uint32_t result;
<> 135:176b8275d35d 506
<> 135:176b8275d35d 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 508 return(result);
<> 135:176b8275d35d 509 }
<> 135:176b8275d35d 510
<> 135:176b8275d35d 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 512 {
<> 135:176b8275d35d 513 uint32_t result;
<> 135:176b8275d35d 514
<> 135:176b8275d35d 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 516 return(result);
<> 135:176b8275d35d 517 }
<> 135:176b8275d35d 518
<> 135:176b8275d35d 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
<> 135:176b8275d35d 520 {
<> 135:176b8275d35d 521 union llreg_u{
<> 135:176b8275d35d 522 uint32_t w32[2];
<> 135:176b8275d35d 523 uint64_t w64;
<> 135:176b8275d35d 524 } llr;
<> 135:176b8275d35d 525 llr.w64 = acc;
<> 135:176b8275d35d 526
<> 135:176b8275d35d 527 #ifndef __ARMEB__ // Little endian
<> 135:176b8275d35d 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 135:176b8275d35d 529 #else // Big endian
<> 135:176b8275d35d 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 135:176b8275d35d 531 #endif
<> 135:176b8275d35d 532
<> 135:176b8275d35d 533 return(llr.w64);
<> 135:176b8275d35d 534 }
<> 135:176b8275d35d 535
<> 135:176b8275d35d 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
<> 135:176b8275d35d 537 {
<> 135:176b8275d35d 538 union llreg_u{
<> 135:176b8275d35d 539 uint32_t w32[2];
<> 135:176b8275d35d 540 uint64_t w64;
<> 135:176b8275d35d 541 } llr;
<> 135:176b8275d35d 542 llr.w64 = acc;
<> 135:176b8275d35d 543
<> 135:176b8275d35d 544 #ifndef __ARMEB__ // Little endian
<> 135:176b8275d35d 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 135:176b8275d35d 546 #else // Big endian
<> 135:176b8275d35d 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 135:176b8275d35d 548 #endif
<> 135:176b8275d35d 549
<> 135:176b8275d35d 550 return(llr.w64);
<> 135:176b8275d35d 551 }
<> 135:176b8275d35d 552
<> 135:176b8275d35d 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 554 {
<> 135:176b8275d35d 555 uint32_t result;
<> 135:176b8275d35d 556
<> 135:176b8275d35d 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 558 return(result);
<> 135:176b8275d35d 559 }
<> 135:176b8275d35d 560
<> 135:176b8275d35d 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 562 {
<> 135:176b8275d35d 563 uint32_t result;
<> 135:176b8275d35d 564
<> 135:176b8275d35d 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 566 return(result);
<> 135:176b8275d35d 567 }
<> 135:176b8275d35d 568
<> 135:176b8275d35d 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 570 {
<> 135:176b8275d35d 571 uint32_t result;
<> 135:176b8275d35d 572
<> 135:176b8275d35d 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 574 return(result);
<> 135:176b8275d35d 575 }
<> 135:176b8275d35d 576
<> 135:176b8275d35d 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 578 {
<> 135:176b8275d35d 579 uint32_t result;
<> 135:176b8275d35d 580
<> 135:176b8275d35d 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 582 return(result);
<> 135:176b8275d35d 583 }
<> 135:176b8275d35d 584
<> 135:176b8275d35d 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
<> 135:176b8275d35d 586 {
<> 135:176b8275d35d 587 union llreg_u{
<> 135:176b8275d35d 588 uint32_t w32[2];
<> 135:176b8275d35d 589 uint64_t w64;
<> 135:176b8275d35d 590 } llr;
<> 135:176b8275d35d 591 llr.w64 = acc;
<> 135:176b8275d35d 592
<> 135:176b8275d35d 593 #ifndef __ARMEB__ // Little endian
<> 135:176b8275d35d 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 135:176b8275d35d 595 #else // Big endian
<> 135:176b8275d35d 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 135:176b8275d35d 597 #endif
<> 135:176b8275d35d 598
<> 135:176b8275d35d 599 return(llr.w64);
<> 135:176b8275d35d 600 }
<> 135:176b8275d35d 601
<> 135:176b8275d35d 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
<> 135:176b8275d35d 603 {
<> 135:176b8275d35d 604 union llreg_u{
<> 135:176b8275d35d 605 uint32_t w32[2];
<> 135:176b8275d35d 606 uint64_t w64;
<> 135:176b8275d35d 607 } llr;
<> 135:176b8275d35d 608 llr.w64 = acc;
<> 135:176b8275d35d 609
<> 135:176b8275d35d 610 #ifndef __ARMEB__ // Little endian
<> 135:176b8275d35d 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 135:176b8275d35d 612 #else // Big endian
<> 135:176b8275d35d 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 135:176b8275d35d 614 #endif
<> 135:176b8275d35d 615
<> 135:176b8275d35d 616 return(llr.w64);
<> 135:176b8275d35d 617 }
<> 135:176b8275d35d 618
<> 135:176b8275d35d 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 620 {
<> 135:176b8275d35d 621 uint32_t result;
<> 135:176b8275d35d 622
<> 135:176b8275d35d 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 624 return(result);
<> 135:176b8275d35d 625 }
<> 135:176b8275d35d 626
<> 135:176b8275d35d 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 628 {
<> 135:176b8275d35d 629 uint32_t result;
<> 135:176b8275d35d 630
<> 135:176b8275d35d 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 632 return(result);
<> 135:176b8275d35d 633 }
<> 135:176b8275d35d 634
<> 135:176b8275d35d 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 636 {
<> 135:176b8275d35d 637 uint32_t result;
<> 135:176b8275d35d 638
<> 135:176b8275d35d 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 640 return(result);
<> 135:176b8275d35d 641 }
<> 135:176b8275d35d 642
<> 135:176b8275d35d 643 #define __PKHBT(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 644 ({ \
<> 135:176b8275d35d 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 135:176b8275d35d 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 135:176b8275d35d 647 __RES; \
<> 135:176b8275d35d 648 })
<> 135:176b8275d35d 649
<> 135:176b8275d35d 650 #define __PKHTB(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 651 ({ \
<> 135:176b8275d35d 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 135:176b8275d35d 653 if (ARG3 == 0) \
<> 135:176b8275d35d 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
<> 135:176b8275d35d 655 else \
<> 135:176b8275d35d 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 135:176b8275d35d 657 __RES; \
<> 135:176b8275d35d 658 })
<> 135:176b8275d35d 659
<> 135:176b8275d35d 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
<> 135:176b8275d35d 661 {
<> 135:176b8275d35d 662 int32_t result;
<> 135:176b8275d35d 663
<> 135:176b8275d35d 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 665 return(result);
<> 135:176b8275d35d 666 }
<> 135:176b8275d35d 667
<> 135:176b8275d35d 668
<> 135:176b8275d35d 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 135:176b8275d35d 670 /* IAR iccarm specific functions */
<> 135:176b8275d35d 671 #include <cmsis_iar.h>
<> 135:176b8275d35d 672
<> 135:176b8275d35d 673
<> 135:176b8275d35d 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 135:176b8275d35d 675 /* TI CCS specific functions */
<> 135:176b8275d35d 676 #include <cmsis_ccs.h>
<> 135:176b8275d35d 677
<> 135:176b8275d35d 678
<> 135:176b8275d35d 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 135:176b8275d35d 680 /* TASKING carm specific functions */
<> 135:176b8275d35d 681 /* not yet supported */
<> 135:176b8275d35d 682
<> 135:176b8275d35d 683
<> 135:176b8275d35d 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 135:176b8275d35d 685 /* Cosmic specific functions */
<> 135:176b8275d35d 686 #include <cmsis_csm.h>
<> 135:176b8275d35d 687
<> 135:176b8275d35d 688 #endif
<> 135:176b8275d35d 689
<> 135:176b8275d35d 690 /*@} end of group CMSIS_SIMD_intrinsics */
<> 135:176b8275d35d 691
<> 135:176b8275d35d 692
<> 135:176b8275d35d 693 #ifdef __cplusplus
<> 135:176b8275d35d 694 }
<> 135:176b8275d35d 695 #endif
<> 135:176b8275d35d 696
<> 135:176b8275d35d 697 #endif /* __CORE_CMSIMD_H */