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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_cmInstr.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**************************************************************************//**
<> 135:176b8275d35d 2 * @file core_cmInstr.h
<> 135:176b8275d35d 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
<> 135:176b8275d35d 4 * @version V4.10
<> 135:176b8275d35d 5 * @date 18. March 2015
<> 135:176b8275d35d 6 *
<> 135:176b8275d35d 7 * @note
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 ******************************************************************************/
<> 135:176b8275d35d 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 135:176b8275d35d 11
<> 135:176b8275d35d 12 All rights reserved.
<> 135:176b8275d35d 13 Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 specific prior written permission.
<> 135:176b8275d35d 23 *
<> 135:176b8275d35d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37
<> 135:176b8275d35d 38 #ifndef __CORE_CMINSTR_H
<> 135:176b8275d35d 39 #define __CORE_CMINSTR_H
<> 135:176b8275d35d 40
<> 135:176b8275d35d 41
<> 135:176b8275d35d 42 /* ########################## Core Instruction Access ######################### */
<> 135:176b8275d35d 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
<> 135:176b8275d35d 44 Access to dedicated instructions
<> 135:176b8275d35d 45 @{
<> 135:176b8275d35d 46 */
<> 135:176b8275d35d 47
<> 135:176b8275d35d 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 135:176b8275d35d 49 /* ARM armcc specific functions */
<> 135:176b8275d35d 50
<> 135:176b8275d35d 51 #if (__ARMCC_VERSION < 400677)
<> 135:176b8275d35d 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 135:176b8275d35d 53 #endif
<> 135:176b8275d35d 54
<> 135:176b8275d35d 55
<> 135:176b8275d35d 56 /** \brief No Operation
<> 135:176b8275d35d 57
<> 135:176b8275d35d 58 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 135:176b8275d35d 59 */
<> 135:176b8275d35d 60 #define __NOP __nop
<> 135:176b8275d35d 61
<> 135:176b8275d35d 62
<> 135:176b8275d35d 63 /** \brief Wait For Interrupt
<> 135:176b8275d35d 64
<> 135:176b8275d35d 65 Wait For Interrupt is a hint instruction that suspends execution
<> 135:176b8275d35d 66 until one of a number of events occurs.
<> 135:176b8275d35d 67 */
<> 135:176b8275d35d 68 #define __WFI __wfi
<> 135:176b8275d35d 69
<> 135:176b8275d35d 70
<> 135:176b8275d35d 71 /** \brief Wait For Event
<> 135:176b8275d35d 72
<> 135:176b8275d35d 73 Wait For Event is a hint instruction that permits the processor to enter
<> 135:176b8275d35d 74 a low-power state until one of a number of events occurs.
<> 135:176b8275d35d 75 */
<> 135:176b8275d35d 76 #define __WFE __wfe
<> 135:176b8275d35d 77
<> 135:176b8275d35d 78
<> 135:176b8275d35d 79 /** \brief Send Event
<> 135:176b8275d35d 80
<> 135:176b8275d35d 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 135:176b8275d35d 82 */
<> 135:176b8275d35d 83 #define __SEV __sev
<> 135:176b8275d35d 84
<> 135:176b8275d35d 85
<> 135:176b8275d35d 86 /** \brief Instruction Synchronization Barrier
<> 135:176b8275d35d 87
<> 135:176b8275d35d 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 135:176b8275d35d 89 so that all instructions following the ISB are fetched from cache or
<> 135:176b8275d35d 90 memory, after the instruction has been completed.
<> 135:176b8275d35d 91 */
<> 135:176b8275d35d 92 #define __ISB() do {\
<> 135:176b8275d35d 93 __schedule_barrier();\
<> 135:176b8275d35d 94 __isb(0xF);\
<> 135:176b8275d35d 95 __schedule_barrier();\
<> 135:176b8275d35d 96 } while (0)
<> 135:176b8275d35d 97
<> 135:176b8275d35d 98 /** \brief Data Synchronization Barrier
<> 135:176b8275d35d 99
<> 135:176b8275d35d 100 This function acts as a special kind of Data Memory Barrier.
<> 135:176b8275d35d 101 It completes when all explicit memory accesses before this instruction complete.
<> 135:176b8275d35d 102 */
<> 135:176b8275d35d 103 #define __DSB() do {\
<> 135:176b8275d35d 104 __schedule_barrier();\
<> 135:176b8275d35d 105 __dsb(0xF);\
<> 135:176b8275d35d 106 __schedule_barrier();\
<> 135:176b8275d35d 107 } while (0)
<> 135:176b8275d35d 108
<> 135:176b8275d35d 109 /** \brief Data Memory Barrier
<> 135:176b8275d35d 110
<> 135:176b8275d35d 111 This function ensures the apparent order of the explicit memory operations before
<> 135:176b8275d35d 112 and after the instruction, without ensuring their completion.
<> 135:176b8275d35d 113 */
<> 135:176b8275d35d 114 #define __DMB() do {\
<> 135:176b8275d35d 115 __schedule_barrier();\
<> 135:176b8275d35d 116 __dmb(0xF);\
<> 135:176b8275d35d 117 __schedule_barrier();\
<> 135:176b8275d35d 118 } while (0)
<> 135:176b8275d35d 119
<> 135:176b8275d35d 120 /** \brief Reverse byte order (32 bit)
<> 135:176b8275d35d 121
<> 135:176b8275d35d 122 This function reverses the byte order in integer value.
<> 135:176b8275d35d 123
<> 135:176b8275d35d 124 \param [in] value Value to reverse
<> 135:176b8275d35d 125 \return Reversed value
<> 135:176b8275d35d 126 */
<> 135:176b8275d35d 127 #define __REV __rev
<> 135:176b8275d35d 128
<> 135:176b8275d35d 129
<> 135:176b8275d35d 130 /** \brief Reverse byte order (16 bit)
<> 135:176b8275d35d 131
<> 135:176b8275d35d 132 This function reverses the byte order in two unsigned short values.
<> 135:176b8275d35d 133
<> 135:176b8275d35d 134 \param [in] value Value to reverse
<> 135:176b8275d35d 135 \return Reversed value
<> 135:176b8275d35d 136 */
<> 135:176b8275d35d 137 #ifndef __NO_EMBEDDED_ASM
<> 135:176b8275d35d 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
<> 135:176b8275d35d 139 {
<> 135:176b8275d35d 140 rev16 r0, r0
<> 135:176b8275d35d 141 bx lr
<> 135:176b8275d35d 142 }
<> 135:176b8275d35d 143 #endif
<> 135:176b8275d35d 144
<> 135:176b8275d35d 145 /** \brief Reverse byte order in signed short value
<> 135:176b8275d35d 146
<> 135:176b8275d35d 147 This function reverses the byte order in a signed short value with sign extension to integer.
<> 135:176b8275d35d 148
<> 135:176b8275d35d 149 \param [in] value Value to reverse
<> 135:176b8275d35d 150 \return Reversed value
<> 135:176b8275d35d 151 */
<> 135:176b8275d35d 152 #ifndef __NO_EMBEDDED_ASM
<> 135:176b8275d35d 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
<> 135:176b8275d35d 154 {
<> 135:176b8275d35d 155 revsh r0, r0
<> 135:176b8275d35d 156 bx lr
<> 135:176b8275d35d 157 }
<> 135:176b8275d35d 158 #endif
<> 135:176b8275d35d 159
<> 135:176b8275d35d 160
<> 135:176b8275d35d 161 /** \brief Rotate Right in unsigned value (32 bit)
<> 135:176b8275d35d 162
<> 135:176b8275d35d 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 135:176b8275d35d 164
<> 135:176b8275d35d 165 \param [in] value Value to rotate
<> 135:176b8275d35d 166 \param [in] value Number of Bits to rotate
<> 135:176b8275d35d 167 \return Rotated value
<> 135:176b8275d35d 168 */
<> 135:176b8275d35d 169 #define __ROR __ror
<> 135:176b8275d35d 170
<> 135:176b8275d35d 171
<> 135:176b8275d35d 172 /** \brief Breakpoint
<> 135:176b8275d35d 173
<> 135:176b8275d35d 174 This function causes the processor to enter Debug state.
<> 135:176b8275d35d 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 135:176b8275d35d 176
<> 135:176b8275d35d 177 \param [in] value is ignored by the processor.
<> 135:176b8275d35d 178 If required, a debugger can use it to store additional information about the breakpoint.
<> 135:176b8275d35d 179 */
<> 135:176b8275d35d 180 #define __BKPT(value) __breakpoint(value)
<> 135:176b8275d35d 181
<> 135:176b8275d35d 182
<> 135:176b8275d35d 183 /** \brief Reverse bit order of value
<> 135:176b8275d35d 184
<> 135:176b8275d35d 185 This function reverses the bit order of the given value.
<> 135:176b8275d35d 186
<> 135:176b8275d35d 187 \param [in] value Value to reverse
<> 135:176b8275d35d 188 \return Reversed value
<> 135:176b8275d35d 189 */
<> 135:176b8275d35d 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 135:176b8275d35d 191 #define __RBIT __rbit
<> 135:176b8275d35d 192 #else
<> 135:176b8275d35d 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 135:176b8275d35d 194 {
<> 135:176b8275d35d 195 uint32_t result;
<> 135:176b8275d35d 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 135:176b8275d35d 197
<> 135:176b8275d35d 198 result = value; // r will be reversed bits of v; first get LSB of v
<> 135:176b8275d35d 199 for (value >>= 1; value; value >>= 1)
<> 135:176b8275d35d 200 {
<> 135:176b8275d35d 201 result <<= 1;
<> 135:176b8275d35d 202 result |= value & 1;
<> 135:176b8275d35d 203 s--;
<> 135:176b8275d35d 204 }
<> 135:176b8275d35d 205 result <<= s; // shift when v's highest bits are zero
<> 135:176b8275d35d 206 return(result);
<> 135:176b8275d35d 207 }
<> 135:176b8275d35d 208 #endif
<> 135:176b8275d35d 209
<> 135:176b8275d35d 210
<> 135:176b8275d35d 211 /** \brief Count leading zeros
<> 135:176b8275d35d 212
<> 135:176b8275d35d 213 This function counts the number of leading zeros of a data value.
<> 135:176b8275d35d 214
<> 135:176b8275d35d 215 \param [in] value Value to count the leading zeros
<> 135:176b8275d35d 216 \return number of leading zeros in value
<> 135:176b8275d35d 217 */
<> 135:176b8275d35d 218 #define __CLZ __clz
<> 135:176b8275d35d 219
<> 135:176b8275d35d 220
<> 135:176b8275d35d 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 135:176b8275d35d 222
<> 135:176b8275d35d 223 /** \brief LDR Exclusive (8 bit)
<> 135:176b8275d35d 224
<> 135:176b8275d35d 225 This function executes a exclusive LDR instruction for 8 bit value.
<> 135:176b8275d35d 226
<> 135:176b8275d35d 227 \param [in] ptr Pointer to data
<> 135:176b8275d35d 228 \return value of type uint8_t at (*ptr)
<> 135:176b8275d35d 229 */
<> 135:176b8275d35d 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
<> 135:176b8275d35d 231
<> 135:176b8275d35d 232
<> 135:176b8275d35d 233 /** \brief LDR Exclusive (16 bit)
<> 135:176b8275d35d 234
<> 135:176b8275d35d 235 This function executes a exclusive LDR instruction for 16 bit values.
<> 135:176b8275d35d 236
<> 135:176b8275d35d 237 \param [in] ptr Pointer to data
<> 135:176b8275d35d 238 \return value of type uint16_t at (*ptr)
<> 135:176b8275d35d 239 */
<> 135:176b8275d35d 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
<> 135:176b8275d35d 241
<> 135:176b8275d35d 242
<> 135:176b8275d35d 243 /** \brief LDR Exclusive (32 bit)
<> 135:176b8275d35d 244
<> 135:176b8275d35d 245 This function executes a exclusive LDR instruction for 32 bit values.
<> 135:176b8275d35d 246
<> 135:176b8275d35d 247 \param [in] ptr Pointer to data
<> 135:176b8275d35d 248 \return value of type uint32_t at (*ptr)
<> 135:176b8275d35d 249 */
<> 135:176b8275d35d 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
<> 135:176b8275d35d 251
<> 135:176b8275d35d 252
<> 135:176b8275d35d 253 /** \brief STR Exclusive (8 bit)
<> 135:176b8275d35d 254
<> 135:176b8275d35d 255 This function executes a exclusive STR instruction for 8 bit values.
<> 135:176b8275d35d 256
<> 135:176b8275d35d 257 \param [in] value Value to store
<> 135:176b8275d35d 258 \param [in] ptr Pointer to location
<> 135:176b8275d35d 259 \return 0 Function succeeded
<> 135:176b8275d35d 260 \return 1 Function failed
<> 135:176b8275d35d 261 */
<> 135:176b8275d35d 262 #define __STREXB(value, ptr) __strex(value, ptr)
<> 135:176b8275d35d 263
<> 135:176b8275d35d 264
<> 135:176b8275d35d 265 /** \brief STR Exclusive (16 bit)
<> 135:176b8275d35d 266
<> 135:176b8275d35d 267 This function executes a exclusive STR instruction for 16 bit values.
<> 135:176b8275d35d 268
<> 135:176b8275d35d 269 \param [in] value Value to store
<> 135:176b8275d35d 270 \param [in] ptr Pointer to location
<> 135:176b8275d35d 271 \return 0 Function succeeded
<> 135:176b8275d35d 272 \return 1 Function failed
<> 135:176b8275d35d 273 */
<> 135:176b8275d35d 274 #define __STREXH(value, ptr) __strex(value, ptr)
<> 135:176b8275d35d 275
<> 135:176b8275d35d 276
<> 135:176b8275d35d 277 /** \brief STR Exclusive (32 bit)
<> 135:176b8275d35d 278
<> 135:176b8275d35d 279 This function executes a exclusive STR instruction for 32 bit values.
<> 135:176b8275d35d 280
<> 135:176b8275d35d 281 \param [in] value Value to store
<> 135:176b8275d35d 282 \param [in] ptr Pointer to location
<> 135:176b8275d35d 283 \return 0 Function succeeded
<> 135:176b8275d35d 284 \return 1 Function failed
<> 135:176b8275d35d 285 */
<> 135:176b8275d35d 286 #define __STREXW(value, ptr) __strex(value, ptr)
<> 135:176b8275d35d 287
<> 135:176b8275d35d 288
<> 135:176b8275d35d 289 /** \brief Remove the exclusive lock
<> 135:176b8275d35d 290
<> 135:176b8275d35d 291 This function removes the exclusive lock which is created by LDREX.
<> 135:176b8275d35d 292
<> 135:176b8275d35d 293 */
<> 135:176b8275d35d 294 #define __CLREX __clrex
<> 135:176b8275d35d 295
<> 135:176b8275d35d 296
<> 135:176b8275d35d 297 /** \brief Signed Saturate
<> 135:176b8275d35d 298
<> 135:176b8275d35d 299 This function saturates a signed value.
<> 135:176b8275d35d 300
<> 135:176b8275d35d 301 \param [in] value Value to be saturated
<> 135:176b8275d35d 302 \param [in] sat Bit position to saturate to (1..32)
<> 135:176b8275d35d 303 \return Saturated value
<> 135:176b8275d35d 304 */
<> 135:176b8275d35d 305 #define __SSAT __ssat
<> 135:176b8275d35d 306
<> 135:176b8275d35d 307
<> 135:176b8275d35d 308 /** \brief Unsigned Saturate
<> 135:176b8275d35d 309
<> 135:176b8275d35d 310 This function saturates an unsigned value.
<> 135:176b8275d35d 311
<> 135:176b8275d35d 312 \param [in] value Value to be saturated
<> 135:176b8275d35d 313 \param [in] sat Bit position to saturate to (0..31)
<> 135:176b8275d35d 314 \return Saturated value
<> 135:176b8275d35d 315 */
<> 135:176b8275d35d 316 #define __USAT __usat
<> 135:176b8275d35d 317
<> 135:176b8275d35d 318
<> 135:176b8275d35d 319 /** \brief Rotate Right with Extend (32 bit)
<> 135:176b8275d35d 320
<> 135:176b8275d35d 321 This function moves each bit of a bitstring right by one bit.
<> 135:176b8275d35d 322 The carry input is shifted in at the left end of the bitstring.
<> 135:176b8275d35d 323
<> 135:176b8275d35d 324 \param [in] value Value to rotate
<> 135:176b8275d35d 325 \return Rotated value
<> 135:176b8275d35d 326 */
<> 135:176b8275d35d 327 #ifndef __NO_EMBEDDED_ASM
<> 135:176b8275d35d 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
<> 135:176b8275d35d 329 {
<> 135:176b8275d35d 330 rrx r0, r0
<> 135:176b8275d35d 331 bx lr
<> 135:176b8275d35d 332 }
<> 135:176b8275d35d 333 #endif
<> 135:176b8275d35d 334
<> 135:176b8275d35d 335
<> 135:176b8275d35d 336 /** \brief LDRT Unprivileged (8 bit)
<> 135:176b8275d35d 337
<> 135:176b8275d35d 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 135:176b8275d35d 339
<> 135:176b8275d35d 340 \param [in] ptr Pointer to data
<> 135:176b8275d35d 341 \return value of type uint8_t at (*ptr)
<> 135:176b8275d35d 342 */
<> 135:176b8275d35d 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
<> 135:176b8275d35d 344
<> 135:176b8275d35d 345
<> 135:176b8275d35d 346 /** \brief LDRT Unprivileged (16 bit)
<> 135:176b8275d35d 347
<> 135:176b8275d35d 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 135:176b8275d35d 349
<> 135:176b8275d35d 350 \param [in] ptr Pointer to data
<> 135:176b8275d35d 351 \return value of type uint16_t at (*ptr)
<> 135:176b8275d35d 352 */
<> 135:176b8275d35d 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
<> 135:176b8275d35d 354
<> 135:176b8275d35d 355
<> 135:176b8275d35d 356 /** \brief LDRT Unprivileged (32 bit)
<> 135:176b8275d35d 357
<> 135:176b8275d35d 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 135:176b8275d35d 359
<> 135:176b8275d35d 360 \param [in] ptr Pointer to data
<> 135:176b8275d35d 361 \return value of type uint32_t at (*ptr)
<> 135:176b8275d35d 362 */
<> 135:176b8275d35d 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
<> 135:176b8275d35d 364
<> 135:176b8275d35d 365
<> 135:176b8275d35d 366 /** \brief STRT Unprivileged (8 bit)
<> 135:176b8275d35d 367
<> 135:176b8275d35d 368 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 135:176b8275d35d 369
<> 135:176b8275d35d 370 \param [in] value Value to store
<> 135:176b8275d35d 371 \param [in] ptr Pointer to location
<> 135:176b8275d35d 372 */
<> 135:176b8275d35d 373 #define __STRBT(value, ptr) __strt(value, ptr)
<> 135:176b8275d35d 374
<> 135:176b8275d35d 375
<> 135:176b8275d35d 376 /** \brief STRT Unprivileged (16 bit)
<> 135:176b8275d35d 377
<> 135:176b8275d35d 378 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 135:176b8275d35d 379
<> 135:176b8275d35d 380 \param [in] value Value to store
<> 135:176b8275d35d 381 \param [in] ptr Pointer to location
<> 135:176b8275d35d 382 */
<> 135:176b8275d35d 383 #define __STRHT(value, ptr) __strt(value, ptr)
<> 135:176b8275d35d 384
<> 135:176b8275d35d 385
<> 135:176b8275d35d 386 /** \brief STRT Unprivileged (32 bit)
<> 135:176b8275d35d 387
<> 135:176b8275d35d 388 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 135:176b8275d35d 389
<> 135:176b8275d35d 390 \param [in] value Value to store
<> 135:176b8275d35d 391 \param [in] ptr Pointer to location
<> 135:176b8275d35d 392 */
<> 135:176b8275d35d 393 #define __STRT(value, ptr) __strt(value, ptr)
<> 135:176b8275d35d 394
<> 135:176b8275d35d 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 135:176b8275d35d 396
<> 135:176b8275d35d 397
<> 135:176b8275d35d 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 135:176b8275d35d 399 /* GNU gcc specific functions */
<> 135:176b8275d35d 400
<> 135:176b8275d35d 401 /* Define macros for porting to both thumb1 and thumb2.
<> 135:176b8275d35d 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
<> 135:176b8275d35d 403 * Otherwise, use general registers, specified by constrant "r" */
<> 135:176b8275d35d 404 #if defined (__thumb__) && !defined (__thumb2__)
<> 135:176b8275d35d 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
<> 135:176b8275d35d 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
<> 135:176b8275d35d 407 #else
<> 135:176b8275d35d 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
<> 135:176b8275d35d 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
<> 135:176b8275d35d 410 #endif
<> 135:176b8275d35d 411
<> 135:176b8275d35d 412 /** \brief No Operation
<> 135:176b8275d35d 413
<> 135:176b8275d35d 414 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 135:176b8275d35d 415 */
<> 135:176b8275d35d 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
<> 135:176b8275d35d 417 {
<> 135:176b8275d35d 418 __ASM volatile ("nop");
<> 135:176b8275d35d 419 }
<> 135:176b8275d35d 420
<> 135:176b8275d35d 421
<> 135:176b8275d35d 422 /** \brief Wait For Interrupt
<> 135:176b8275d35d 423
<> 135:176b8275d35d 424 Wait For Interrupt is a hint instruction that suspends execution
<> 135:176b8275d35d 425 until one of a number of events occurs.
<> 135:176b8275d35d 426 */
<> 135:176b8275d35d 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
<> 135:176b8275d35d 428 {
<> 135:176b8275d35d 429 __ASM volatile ("wfi");
<> 135:176b8275d35d 430 }
<> 135:176b8275d35d 431
<> 135:176b8275d35d 432
<> 135:176b8275d35d 433 /** \brief Wait For Event
<> 135:176b8275d35d 434
<> 135:176b8275d35d 435 Wait For Event is a hint instruction that permits the processor to enter
<> 135:176b8275d35d 436 a low-power state until one of a number of events occurs.
<> 135:176b8275d35d 437 */
<> 135:176b8275d35d 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
<> 135:176b8275d35d 439 {
<> 135:176b8275d35d 440 __ASM volatile ("wfe");
<> 135:176b8275d35d 441 }
<> 135:176b8275d35d 442
<> 135:176b8275d35d 443
<> 135:176b8275d35d 444 /** \brief Send Event
<> 135:176b8275d35d 445
<> 135:176b8275d35d 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 135:176b8275d35d 447 */
<> 135:176b8275d35d 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
<> 135:176b8275d35d 449 {
<> 135:176b8275d35d 450 __ASM volatile ("sev");
<> 135:176b8275d35d 451 }
<> 135:176b8275d35d 452
<> 135:176b8275d35d 453
<> 135:176b8275d35d 454 /** \brief Instruction Synchronization Barrier
<> 135:176b8275d35d 455
<> 135:176b8275d35d 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 135:176b8275d35d 457 so that all instructions following the ISB are fetched from cache or
<> 135:176b8275d35d 458 memory, after the instruction has been completed.
<> 135:176b8275d35d 459 */
<> 135:176b8275d35d 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
<> 135:176b8275d35d 461 {
<> 135:176b8275d35d 462 __ASM volatile ("isb 0xF":::"memory");
<> 135:176b8275d35d 463 }
<> 135:176b8275d35d 464
<> 135:176b8275d35d 465
<> 135:176b8275d35d 466 /** \brief Data Synchronization Barrier
<> 135:176b8275d35d 467
<> 135:176b8275d35d 468 This function acts as a special kind of Data Memory Barrier.
<> 135:176b8275d35d 469 It completes when all explicit memory accesses before this instruction complete.
<> 135:176b8275d35d 470 */
<> 135:176b8275d35d 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
<> 135:176b8275d35d 472 {
<> 135:176b8275d35d 473 __ASM volatile ("dsb 0xF":::"memory");
<> 135:176b8275d35d 474 }
<> 135:176b8275d35d 475
<> 135:176b8275d35d 476
<> 135:176b8275d35d 477 /** \brief Data Memory Barrier
<> 135:176b8275d35d 478
<> 135:176b8275d35d 479 This function ensures the apparent order of the explicit memory operations before
<> 135:176b8275d35d 480 and after the instruction, without ensuring their completion.
<> 135:176b8275d35d 481 */
<> 135:176b8275d35d 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
<> 135:176b8275d35d 483 {
<> 135:176b8275d35d 484 __ASM volatile ("dmb 0xF":::"memory");
<> 135:176b8275d35d 485 }
<> 135:176b8275d35d 486
<> 135:176b8275d35d 487
<> 135:176b8275d35d 488 /** \brief Reverse byte order (32 bit)
<> 135:176b8275d35d 489
<> 135:176b8275d35d 490 This function reverses the byte order in integer value.
<> 135:176b8275d35d 491
<> 135:176b8275d35d 492 \param [in] value Value to reverse
<> 135:176b8275d35d 493 \return Reversed value
<> 135:176b8275d35d 494 */
<> 135:176b8275d35d 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
<> 135:176b8275d35d 496 {
<> 135:176b8275d35d 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
<> 135:176b8275d35d 498 return __builtin_bswap32(value);
<> 135:176b8275d35d 499 #else
<> 135:176b8275d35d 500 uint32_t result;
<> 135:176b8275d35d 501
<> 135:176b8275d35d 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 135:176b8275d35d 503 return(result);
<> 135:176b8275d35d 504 #endif
<> 135:176b8275d35d 505 }
<> 135:176b8275d35d 506
<> 135:176b8275d35d 507
<> 135:176b8275d35d 508 /** \brief Reverse byte order (16 bit)
<> 135:176b8275d35d 509
<> 135:176b8275d35d 510 This function reverses the byte order in two unsigned short values.
<> 135:176b8275d35d 511
<> 135:176b8275d35d 512 \param [in] value Value to reverse
<> 135:176b8275d35d 513 \return Reversed value
<> 135:176b8275d35d 514 */
<> 135:176b8275d35d 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
<> 135:176b8275d35d 516 {
<> 135:176b8275d35d 517 uint32_t result;
<> 135:176b8275d35d 518
<> 135:176b8275d35d 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 135:176b8275d35d 520 return(result);
<> 135:176b8275d35d 521 }
<> 135:176b8275d35d 522
<> 135:176b8275d35d 523
<> 135:176b8275d35d 524 /** \brief Reverse byte order in signed short value
<> 135:176b8275d35d 525
<> 135:176b8275d35d 526 This function reverses the byte order in a signed short value with sign extension to integer.
<> 135:176b8275d35d 527
<> 135:176b8275d35d 528 \param [in] value Value to reverse
<> 135:176b8275d35d 529 \return Reversed value
<> 135:176b8275d35d 530 */
<> 135:176b8275d35d 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
<> 135:176b8275d35d 532 {
<> 135:176b8275d35d 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 135:176b8275d35d 534 return (short)__builtin_bswap16(value);
<> 135:176b8275d35d 535 #else
<> 135:176b8275d35d 536 uint32_t result;
<> 135:176b8275d35d 537
<> 135:176b8275d35d 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 135:176b8275d35d 539 return(result);
<> 135:176b8275d35d 540 #endif
<> 135:176b8275d35d 541 }
<> 135:176b8275d35d 542
<> 135:176b8275d35d 543
<> 135:176b8275d35d 544 /** \brief Rotate Right in unsigned value (32 bit)
<> 135:176b8275d35d 545
<> 135:176b8275d35d 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 135:176b8275d35d 547
<> 135:176b8275d35d 548 \param [in] value Value to rotate
<> 135:176b8275d35d 549 \param [in] value Number of Bits to rotate
<> 135:176b8275d35d 550 \return Rotated value
<> 135:176b8275d35d 551 */
<> 135:176b8275d35d 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 553 {
<> 135:176b8275d35d 554 return (op1 >> op2) | (op1 << (32 - op2));
<> 135:176b8275d35d 555 }
<> 135:176b8275d35d 556
<> 135:176b8275d35d 557
<> 135:176b8275d35d 558 /** \brief Breakpoint
<> 135:176b8275d35d 559
<> 135:176b8275d35d 560 This function causes the processor to enter Debug state.
<> 135:176b8275d35d 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 135:176b8275d35d 562
<> 135:176b8275d35d 563 \param [in] value is ignored by the processor.
<> 135:176b8275d35d 564 If required, a debugger can use it to store additional information about the breakpoint.
<> 135:176b8275d35d 565 */
<> 135:176b8275d35d 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
<> 135:176b8275d35d 567
<> 135:176b8275d35d 568
<> 135:176b8275d35d 569 /** \brief Reverse bit order of value
<> 135:176b8275d35d 570
<> 135:176b8275d35d 571 This function reverses the bit order of the given value.
<> 135:176b8275d35d 572
<> 135:176b8275d35d 573 \param [in] value Value to reverse
<> 135:176b8275d35d 574 \return Reversed value
<> 135:176b8275d35d 575 */
<> 135:176b8275d35d 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 135:176b8275d35d 577 {
<> 135:176b8275d35d 578 uint32_t result;
<> 135:176b8275d35d 579
<> 135:176b8275d35d 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 135:176b8275d35d 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
<> 135:176b8275d35d 582 #else
<> 135:176b8275d35d 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 135:176b8275d35d 584
<> 135:176b8275d35d 585 result = value; // r will be reversed bits of v; first get LSB of v
<> 135:176b8275d35d 586 for (value >>= 1; value; value >>= 1)
<> 135:176b8275d35d 587 {
<> 135:176b8275d35d 588 result <<= 1;
<> 135:176b8275d35d 589 result |= value & 1;
<> 135:176b8275d35d 590 s--;
<> 135:176b8275d35d 591 }
<> 135:176b8275d35d 592 result <<= s; // shift when v's highest bits are zero
<> 135:176b8275d35d 593 #endif
<> 135:176b8275d35d 594 return(result);
<> 135:176b8275d35d 595 }
<> 135:176b8275d35d 596
<> 135:176b8275d35d 597
<> 135:176b8275d35d 598 /** \brief Count leading zeros
<> 135:176b8275d35d 599
<> 135:176b8275d35d 600 This function counts the number of leading zeros of a data value.
<> 135:176b8275d35d 601
<> 135:176b8275d35d 602 \param [in] value Value to count the leading zeros
<> 135:176b8275d35d 603 \return number of leading zeros in value
<> 135:176b8275d35d 604 */
<> 135:176b8275d35d 605 #define __CLZ __builtin_clz
<> 135:176b8275d35d 606
<> 135:176b8275d35d 607
<> 135:176b8275d35d 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 135:176b8275d35d 609
<> 135:176b8275d35d 610 /** \brief LDR Exclusive (8 bit)
<> 135:176b8275d35d 611
<> 135:176b8275d35d 612 This function executes a exclusive LDR instruction for 8 bit value.
<> 135:176b8275d35d 613
<> 135:176b8275d35d 614 \param [in] ptr Pointer to data
<> 135:176b8275d35d 615 \return value of type uint8_t at (*ptr)
<> 135:176b8275d35d 616 */
<> 135:176b8275d35d 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
<> 135:176b8275d35d 618 {
<> 135:176b8275d35d 619 uint32_t result;
<> 135:176b8275d35d 620
<> 135:176b8275d35d 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 135:176b8275d35d 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
<> 135:176b8275d35d 623 #else
<> 135:176b8275d35d 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 135:176b8275d35d 625 accepted by assembler. So has to use following less efficient pattern.
<> 135:176b8275d35d 626 */
<> 135:176b8275d35d 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 135:176b8275d35d 628 #endif
<> 135:176b8275d35d 629 return ((uint8_t) result); /* Add explicit type cast here */
<> 135:176b8275d35d 630 }
<> 135:176b8275d35d 631
<> 135:176b8275d35d 632
<> 135:176b8275d35d 633 /** \brief LDR Exclusive (16 bit)
<> 135:176b8275d35d 634
<> 135:176b8275d35d 635 This function executes a exclusive LDR instruction for 16 bit values.
<> 135:176b8275d35d 636
<> 135:176b8275d35d 637 \param [in] ptr Pointer to data
<> 135:176b8275d35d 638 \return value of type uint16_t at (*ptr)
<> 135:176b8275d35d 639 */
<> 135:176b8275d35d 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
<> 135:176b8275d35d 641 {
<> 135:176b8275d35d 642 uint32_t result;
<> 135:176b8275d35d 643
<> 135:176b8275d35d 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 135:176b8275d35d 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
<> 135:176b8275d35d 646 #else
<> 135:176b8275d35d 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 135:176b8275d35d 648 accepted by assembler. So has to use following less efficient pattern.
<> 135:176b8275d35d 649 */
<> 135:176b8275d35d 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 135:176b8275d35d 651 #endif
<> 135:176b8275d35d 652 return ((uint16_t) result); /* Add explicit type cast here */
<> 135:176b8275d35d 653 }
<> 135:176b8275d35d 654
<> 135:176b8275d35d 655
<> 135:176b8275d35d 656 /** \brief LDR Exclusive (32 bit)
<> 135:176b8275d35d 657
<> 135:176b8275d35d 658 This function executes a exclusive LDR instruction for 32 bit values.
<> 135:176b8275d35d 659
<> 135:176b8275d35d 660 \param [in] ptr Pointer to data
<> 135:176b8275d35d 661 \return value of type uint32_t at (*ptr)
<> 135:176b8275d35d 662 */
<> 135:176b8275d35d 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
<> 135:176b8275d35d 664 {
<> 135:176b8275d35d 665 uint32_t result;
<> 135:176b8275d35d 666
<> 135:176b8275d35d 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
<> 135:176b8275d35d 668 return(result);
<> 135:176b8275d35d 669 }
<> 135:176b8275d35d 670
<> 135:176b8275d35d 671
<> 135:176b8275d35d 672 /** \brief STR Exclusive (8 bit)
<> 135:176b8275d35d 673
<> 135:176b8275d35d 674 This function executes a exclusive STR instruction for 8 bit values.
<> 135:176b8275d35d 675
<> 135:176b8275d35d 676 \param [in] value Value to store
<> 135:176b8275d35d 677 \param [in] ptr Pointer to location
<> 135:176b8275d35d 678 \return 0 Function succeeded
<> 135:176b8275d35d 679 \return 1 Function failed
<> 135:176b8275d35d 680 */
<> 135:176b8275d35d 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
<> 135:176b8275d35d 682 {
<> 135:176b8275d35d 683 uint32_t result;
<> 135:176b8275d35d 684
<> 135:176b8275d35d 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 135:176b8275d35d 686 return(result);
<> 135:176b8275d35d 687 }
<> 135:176b8275d35d 688
<> 135:176b8275d35d 689
<> 135:176b8275d35d 690 /** \brief STR Exclusive (16 bit)
<> 135:176b8275d35d 691
<> 135:176b8275d35d 692 This function executes a exclusive STR instruction for 16 bit values.
<> 135:176b8275d35d 693
<> 135:176b8275d35d 694 \param [in] value Value to store
<> 135:176b8275d35d 695 \param [in] ptr Pointer to location
<> 135:176b8275d35d 696 \return 0 Function succeeded
<> 135:176b8275d35d 697 \return 1 Function failed
<> 135:176b8275d35d 698 */
<> 135:176b8275d35d 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
<> 135:176b8275d35d 700 {
<> 135:176b8275d35d 701 uint32_t result;
<> 135:176b8275d35d 702
<> 135:176b8275d35d 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 135:176b8275d35d 704 return(result);
<> 135:176b8275d35d 705 }
<> 135:176b8275d35d 706
<> 135:176b8275d35d 707
<> 135:176b8275d35d 708 /** \brief STR Exclusive (32 bit)
<> 135:176b8275d35d 709
<> 135:176b8275d35d 710 This function executes a exclusive STR instruction for 32 bit values.
<> 135:176b8275d35d 711
<> 135:176b8275d35d 712 \param [in] value Value to store
<> 135:176b8275d35d 713 \param [in] ptr Pointer to location
<> 135:176b8275d35d 714 \return 0 Function succeeded
<> 135:176b8275d35d 715 \return 1 Function failed
<> 135:176b8275d35d 716 */
<> 135:176b8275d35d 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
<> 135:176b8275d35d 718 {
<> 135:176b8275d35d 719 uint32_t result;
<> 135:176b8275d35d 720
<> 135:176b8275d35d 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
<> 135:176b8275d35d 722 return(result);
<> 135:176b8275d35d 723 }
<> 135:176b8275d35d 724
<> 135:176b8275d35d 725
<> 135:176b8275d35d 726 /** \brief Remove the exclusive lock
<> 135:176b8275d35d 727
<> 135:176b8275d35d 728 This function removes the exclusive lock which is created by LDREX.
<> 135:176b8275d35d 729
<> 135:176b8275d35d 730 */
<> 135:176b8275d35d 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
<> 135:176b8275d35d 732 {
<> 135:176b8275d35d 733 __ASM volatile ("clrex" ::: "memory");
<> 135:176b8275d35d 734 }
<> 135:176b8275d35d 735
<> 135:176b8275d35d 736
<> 135:176b8275d35d 737 /** \brief Signed Saturate
<> 135:176b8275d35d 738
<> 135:176b8275d35d 739 This function saturates a signed value.
<> 135:176b8275d35d 740
<> 135:176b8275d35d 741 \param [in] value Value to be saturated
<> 135:176b8275d35d 742 \param [in] sat Bit position to saturate to (1..32)
<> 135:176b8275d35d 743 \return Saturated value
<> 135:176b8275d35d 744 */
<> 135:176b8275d35d 745 #define __SSAT(ARG1,ARG2) \
<> 135:176b8275d35d 746 ({ \
<> 135:176b8275d35d 747 uint32_t __RES, __ARG1 = (ARG1); \
<> 135:176b8275d35d 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 135:176b8275d35d 749 __RES; \
<> 135:176b8275d35d 750 })
<> 135:176b8275d35d 751
<> 135:176b8275d35d 752
<> 135:176b8275d35d 753 /** \brief Unsigned Saturate
<> 135:176b8275d35d 754
<> 135:176b8275d35d 755 This function saturates an unsigned value.
<> 135:176b8275d35d 756
<> 135:176b8275d35d 757 \param [in] value Value to be saturated
<> 135:176b8275d35d 758 \param [in] sat Bit position to saturate to (0..31)
<> 135:176b8275d35d 759 \return Saturated value
<> 135:176b8275d35d 760 */
<> 135:176b8275d35d 761 #define __USAT(ARG1,ARG2) \
<> 135:176b8275d35d 762 ({ \
<> 135:176b8275d35d 763 uint32_t __RES, __ARG1 = (ARG1); \
<> 135:176b8275d35d 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 135:176b8275d35d 765 __RES; \
<> 135:176b8275d35d 766 })
<> 135:176b8275d35d 767
<> 135:176b8275d35d 768
<> 135:176b8275d35d 769 /** \brief Rotate Right with Extend (32 bit)
<> 135:176b8275d35d 770
<> 135:176b8275d35d 771 This function moves each bit of a bitstring right by one bit.
<> 135:176b8275d35d 772 The carry input is shifted in at the left end of the bitstring.
<> 135:176b8275d35d 773
<> 135:176b8275d35d 774 \param [in] value Value to rotate
<> 135:176b8275d35d 775 \return Rotated value
<> 135:176b8275d35d 776 */
<> 135:176b8275d35d 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
<> 135:176b8275d35d 778 {
<> 135:176b8275d35d 779 uint32_t result;
<> 135:176b8275d35d 780
<> 135:176b8275d35d 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 135:176b8275d35d 782 return(result);
<> 135:176b8275d35d 783 }
<> 135:176b8275d35d 784
<> 135:176b8275d35d 785
<> 135:176b8275d35d 786 /** \brief LDRT Unprivileged (8 bit)
<> 135:176b8275d35d 787
<> 135:176b8275d35d 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 135:176b8275d35d 789
<> 135:176b8275d35d 790 \param [in] ptr Pointer to data
<> 135:176b8275d35d 791 \return value of type uint8_t at (*ptr)
<> 135:176b8275d35d 792 */
<> 135:176b8275d35d 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
<> 135:176b8275d35d 794 {
<> 135:176b8275d35d 795 uint32_t result;
<> 135:176b8275d35d 796
<> 135:176b8275d35d 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 135:176b8275d35d 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 135:176b8275d35d 799 #else
<> 135:176b8275d35d 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 135:176b8275d35d 801 accepted by assembler. So has to use following less efficient pattern.
<> 135:176b8275d35d 802 */
<> 135:176b8275d35d 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 135:176b8275d35d 804 #endif
<> 135:176b8275d35d 805 return ((uint8_t) result); /* Add explicit type cast here */
<> 135:176b8275d35d 806 }
<> 135:176b8275d35d 807
<> 135:176b8275d35d 808
<> 135:176b8275d35d 809 /** \brief LDRT Unprivileged (16 bit)
<> 135:176b8275d35d 810
<> 135:176b8275d35d 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 135:176b8275d35d 812
<> 135:176b8275d35d 813 \param [in] ptr Pointer to data
<> 135:176b8275d35d 814 \return value of type uint16_t at (*ptr)
<> 135:176b8275d35d 815 */
<> 135:176b8275d35d 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
<> 135:176b8275d35d 817 {
<> 135:176b8275d35d 818 uint32_t result;
<> 135:176b8275d35d 819
<> 135:176b8275d35d 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 135:176b8275d35d 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
<> 135:176b8275d35d 822 #else
<> 135:176b8275d35d 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 135:176b8275d35d 824 accepted by assembler. So has to use following less efficient pattern.
<> 135:176b8275d35d 825 */
<> 135:176b8275d35d 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 135:176b8275d35d 827 #endif
<> 135:176b8275d35d 828 return ((uint16_t) result); /* Add explicit type cast here */
<> 135:176b8275d35d 829 }
<> 135:176b8275d35d 830
<> 135:176b8275d35d 831
<> 135:176b8275d35d 832 /** \brief LDRT Unprivileged (32 bit)
<> 135:176b8275d35d 833
<> 135:176b8275d35d 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 135:176b8275d35d 835
<> 135:176b8275d35d 836 \param [in] ptr Pointer to data
<> 135:176b8275d35d 837 \return value of type uint32_t at (*ptr)
<> 135:176b8275d35d 838 */
<> 135:176b8275d35d 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
<> 135:176b8275d35d 840 {
<> 135:176b8275d35d 841 uint32_t result;
<> 135:176b8275d35d 842
<> 135:176b8275d35d 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 135:176b8275d35d 844 return(result);
<> 135:176b8275d35d 845 }
<> 135:176b8275d35d 846
<> 135:176b8275d35d 847
<> 135:176b8275d35d 848 /** \brief STRT Unprivileged (8 bit)
<> 135:176b8275d35d 849
<> 135:176b8275d35d 850 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 135:176b8275d35d 851
<> 135:176b8275d35d 852 \param [in] value Value to store
<> 135:176b8275d35d 853 \param [in] ptr Pointer to location
<> 135:176b8275d35d 854 */
<> 135:176b8275d35d 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
<> 135:176b8275d35d 856 {
<> 135:176b8275d35d 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 135:176b8275d35d 858 }
<> 135:176b8275d35d 859
<> 135:176b8275d35d 860
<> 135:176b8275d35d 861 /** \brief STRT Unprivileged (16 bit)
<> 135:176b8275d35d 862
<> 135:176b8275d35d 863 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 135:176b8275d35d 864
<> 135:176b8275d35d 865 \param [in] value Value to store
<> 135:176b8275d35d 866 \param [in] ptr Pointer to location
<> 135:176b8275d35d 867 */
<> 135:176b8275d35d 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
<> 135:176b8275d35d 869 {
<> 135:176b8275d35d 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 135:176b8275d35d 871 }
<> 135:176b8275d35d 872
<> 135:176b8275d35d 873
<> 135:176b8275d35d 874 /** \brief STRT Unprivileged (32 bit)
<> 135:176b8275d35d 875
<> 135:176b8275d35d 876 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 135:176b8275d35d 877
<> 135:176b8275d35d 878 \param [in] value Value to store
<> 135:176b8275d35d 879 \param [in] ptr Pointer to location
<> 135:176b8275d35d 880 */
<> 135:176b8275d35d 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
<> 135:176b8275d35d 882 {
<> 135:176b8275d35d 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
<> 135:176b8275d35d 884 }
<> 135:176b8275d35d 885
<> 135:176b8275d35d 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 135:176b8275d35d 887
<> 135:176b8275d35d 888
<> 135:176b8275d35d 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 135:176b8275d35d 890 /* IAR iccarm specific functions */
<> 135:176b8275d35d 891 #include <cmsis_iar.h>
<> 135:176b8275d35d 892
<> 135:176b8275d35d 893
<> 135:176b8275d35d 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 135:176b8275d35d 895 /* TI CCS specific functions */
<> 135:176b8275d35d 896 #include <cmsis_ccs.h>
<> 135:176b8275d35d 897
<> 135:176b8275d35d 898
<> 135:176b8275d35d 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 135:176b8275d35d 900 /* TASKING carm specific functions */
<> 135:176b8275d35d 901 /*
<> 135:176b8275d35d 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 135:176b8275d35d 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 135:176b8275d35d 904 * Including the CMSIS ones.
<> 135:176b8275d35d 905 */
<> 135:176b8275d35d 906
<> 135:176b8275d35d 907
<> 135:176b8275d35d 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 135:176b8275d35d 909 /* Cosmic specific functions */
<> 135:176b8275d35d 910 #include <cmsis_csm.h>
<> 135:176b8275d35d 911
<> 135:176b8275d35d 912 #endif
<> 135:176b8275d35d 913
<> 135:176b8275d35d 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
<> 135:176b8275d35d 915
<> 135:176b8275d35d 916 #endif /* __CORE_CMINSTR_H */