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TARGET_MAX32630FTHR/core_cm7.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:: <>
Date:: Tue Mar 14 16:20:51 2017 +0000
Revision:: 138:093f2bd7b9eb
Parent:: 135:176b8275d35d
Child:: 145:64910690c574

Release 138 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	135:176b8275d35d	1	/************************************************************************//
<>	135:176b8275d35d	2	* @file core_cm7.h
<>	135:176b8275d35d	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
<>	135:176b8275d35d	4	* @version V4.10
<>	135:176b8275d35d	5	* @date 18. March 2015
<>	135:176b8275d35d	6	*
<>	135:176b8275d35d	7	* @note
<>	135:176b8275d35d	8	*
<>	135:176b8275d35d	9	******************************************************************************/
<>	135:176b8275d35d	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
<>	135:176b8275d35d	11
<>	135:176b8275d35d	12	All rights reserved.
<>	135:176b8275d35d	13	Redistribution and use in source and binary forms, with or without
<>	135:176b8275d35d	14	modification, are permitted provided that the following conditions are met:
<>	135:176b8275d35d	15	- Redistributions of source code must retain the above copyright
<>	135:176b8275d35d	16	notice, this list of conditions and the following disclaimer.
<>	135:176b8275d35d	17	- Redistributions in binary form must reproduce the above copyright
<>	135:176b8275d35d	18	notice, this list of conditions and the following disclaimer in the
<>	135:176b8275d35d	19	documentation and/or other materials provided with the distribution.
<>	135:176b8275d35d	20	- Neither the name of ARM nor the names of its contributors may be used
<>	135:176b8275d35d	21	to endorse or promote products derived from this software without
<>	135:176b8275d35d	22	specific prior written permission.
<>	135:176b8275d35d	23	*
<>	135:176b8275d35d	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	135:176b8275d35d	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	135:176b8275d35d	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<>	135:176b8275d35d	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<>	135:176b8275d35d	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<>	135:176b8275d35d	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<>	135:176b8275d35d	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<>	135:176b8275d35d	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<>	135:176b8275d35d	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<>	135:176b8275d35d	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<>	135:176b8275d35d	34	POSSIBILITY OF SUCH DAMAGE.
<>	135:176b8275d35d	35	---------------------------------------------------------------------------*/
<>	135:176b8275d35d	36
<>	135:176b8275d35d	37
<>	135:176b8275d35d	38	#if defined ( __ICCARM__ )
<>	135:176b8275d35d	39	#pragma system_include /* treat file as system include file for MISRA check */
<>	135:176b8275d35d	40	#endif
<>	135:176b8275d35d	41
<>	135:176b8275d35d	42	#ifndef __CORE_CM7_H_GENERIC
<>	135:176b8275d35d	43	#define __CORE_CM7_H_GENERIC
<>	135:176b8275d35d	44
<>	135:176b8275d35d	45	#ifdef __cplusplus
<>	135:176b8275d35d	46	extern "C" {
<>	135:176b8275d35d	47	#endif
<>	135:176b8275d35d	48
<>	135:176b8275d35d	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<>	135:176b8275d35d	50	CMSIS violates the following MISRA-C:2004 rules:
<>	135:176b8275d35d	51
<>	135:176b8275d35d	52	\li Required Rule 8.5, object/function definition in header file.<br>
<>	135:176b8275d35d	53	Function definitions in header files are used to allow 'inlining'.
<>	135:176b8275d35d	54
<>	135:176b8275d35d	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<>	135:176b8275d35d	56	Unions are used for effective representation of core registers.
<>	135:176b8275d35d	57
<>	135:176b8275d35d	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
<>	135:176b8275d35d	59	Function-like macros are used to allow more efficient code.
<>	135:176b8275d35d	60	*/
<>	135:176b8275d35d	61
<>	135:176b8275d35d	62
<>	135:176b8275d35d	63	/*******************************************************************************
<>	135:176b8275d35d	64	* CMSIS definitions
<>	135:176b8275d35d	65	******************************************************************************/
<>	135:176b8275d35d	66	/** \ingroup Cortex_M7
<>	135:176b8275d35d	67	@{
<>	135:176b8275d35d	68	*/
<>	135:176b8275d35d	69
<>	135:176b8275d35d	70	/* CMSIS CM7 definitions */
<>	135:176b8275d35d	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
<>	135:176b8275d35d	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
<>	135:176b8275d35d	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
<>	135:176b8275d35d	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
<>	135:176b8275d35d	75
<>	135:176b8275d35d	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
<>	135:176b8275d35d	77
<>	135:176b8275d35d	78
<>	135:176b8275d35d	79	#if defined ( __CC_ARM )
<>	135:176b8275d35d	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
<>	135:176b8275d35d	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
<>	135:176b8275d35d	82	#define __STATIC_INLINE static __inline
<>	135:176b8275d35d	83
<>	135:176b8275d35d	84	#elif defined ( __GNUC__ )
<>	135:176b8275d35d	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
<>	135:176b8275d35d	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
<>	135:176b8275d35d	87	#define __STATIC_INLINE static inline
<>	135:176b8275d35d	88
<>	135:176b8275d35d	89	#elif defined ( __ICCARM__ )
<>	135:176b8275d35d	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
<>	135:176b8275d35d	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
<>	135:176b8275d35d	92	#define __STATIC_INLINE static inline
<>	135:176b8275d35d	93
<>	135:176b8275d35d	94	#elif defined ( __TMS470__ )
<>	135:176b8275d35d	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
<>	135:176b8275d35d	96	#define __STATIC_INLINE static inline
<>	135:176b8275d35d	97
<>	135:176b8275d35d	98	#elif defined ( __TASKING__ )
<>	135:176b8275d35d	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
<>	135:176b8275d35d	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
<>	135:176b8275d35d	101	#define __STATIC_INLINE static inline
<>	135:176b8275d35d	102
<>	135:176b8275d35d	103	#elif defined ( __CSMC__ )
<>	135:176b8275d35d	104	#define __packed
<>	135:176b8275d35d	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
<>	135:176b8275d35d	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
<>	135:176b8275d35d	107	#define __STATIC_INLINE static inline
<>	135:176b8275d35d	108
<>	135:176b8275d35d	109	#endif
<>	135:176b8275d35d	110
<>	135:176b8275d35d	111	/** __FPU_USED indicates whether an FPU is used or not.
<>	135:176b8275d35d	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<>	135:176b8275d35d	113	*/
<>	135:176b8275d35d	114	#if defined ( __CC_ARM )
<>	135:176b8275d35d	115	#if defined __TARGET_FPU_VFP
<>	135:176b8275d35d	116	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	117	#define __FPU_USED 1
<>	135:176b8275d35d	118	#else
<>	135:176b8275d35d	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	135:176b8275d35d	120	#define __FPU_USED 0
<>	135:176b8275d35d	121	#endif
<>	135:176b8275d35d	122	#else
<>	135:176b8275d35d	123	#define __FPU_USED 0
<>	135:176b8275d35d	124	#endif
<>	135:176b8275d35d	125
<>	135:176b8275d35d	126	#elif defined ( __GNUC__ )
<>	135:176b8275d35d	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
<>	135:176b8275d35d	128	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	129	#define __FPU_USED 1
<>	135:176b8275d35d	130	#else
<>	135:176b8275d35d	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	135:176b8275d35d	132	#define __FPU_USED 0
<>	135:176b8275d35d	133	#endif
<>	135:176b8275d35d	134	#else
<>	135:176b8275d35d	135	#define __FPU_USED 0
<>	135:176b8275d35d	136	#endif
<>	135:176b8275d35d	137
<>	135:176b8275d35d	138	#elif defined ( __ICCARM__ )
<>	135:176b8275d35d	139	#if defined __ARMVFP__
<>	135:176b8275d35d	140	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	141	#define __FPU_USED 1
<>	135:176b8275d35d	142	#else
<>	135:176b8275d35d	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	135:176b8275d35d	144	#define __FPU_USED 0
<>	135:176b8275d35d	145	#endif
<>	135:176b8275d35d	146	#else
<>	135:176b8275d35d	147	#define __FPU_USED 0
<>	135:176b8275d35d	148	#endif
<>	135:176b8275d35d	149
<>	135:176b8275d35d	150	#elif defined ( __TMS470__ )
<>	135:176b8275d35d	151	#if defined __TI_VFP_SUPPORT__
<>	135:176b8275d35d	152	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	153	#define __FPU_USED 1
<>	135:176b8275d35d	154	#else
<>	135:176b8275d35d	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	135:176b8275d35d	156	#define __FPU_USED 0
<>	135:176b8275d35d	157	#endif
<>	135:176b8275d35d	158	#else
<>	135:176b8275d35d	159	#define __FPU_USED 0
<>	135:176b8275d35d	160	#endif
<>	135:176b8275d35d	161
<>	135:176b8275d35d	162	#elif defined ( __TASKING__ )
<>	135:176b8275d35d	163	#if defined __FPU_VFP__
<>	135:176b8275d35d	164	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	165	#define __FPU_USED 1
<>	135:176b8275d35d	166	#else
<>	135:176b8275d35d	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	135:176b8275d35d	168	#define __FPU_USED 0
<>	135:176b8275d35d	169	#endif
<>	135:176b8275d35d	170	#else
<>	135:176b8275d35d	171	#define __FPU_USED 0
<>	135:176b8275d35d	172	#endif
<>	135:176b8275d35d	173
<>	135:176b8275d35d	174	#elif defined ( __CSMC__ ) /* Cosmic */
<>	135:176b8275d35d	175	#if ( __CSMC__ & 0x400) // FPU present for parser
<>	135:176b8275d35d	176	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	177	#define __FPU_USED 1
<>	135:176b8275d35d	178	#else
<>	135:176b8275d35d	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	135:176b8275d35d	180	#define __FPU_USED 0
<>	135:176b8275d35d	181	#endif
<>	135:176b8275d35d	182	#else
<>	135:176b8275d35d	183	#define __FPU_USED 0
<>	135:176b8275d35d	184	#endif
<>	135:176b8275d35d	185	#endif
<>	135:176b8275d35d	186
<>	135:176b8275d35d	187	#include <stdint.h> /* standard types definitions */
<>	135:176b8275d35d	188	#include <core_cmInstr.h> /* Core Instruction Access */
<>	135:176b8275d35d	189	#include <core_cmFunc.h> /* Core Function Access */
<>	135:176b8275d35d	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
<>	135:176b8275d35d	191
<>	135:176b8275d35d	192	#ifdef __cplusplus
<>	135:176b8275d35d	193	}
<>	135:176b8275d35d	194	#endif
<>	135:176b8275d35d	195
<>	135:176b8275d35d	196	#endif /* __CORE_CM7_H_GENERIC */
<>	135:176b8275d35d	197
<>	135:176b8275d35d	198	#ifndef __CMSIS_GENERIC
<>	135:176b8275d35d	199
<>	135:176b8275d35d	200	#ifndef __CORE_CM7_H_DEPENDANT
<>	135:176b8275d35d	201	#define __CORE_CM7_H_DEPENDANT
<>	135:176b8275d35d	202
<>	135:176b8275d35d	203	#ifdef __cplusplus
<>	135:176b8275d35d	204	extern "C" {
<>	135:176b8275d35d	205	#endif
<>	135:176b8275d35d	206
<>	135:176b8275d35d	207	/* check device defines and use defaults */
<>	135:176b8275d35d	208	#if defined __CHECK_DEVICE_DEFINES
<>	135:176b8275d35d	209	#ifndef __CM7_REV
<>	135:176b8275d35d	210	#define __CM7_REV 0x0000
<>	135:176b8275d35d	211	#warning "__CM7_REV not defined in device header file; using default!"
<>	135:176b8275d35d	212	#endif
<>	135:176b8275d35d	213
<>	135:176b8275d35d	214	#ifndef __FPU_PRESENT
<>	135:176b8275d35d	215	#define __FPU_PRESENT 0
<>	135:176b8275d35d	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
<>	135:176b8275d35d	217	#endif
<>	135:176b8275d35d	218
<>	135:176b8275d35d	219	#ifndef __MPU_PRESENT
<>	135:176b8275d35d	220	#define __MPU_PRESENT 0
<>	135:176b8275d35d	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
<>	135:176b8275d35d	222	#endif
<>	135:176b8275d35d	223
<>	135:176b8275d35d	224	#ifndef __ICACHE_PRESENT
<>	135:176b8275d35d	225	#define __ICACHE_PRESENT 0
<>	135:176b8275d35d	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
<>	135:176b8275d35d	227	#endif
<>	135:176b8275d35d	228
<>	135:176b8275d35d	229	#ifndef __DCACHE_PRESENT
<>	135:176b8275d35d	230	#define __DCACHE_PRESENT 0
<>	135:176b8275d35d	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
<>	135:176b8275d35d	232	#endif
<>	135:176b8275d35d	233
<>	135:176b8275d35d	234	#ifndef __DTCM_PRESENT
<>	135:176b8275d35d	235	#define __DTCM_PRESENT 0
<>	135:176b8275d35d	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
<>	135:176b8275d35d	237	#endif
<>	135:176b8275d35d	238
<>	135:176b8275d35d	239	#ifndef __NVIC_PRIO_BITS
<>	135:176b8275d35d	240	#define __NVIC_PRIO_BITS 3
<>	135:176b8275d35d	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<>	135:176b8275d35d	242	#endif
<>	135:176b8275d35d	243
<>	135:176b8275d35d	244	#ifndef __Vendor_SysTickConfig
<>	135:176b8275d35d	245	#define __Vendor_SysTickConfig 0
<>	135:176b8275d35d	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<>	135:176b8275d35d	247	#endif
<>	135:176b8275d35d	248	#endif
<>	135:176b8275d35d	249
<>	135:176b8275d35d	250	/* IO definitions (access restrictions to peripheral registers) */
<>	135:176b8275d35d	251	/**
<>	135:176b8275d35d	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
<>	135:176b8275d35d	253
<>	135:176b8275d35d	254	<strong>IO Type Qualifiers</strong> are used
<>	135:176b8275d35d	255	\li to specify the access to peripheral variables.
<>	135:176b8275d35d	256	\li for automatic generation of peripheral register debug information.
<>	135:176b8275d35d	257	*/
<>	135:176b8275d35d	258	#ifdef __cplusplus
<>	135:176b8275d35d	259	#define __I volatile /!< Defines 'read only' permissions /
<>	135:176b8275d35d	260	#else
<>	135:176b8275d35d	261	#define __I volatile const /!< Defines 'read only' permissions /
<>	135:176b8275d35d	262	#endif
<>	135:176b8275d35d	263	#define __O volatile /!< Defines 'write only' permissions /
<>	135:176b8275d35d	264	#define __IO volatile /!< Defines 'read / write' permissions /
<>	135:176b8275d35d	265
<>	135:176b8275d35d	266	#ifdef __cplusplus
<>	135:176b8275d35d	267	#define __IM volatile /!< Defines 'read only' permissions /
<>	135:176b8275d35d	268	#else
<>	135:176b8275d35d	269	#define __IM volatile const /!< Defines 'read only' permissions /
<>	135:176b8275d35d	270	#endif
<>	135:176b8275d35d	271	#define __OM volatile /!< Defines 'write only' permissions /
<>	135:176b8275d35d	272	#define __IOM volatile /!< Defines 'read / write' permissions /
<>	135:176b8275d35d	273
<>	135:176b8275d35d	274	/@} end of group Cortex_M7 /
<>	135:176b8275d35d	275
<>	135:176b8275d35d	276
<>	135:176b8275d35d	277
<>	135:176b8275d35d	278	/*******************************************************************************
<>	135:176b8275d35d	279	* Register Abstraction
<>	135:176b8275d35d	280	Core Register contain:
<>	135:176b8275d35d	281	- Core Register
<>	135:176b8275d35d	282	- Core NVIC Register
<>	135:176b8275d35d	283	- Core SCB Register
<>	135:176b8275d35d	284	- Core SysTick Register
<>	135:176b8275d35d	285	- Core Debug Register
<>	135:176b8275d35d	286	- Core MPU Register
<>	135:176b8275d35d	287	- Core FPU Register
<>	135:176b8275d35d	288	******************************************************************************/
<>	135:176b8275d35d	289	/** \defgroup CMSIS_core_register Defines and Type Definitions
<>	135:176b8275d35d	290	\brief Type definitions and defines for Cortex-M processor based devices.
<>	135:176b8275d35d	291	*/
<>	135:176b8275d35d	292
<>	135:176b8275d35d	293	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	294	\defgroup CMSIS_CORE Status and Control Registers
<>	135:176b8275d35d	295	\brief Core Register type definitions.
<>	135:176b8275d35d	296	@{
<>	135:176b8275d35d	297	*/
<>	135:176b8275d35d	298
<>	135:176b8275d35d	299	/** \brief Union type to access the Application Program Status Register (APSR).
<>	135:176b8275d35d	300	*/
<>	135:176b8275d35d	301	typedef union
<>	135:176b8275d35d	302	{
<>	135:176b8275d35d	303	struct
<>	135:176b8275d35d	304	{
<>	135:176b8275d35d	305	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
<>	135:176b8275d35d	306	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
<>	135:176b8275d35d	307	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
<>	135:176b8275d35d	308	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
<>	135:176b8275d35d	309	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
<>	135:176b8275d35d	310	uint32_t C:1; /!< bit: 29 Carry condition code flag /
<>	135:176b8275d35d	311	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
<>	135:176b8275d35d	312	uint32_t N:1; /!< bit: 31 Negative condition code flag /
<>	135:176b8275d35d	313	} b; /!< Structure used for bit access /
<>	135:176b8275d35d	314	uint32_t w; /!< Type used for word access /
<>	135:176b8275d35d	315	} APSR_Type;
<>	135:176b8275d35d	316
<>	135:176b8275d35d	317	/* APSR Register Definitions */
<>	135:176b8275d35d	318	#define APSR_N_Pos 31 /!< APSR: N Position /
<>	135:176b8275d35d	319	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
<>	135:176b8275d35d	320
<>	135:176b8275d35d	321	#define APSR_Z_Pos 30 /!< APSR: Z Position /
<>	135:176b8275d35d	322	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
<>	135:176b8275d35d	323
<>	135:176b8275d35d	324	#define APSR_C_Pos 29 /!< APSR: C Position /
<>	135:176b8275d35d	325	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
<>	135:176b8275d35d	326
<>	135:176b8275d35d	327	#define APSR_V_Pos 28 /!< APSR: V Position /
<>	135:176b8275d35d	328	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
<>	135:176b8275d35d	329
<>	135:176b8275d35d	330	#define APSR_Q_Pos 27 /!< APSR: Q Position /
<>	135:176b8275d35d	331	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
<>	135:176b8275d35d	332
<>	135:176b8275d35d	333	#define APSR_GE_Pos 16 /!< APSR: GE Position /
<>	135:176b8275d35d	334	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
<>	135:176b8275d35d	335
<>	135:176b8275d35d	336
<>	135:176b8275d35d	337	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
<>	135:176b8275d35d	338	*/
<>	135:176b8275d35d	339	typedef union
<>	135:176b8275d35d	340	{
<>	135:176b8275d35d	341	struct
<>	135:176b8275d35d	342	{
<>	135:176b8275d35d	343	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
<>	135:176b8275d35d	344	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
<>	135:176b8275d35d	345	} b; /!< Structure used for bit access /
<>	135:176b8275d35d	346	uint32_t w; /!< Type used for word access /
<>	135:176b8275d35d	347	} IPSR_Type;
<>	135:176b8275d35d	348
<>	135:176b8275d35d	349	/* IPSR Register Definitions */
<>	135:176b8275d35d	350	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
<>	135:176b8275d35d	351	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
<>	135:176b8275d35d	352
<>	135:176b8275d35d	353
<>	135:176b8275d35d	354	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<>	135:176b8275d35d	355	*/
<>	135:176b8275d35d	356	typedef union
<>	135:176b8275d35d	357	{
<>	135:176b8275d35d	358	struct
<>	135:176b8275d35d	359	{
<>	135:176b8275d35d	360	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
<>	135:176b8275d35d	361	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
<>	135:176b8275d35d	362	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
<>	135:176b8275d35d	363	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
<>	135:176b8275d35d	364	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
<>	135:176b8275d35d	365	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
<>	135:176b8275d35d	366	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
<>	135:176b8275d35d	367	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
<>	135:176b8275d35d	368	uint32_t C:1; /!< bit: 29 Carry condition code flag /
<>	135:176b8275d35d	369	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
<>	135:176b8275d35d	370	uint32_t N:1; /!< bit: 31 Negative condition code flag /
<>	135:176b8275d35d	371	} b; /!< Structure used for bit access /
<>	135:176b8275d35d	372	uint32_t w; /!< Type used for word access /
<>	135:176b8275d35d	373	} xPSR_Type;
<>	135:176b8275d35d	374
<>	135:176b8275d35d	375	/* xPSR Register Definitions */
<>	135:176b8275d35d	376	#define xPSR_N_Pos 31 /!< xPSR: N Position /
<>	135:176b8275d35d	377	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
<>	135:176b8275d35d	378
<>	135:176b8275d35d	379	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
<>	135:176b8275d35d	380	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
<>	135:176b8275d35d	381
<>	135:176b8275d35d	382	#define xPSR_C_Pos 29 /!< xPSR: C Position /
<>	135:176b8275d35d	383	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
<>	135:176b8275d35d	384
<>	135:176b8275d35d	385	#define xPSR_V_Pos 28 /!< xPSR: V Position /
<>	135:176b8275d35d	386	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
<>	135:176b8275d35d	387
<>	135:176b8275d35d	388	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
<>	135:176b8275d35d	389	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
<>	135:176b8275d35d	390
<>	135:176b8275d35d	391	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
<>	135:176b8275d35d	392	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
<>	135:176b8275d35d	393
<>	135:176b8275d35d	394	#define xPSR_T_Pos 24 /!< xPSR: T Position /
<>	135:176b8275d35d	395	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
<>	135:176b8275d35d	396
<>	135:176b8275d35d	397	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
<>	135:176b8275d35d	398	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
<>	135:176b8275d35d	399
<>	135:176b8275d35d	400	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
<>	135:176b8275d35d	401	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
<>	135:176b8275d35d	402
<>	135:176b8275d35d	403
<>	135:176b8275d35d	404	/** \brief Union type to access the Control Registers (CONTROL).
<>	135:176b8275d35d	405	*/
<>	135:176b8275d35d	406	typedef union
<>	135:176b8275d35d	407	{
<>	135:176b8275d35d	408	struct
<>	135:176b8275d35d	409	{
<>	135:176b8275d35d	410	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
<>	135:176b8275d35d	411	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
<>	135:176b8275d35d	412	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
<>	135:176b8275d35d	413	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
<>	135:176b8275d35d	414	} b; /!< Structure used for bit access /
<>	135:176b8275d35d	415	uint32_t w; /!< Type used for word access /
<>	135:176b8275d35d	416	} CONTROL_Type;
<>	135:176b8275d35d	417
<>	135:176b8275d35d	418	/* CONTROL Register Definitions */
<>	135:176b8275d35d	419	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
<>	135:176b8275d35d	420	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
<>	135:176b8275d35d	421
<>	135:176b8275d35d	422	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
<>	135:176b8275d35d	423	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
<>	135:176b8275d35d	424
<>	135:176b8275d35d	425	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
<>	135:176b8275d35d	426	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
<>	135:176b8275d35d	427
<>	135:176b8275d35d	428	/@} end of group CMSIS_CORE /
<>	135:176b8275d35d	429
<>	135:176b8275d35d	430
<>	135:176b8275d35d	431	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	432	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<>	135:176b8275d35d	433	\brief Type definitions for the NVIC Registers
<>	135:176b8275d35d	434	@{
<>	135:176b8275d35d	435	*/
<>	135:176b8275d35d	436
<>	135:176b8275d35d	437	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<>	135:176b8275d35d	438	*/
<>	135:176b8275d35d	439	typedef struct
<>	135:176b8275d35d	440	{
<>	135:176b8275d35d	441	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
<>	135:176b8275d35d	442	uint32_t RESERVED0[24];
<>	135:176b8275d35d	443	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
<>	135:176b8275d35d	444	uint32_t RSERVED1[24];
<>	135:176b8275d35d	445	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
<>	135:176b8275d35d	446	uint32_t RESERVED2[24];
<>	135:176b8275d35d	447	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
<>	135:176b8275d35d	448	uint32_t RESERVED3[24];
<>	135:176b8275d35d	449	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
<>	135:176b8275d35d	450	uint32_t RESERVED4[56];
<>	135:176b8275d35d	451	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
<>	135:176b8275d35d	452	uint32_t RESERVED5[644];
<>	135:176b8275d35d	453	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
<>	135:176b8275d35d	454	} NVIC_Type;
<>	135:176b8275d35d	455
<>	135:176b8275d35d	456	/* Software Triggered Interrupt Register Definitions */
<>	135:176b8275d35d	457	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
<>	135:176b8275d35d	458	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
<>	135:176b8275d35d	459
<>	135:176b8275d35d	460	/@} end of group CMSIS_NVIC /
<>	135:176b8275d35d	461
<>	135:176b8275d35d	462
<>	135:176b8275d35d	463	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	464	\defgroup CMSIS_SCB System Control Block (SCB)
<>	135:176b8275d35d	465	\brief Type definitions for the System Control Block Registers
<>	135:176b8275d35d	466	@{
<>	135:176b8275d35d	467	*/
<>	135:176b8275d35d	468
<>	135:176b8275d35d	469	/** \brief Structure type to access the System Control Block (SCB).
<>	135:176b8275d35d	470	*/
<>	135:176b8275d35d	471	typedef struct
<>	135:176b8275d35d	472	{
<>	135:176b8275d35d	473	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
<>	135:176b8275d35d	474	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
<>	135:176b8275d35d	475	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
<>	135:176b8275d35d	476	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
<>	135:176b8275d35d	477	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
<>	135:176b8275d35d	478	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
<>	135:176b8275d35d	479	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
<>	135:176b8275d35d	480	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
<>	135:176b8275d35d	481	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
<>	135:176b8275d35d	482	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
<>	135:176b8275d35d	483	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
<>	135:176b8275d35d	484	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
<>	135:176b8275d35d	485	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
<>	135:176b8275d35d	486	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
<>	135:176b8275d35d	487	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
<>	135:176b8275d35d	488	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
<>	135:176b8275d35d	489	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
<>	135:176b8275d35d	490	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
<>	135:176b8275d35d	491	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
<>	135:176b8275d35d	492	uint32_t RESERVED0[1];
<>	135:176b8275d35d	493	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
<>	135:176b8275d35d	494	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
<>	135:176b8275d35d	495	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
<>	135:176b8275d35d	496	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
<>	135:176b8275d35d	497	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
<>	135:176b8275d35d	498	uint32_t RESERVED3[93];
<>	135:176b8275d35d	499	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
<>	135:176b8275d35d	500	uint32_t RESERVED4[15];
<>	135:176b8275d35d	501	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
<>	135:176b8275d35d	502	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
<>	135:176b8275d35d	503	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
<>	135:176b8275d35d	504	uint32_t RESERVED5[1];
<>	135:176b8275d35d	505	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
<>	135:176b8275d35d	506	uint32_t RESERVED6[1];
<>	135:176b8275d35d	507	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
<>	135:176b8275d35d	508	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
<>	135:176b8275d35d	509	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
<>	135:176b8275d35d	510	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
<>	135:176b8275d35d	511	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
<>	135:176b8275d35d	512	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
<>	135:176b8275d35d	513	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
<>	135:176b8275d35d	514	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
<>	135:176b8275d35d	515	uint32_t RESERVED7[6];
<>	135:176b8275d35d	516	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
<>	135:176b8275d35d	517	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
<>	135:176b8275d35d	518	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
<>	135:176b8275d35d	519	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
<>	135:176b8275d35d	520	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
<>	135:176b8275d35d	521	uint32_t RESERVED8[1];
<>	135:176b8275d35d	522	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
<>	135:176b8275d35d	523	} SCB_Type;
<>	135:176b8275d35d	524
<>	135:176b8275d35d	525	/* SCB CPUID Register Definitions */
<>	135:176b8275d35d	526	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
<>	135:176b8275d35d	527	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
<>	135:176b8275d35d	528
<>	135:176b8275d35d	529	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
<>	135:176b8275d35d	530	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
<>	135:176b8275d35d	531
<>	135:176b8275d35d	532	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
<>	135:176b8275d35d	533	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
<>	135:176b8275d35d	534
<>	135:176b8275d35d	535	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
<>	135:176b8275d35d	536	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
<>	135:176b8275d35d	537
<>	135:176b8275d35d	538	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
<>	135:176b8275d35d	539	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
<>	135:176b8275d35d	540
<>	135:176b8275d35d	541	/* SCB Interrupt Control State Register Definitions */
<>	135:176b8275d35d	542	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
<>	135:176b8275d35d	543	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
<>	135:176b8275d35d	544
<>	135:176b8275d35d	545	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
<>	135:176b8275d35d	546	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
<>	135:176b8275d35d	547
<>	135:176b8275d35d	548	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
<>	135:176b8275d35d	549	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
<>	135:176b8275d35d	550
<>	135:176b8275d35d	551	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
<>	135:176b8275d35d	552	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
<>	135:176b8275d35d	553
<>	135:176b8275d35d	554	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
<>	135:176b8275d35d	555	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
<>	135:176b8275d35d	556
<>	135:176b8275d35d	557	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
<>	135:176b8275d35d	558	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
<>	135:176b8275d35d	559
<>	135:176b8275d35d	560	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
<>	135:176b8275d35d	561	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
<>	135:176b8275d35d	562
<>	135:176b8275d35d	563	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
<>	135:176b8275d35d	564	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
<>	135:176b8275d35d	565
<>	135:176b8275d35d	566	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
<>	135:176b8275d35d	567	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
<>	135:176b8275d35d	568
<>	135:176b8275d35d	569	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
<>	135:176b8275d35d	570	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
<>	135:176b8275d35d	571
<>	135:176b8275d35d	572	/* SCB Vector Table Offset Register Definitions */
<>	135:176b8275d35d	573	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
<>	135:176b8275d35d	574	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
<>	135:176b8275d35d	575
<>	135:176b8275d35d	576	/* SCB Application Interrupt and Reset Control Register Definitions */
<>	135:176b8275d35d	577	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
<>	135:176b8275d35d	578	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
<>	135:176b8275d35d	579
<>	135:176b8275d35d	580	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
<>	135:176b8275d35d	581	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
<>	135:176b8275d35d	582
<>	135:176b8275d35d	583	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
<>	135:176b8275d35d	584	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
<>	135:176b8275d35d	585
<>	135:176b8275d35d	586	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
<>	135:176b8275d35d	587	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
<>	135:176b8275d35d	588
<>	135:176b8275d35d	589	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
<>	135:176b8275d35d	590	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
<>	135:176b8275d35d	591
<>	135:176b8275d35d	592	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
<>	135:176b8275d35d	593	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
<>	135:176b8275d35d	594
<>	135:176b8275d35d	595	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
<>	135:176b8275d35d	596	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
<>	135:176b8275d35d	597
<>	135:176b8275d35d	598	/* SCB System Control Register Definitions */
<>	135:176b8275d35d	599	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
<>	135:176b8275d35d	600	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
<>	135:176b8275d35d	601
<>	135:176b8275d35d	602	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
<>	135:176b8275d35d	603	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
<>	135:176b8275d35d	604
<>	135:176b8275d35d	605	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
<>	135:176b8275d35d	606	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
<>	135:176b8275d35d	607
<>	135:176b8275d35d	608	/* SCB Configuration Control Register Definitions */
<>	135:176b8275d35d	609	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
<>	135:176b8275d35d	610	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
<>	135:176b8275d35d	611
<>	135:176b8275d35d	612	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
<>	135:176b8275d35d	613	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
<>	135:176b8275d35d	614
<>	135:176b8275d35d	615	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
<>	135:176b8275d35d	616	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
<>	135:176b8275d35d	617
<>	135:176b8275d35d	618	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
<>	135:176b8275d35d	619	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
<>	135:176b8275d35d	620
<>	135:176b8275d35d	621	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
<>	135:176b8275d35d	622	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
<>	135:176b8275d35d	623
<>	135:176b8275d35d	624	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
<>	135:176b8275d35d	625	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
<>	135:176b8275d35d	626
<>	135:176b8275d35d	627	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
<>	135:176b8275d35d	628	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
<>	135:176b8275d35d	629
<>	135:176b8275d35d	630	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
<>	135:176b8275d35d	631	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
<>	135:176b8275d35d	632
<>	135:176b8275d35d	633	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
<>	135:176b8275d35d	634	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
<>	135:176b8275d35d	635
<>	135:176b8275d35d	636	/* SCB System Handler Control and State Register Definitions */
<>	135:176b8275d35d	637	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
<>	135:176b8275d35d	638	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
<>	135:176b8275d35d	639
<>	135:176b8275d35d	640	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
<>	135:176b8275d35d	641	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
<>	135:176b8275d35d	642
<>	135:176b8275d35d	643	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
<>	135:176b8275d35d	644	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
<>	135:176b8275d35d	645
<>	135:176b8275d35d	646	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
<>	135:176b8275d35d	647	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
<>	135:176b8275d35d	648
<>	135:176b8275d35d	649	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
<>	135:176b8275d35d	650	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
<>	135:176b8275d35d	651
<>	135:176b8275d35d	652	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
<>	135:176b8275d35d	653	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
<>	135:176b8275d35d	654
<>	135:176b8275d35d	655	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
<>	135:176b8275d35d	656	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
<>	135:176b8275d35d	657
<>	135:176b8275d35d	658	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
<>	135:176b8275d35d	659	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
<>	135:176b8275d35d	660
<>	135:176b8275d35d	661	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
<>	135:176b8275d35d	662	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
<>	135:176b8275d35d	663
<>	135:176b8275d35d	664	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
<>	135:176b8275d35d	665	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
<>	135:176b8275d35d	666
<>	135:176b8275d35d	667	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
<>	135:176b8275d35d	668	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
<>	135:176b8275d35d	669
<>	135:176b8275d35d	670	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
<>	135:176b8275d35d	671	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
<>	135:176b8275d35d	672
<>	135:176b8275d35d	673	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
<>	135:176b8275d35d	674	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
<>	135:176b8275d35d	675
<>	135:176b8275d35d	676	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
<>	135:176b8275d35d	677	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
<>	135:176b8275d35d	678
<>	135:176b8275d35d	679	/* SCB Configurable Fault Status Registers Definitions */
<>	135:176b8275d35d	680	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
<>	135:176b8275d35d	681	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
<>	135:176b8275d35d	682
<>	135:176b8275d35d	683	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
<>	135:176b8275d35d	684	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
<>	135:176b8275d35d	685
<>	135:176b8275d35d	686	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
<>	135:176b8275d35d	687	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
<>	135:176b8275d35d	688
<>	135:176b8275d35d	689	/* SCB Hard Fault Status Registers Definitions */
<>	135:176b8275d35d	690	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
<>	135:176b8275d35d	691	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
<>	135:176b8275d35d	692
<>	135:176b8275d35d	693	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
<>	135:176b8275d35d	694	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
<>	135:176b8275d35d	695
<>	135:176b8275d35d	696	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
<>	135:176b8275d35d	697	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
<>	135:176b8275d35d	698
<>	135:176b8275d35d	699	/* SCB Debug Fault Status Register Definitions */
<>	135:176b8275d35d	700	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
<>	135:176b8275d35d	701	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
<>	135:176b8275d35d	702
<>	135:176b8275d35d	703	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
<>	135:176b8275d35d	704	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
<>	135:176b8275d35d	705
<>	135:176b8275d35d	706	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
<>	135:176b8275d35d	707	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
<>	135:176b8275d35d	708
<>	135:176b8275d35d	709	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
<>	135:176b8275d35d	710	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
<>	135:176b8275d35d	711
<>	135:176b8275d35d	712	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
<>	135:176b8275d35d	713	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
<>	135:176b8275d35d	714
<>	135:176b8275d35d	715	/* Cache Level ID register */
<>	135:176b8275d35d	716	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
<>	135:176b8275d35d	717	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
<>	135:176b8275d35d	718
<>	135:176b8275d35d	719	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
<>	135:176b8275d35d	720	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
<>	135:176b8275d35d	721
<>	135:176b8275d35d	722	/* Cache Type register */
<>	135:176b8275d35d	723	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
<>	135:176b8275d35d	724	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
<>	135:176b8275d35d	725
<>	135:176b8275d35d	726	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
<>	135:176b8275d35d	727	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
<>	135:176b8275d35d	728
<>	135:176b8275d35d	729	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
<>	135:176b8275d35d	730	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
<>	135:176b8275d35d	731
<>	135:176b8275d35d	732	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
<>	135:176b8275d35d	733	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
<>	135:176b8275d35d	734
<>	135:176b8275d35d	735	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
<>	135:176b8275d35d	736	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
<>	135:176b8275d35d	737
<>	135:176b8275d35d	738	/* Cache Size ID Register */
<>	135:176b8275d35d	739	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
<>	135:176b8275d35d	740	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
<>	135:176b8275d35d	741
<>	135:176b8275d35d	742	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
<>	135:176b8275d35d	743	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
<>	135:176b8275d35d	744
<>	135:176b8275d35d	745	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
<>	135:176b8275d35d	746	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
<>	135:176b8275d35d	747
<>	135:176b8275d35d	748	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
<>	135:176b8275d35d	749	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
<>	135:176b8275d35d	750
<>	135:176b8275d35d	751	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
<>	135:176b8275d35d	752	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
<>	135:176b8275d35d	753
<>	135:176b8275d35d	754	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
<>	135:176b8275d35d	755	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
<>	135:176b8275d35d	756
<>	135:176b8275d35d	757	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
<>	135:176b8275d35d	758	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
<>	135:176b8275d35d	759
<>	135:176b8275d35d	760	/* Cache Size Selection Register */
<>	135:176b8275d35d	761	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
<>	135:176b8275d35d	762	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
<>	135:176b8275d35d	763
<>	135:176b8275d35d	764	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
<>	135:176b8275d35d	765	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
<>	135:176b8275d35d	766
<>	135:176b8275d35d	767	/* SCB Software Triggered Interrupt Register */
<>	135:176b8275d35d	768	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
<>	135:176b8275d35d	769	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
<>	135:176b8275d35d	770
<>	135:176b8275d35d	771	/* Instruction Tightly-Coupled Memory Control Register*/
<>	135:176b8275d35d	772	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
<>	135:176b8275d35d	773	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
<>	135:176b8275d35d	774
<>	135:176b8275d35d	775	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
<>	135:176b8275d35d	776	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
<>	135:176b8275d35d	777
<>	135:176b8275d35d	778	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
<>	135:176b8275d35d	779	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
<>	135:176b8275d35d	780
<>	135:176b8275d35d	781	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
<>	135:176b8275d35d	782	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
<>	135:176b8275d35d	783
<>	135:176b8275d35d	784	/* Data Tightly-Coupled Memory Control Registers */
<>	135:176b8275d35d	785	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
<>	135:176b8275d35d	786	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
<>	135:176b8275d35d	787
<>	135:176b8275d35d	788	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
<>	135:176b8275d35d	789	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
<>	135:176b8275d35d	790
<>	135:176b8275d35d	791	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
<>	135:176b8275d35d	792	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
<>	135:176b8275d35d	793
<>	135:176b8275d35d	794	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
<>	135:176b8275d35d	795	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
<>	135:176b8275d35d	796
<>	135:176b8275d35d	797	/* AHBP Control Register */
<>	135:176b8275d35d	798	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
<>	135:176b8275d35d	799	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
<>	135:176b8275d35d	800
<>	135:176b8275d35d	801	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
<>	135:176b8275d35d	802	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
<>	135:176b8275d35d	803
<>	135:176b8275d35d	804	/* L1 Cache Control Register */
<>	135:176b8275d35d	805	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
<>	135:176b8275d35d	806	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
<>	135:176b8275d35d	807
<>	135:176b8275d35d	808	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
<>	135:176b8275d35d	809	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
<>	135:176b8275d35d	810
<>	135:176b8275d35d	811	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
<>	135:176b8275d35d	812	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
<>	135:176b8275d35d	813
<>	135:176b8275d35d	814	/* AHBS control register */
<>	135:176b8275d35d	815	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
<>	135:176b8275d35d	816	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
<>	135:176b8275d35d	817
<>	135:176b8275d35d	818	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
<>	135:176b8275d35d	819	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
<>	135:176b8275d35d	820
<>	135:176b8275d35d	821	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
<>	135:176b8275d35d	822	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
<>	135:176b8275d35d	823
<>	135:176b8275d35d	824	/* Auxiliary Bus Fault Status Register */
<>	135:176b8275d35d	825	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
<>	135:176b8275d35d	826	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
<>	135:176b8275d35d	827
<>	135:176b8275d35d	828	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
<>	135:176b8275d35d	829	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
<>	135:176b8275d35d	830
<>	135:176b8275d35d	831	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
<>	135:176b8275d35d	832	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
<>	135:176b8275d35d	833
<>	135:176b8275d35d	834	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
<>	135:176b8275d35d	835	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
<>	135:176b8275d35d	836
<>	135:176b8275d35d	837	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
<>	135:176b8275d35d	838	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
<>	135:176b8275d35d	839
<>	135:176b8275d35d	840	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
<>	135:176b8275d35d	841	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
<>	135:176b8275d35d	842
<>	135:176b8275d35d	843	/@} end of group CMSIS_SCB /
<>	135:176b8275d35d	844
<>	135:176b8275d35d	845
<>	135:176b8275d35d	846	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	847	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<>	135:176b8275d35d	848	\brief Type definitions for the System Control and ID Register not in the SCB
<>	135:176b8275d35d	849	@{
<>	135:176b8275d35d	850	*/
<>	135:176b8275d35d	851
<>	135:176b8275d35d	852	/** \brief Structure type to access the System Control and ID Register not in the SCB.
<>	135:176b8275d35d	853	*/
<>	135:176b8275d35d	854	typedef struct
<>	135:176b8275d35d	855	{
<>	135:176b8275d35d	856	uint32_t RESERVED0[1];
<>	135:176b8275d35d	857	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
<>	135:176b8275d35d	858	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
<>	135:176b8275d35d	859	} SCnSCB_Type;
<>	135:176b8275d35d	860
<>	135:176b8275d35d	861	/* Interrupt Controller Type Register Definitions */
<>	135:176b8275d35d	862	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
<>	135:176b8275d35d	863	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
<>	135:176b8275d35d	864
<>	135:176b8275d35d	865	/* Auxiliary Control Register Definitions */
<>	135:176b8275d35d	866	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
<>	135:176b8275d35d	867	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
<>	135:176b8275d35d	868
<>	135:176b8275d35d	869	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
<>	135:176b8275d35d	870	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
<>	135:176b8275d35d	871
<>	135:176b8275d35d	872	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
<>	135:176b8275d35d	873	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
<>	135:176b8275d35d	874
<>	135:176b8275d35d	875	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
<>	135:176b8275d35d	876	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
<>	135:176b8275d35d	877
<>	135:176b8275d35d	878	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
<>	135:176b8275d35d	879	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
<>	135:176b8275d35d	880
<>	135:176b8275d35d	881	/@} end of group CMSIS_SCnotSCB /
<>	135:176b8275d35d	882
<>	135:176b8275d35d	883
<>	135:176b8275d35d	884	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	885	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
<>	135:176b8275d35d	886	\brief Type definitions for the System Timer Registers.
<>	135:176b8275d35d	887	@{
<>	135:176b8275d35d	888	*/
<>	135:176b8275d35d	889
<>	135:176b8275d35d	890	/** \brief Structure type to access the System Timer (SysTick).
<>	135:176b8275d35d	891	*/
<>	135:176b8275d35d	892	typedef struct
<>	135:176b8275d35d	893	{
<>	135:176b8275d35d	894	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
<>	135:176b8275d35d	895	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
<>	135:176b8275d35d	896	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
<>	135:176b8275d35d	897	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
<>	135:176b8275d35d	898	} SysTick_Type;
<>	135:176b8275d35d	899
<>	135:176b8275d35d	900	/* SysTick Control / Status Register Definitions */
<>	135:176b8275d35d	901	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
<>	135:176b8275d35d	902	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
<>	135:176b8275d35d	903
<>	135:176b8275d35d	904	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
<>	135:176b8275d35d	905	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
<>	135:176b8275d35d	906
<>	135:176b8275d35d	907	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
<>	135:176b8275d35d	908	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
<>	135:176b8275d35d	909
<>	135:176b8275d35d	910	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
<>	135:176b8275d35d	911	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
<>	135:176b8275d35d	912
<>	135:176b8275d35d	913	/* SysTick Reload Register Definitions */
<>	135:176b8275d35d	914	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
<>	135:176b8275d35d	915	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
<>	135:176b8275d35d	916
<>	135:176b8275d35d	917	/* SysTick Current Register Definitions */
<>	135:176b8275d35d	918	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
<>	135:176b8275d35d	919	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
<>	135:176b8275d35d	920
<>	135:176b8275d35d	921	/* SysTick Calibration Register Definitions */
<>	135:176b8275d35d	922	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
<>	135:176b8275d35d	923	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
<>	135:176b8275d35d	924
<>	135:176b8275d35d	925	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
<>	135:176b8275d35d	926	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
<>	135:176b8275d35d	927
<>	135:176b8275d35d	928	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
<>	135:176b8275d35d	929	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
<>	135:176b8275d35d	930
<>	135:176b8275d35d	931	/@} end of group CMSIS_SysTick /
<>	135:176b8275d35d	932
<>	135:176b8275d35d	933
<>	135:176b8275d35d	934	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	935	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<>	135:176b8275d35d	936	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<>	135:176b8275d35d	937	@{
<>	135:176b8275d35d	938	*/
<>	135:176b8275d35d	939
<>	135:176b8275d35d	940	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<>	135:176b8275d35d	941	*/
<>	135:176b8275d35d	942	typedef struct
<>	135:176b8275d35d	943	{
<>	135:176b8275d35d	944	__O union
<>	135:176b8275d35d	945	{
<>	135:176b8275d35d	946	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
<>	135:176b8275d35d	947	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
<>	135:176b8275d35d	948	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
<>	135:176b8275d35d	949	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
<>	135:176b8275d35d	950	uint32_t RESERVED0[864];
<>	135:176b8275d35d	951	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
<>	135:176b8275d35d	952	uint32_t RESERVED1[15];
<>	135:176b8275d35d	953	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
<>	135:176b8275d35d	954	uint32_t RESERVED2[15];
<>	135:176b8275d35d	955	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
<>	135:176b8275d35d	956	uint32_t RESERVED3[29];
<>	135:176b8275d35d	957	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
<>	135:176b8275d35d	958	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
<>	135:176b8275d35d	959	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
<>	135:176b8275d35d	960	uint32_t RESERVED4[43];
<>	135:176b8275d35d	961	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
<>	135:176b8275d35d	962	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
<>	135:176b8275d35d	963	uint32_t RESERVED5[6];
<>	135:176b8275d35d	964	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
<>	135:176b8275d35d	965	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
<>	135:176b8275d35d	966	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
<>	135:176b8275d35d	967	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
<>	135:176b8275d35d	968	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
<>	135:176b8275d35d	969	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
<>	135:176b8275d35d	970	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
<>	135:176b8275d35d	971	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
<>	135:176b8275d35d	972	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
<>	135:176b8275d35d	973	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
<>	135:176b8275d35d	974	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
<>	135:176b8275d35d	975	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
<>	135:176b8275d35d	976	} ITM_Type;
<>	135:176b8275d35d	977
<>	135:176b8275d35d	978	/* ITM Trace Privilege Register Definitions */
<>	135:176b8275d35d	979	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
<>	135:176b8275d35d	980	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
<>	135:176b8275d35d	981
<>	135:176b8275d35d	982	/* ITM Trace Control Register Definitions */
<>	135:176b8275d35d	983	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
<>	135:176b8275d35d	984	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
<>	135:176b8275d35d	985
<>	135:176b8275d35d	986	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
<>	135:176b8275d35d	987	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
<>	135:176b8275d35d	988
<>	135:176b8275d35d	989	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
<>	135:176b8275d35d	990	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
<>	135:176b8275d35d	991
<>	135:176b8275d35d	992	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
<>	135:176b8275d35d	993	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
<>	135:176b8275d35d	994
<>	135:176b8275d35d	995	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
<>	135:176b8275d35d	996	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
<>	135:176b8275d35d	997
<>	135:176b8275d35d	998	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
<>	135:176b8275d35d	999	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
<>	135:176b8275d35d	1000
<>	135:176b8275d35d	1001	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
<>	135:176b8275d35d	1002	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
<>	135:176b8275d35d	1003
<>	135:176b8275d35d	1004	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
<>	135:176b8275d35d	1005	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
<>	135:176b8275d35d	1006
<>	135:176b8275d35d	1007	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
<>	135:176b8275d35d	1008	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
<>	135:176b8275d35d	1009
<>	135:176b8275d35d	1010	/* ITM Integration Write Register Definitions */
<>	135:176b8275d35d	1011	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
<>	135:176b8275d35d	1012	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
<>	135:176b8275d35d	1013
<>	135:176b8275d35d	1014	/* ITM Integration Read Register Definitions */
<>	135:176b8275d35d	1015	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
<>	135:176b8275d35d	1016	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
<>	135:176b8275d35d	1017
<>	135:176b8275d35d	1018	/* ITM Integration Mode Control Register Definitions */
<>	135:176b8275d35d	1019	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
<>	135:176b8275d35d	1020	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
<>	135:176b8275d35d	1021
<>	135:176b8275d35d	1022	/* ITM Lock Status Register Definitions */
<>	135:176b8275d35d	1023	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
<>	135:176b8275d35d	1024	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
<>	135:176b8275d35d	1025
<>	135:176b8275d35d	1026	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
<>	135:176b8275d35d	1027	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
<>	135:176b8275d35d	1028
<>	135:176b8275d35d	1029	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
<>	135:176b8275d35d	1030	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
<>	135:176b8275d35d	1031
<>	135:176b8275d35d	1032	/@}/ /* end of group CMSIS_ITM */
<>	135:176b8275d35d	1033
<>	135:176b8275d35d	1034
<>	135:176b8275d35d	1035	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	1036	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<>	135:176b8275d35d	1037	\brief Type definitions for the Data Watchpoint and Trace (DWT)
<>	135:176b8275d35d	1038	@{
<>	135:176b8275d35d	1039	*/
<>	135:176b8275d35d	1040
<>	135:176b8275d35d	1041	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<>	135:176b8275d35d	1042	*/
<>	135:176b8275d35d	1043	typedef struct
<>	135:176b8275d35d	1044	{
<>	135:176b8275d35d	1045	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
<>	135:176b8275d35d	1046	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
<>	135:176b8275d35d	1047	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
<>	135:176b8275d35d	1048	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
<>	135:176b8275d35d	1049	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
<>	135:176b8275d35d	1050	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
<>	135:176b8275d35d	1051	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
<>	135:176b8275d35d	1052	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
<>	135:176b8275d35d	1053	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
<>	135:176b8275d35d	1054	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
<>	135:176b8275d35d	1055	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
<>	135:176b8275d35d	1056	uint32_t RESERVED0[1];
<>	135:176b8275d35d	1057	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
<>	135:176b8275d35d	1058	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
<>	135:176b8275d35d	1059	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
<>	135:176b8275d35d	1060	uint32_t RESERVED1[1];
<>	135:176b8275d35d	1061	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
<>	135:176b8275d35d	1062	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
<>	135:176b8275d35d	1063	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
<>	135:176b8275d35d	1064	uint32_t RESERVED2[1];
<>	135:176b8275d35d	1065	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
<>	135:176b8275d35d	1066	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
<>	135:176b8275d35d	1067	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
<>	135:176b8275d35d	1068	uint32_t RESERVED3[981];
<>	135:176b8275d35d	1069	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
<>	135:176b8275d35d	1070	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
<>	135:176b8275d35d	1071	} DWT_Type;
<>	135:176b8275d35d	1072
<>	135:176b8275d35d	1073	/* DWT Control Register Definitions */
<>	135:176b8275d35d	1074	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
<>	135:176b8275d35d	1075	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
<>	135:176b8275d35d	1076
<>	135:176b8275d35d	1077	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
<>	135:176b8275d35d	1078	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
<>	135:176b8275d35d	1079
<>	135:176b8275d35d	1080	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
<>	135:176b8275d35d	1081	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
<>	135:176b8275d35d	1082
<>	135:176b8275d35d	1083	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
<>	135:176b8275d35d	1084	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
<>	135:176b8275d35d	1085
<>	135:176b8275d35d	1086	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
<>	135:176b8275d35d	1087	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
<>	135:176b8275d35d	1088
<>	135:176b8275d35d	1089	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
<>	135:176b8275d35d	1090	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
<>	135:176b8275d35d	1091
<>	135:176b8275d35d	1092	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
<>	135:176b8275d35d	1093	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
<>	135:176b8275d35d	1094
<>	135:176b8275d35d	1095	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
<>	135:176b8275d35d	1096	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
<>	135:176b8275d35d	1097
<>	135:176b8275d35d	1098	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
<>	135:176b8275d35d	1099	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
<>	135:176b8275d35d	1100
<>	135:176b8275d35d	1101	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
<>	135:176b8275d35d	1102	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
<>	135:176b8275d35d	1103
<>	135:176b8275d35d	1104	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
<>	135:176b8275d35d	1105	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
<>	135:176b8275d35d	1106
<>	135:176b8275d35d	1107	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
<>	135:176b8275d35d	1108	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
<>	135:176b8275d35d	1109
<>	135:176b8275d35d	1110	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
<>	135:176b8275d35d	1111	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
<>	135:176b8275d35d	1112
<>	135:176b8275d35d	1113	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
<>	135:176b8275d35d	1114	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
<>	135:176b8275d35d	1115
<>	135:176b8275d35d	1116	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
<>	135:176b8275d35d	1117	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
<>	135:176b8275d35d	1118
<>	135:176b8275d35d	1119	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
<>	135:176b8275d35d	1120	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
<>	135:176b8275d35d	1121
<>	135:176b8275d35d	1122	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
<>	135:176b8275d35d	1123	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
<>	135:176b8275d35d	1124
<>	135:176b8275d35d	1125	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
<>	135:176b8275d35d	1126	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
<>	135:176b8275d35d	1127
<>	135:176b8275d35d	1128	/* DWT CPI Count Register Definitions */
<>	135:176b8275d35d	1129	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
<>	135:176b8275d35d	1130	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
<>	135:176b8275d35d	1131
<>	135:176b8275d35d	1132	/* DWT Exception Overhead Count Register Definitions */
<>	135:176b8275d35d	1133	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
<>	135:176b8275d35d	1134	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
<>	135:176b8275d35d	1135
<>	135:176b8275d35d	1136	/* DWT Sleep Count Register Definitions */
<>	135:176b8275d35d	1137	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
<>	135:176b8275d35d	1138	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
<>	135:176b8275d35d	1139
<>	135:176b8275d35d	1140	/* DWT LSU Count Register Definitions */
<>	135:176b8275d35d	1141	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
<>	135:176b8275d35d	1142	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
<>	135:176b8275d35d	1143
<>	135:176b8275d35d	1144	/* DWT Folded-instruction Count Register Definitions */
<>	135:176b8275d35d	1145	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
<>	135:176b8275d35d	1146	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
<>	135:176b8275d35d	1147
<>	135:176b8275d35d	1148	/* DWT Comparator Mask Register Definitions */
<>	135:176b8275d35d	1149	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
<>	135:176b8275d35d	1150	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
<>	135:176b8275d35d	1151
<>	135:176b8275d35d	1152	/* DWT Comparator Function Register Definitions */
<>	135:176b8275d35d	1153	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
<>	135:176b8275d35d	1154	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
<>	135:176b8275d35d	1155
<>	135:176b8275d35d	1156	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
<>	135:176b8275d35d	1157	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
<>	135:176b8275d35d	1158
<>	135:176b8275d35d	1159	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
<>	135:176b8275d35d	1160	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
<>	135:176b8275d35d	1161
<>	135:176b8275d35d	1162	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
<>	135:176b8275d35d	1163	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
<>	135:176b8275d35d	1164
<>	135:176b8275d35d	1165	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
<>	135:176b8275d35d	1166	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
<>	135:176b8275d35d	1167
<>	135:176b8275d35d	1168	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
<>	135:176b8275d35d	1169	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
<>	135:176b8275d35d	1170
<>	135:176b8275d35d	1171	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
<>	135:176b8275d35d	1172	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
<>	135:176b8275d35d	1173
<>	135:176b8275d35d	1174	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
<>	135:176b8275d35d	1175	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
<>	135:176b8275d35d	1176
<>	135:176b8275d35d	1177	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
<>	135:176b8275d35d	1178	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
<>	135:176b8275d35d	1179
<>	135:176b8275d35d	1180	/@}/ /* end of group CMSIS_DWT */
<>	135:176b8275d35d	1181
<>	135:176b8275d35d	1182
<>	135:176b8275d35d	1183	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	1184	\defgroup CMSIS_TPI Trace Port Interface (TPI)
<>	135:176b8275d35d	1185	\brief Type definitions for the Trace Port Interface (TPI)
<>	135:176b8275d35d	1186	@{
<>	135:176b8275d35d	1187	*/
<>	135:176b8275d35d	1188
<>	135:176b8275d35d	1189	/** \brief Structure type to access the Trace Port Interface Register (TPI).
<>	135:176b8275d35d	1190	*/
<>	135:176b8275d35d	1191	typedef struct
<>	135:176b8275d35d	1192	{
<>	135:176b8275d35d	1193	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
<>	135:176b8275d35d	1194	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
<>	135:176b8275d35d	1195	uint32_t RESERVED0[2];
<>	135:176b8275d35d	1196	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
<>	135:176b8275d35d	1197	uint32_t RESERVED1[55];
<>	135:176b8275d35d	1198	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
<>	135:176b8275d35d	1199	uint32_t RESERVED2[131];
<>	135:176b8275d35d	1200	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
<>	135:176b8275d35d	1201	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
<>	135:176b8275d35d	1202	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
<>	135:176b8275d35d	1203	uint32_t RESERVED3[759];
<>	135:176b8275d35d	1204	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
<>	135:176b8275d35d	1205	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
<>	135:176b8275d35d	1206	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
<>	135:176b8275d35d	1207	uint32_t RESERVED4[1];
<>	135:176b8275d35d	1208	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
<>	135:176b8275d35d	1209	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
<>	135:176b8275d35d	1210	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
<>	135:176b8275d35d	1211	uint32_t RESERVED5[39];
<>	135:176b8275d35d	1212	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
<>	135:176b8275d35d	1213	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
<>	135:176b8275d35d	1214	uint32_t RESERVED7[8];
<>	135:176b8275d35d	1215	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
<>	135:176b8275d35d	1216	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
<>	135:176b8275d35d	1217	} TPI_Type;
<>	135:176b8275d35d	1218
<>	135:176b8275d35d	1219	/* TPI Asynchronous Clock Prescaler Register Definitions */
<>	135:176b8275d35d	1220	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
<>	135:176b8275d35d	1221	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
<>	135:176b8275d35d	1222
<>	135:176b8275d35d	1223	/* TPI Selected Pin Protocol Register Definitions */
<>	135:176b8275d35d	1224	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
<>	135:176b8275d35d	1225	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
<>	135:176b8275d35d	1226
<>	135:176b8275d35d	1227	/* TPI Formatter and Flush Status Register Definitions */
<>	135:176b8275d35d	1228	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
<>	135:176b8275d35d	1229	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
<>	135:176b8275d35d	1230
<>	135:176b8275d35d	1231	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
<>	135:176b8275d35d	1232	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
<>	135:176b8275d35d	1233
<>	135:176b8275d35d	1234	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
<>	135:176b8275d35d	1235	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
<>	135:176b8275d35d	1236
<>	135:176b8275d35d	1237	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
<>	135:176b8275d35d	1238	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
<>	135:176b8275d35d	1239
<>	135:176b8275d35d	1240	/* TPI Formatter and Flush Control Register Definitions */
<>	135:176b8275d35d	1241	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
<>	135:176b8275d35d	1242	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
<>	135:176b8275d35d	1243
<>	135:176b8275d35d	1244	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
<>	135:176b8275d35d	1245	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
<>	135:176b8275d35d	1246
<>	135:176b8275d35d	1247	/* TPI TRIGGER Register Definitions */
<>	135:176b8275d35d	1248	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
<>	135:176b8275d35d	1249	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
<>	135:176b8275d35d	1250
<>	135:176b8275d35d	1251	/* TPI Integration ETM Data Register Definitions (FIFO0) */
<>	135:176b8275d35d	1252	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
<>	135:176b8275d35d	1253	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
<>	135:176b8275d35d	1254
<>	135:176b8275d35d	1255	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
<>	135:176b8275d35d	1256	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
<>	135:176b8275d35d	1257
<>	135:176b8275d35d	1258	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
<>	135:176b8275d35d	1259	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
<>	135:176b8275d35d	1260
<>	135:176b8275d35d	1261	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
<>	135:176b8275d35d	1262	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
<>	135:176b8275d35d	1263
<>	135:176b8275d35d	1264	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
<>	135:176b8275d35d	1265	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
<>	135:176b8275d35d	1266
<>	135:176b8275d35d	1267	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
<>	135:176b8275d35d	1268	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
<>	135:176b8275d35d	1269
<>	135:176b8275d35d	1270	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
<>	135:176b8275d35d	1271	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
<>	135:176b8275d35d	1272
<>	135:176b8275d35d	1273	/* TPI ITATBCTR2 Register Definitions */
<>	135:176b8275d35d	1274	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
<>	135:176b8275d35d	1275	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
<>	135:176b8275d35d	1276
<>	135:176b8275d35d	1277	/* TPI Integration ITM Data Register Definitions (FIFO1) */
<>	135:176b8275d35d	1278	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
<>	135:176b8275d35d	1279	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
<>	135:176b8275d35d	1280
<>	135:176b8275d35d	1281	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
<>	135:176b8275d35d	1282	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
<>	135:176b8275d35d	1283
<>	135:176b8275d35d	1284	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
<>	135:176b8275d35d	1285	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
<>	135:176b8275d35d	1286
<>	135:176b8275d35d	1287	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
<>	135:176b8275d35d	1288	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
<>	135:176b8275d35d	1289
<>	135:176b8275d35d	1290	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
<>	135:176b8275d35d	1291	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
<>	135:176b8275d35d	1292
<>	135:176b8275d35d	1293	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
<>	135:176b8275d35d	1294	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
<>	135:176b8275d35d	1295
<>	135:176b8275d35d	1296	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
<>	135:176b8275d35d	1297	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
<>	135:176b8275d35d	1298
<>	135:176b8275d35d	1299	/* TPI ITATBCTR0 Register Definitions */
<>	135:176b8275d35d	1300	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
<>	135:176b8275d35d	1301	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
<>	135:176b8275d35d	1302
<>	135:176b8275d35d	1303	/* TPI Integration Mode Control Register Definitions */
<>	135:176b8275d35d	1304	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
<>	135:176b8275d35d	1305	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
<>	135:176b8275d35d	1306
<>	135:176b8275d35d	1307	/* TPI DEVID Register Definitions */
<>	135:176b8275d35d	1308	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
<>	135:176b8275d35d	1309	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
<>	135:176b8275d35d	1310
<>	135:176b8275d35d	1311	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
<>	135:176b8275d35d	1312	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
<>	135:176b8275d35d	1313
<>	135:176b8275d35d	1314	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
<>	135:176b8275d35d	1315	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
<>	135:176b8275d35d	1316
<>	135:176b8275d35d	1317	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
<>	135:176b8275d35d	1318	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
<>	135:176b8275d35d	1319
<>	135:176b8275d35d	1320	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
<>	135:176b8275d35d	1321	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
<>	135:176b8275d35d	1322
<>	135:176b8275d35d	1323	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
<>	135:176b8275d35d	1324	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
<>	135:176b8275d35d	1325
<>	135:176b8275d35d	1326	/* TPI DEVTYPE Register Definitions */
<>	135:176b8275d35d	1327	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
<>	135:176b8275d35d	1328	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
<>	135:176b8275d35d	1329
<>	135:176b8275d35d	1330	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
<>	135:176b8275d35d	1331	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
<>	135:176b8275d35d	1332
<>	135:176b8275d35d	1333	/@}/ /* end of group CMSIS_TPI */
<>	135:176b8275d35d	1334
<>	135:176b8275d35d	1335
<>	135:176b8275d35d	1336	#if (__MPU_PRESENT == 1)
<>	135:176b8275d35d	1337	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	1338	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
<>	135:176b8275d35d	1339	\brief Type definitions for the Memory Protection Unit (MPU)
<>	135:176b8275d35d	1340	@{
<>	135:176b8275d35d	1341	*/
<>	135:176b8275d35d	1342
<>	135:176b8275d35d	1343	/** \brief Structure type to access the Memory Protection Unit (MPU).
<>	135:176b8275d35d	1344	*/
<>	135:176b8275d35d	1345	typedef struct
<>	135:176b8275d35d	1346	{
<>	135:176b8275d35d	1347	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
<>	135:176b8275d35d	1348	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
<>	135:176b8275d35d	1349	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
<>	135:176b8275d35d	1350	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
<>	135:176b8275d35d	1351	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
<>	135:176b8275d35d	1352	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
<>	135:176b8275d35d	1353	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
<>	135:176b8275d35d	1354	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
<>	135:176b8275d35d	1355	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
<>	135:176b8275d35d	1356	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
<>	135:176b8275d35d	1357	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
<>	135:176b8275d35d	1358	} MPU_Type;
<>	135:176b8275d35d	1359
<>	135:176b8275d35d	1360	/* MPU Type Register */
<>	135:176b8275d35d	1361	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
<>	135:176b8275d35d	1362	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
<>	135:176b8275d35d	1363
<>	135:176b8275d35d	1364	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
<>	135:176b8275d35d	1365	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
<>	135:176b8275d35d	1366
<>	135:176b8275d35d	1367	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
<>	135:176b8275d35d	1368	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
<>	135:176b8275d35d	1369
<>	135:176b8275d35d	1370	/* MPU Control Register */
<>	135:176b8275d35d	1371	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
<>	135:176b8275d35d	1372	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
<>	135:176b8275d35d	1373
<>	135:176b8275d35d	1374	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
<>	135:176b8275d35d	1375	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
<>	135:176b8275d35d	1376
<>	135:176b8275d35d	1377	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
<>	135:176b8275d35d	1378	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
<>	135:176b8275d35d	1379
<>	135:176b8275d35d	1380	/* MPU Region Number Register */
<>	135:176b8275d35d	1381	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
<>	135:176b8275d35d	1382	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
<>	135:176b8275d35d	1383
<>	135:176b8275d35d	1384	/* MPU Region Base Address Register */
<>	135:176b8275d35d	1385	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
<>	135:176b8275d35d	1386	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
<>	135:176b8275d35d	1387
<>	135:176b8275d35d	1388	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
<>	135:176b8275d35d	1389	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
<>	135:176b8275d35d	1390
<>	135:176b8275d35d	1391	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
<>	135:176b8275d35d	1392	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
<>	135:176b8275d35d	1393
<>	135:176b8275d35d	1394	/* MPU Region Attribute and Size Register */
<>	135:176b8275d35d	1395	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
<>	135:176b8275d35d	1396	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
<>	135:176b8275d35d	1397
<>	135:176b8275d35d	1398	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
<>	135:176b8275d35d	1399	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
<>	135:176b8275d35d	1400
<>	135:176b8275d35d	1401	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
<>	135:176b8275d35d	1402	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
<>	135:176b8275d35d	1403
<>	135:176b8275d35d	1404	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
<>	135:176b8275d35d	1405	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
<>	135:176b8275d35d	1406
<>	135:176b8275d35d	1407	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
<>	135:176b8275d35d	1408	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
<>	135:176b8275d35d	1409
<>	135:176b8275d35d	1410	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
<>	135:176b8275d35d	1411	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
<>	135:176b8275d35d	1412
<>	135:176b8275d35d	1413	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
<>	135:176b8275d35d	1414	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
<>	135:176b8275d35d	1415
<>	135:176b8275d35d	1416	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
<>	135:176b8275d35d	1417	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
<>	135:176b8275d35d	1418
<>	135:176b8275d35d	1419	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
<>	135:176b8275d35d	1420	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
<>	135:176b8275d35d	1421
<>	135:176b8275d35d	1422	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
<>	135:176b8275d35d	1423	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
<>	135:176b8275d35d	1424
<>	135:176b8275d35d	1425	/@} end of group CMSIS_MPU /
<>	135:176b8275d35d	1426	#endif
<>	135:176b8275d35d	1427
<>	135:176b8275d35d	1428
<>	135:176b8275d35d	1429	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	1430	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	1431	\defgroup CMSIS_FPU Floating Point Unit (FPU)
<>	135:176b8275d35d	1432	\brief Type definitions for the Floating Point Unit (FPU)
<>	135:176b8275d35d	1433	@{
<>	135:176b8275d35d	1434	*/
<>	135:176b8275d35d	1435
<>	135:176b8275d35d	1436	/** \brief Structure type to access the Floating Point Unit (FPU).
<>	135:176b8275d35d	1437	*/
<>	135:176b8275d35d	1438	typedef struct
<>	135:176b8275d35d	1439	{
<>	135:176b8275d35d	1440	uint32_t RESERVED0[1];
<>	135:176b8275d35d	1441	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
<>	135:176b8275d35d	1442	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
<>	135:176b8275d35d	1443	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
<>	135:176b8275d35d	1444	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
<>	135:176b8275d35d	1445	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
<>	135:176b8275d35d	1446	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
<>	135:176b8275d35d	1447	} FPU_Type;
<>	135:176b8275d35d	1448
<>	135:176b8275d35d	1449	/* Floating-Point Context Control Register */
<>	135:176b8275d35d	1450	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
<>	135:176b8275d35d	1451	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
<>	135:176b8275d35d	1452
<>	135:176b8275d35d	1453	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
<>	135:176b8275d35d	1454	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
<>	135:176b8275d35d	1455
<>	135:176b8275d35d	1456	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
<>	135:176b8275d35d	1457	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
<>	135:176b8275d35d	1458
<>	135:176b8275d35d	1459	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
<>	135:176b8275d35d	1460	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
<>	135:176b8275d35d	1461
<>	135:176b8275d35d	1462	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
<>	135:176b8275d35d	1463	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
<>	135:176b8275d35d	1464
<>	135:176b8275d35d	1465	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
<>	135:176b8275d35d	1466	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
<>	135:176b8275d35d	1467
<>	135:176b8275d35d	1468	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
<>	135:176b8275d35d	1469	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
<>	135:176b8275d35d	1470
<>	135:176b8275d35d	1471	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
<>	135:176b8275d35d	1472	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
<>	135:176b8275d35d	1473
<>	135:176b8275d35d	1474	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
<>	135:176b8275d35d	1475	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
<>	135:176b8275d35d	1476
<>	135:176b8275d35d	1477	/* Floating-Point Context Address Register */
<>	135:176b8275d35d	1478	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
<>	135:176b8275d35d	1479	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
<>	135:176b8275d35d	1480
<>	135:176b8275d35d	1481	/* Floating-Point Default Status Control Register */
<>	135:176b8275d35d	1482	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
<>	135:176b8275d35d	1483	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
<>	135:176b8275d35d	1484
<>	135:176b8275d35d	1485	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
<>	135:176b8275d35d	1486	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
<>	135:176b8275d35d	1487
<>	135:176b8275d35d	1488	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
<>	135:176b8275d35d	1489	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
<>	135:176b8275d35d	1490
<>	135:176b8275d35d	1491	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
<>	135:176b8275d35d	1492	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
<>	135:176b8275d35d	1493
<>	135:176b8275d35d	1494	/* Media and FP Feature Register 0 */
<>	135:176b8275d35d	1495	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
<>	135:176b8275d35d	1496	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
<>	135:176b8275d35d	1497
<>	135:176b8275d35d	1498	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
<>	135:176b8275d35d	1499	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
<>	135:176b8275d35d	1500
<>	135:176b8275d35d	1501	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
<>	135:176b8275d35d	1502	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
<>	135:176b8275d35d	1503
<>	135:176b8275d35d	1504	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
<>	135:176b8275d35d	1505	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
<>	135:176b8275d35d	1506
<>	135:176b8275d35d	1507	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
<>	135:176b8275d35d	1508	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
<>	135:176b8275d35d	1509
<>	135:176b8275d35d	1510	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
<>	135:176b8275d35d	1511	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
<>	135:176b8275d35d	1512
<>	135:176b8275d35d	1513	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
<>	135:176b8275d35d	1514	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
<>	135:176b8275d35d	1515
<>	135:176b8275d35d	1516	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
<>	135:176b8275d35d	1517	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
<>	135:176b8275d35d	1518
<>	135:176b8275d35d	1519	/* Media and FP Feature Register 1 */
<>	135:176b8275d35d	1520	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
<>	135:176b8275d35d	1521	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
<>	135:176b8275d35d	1522
<>	135:176b8275d35d	1523	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
<>	135:176b8275d35d	1524	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
<>	135:176b8275d35d	1525
<>	135:176b8275d35d	1526	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
<>	135:176b8275d35d	1527	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
<>	135:176b8275d35d	1528
<>	135:176b8275d35d	1529	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
<>	135:176b8275d35d	1530	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
<>	135:176b8275d35d	1531
<>	135:176b8275d35d	1532	/* Media and FP Feature Register 2 */
<>	135:176b8275d35d	1533
<>	135:176b8275d35d	1534	/@} end of group CMSIS_FPU /
<>	135:176b8275d35d	1535	#endif
<>	135:176b8275d35d	1536
<>	135:176b8275d35d	1537
<>	135:176b8275d35d	1538	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	1539	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<>	135:176b8275d35d	1540	\brief Type definitions for the Core Debug Registers
<>	135:176b8275d35d	1541	@{
<>	135:176b8275d35d	1542	*/
<>	135:176b8275d35d	1543
<>	135:176b8275d35d	1544	/** \brief Structure type to access the Core Debug Register (CoreDebug).
<>	135:176b8275d35d	1545	*/
<>	135:176b8275d35d	1546	typedef struct
<>	135:176b8275d35d	1547	{
<>	135:176b8275d35d	1548	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
<>	135:176b8275d35d	1549	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
<>	135:176b8275d35d	1550	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
<>	135:176b8275d35d	1551	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
<>	135:176b8275d35d	1552	} CoreDebug_Type;
<>	135:176b8275d35d	1553
<>	135:176b8275d35d	1554	/* Debug Halting Control and Status Register */
<>	135:176b8275d35d	1555	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
<>	135:176b8275d35d	1556	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
<>	135:176b8275d35d	1557
<>	135:176b8275d35d	1558	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
<>	135:176b8275d35d	1559	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
<>	135:176b8275d35d	1560
<>	135:176b8275d35d	1561	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
<>	135:176b8275d35d	1562	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
<>	135:176b8275d35d	1563
<>	135:176b8275d35d	1564	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
<>	135:176b8275d35d	1565	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
<>	135:176b8275d35d	1566
<>	135:176b8275d35d	1567	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
<>	135:176b8275d35d	1568	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
<>	135:176b8275d35d	1569
<>	135:176b8275d35d	1570	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
<>	135:176b8275d35d	1571	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
<>	135:176b8275d35d	1572
<>	135:176b8275d35d	1573	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
<>	135:176b8275d35d	1574	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
<>	135:176b8275d35d	1575
<>	135:176b8275d35d	1576	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
<>	135:176b8275d35d	1577	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
<>	135:176b8275d35d	1578
<>	135:176b8275d35d	1579	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
<>	135:176b8275d35d	1580	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
<>	135:176b8275d35d	1581
<>	135:176b8275d35d	1582	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
<>	135:176b8275d35d	1583	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
<>	135:176b8275d35d	1584
<>	135:176b8275d35d	1585	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
<>	135:176b8275d35d	1586	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
<>	135:176b8275d35d	1587
<>	135:176b8275d35d	1588	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
<>	135:176b8275d35d	1589	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
<>	135:176b8275d35d	1590
<>	135:176b8275d35d	1591	/* Debug Core Register Selector Register */
<>	135:176b8275d35d	1592	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
<>	135:176b8275d35d	1593	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
<>	135:176b8275d35d	1594
<>	135:176b8275d35d	1595	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
<>	135:176b8275d35d	1596	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
<>	135:176b8275d35d	1597
<>	135:176b8275d35d	1598	/* Debug Exception and Monitor Control Register */
<>	135:176b8275d35d	1599	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
<>	135:176b8275d35d	1600	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
<>	135:176b8275d35d	1601
<>	135:176b8275d35d	1602	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
<>	135:176b8275d35d	1603	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
<>	135:176b8275d35d	1604
<>	135:176b8275d35d	1605	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
<>	135:176b8275d35d	1606	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
<>	135:176b8275d35d	1607
<>	135:176b8275d35d	1608	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
<>	135:176b8275d35d	1609	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
<>	135:176b8275d35d	1610
<>	135:176b8275d35d	1611	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
<>	135:176b8275d35d	1612	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
<>	135:176b8275d35d	1613
<>	135:176b8275d35d	1614	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
<>	135:176b8275d35d	1615	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
<>	135:176b8275d35d	1616
<>	135:176b8275d35d	1617	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
<>	135:176b8275d35d	1618	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
<>	135:176b8275d35d	1619
<>	135:176b8275d35d	1620	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
<>	135:176b8275d35d	1621	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
<>	135:176b8275d35d	1622
<>	135:176b8275d35d	1623	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
<>	135:176b8275d35d	1624	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
<>	135:176b8275d35d	1625
<>	135:176b8275d35d	1626	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
<>	135:176b8275d35d	1627	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
<>	135:176b8275d35d	1628
<>	135:176b8275d35d	1629	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
<>	135:176b8275d35d	1630	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
<>	135:176b8275d35d	1631
<>	135:176b8275d35d	1632	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
<>	135:176b8275d35d	1633	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
<>	135:176b8275d35d	1634
<>	135:176b8275d35d	1635	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
<>	135:176b8275d35d	1636	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
<>	135:176b8275d35d	1637
<>	135:176b8275d35d	1638	/@} end of group CMSIS_CoreDebug /
<>	135:176b8275d35d	1639
<>	135:176b8275d35d	1640
<>	135:176b8275d35d	1641	/** \ingroup CMSIS_core_register
<>	135:176b8275d35d	1642	\defgroup CMSIS_core_base Core Definitions
<>	135:176b8275d35d	1643	\brief Definitions for base addresses, unions, and structures.
<>	135:176b8275d35d	1644	@{
<>	135:176b8275d35d	1645	*/
<>	135:176b8275d35d	1646
<>	135:176b8275d35d	1647	/* Memory mapping of Cortex-M4 Hardware */
<>	135:176b8275d35d	1648	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
<>	135:176b8275d35d	1649	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
<>	135:176b8275d35d	1650	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
<>	135:176b8275d35d	1651	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
<>	135:176b8275d35d	1652	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
<>	135:176b8275d35d	1653	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
<>	135:176b8275d35d	1654	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
<>	135:176b8275d35d	1655	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
<>	135:176b8275d35d	1656
<>	135:176b8275d35d	1657	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
<>	135:176b8275d35d	1658	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
<>	135:176b8275d35d	1659	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
<>	135:176b8275d35d	1660	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
<>	135:176b8275d35d	1661	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
<>	135:176b8275d35d	1662	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
<>	135:176b8275d35d	1663	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
<>	135:176b8275d35d	1664	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
<>	135:176b8275d35d	1665
<>	135:176b8275d35d	1666	#if (__MPU_PRESENT == 1)
<>	135:176b8275d35d	1667	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
<>	135:176b8275d35d	1668	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
<>	135:176b8275d35d	1669	#endif
<>	135:176b8275d35d	1670
<>	135:176b8275d35d	1671	#if (__FPU_PRESENT == 1)
<>	135:176b8275d35d	1672	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
<>	135:176b8275d35d	1673	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
<>	135:176b8275d35d	1674	#endif
<>	135:176b8275d35d	1675
<>	135:176b8275d35d	1676	/@} /
<>	135:176b8275d35d	1677
<>	135:176b8275d35d	1678
<>	135:176b8275d35d	1679
<>	135:176b8275d35d	1680	/*******************************************************************************
<>	135:176b8275d35d	1681	* Hardware Abstraction Layer
<>	135:176b8275d35d	1682	Core Function Interface contains:
<>	135:176b8275d35d	1683	- Core NVIC Functions
<>	135:176b8275d35d	1684	- Core SysTick Functions
<>	135:176b8275d35d	1685	- Core Debug Functions
<>	135:176b8275d35d	1686	- Core Register Access Functions
<>	135:176b8275d35d	1687	******************************************************************************/
<>	135:176b8275d35d	1688	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<>	135:176b8275d35d	1689	*/
<>	135:176b8275d35d	1690
<>	135:176b8275d35d	1691
<>	135:176b8275d35d	1692
<>	135:176b8275d35d	1693	/* ########################## NVIC functions #################################### */
<>	135:176b8275d35d	1694	/** \ingroup CMSIS_Core_FunctionInterface
<>	135:176b8275d35d	1695	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
<>	135:176b8275d35d	1696	\brief Functions that manage interrupts and exceptions via the NVIC.
<>	135:176b8275d35d	1697	@{
<>	135:176b8275d35d	1698	*/
<>	135:176b8275d35d	1699
<>	135:176b8275d35d	1700	/** \brief Set Priority Grouping
<>	135:176b8275d35d	1701
<>	135:176b8275d35d	1702	The function sets the priority grouping field using the required unlock sequence.
<>	135:176b8275d35d	1703	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<>	135:176b8275d35d	1704	Only values from 0..7 are used.
<>	135:176b8275d35d	1705	In case of a conflict between priority grouping and available
<>	135:176b8275d35d	1706	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<>	135:176b8275d35d	1707
<>	135:176b8275d35d	1708	\param [in] PriorityGroup Priority grouping field.
<>	135:176b8275d35d	1709	*/
<>	135:176b8275d35d	1710	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<>	135:176b8275d35d	1711	{
<>	135:176b8275d35d	1712	uint32_t reg_value;
<>	135:176b8275d35d	1713	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	135:176b8275d35d	1714
<>	135:176b8275d35d	1715	reg_value = SCB->AIRCR; /* read old register configuration */
<>	135:176b8275d35d	1716	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<>	135:176b8275d35d	1717	reg_value = (reg_value \|
<>	135:176b8275d35d	1718	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	135:176b8275d35d	1719	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<>	135:176b8275d35d	1720	SCB->AIRCR = reg_value;
<>	135:176b8275d35d	1721	}
<>	135:176b8275d35d	1722
<>	135:176b8275d35d	1723
<>	135:176b8275d35d	1724	/** \brief Get Priority Grouping
<>	135:176b8275d35d	1725
<>	135:176b8275d35d	1726	The function reads the priority grouping field from the NVIC Interrupt Controller.
<>	135:176b8275d35d	1727
<>	135:176b8275d35d	1728	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<>	135:176b8275d35d	1729	*/
<>	135:176b8275d35d	1730	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
<>	135:176b8275d35d	1731	{
<>	135:176b8275d35d	1732	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<>	135:176b8275d35d	1733	}
<>	135:176b8275d35d	1734
<>	135:176b8275d35d	1735
<>	135:176b8275d35d	1736	/** \brief Enable External Interrupt
<>	135:176b8275d35d	1737
<>	135:176b8275d35d	1738	The function enables a device-specific interrupt in the NVIC interrupt controller.
<>	135:176b8275d35d	1739
<>	135:176b8275d35d	1740	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	135:176b8275d35d	1741	*/
<>	135:176b8275d35d	1742	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<>	135:176b8275d35d	1743	{
<>	135:176b8275d35d	1744	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	135:176b8275d35d	1745	}
<>	135:176b8275d35d	1746
<>	135:176b8275d35d	1747
<>	135:176b8275d35d	1748	/** \brief Disable External Interrupt
<>	135:176b8275d35d	1749
<>	135:176b8275d35d	1750	The function disables a device-specific interrupt in the NVIC interrupt controller.
<>	135:176b8275d35d	1751
<>	135:176b8275d35d	1752	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	135:176b8275d35d	1753	*/
<>	135:176b8275d35d	1754	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<>	135:176b8275d35d	1755	{
<>	135:176b8275d35d	1756	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	135:176b8275d35d	1757	__DSB();
<>	135:176b8275d35d	1758	__ISB();
<>	135:176b8275d35d	1759	}
<>	135:176b8275d35d	1760
<>	135:176b8275d35d	1761
<>	135:176b8275d35d	1762	/** \brief Get Pending Interrupt
<>	135:176b8275d35d	1763
<>	135:176b8275d35d	1764	The function reads the pending register in the NVIC and returns the pending bit
<>	135:176b8275d35d	1765	for the specified interrupt.
<>	135:176b8275d35d	1766
<>	135:176b8275d35d	1767	\param [in] IRQn Interrupt number.
<>	135:176b8275d35d	1768
<>	135:176b8275d35d	1769	\return 0 Interrupt status is not pending.
<>	135:176b8275d35d	1770	\return 1 Interrupt status is pending.
<>	135:176b8275d35d	1771	*/
<>	135:176b8275d35d	1772	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<>	135:176b8275d35d	1773	{
<>	135:176b8275d35d	1774	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<>	135:176b8275d35d	1775	}
<>	135:176b8275d35d	1776
<>	135:176b8275d35d	1777
<>	135:176b8275d35d	1778	/** \brief Set Pending Interrupt
<>	135:176b8275d35d	1779
<>	135:176b8275d35d	1780	The function sets the pending bit of an external interrupt.
<>	135:176b8275d35d	1781
<>	135:176b8275d35d	1782	\param [in] IRQn Interrupt number. Value cannot be negative.
<>	135:176b8275d35d	1783	*/
<>	135:176b8275d35d	1784	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<>	135:176b8275d35d	1785	{
<>	135:176b8275d35d	1786	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	135:176b8275d35d	1787	}
<>	135:176b8275d35d	1788
<>	135:176b8275d35d	1789
<>	135:176b8275d35d	1790	/** \brief Clear Pending Interrupt
<>	135:176b8275d35d	1791
<>	135:176b8275d35d	1792	The function clears the pending bit of an external interrupt.
<>	135:176b8275d35d	1793
<>	135:176b8275d35d	1794	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	135:176b8275d35d	1795	*/
<>	135:176b8275d35d	1796	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<>	135:176b8275d35d	1797	{
<>	135:176b8275d35d	1798	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	135:176b8275d35d	1799	}
<>	135:176b8275d35d	1800
<>	135:176b8275d35d	1801
<>	135:176b8275d35d	1802	/** \brief Get Active Interrupt
<>	135:176b8275d35d	1803
<>	135:176b8275d35d	1804	The function reads the active register in NVIC and returns the active bit.
<>	135:176b8275d35d	1805
<>	135:176b8275d35d	1806	\param [in] IRQn Interrupt number.
<>	135:176b8275d35d	1807
<>	135:176b8275d35d	1808	\return 0 Interrupt status is not active.
<>	135:176b8275d35d	1809	\return 1 Interrupt status is active.
<>	135:176b8275d35d	1810	*/
<>	135:176b8275d35d	1811	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
<>	135:176b8275d35d	1812	{
<>	135:176b8275d35d	1813	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<>	135:176b8275d35d	1814	}
<>	135:176b8275d35d	1815
<>	135:176b8275d35d	1816
<>	135:176b8275d35d	1817	/** \brief Set Interrupt Priority
<>	135:176b8275d35d	1818
<>	135:176b8275d35d	1819	The function sets the priority of an interrupt.
<>	135:176b8275d35d	1820
<>	135:176b8275d35d	1821	\note The priority cannot be set for every core interrupt.
<>	135:176b8275d35d	1822
<>	135:176b8275d35d	1823	\param [in] IRQn Interrupt number.
<>	135:176b8275d35d	1824	\param [in] priority Priority to set.
<>	135:176b8275d35d	1825	*/
<>	135:176b8275d35d	1826	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<>	135:176b8275d35d	1827	{
<>	135:176b8275d35d	1828	if((int32_t)IRQn < 0) {
<>	135:176b8275d35d	1829	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<>	135:176b8275d35d	1830	}
<>	135:176b8275d35d	1831	else {
<>	135:176b8275d35d	1832	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<>	135:176b8275d35d	1833	}
<>	135:176b8275d35d	1834	}
<>	135:176b8275d35d	1835
<>	135:176b8275d35d	1836
<>	135:176b8275d35d	1837	/** \brief Get Interrupt Priority
<>	135:176b8275d35d	1838
<>	135:176b8275d35d	1839	The function reads the priority of an interrupt. The interrupt
<>	135:176b8275d35d	1840	number can be positive to specify an external (device specific)
<>	135:176b8275d35d	1841	interrupt, or negative to specify an internal (core) interrupt.
<>	135:176b8275d35d	1842
<>	135:176b8275d35d	1843
<>	135:176b8275d35d	1844	\param [in] IRQn Interrupt number.
<>	135:176b8275d35d	1845	\return Interrupt Priority. Value is aligned automatically to the implemented
<>	135:176b8275d35d	1846	priority bits of the microcontroller.
<>	135:176b8275d35d	1847	*/
<>	135:176b8275d35d	1848	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<>	135:176b8275d35d	1849	{
<>	135:176b8275d35d	1850
<>	135:176b8275d35d	1851	if((int32_t)IRQn < 0) {
<>	135:176b8275d35d	1852	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<>	135:176b8275d35d	1853	}
<>	135:176b8275d35d	1854	else {
<>	135:176b8275d35d	1855	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<>	135:176b8275d35d	1856	}
<>	135:176b8275d35d	1857	}
<>	135:176b8275d35d	1858
<>	135:176b8275d35d	1859
<>	135:176b8275d35d	1860	/** \brief Encode Priority
<>	135:176b8275d35d	1861
<>	135:176b8275d35d	1862	The function encodes the priority for an interrupt with the given priority group,
<>	135:176b8275d35d	1863	preemptive priority value, and subpriority value.
<>	135:176b8275d35d	1864	In case of a conflict between priority grouping and available
<>	135:176b8275d35d	1865	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<>	135:176b8275d35d	1866
<>	135:176b8275d35d	1867	\param [in] PriorityGroup Used priority group.
<>	135:176b8275d35d	1868	\param [in] PreemptPriority Preemptive priority value (starting from 0).
<>	135:176b8275d35d	1869	\param [in] SubPriority Subpriority value (starting from 0).
<>	135:176b8275d35d	1870	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<>	135:176b8275d35d	1871	*/
<>	135:176b8275d35d	1872	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<>	135:176b8275d35d	1873	{
<>	135:176b8275d35d	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	135:176b8275d35d	1875	uint32_t PreemptPriorityBits;
<>	135:176b8275d35d	1876	uint32_t SubPriorityBits;
<>	135:176b8275d35d	1877
<>	135:176b8275d35d	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	135:176b8275d35d	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	135:176b8275d35d	1880
<>	135:176b8275d35d	1881	return (
<>	135:176b8275d35d	1882	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
<>	135:176b8275d35d	1883	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<>	135:176b8275d35d	1884	);
<>	135:176b8275d35d	1885	}
<>	135:176b8275d35d	1886
<>	135:176b8275d35d	1887
<>	135:176b8275d35d	1888	/** \brief Decode Priority
<>	135:176b8275d35d	1889
<>	135:176b8275d35d	1890	The function decodes an interrupt priority value with a given priority group to
<>	135:176b8275d35d	1891	preemptive priority value and subpriority value.
<>	135:176b8275d35d	1892	In case of a conflict between priority grouping and available
<>	135:176b8275d35d	1893	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<>	135:176b8275d35d	1894
<>	135:176b8275d35d	1895	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<>	135:176b8275d35d	1896	\param [in] PriorityGroup Used priority group.
<>	135:176b8275d35d	1897	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
<>	135:176b8275d35d	1898	\param [out] pSubPriority Subpriority value (starting from 0).
<>	135:176b8275d35d	1899	*/
<>	135:176b8275d35d	1900	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<>	135:176b8275d35d	1901	{
<>	135:176b8275d35d	1902	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	135:176b8275d35d	1903	uint32_t PreemptPriorityBits;
<>	135:176b8275d35d	1904	uint32_t SubPriorityBits;
<>	135:176b8275d35d	1905
<>	135:176b8275d35d	1906	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	135:176b8275d35d	1907	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	135:176b8275d35d	1908
<>	135:176b8275d35d	1909	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<>	135:176b8275d35d	1910	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<>	135:176b8275d35d	1911	}
<>	135:176b8275d35d	1912
<>	135:176b8275d35d	1913
<>	135:176b8275d35d	1914	/** \brief System Reset
<>	135:176b8275d35d	1915
<>	135:176b8275d35d	1916	The function initiates a system reset request to reset the MCU.
<>	135:176b8275d35d	1917	*/
<>	135:176b8275d35d	1918	__STATIC_INLINE void NVIC_SystemReset(void)
<>	135:176b8275d35d	1919	{
<>	135:176b8275d35d	1920	__DSB(); /* Ensure all outstanding memory accesses included
<>	135:176b8275d35d	1921	buffered write are completed before reset */
<>	135:176b8275d35d	1922	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	135:176b8275d35d	1923	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
<>	135:176b8275d35d	1924	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<>	135:176b8275d35d	1925	__DSB(); /* Ensure completion of memory access */
<>	135:176b8275d35d	1926	while(1) { __NOP(); } /* wait until reset */
<>	135:176b8275d35d	1927	}
<>	135:176b8275d35d	1928
<>	135:176b8275d35d	1929	/@} end of CMSIS_Core_NVICFunctions /
<>	135:176b8275d35d	1930
<>	135:176b8275d35d	1931
<>	135:176b8275d35d	1932	/* ########################## FPU functions #################################### */
<>	135:176b8275d35d	1933	/** \ingroup CMSIS_Core_FunctionInterface
<>	135:176b8275d35d	1934	\defgroup CMSIS_Core_FpuFunctions FPU Functions
<>	135:176b8275d35d	1935	\brief Function that provides FPU type.
<>	135:176b8275d35d	1936	@{
<>	135:176b8275d35d	1937	*/
<>	135:176b8275d35d	1938
<>	135:176b8275d35d	1939	/**
<>	135:176b8275d35d	1940	\fn uint32_t SCB_GetFPUType(void)
<>	135:176b8275d35d	1941	\brief get FPU type
<>	135:176b8275d35d	1942	\returns
<>	135:176b8275d35d	1943	- \b 0: No FPU
<>	135:176b8275d35d	1944	- \b 1: Single precision FPU
<>	135:176b8275d35d	1945	- \b 2: Double + Single precision FPU
<>	135:176b8275d35d	1946	*/
<>	135:176b8275d35d	1947	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
<>	135:176b8275d35d	1948	{
<>	135:176b8275d35d	1949	uint32_t mvfr0;
<>	135:176b8275d35d	1950
<>	135:176b8275d35d	1951	mvfr0 = SCB->MVFR0;
<>	135:176b8275d35d	1952	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
<>	135:176b8275d35d	1953	return 2UL; // Double + Single precision FPU
<>	135:176b8275d35d	1954	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
<>	135:176b8275d35d	1955	return 1UL; // Single precision FPU
<>	135:176b8275d35d	1956	} else {
<>	135:176b8275d35d	1957	return 0UL; // No FPU
<>	135:176b8275d35d	1958	}
<>	135:176b8275d35d	1959	}
<>	135:176b8275d35d	1960
<>	135:176b8275d35d	1961
<>	135:176b8275d35d	1962	/@} end of CMSIS_Core_FpuFunctions /
<>	135:176b8275d35d	1963
<>	135:176b8275d35d	1964
<>	135:176b8275d35d	1965
<>	135:176b8275d35d	1966	/* ########################## Cache functions #################################### */
<>	135:176b8275d35d	1967	/** \ingroup CMSIS_Core_FunctionInterface
<>	135:176b8275d35d	1968	\defgroup CMSIS_Core_CacheFunctions Cache Functions
<>	135:176b8275d35d	1969	\brief Functions that configure Instruction and Data cache.
<>	135:176b8275d35d	1970	@{
<>	135:176b8275d35d	1971	*/
<>	135:176b8275d35d	1972
<>	135:176b8275d35d	1973	/* Cache Size ID Register Macros */
<>	135:176b8275d35d	1974	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
<>	135:176b8275d35d	1975	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
<>	135:176b8275d35d	1976	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
<>	135:176b8275d35d	1977
<>	135:176b8275d35d	1978
<>	135:176b8275d35d	1979	/** \brief Enable I-Cache
<>	135:176b8275d35d	1980
<>	135:176b8275d35d	1981	The function turns on I-Cache
<>	135:176b8275d35d	1982	*/
<>	135:176b8275d35d	1983	__STATIC_INLINE void SCB_EnableICache (void)
<>	135:176b8275d35d	1984	{
<>	135:176b8275d35d	1985	#if (__ICACHE_PRESENT == 1)
<>	135:176b8275d35d	1986	__DSB();
<>	135:176b8275d35d	1987	__ISB();
<>	135:176b8275d35d	1988	SCB->ICIALLU = 0UL; // invalidate I-Cache
<>	135:176b8275d35d	1989	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
<>	135:176b8275d35d	1990	__DSB();
<>	135:176b8275d35d	1991	__ISB();
<>	135:176b8275d35d	1992	#endif
<>	135:176b8275d35d	1993	}
<>	135:176b8275d35d	1994
<>	135:176b8275d35d	1995
<>	135:176b8275d35d	1996	/** \brief Disable I-Cache
<>	135:176b8275d35d	1997
<>	135:176b8275d35d	1998	The function turns off I-Cache
<>	135:176b8275d35d	1999	*/
<>	135:176b8275d35d	2000	__STATIC_INLINE void SCB_DisableICache (void)
<>	135:176b8275d35d	2001	{
<>	135:176b8275d35d	2002	#if (__ICACHE_PRESENT == 1)
<>	135:176b8275d35d	2003	__DSB();
<>	135:176b8275d35d	2004	__ISB();
<>	135:176b8275d35d	2005	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
<>	135:176b8275d35d	2006	SCB->ICIALLU = 0UL; // invalidate I-Cache
<>	135:176b8275d35d	2007	__DSB();
<>	135:176b8275d35d	2008	__ISB();
<>	135:176b8275d35d	2009	#endif
<>	135:176b8275d35d	2010	}
<>	135:176b8275d35d	2011
<>	135:176b8275d35d	2012
<>	135:176b8275d35d	2013	/** \brief Invalidate I-Cache
<>	135:176b8275d35d	2014
<>	135:176b8275d35d	2015	The function invalidates I-Cache
<>	135:176b8275d35d	2016	*/
<>	135:176b8275d35d	2017	__STATIC_INLINE void SCB_InvalidateICache (void)
<>	135:176b8275d35d	2018	{
<>	135:176b8275d35d	2019	#if (__ICACHE_PRESENT == 1)
<>	135:176b8275d35d	2020	__DSB();
<>	135:176b8275d35d	2021	__ISB();
<>	135:176b8275d35d	2022	SCB->ICIALLU = 0UL;
<>	135:176b8275d35d	2023	__DSB();
<>	135:176b8275d35d	2024	__ISB();
<>	135:176b8275d35d	2025	#endif
<>	135:176b8275d35d	2026	}
<>	135:176b8275d35d	2027
<>	135:176b8275d35d	2028
<>	135:176b8275d35d	2029	/** \brief Enable D-Cache
<>	135:176b8275d35d	2030
<>	135:176b8275d35d	2031	The function turns on D-Cache
<>	135:176b8275d35d	2032	*/
<>	135:176b8275d35d	2033	__STATIC_INLINE void SCB_EnableDCache (void)
<>	135:176b8275d35d	2034	{
<>	135:176b8275d35d	2035	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2036	uint32_t ccsidr, sshift, wshift, sw;
<>	135:176b8275d35d	2037	uint32_t sets, ways;
<>	135:176b8275d35d	2038
<>	135:176b8275d35d	2039	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
<>	135:176b8275d35d	2040	ccsidr = SCB->CCSIDR;
<>	135:176b8275d35d	2041	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<>	135:176b8275d35d	2042	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<>	135:176b8275d35d	2043	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<>	135:176b8275d35d	2044	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<>	135:176b8275d35d	2045
<>	135:176b8275d35d	2046	__DSB();
<>	135:176b8275d35d	2047
<>	135:176b8275d35d	2048	do { // invalidate D-Cache
<>	135:176b8275d35d	2049	uint32_t tmpways = ways;
<>	135:176b8275d35d	2050	do {
<>	135:176b8275d35d	2051	sw = ((tmpways << wshift) \| (sets << sshift));
<>	135:176b8275d35d	2052	SCB->DCISW = sw;
<>	135:176b8275d35d	2053	} while(tmpways--);
<>	135:176b8275d35d	2054	} while(sets--);
<>	135:176b8275d35d	2055	__DSB();
<>	135:176b8275d35d	2056
<>	135:176b8275d35d	2057	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
<>	135:176b8275d35d	2058
<>	135:176b8275d35d	2059	__DSB();
<>	135:176b8275d35d	2060	__ISB();
<>	135:176b8275d35d	2061	#endif
<>	135:176b8275d35d	2062	}
<>	135:176b8275d35d	2063
<>	135:176b8275d35d	2064
<>	135:176b8275d35d	2065	/** \brief Disable D-Cache
<>	135:176b8275d35d	2066
<>	135:176b8275d35d	2067	The function turns off D-Cache
<>	135:176b8275d35d	2068	*/
<>	135:176b8275d35d	2069	__STATIC_INLINE void SCB_DisableDCache (void)
<>	135:176b8275d35d	2070	{
<>	135:176b8275d35d	2071	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2072	uint32_t ccsidr, sshift, wshift, sw;
<>	135:176b8275d35d	2073	uint32_t sets, ways;
<>	135:176b8275d35d	2074
<>	135:176b8275d35d	2075	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
<>	135:176b8275d35d	2076	ccsidr = SCB->CCSIDR;
<>	135:176b8275d35d	2077	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<>	135:176b8275d35d	2078	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<>	135:176b8275d35d	2079	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<>	135:176b8275d35d	2080	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<>	135:176b8275d35d	2081
<>	135:176b8275d35d	2082	__DSB();
<>	135:176b8275d35d	2083
<>	135:176b8275d35d	2084	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
<>	135:176b8275d35d	2085
<>	135:176b8275d35d	2086	do { // clean & invalidate D-Cache
<>	135:176b8275d35d	2087	uint32_t tmpways = ways;
<>	135:176b8275d35d	2088	do {
<>	135:176b8275d35d	2089	sw = ((tmpways << wshift) \| (sets << sshift));
<>	135:176b8275d35d	2090	SCB->DCCISW = sw;
<>	135:176b8275d35d	2091	} while(tmpways--);
<>	135:176b8275d35d	2092	} while(sets--);
<>	135:176b8275d35d	2093
<>	135:176b8275d35d	2094
<>	135:176b8275d35d	2095	__DSB();
<>	135:176b8275d35d	2096	__ISB();
<>	135:176b8275d35d	2097	#endif
<>	135:176b8275d35d	2098	}
<>	135:176b8275d35d	2099
<>	135:176b8275d35d	2100
<>	135:176b8275d35d	2101	/** \brief Invalidate D-Cache
<>	135:176b8275d35d	2102
<>	135:176b8275d35d	2103	The function invalidates D-Cache
<>	135:176b8275d35d	2104	*/
<>	135:176b8275d35d	2105	__STATIC_INLINE void SCB_InvalidateDCache (void)
<>	135:176b8275d35d	2106	{
<>	135:176b8275d35d	2107	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2108	uint32_t ccsidr, sshift, wshift, sw;
<>	135:176b8275d35d	2109	uint32_t sets, ways;
<>	135:176b8275d35d	2110
<>	135:176b8275d35d	2111	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
<>	135:176b8275d35d	2112	ccsidr = SCB->CCSIDR;
<>	135:176b8275d35d	2113	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<>	135:176b8275d35d	2114	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<>	135:176b8275d35d	2115	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<>	135:176b8275d35d	2116	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<>	135:176b8275d35d	2117
<>	135:176b8275d35d	2118	__DSB();
<>	135:176b8275d35d	2119
<>	135:176b8275d35d	2120	do { // invalidate D-Cache
<>	135:176b8275d35d	2121	uint32_t tmpways = ways;
<>	135:176b8275d35d	2122	do {
<>	135:176b8275d35d	2123	sw = ((tmpways << wshift) \| (sets << sshift));
<>	135:176b8275d35d	2124	SCB->DCISW = sw;
<>	135:176b8275d35d	2125	} while(tmpways--);
<>	135:176b8275d35d	2126	} while(sets--);
<>	135:176b8275d35d	2127
<>	135:176b8275d35d	2128	__DSB();
<>	135:176b8275d35d	2129	__ISB();
<>	135:176b8275d35d	2130	#endif
<>	135:176b8275d35d	2131	}
<>	135:176b8275d35d	2132
<>	135:176b8275d35d	2133
<>	135:176b8275d35d	2134	/** \brief Clean D-Cache
<>	135:176b8275d35d	2135
<>	135:176b8275d35d	2136	The function cleans D-Cache
<>	135:176b8275d35d	2137	*/
<>	135:176b8275d35d	2138	__STATIC_INLINE void SCB_CleanDCache (void)
<>	135:176b8275d35d	2139	{
<>	135:176b8275d35d	2140	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2141	uint32_t ccsidr, sshift, wshift, sw;
<>	135:176b8275d35d	2142	uint32_t sets, ways;
<>	135:176b8275d35d	2143
<>	135:176b8275d35d	2144	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
<>	135:176b8275d35d	2145	ccsidr = SCB->CCSIDR;
<>	135:176b8275d35d	2146	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<>	135:176b8275d35d	2147	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<>	135:176b8275d35d	2148	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<>	135:176b8275d35d	2149	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<>	135:176b8275d35d	2150
<>	135:176b8275d35d	2151	__DSB();
<>	135:176b8275d35d	2152
<>	135:176b8275d35d	2153	do { // clean D-Cache
<>	135:176b8275d35d	2154	uint32_t tmpways = ways;
<>	135:176b8275d35d	2155	do {
<>	135:176b8275d35d	2156	sw = ((tmpways << wshift) \| (sets << sshift));
<>	135:176b8275d35d	2157	SCB->DCCSW = sw;
<>	135:176b8275d35d	2158	} while(tmpways--);
<>	135:176b8275d35d	2159	} while(sets--);
<>	135:176b8275d35d	2160
<>	135:176b8275d35d	2161	__DSB();
<>	135:176b8275d35d	2162	__ISB();
<>	135:176b8275d35d	2163	#endif
<>	135:176b8275d35d	2164	}
<>	135:176b8275d35d	2165
<>	135:176b8275d35d	2166
<>	135:176b8275d35d	2167	/** \brief Clean & Invalidate D-Cache
<>	135:176b8275d35d	2168
<>	135:176b8275d35d	2169	The function cleans and Invalidates D-Cache
<>	135:176b8275d35d	2170	*/
<>	135:176b8275d35d	2171	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
<>	135:176b8275d35d	2172	{
<>	135:176b8275d35d	2173	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2174	uint32_t ccsidr, sshift, wshift, sw;
<>	135:176b8275d35d	2175	uint32_t sets, ways;
<>	135:176b8275d35d	2176
<>	135:176b8275d35d	2177	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
<>	135:176b8275d35d	2178	ccsidr = SCB->CCSIDR;
<>	135:176b8275d35d	2179	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<>	135:176b8275d35d	2180	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<>	135:176b8275d35d	2181	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<>	135:176b8275d35d	2182	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<>	135:176b8275d35d	2183
<>	135:176b8275d35d	2184	__DSB();
<>	135:176b8275d35d	2185
<>	135:176b8275d35d	2186	do { // clean & invalidate D-Cache
<>	135:176b8275d35d	2187	uint32_t tmpways = ways;
<>	135:176b8275d35d	2188	do {
<>	135:176b8275d35d	2189	sw = ((tmpways << wshift) \| (sets << sshift));
<>	135:176b8275d35d	2190	SCB->DCCISW = sw;
<>	135:176b8275d35d	2191	} while(tmpways--);
<>	135:176b8275d35d	2192	} while(sets--);
<>	135:176b8275d35d	2193
<>	135:176b8275d35d	2194	__DSB();
<>	135:176b8275d35d	2195	__ISB();
<>	135:176b8275d35d	2196	#endif
<>	135:176b8275d35d	2197	}
<>	135:176b8275d35d	2198
<>	135:176b8275d35d	2199
<>	135:176b8275d35d	2200	/**
<>	135:176b8275d35d	2201	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
<>	135:176b8275d35d	2202	\brief D-Cache Invalidate by address
<>	135:176b8275d35d	2203	\param[in] addr address (aligned to 32-byte boundary)
<>	135:176b8275d35d	2204	\param[in] dsize size of memory block (in number of bytes)
<>	135:176b8275d35d	2205	*/
<>	135:176b8275d35d	2206	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
<>	135:176b8275d35d	2207	{
<>	135:176b8275d35d	2208	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2209	int32_t op_size = dsize;
<>	135:176b8275d35d	2210	uint32_t op_addr = (uint32_t)addr;
<>	135:176b8275d35d	2211	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
<>	135:176b8275d35d	2212
<>	135:176b8275d35d	2213	__DSB();
<>	135:176b8275d35d	2214
<>	135:176b8275d35d	2215	while (op_size > 0) {
<>	135:176b8275d35d	2216	SCB->DCIMVAC = op_addr;
<>	135:176b8275d35d	2217	op_addr += linesize;
<>	135:176b8275d35d	2218	op_size -= (int32_t)linesize;
<>	135:176b8275d35d	2219	}
<>	135:176b8275d35d	2220
<>	135:176b8275d35d	2221	__DSB();
<>	135:176b8275d35d	2222	__ISB();
<>	135:176b8275d35d	2223	#endif
<>	135:176b8275d35d	2224	}
<>	135:176b8275d35d	2225
<>	135:176b8275d35d	2226
<>	135:176b8275d35d	2227	/**
<>	135:176b8275d35d	2228	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
<>	135:176b8275d35d	2229	\brief D-Cache Clean by address
<>	135:176b8275d35d	2230	\param[in] addr address (aligned to 32-byte boundary)
<>	135:176b8275d35d	2231	\param[in] dsize size of memory block (in number of bytes)
<>	135:176b8275d35d	2232	*/
<>	135:176b8275d35d	2233	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
<>	135:176b8275d35d	2234	{
<>	135:176b8275d35d	2235	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2236	int32_t op_size = dsize;
<>	135:176b8275d35d	2237	uint32_t op_addr = (uint32_t) addr;
<>	135:176b8275d35d	2238	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
<>	135:176b8275d35d	2239
<>	135:176b8275d35d	2240	__DSB();
<>	135:176b8275d35d	2241
<>	135:176b8275d35d	2242	while (op_size > 0) {
<>	135:176b8275d35d	2243	SCB->DCCMVAC = op_addr;
<>	135:176b8275d35d	2244	op_addr += linesize;
<>	135:176b8275d35d	2245	op_size -= (int32_t)linesize;
<>	135:176b8275d35d	2246	}
<>	135:176b8275d35d	2247
<>	135:176b8275d35d	2248	__DSB();
<>	135:176b8275d35d	2249	__ISB();
<>	135:176b8275d35d	2250	#endif
<>	135:176b8275d35d	2251	}
<>	135:176b8275d35d	2252
<>	135:176b8275d35d	2253
<>	135:176b8275d35d	2254	/**
<>	135:176b8275d35d	2255	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
<>	135:176b8275d35d	2256	\brief D-Cache Clean and Invalidate by address
<>	135:176b8275d35d	2257	\param[in] addr address (aligned to 32-byte boundary)
<>	135:176b8275d35d	2258	\param[in] dsize size of memory block (in number of bytes)
<>	135:176b8275d35d	2259	*/
<>	135:176b8275d35d	2260	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
<>	135:176b8275d35d	2261	{
<>	135:176b8275d35d	2262	#if (__DCACHE_PRESENT == 1)
<>	135:176b8275d35d	2263	int32_t op_size = dsize;
<>	135:176b8275d35d	2264	uint32_t op_addr = (uint32_t) addr;
<>	135:176b8275d35d	2265	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
<>	135:176b8275d35d	2266
<>	135:176b8275d35d	2267	__DSB();
<>	135:176b8275d35d	2268
<>	135:176b8275d35d	2269	while (op_size > 0) {
<>	135:176b8275d35d	2270	SCB->DCCIMVAC = op_addr;
<>	135:176b8275d35d	2271	op_addr += linesize;
<>	135:176b8275d35d	2272	op_size -= (int32_t)linesize;
<>	135:176b8275d35d	2273	}
<>	135:176b8275d35d	2274
<>	135:176b8275d35d	2275	__DSB();
<>	135:176b8275d35d	2276	__ISB();
<>	135:176b8275d35d	2277	#endif
<>	135:176b8275d35d	2278	}
<>	135:176b8275d35d	2279
<>	135:176b8275d35d	2280
<>	135:176b8275d35d	2281	/@} end of CMSIS_Core_CacheFunctions /
<>	135:176b8275d35d	2282
<>	135:176b8275d35d	2283
<>	135:176b8275d35d	2284
<>	135:176b8275d35d	2285	/* ################################## SysTick function ############################################ */
<>	135:176b8275d35d	2286	/** \ingroup CMSIS_Core_FunctionInterface
<>	135:176b8275d35d	2287	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<>	135:176b8275d35d	2288	\brief Functions that configure the System.
<>	135:176b8275d35d	2289	@{
<>	135:176b8275d35d	2290	*/
<>	135:176b8275d35d	2291
<>	135:176b8275d35d	2292	#if (__Vendor_SysTickConfig == 0)
<>	135:176b8275d35d	2293
<>	135:176b8275d35d	2294	/** \brief System Tick Configuration
<>	135:176b8275d35d	2295
<>	135:176b8275d35d	2296	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<>	135:176b8275d35d	2297	Counter is in free running mode to generate periodic interrupts.
<>	135:176b8275d35d	2298
<>	135:176b8275d35d	2299	\param [in] ticks Number of ticks between two interrupts.
<>	135:176b8275d35d	2300
<>	135:176b8275d35d	2301	\return 0 Function succeeded.
<>	135:176b8275d35d	2302	\return 1 Function failed.
<>	135:176b8275d35d	2303
<>	135:176b8275d35d	2304	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<>	135:176b8275d35d	2305	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<>	135:176b8275d35d	2306	must contain a vendor-specific implementation of this function.
<>	135:176b8275d35d	2307
<>	135:176b8275d35d	2308	*/
<>	135:176b8275d35d	2309	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<>	135:176b8275d35d	2310	{
<>	135:176b8275d35d	2311	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<>	135:176b8275d35d	2312
<>	135:176b8275d35d	2313	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<>	135:176b8275d35d	2314	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<>	135:176b8275d35d	2315	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<>	135:176b8275d35d	2316	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
<>	135:176b8275d35d	2317	SysTick_CTRL_TICKINT_Msk \|
<>	135:176b8275d35d	2318	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<>	135:176b8275d35d	2319	return (0UL); /* Function successful */
<>	135:176b8275d35d	2320	}
<>	135:176b8275d35d	2321
<>	135:176b8275d35d	2322	#endif
<>	135:176b8275d35d	2323
<>	135:176b8275d35d	2324	/@} end of CMSIS_Core_SysTickFunctions /
<>	135:176b8275d35d	2325
<>	135:176b8275d35d	2326
<>	135:176b8275d35d	2327
<>	135:176b8275d35d	2328	/* ##################################### Debug In/Output function ########################################### */
<>	135:176b8275d35d	2329	/** \ingroup CMSIS_Core_FunctionInterface
<>	135:176b8275d35d	2330	\defgroup CMSIS_core_DebugFunctions ITM Functions
<>	135:176b8275d35d	2331	\brief Functions that access the ITM debug interface.
<>	135:176b8275d35d	2332	@{
<>	135:176b8275d35d	2333	*/
<>	135:176b8275d35d	2334
<>	135:176b8275d35d	2335	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
<>	135:176b8275d35d	2336	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
<>	135:176b8275d35d	2337
<>	135:176b8275d35d	2338
<>	135:176b8275d35d	2339	/** \brief ITM Send Character
<>	135:176b8275d35d	2340
<>	135:176b8275d35d	2341	The function transmits a character via the ITM channel 0, and
<>	135:176b8275d35d	2342	\li Just returns when no debugger is connected that has booked the output.
<>	135:176b8275d35d	2343	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<>	135:176b8275d35d	2344
<>	135:176b8275d35d	2345	\param [in] ch Character to transmit.
<>	135:176b8275d35d	2346
<>	135:176b8275d35d	2347	\returns Character to transmit.
<>	135:176b8275d35d	2348	*/
<>	135:176b8275d35d	2349	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<>	135:176b8275d35d	2350	{
<>	135:176b8275d35d	2351	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<>	135:176b8275d35d	2352	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<>	135:176b8275d35d	2353	{
<>	135:176b8275d35d	2354	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<>	135:176b8275d35d	2355	ITM->PORT[0].u8 = (uint8_t)ch;
<>	135:176b8275d35d	2356	}
<>	135:176b8275d35d	2357	return (ch);
<>	135:176b8275d35d	2358	}
<>	135:176b8275d35d	2359
<>	135:176b8275d35d	2360
<>	135:176b8275d35d	2361	/** \brief ITM Receive Character
<>	135:176b8275d35d	2362
<>	135:176b8275d35d	2363	The function inputs a character via the external variable \ref ITM_RxBuffer.
<>	135:176b8275d35d	2364
<>	135:176b8275d35d	2365	\return Received character.
<>	135:176b8275d35d	2366	\return -1 No character pending.
<>	135:176b8275d35d	2367	*/
<>	135:176b8275d35d	2368	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<>	135:176b8275d35d	2369	int32_t ch = -1; /* no character available */
<>	135:176b8275d35d	2370
<>	135:176b8275d35d	2371	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<>	135:176b8275d35d	2372	ch = ITM_RxBuffer;
<>	135:176b8275d35d	2373	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<>	135:176b8275d35d	2374	}
<>	135:176b8275d35d	2375
<>	135:176b8275d35d	2376	return (ch);
<>	135:176b8275d35d	2377	}
<>	135:176b8275d35d	2378
<>	135:176b8275d35d	2379
<>	135:176b8275d35d	2380	/** \brief ITM Check Character
<>	135:176b8275d35d	2381
<>	135:176b8275d35d	2382	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<>	135:176b8275d35d	2383
<>	135:176b8275d35d	2384	\return 0 No character available.
<>	135:176b8275d35d	2385	\return 1 Character available.
<>	135:176b8275d35d	2386	*/
<>	135:176b8275d35d	2387	__STATIC_INLINE int32_t ITM_CheckChar (void) {
<>	135:176b8275d35d	2388
<>	135:176b8275d35d	2389	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<>	135:176b8275d35d	2390	return (0); /* no character available */
<>	135:176b8275d35d	2391	} else {
<>	135:176b8275d35d	2392	return (1); /* character available */
<>	135:176b8275d35d	2393	}
<>	135:176b8275d35d	2394	}
<>	135:176b8275d35d	2395
<>	135:176b8275d35d	2396	/@} end of CMSIS_core_DebugFunctions /
<>	135:176b8275d35d	2397
<>	135:176b8275d35d	2398
<>	135:176b8275d35d	2399
<>	135:176b8275d35d	2400
<>	135:176b8275d35d	2401	#ifdef __cplusplus
<>	135:176b8275d35d	2402	}
<>	135:176b8275d35d	2403	#endif
<>	135:176b8275d35d	2404
<>	135:176b8275d35d	2405	#endif /* __CORE_CM7_H_DEPENDANT */
<>	135:176b8275d35d	2406
<>	135:176b8275d35d	2407	#endif /* __CMSIS_GENERIC */