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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_cm4_simd.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**************************************************************************//**
<> 135:176b8275d35d 2 * @file core_cm4_simd.h
<> 135:176b8275d35d 3 * @brief CMSIS Cortex-M4 SIMD Header File
<> 135:176b8275d35d 4 * @version V3.20
<> 135:176b8275d35d 5 * @date 25. February 2013
<> 135:176b8275d35d 6 *
<> 135:176b8275d35d 7 * @note
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 ******************************************************************************/
<> 135:176b8275d35d 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
<> 135:176b8275d35d 11
<> 135:176b8275d35d 12 All rights reserved.
<> 135:176b8275d35d 13 Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 specific prior written permission.
<> 135:176b8275d35d 23 *
<> 135:176b8275d35d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37
<> 135:176b8275d35d 38 #ifdef __cplusplus
<> 135:176b8275d35d 39 extern "C" {
<> 135:176b8275d35d 40 #endif
<> 135:176b8275d35d 41
<> 135:176b8275d35d 42 #ifndef __CORE_CM4_SIMD_H
<> 135:176b8275d35d 43 #define __CORE_CM4_SIMD_H
<> 135:176b8275d35d 44
<> 135:176b8275d35d 45
<> 135:176b8275d35d 46 /*******************************************************************************
<> 135:176b8275d35d 47 * Hardware Abstraction Layer
<> 135:176b8275d35d 48 ******************************************************************************/
<> 135:176b8275d35d 49
<> 135:176b8275d35d 50
<> 135:176b8275d35d 51 /* ################### Compiler specific Intrinsics ########################### */
<> 135:176b8275d35d 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
<> 135:176b8275d35d 53 Access to dedicated SIMD instructions
<> 135:176b8275d35d 54 @{
<> 135:176b8275d35d 55 */
<> 135:176b8275d35d 56
<> 135:176b8275d35d 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 135:176b8275d35d 58 /* ARM armcc specific functions */
<> 135:176b8275d35d 59
<> 135:176b8275d35d 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 61 #define __SADD8 __sadd8
<> 135:176b8275d35d 62 #define __QADD8 __qadd8
<> 135:176b8275d35d 63 #define __SHADD8 __shadd8
<> 135:176b8275d35d 64 #define __UADD8 __uadd8
<> 135:176b8275d35d 65 #define __UQADD8 __uqadd8
<> 135:176b8275d35d 66 #define __UHADD8 __uhadd8
<> 135:176b8275d35d 67 #define __SSUB8 __ssub8
<> 135:176b8275d35d 68 #define __QSUB8 __qsub8
<> 135:176b8275d35d 69 #define __SHSUB8 __shsub8
<> 135:176b8275d35d 70 #define __USUB8 __usub8
<> 135:176b8275d35d 71 #define __UQSUB8 __uqsub8
<> 135:176b8275d35d 72 #define __UHSUB8 __uhsub8
<> 135:176b8275d35d 73 #define __SADD16 __sadd16
<> 135:176b8275d35d 74 #define __QADD16 __qadd16
<> 135:176b8275d35d 75 #define __SHADD16 __shadd16
<> 135:176b8275d35d 76 #define __UADD16 __uadd16
<> 135:176b8275d35d 77 #define __UQADD16 __uqadd16
<> 135:176b8275d35d 78 #define __UHADD16 __uhadd16
<> 135:176b8275d35d 79 #define __SSUB16 __ssub16
<> 135:176b8275d35d 80 #define __QSUB16 __qsub16
<> 135:176b8275d35d 81 #define __SHSUB16 __shsub16
<> 135:176b8275d35d 82 #define __USUB16 __usub16
<> 135:176b8275d35d 83 #define __UQSUB16 __uqsub16
<> 135:176b8275d35d 84 #define __UHSUB16 __uhsub16
<> 135:176b8275d35d 85 #define __SASX __sasx
<> 135:176b8275d35d 86 #define __QASX __qasx
<> 135:176b8275d35d 87 #define __SHASX __shasx
<> 135:176b8275d35d 88 #define __UASX __uasx
<> 135:176b8275d35d 89 #define __UQASX __uqasx
<> 135:176b8275d35d 90 #define __UHASX __uhasx
<> 135:176b8275d35d 91 #define __SSAX __ssax
<> 135:176b8275d35d 92 #define __QSAX __qsax
<> 135:176b8275d35d 93 #define __SHSAX __shsax
<> 135:176b8275d35d 94 #define __USAX __usax
<> 135:176b8275d35d 95 #define __UQSAX __uqsax
<> 135:176b8275d35d 96 #define __UHSAX __uhsax
<> 135:176b8275d35d 97 #define __USAD8 __usad8
<> 135:176b8275d35d 98 #define __USADA8 __usada8
<> 135:176b8275d35d 99 #define __SSAT16 __ssat16
<> 135:176b8275d35d 100 #define __USAT16 __usat16
<> 135:176b8275d35d 101 #define __UXTB16 __uxtb16
<> 135:176b8275d35d 102 #define __UXTAB16 __uxtab16
<> 135:176b8275d35d 103 #define __SXTB16 __sxtb16
<> 135:176b8275d35d 104 #define __SXTAB16 __sxtab16
<> 135:176b8275d35d 105 #define __SMUAD __smuad
<> 135:176b8275d35d 106 #define __SMUADX __smuadx
<> 135:176b8275d35d 107 #define __SMLAD __smlad
<> 135:176b8275d35d 108 #define __SMLADX __smladx
<> 135:176b8275d35d 109 #define __SMLALD __smlald
<> 135:176b8275d35d 110 #define __SMLALDX __smlaldx
<> 135:176b8275d35d 111 #define __SMUSD __smusd
<> 135:176b8275d35d 112 #define __SMUSDX __smusdx
<> 135:176b8275d35d 113 #define __SMLSD __smlsd
<> 135:176b8275d35d 114 #define __SMLSDX __smlsdx
<> 135:176b8275d35d 115 #define __SMLSLD __smlsld
<> 135:176b8275d35d 116 #define __SMLSLDX __smlsldx
<> 135:176b8275d35d 117 #define __SEL __sel
<> 135:176b8275d35d 118 #define __QADD __qadd
<> 135:176b8275d35d 119 #define __QSUB __qsub
<> 135:176b8275d35d 120
<> 135:176b8275d35d 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
<> 135:176b8275d35d 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
<> 135:176b8275d35d 123
<> 135:176b8275d35d 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
<> 135:176b8275d35d 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
<> 135:176b8275d35d 126
<> 135:176b8275d35d 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
<> 135:176b8275d35d 128 ((int64_t)(ARG3) << 32) ) >> 32))
<> 135:176b8275d35d 129
<> 135:176b8275d35d 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 131
<> 135:176b8275d35d 132
<> 135:176b8275d35d 133
<> 135:176b8275d35d 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 135:176b8275d35d 135 /* IAR iccarm specific functions */
<> 135:176b8275d35d 136
<> 135:176b8275d35d 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 138 #include <cmsis_iar.h>
<> 135:176b8275d35d 139
<> 135:176b8275d35d 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 141
<> 135:176b8275d35d 142
<> 135:176b8275d35d 143
<> 135:176b8275d35d 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 135:176b8275d35d 145 /* TI CCS specific functions */
<> 135:176b8275d35d 146
<> 135:176b8275d35d 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 148 #include <cmsis_ccs.h>
<> 135:176b8275d35d 149
<> 135:176b8275d35d 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 151
<> 135:176b8275d35d 152
<> 135:176b8275d35d 153
<> 135:176b8275d35d 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 135:176b8275d35d 155 /* GNU gcc specific functions */
<> 135:176b8275d35d 156
<> 135:176b8275d35d 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 159 {
<> 135:176b8275d35d 160 uint32_t result;
<> 135:176b8275d35d 161
<> 135:176b8275d35d 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 163 return(result);
<> 135:176b8275d35d 164 }
<> 135:176b8275d35d 165
<> 135:176b8275d35d 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 167 {
<> 135:176b8275d35d 168 uint32_t result;
<> 135:176b8275d35d 169
<> 135:176b8275d35d 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 171 return(result);
<> 135:176b8275d35d 172 }
<> 135:176b8275d35d 173
<> 135:176b8275d35d 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 175 {
<> 135:176b8275d35d 176 uint32_t result;
<> 135:176b8275d35d 177
<> 135:176b8275d35d 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 179 return(result);
<> 135:176b8275d35d 180 }
<> 135:176b8275d35d 181
<> 135:176b8275d35d 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 183 {
<> 135:176b8275d35d 184 uint32_t result;
<> 135:176b8275d35d 185
<> 135:176b8275d35d 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 187 return(result);
<> 135:176b8275d35d 188 }
<> 135:176b8275d35d 189
<> 135:176b8275d35d 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 191 {
<> 135:176b8275d35d 192 uint32_t result;
<> 135:176b8275d35d 193
<> 135:176b8275d35d 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 195 return(result);
<> 135:176b8275d35d 196 }
<> 135:176b8275d35d 197
<> 135:176b8275d35d 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 199 {
<> 135:176b8275d35d 200 uint32_t result;
<> 135:176b8275d35d 201
<> 135:176b8275d35d 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 203 return(result);
<> 135:176b8275d35d 204 }
<> 135:176b8275d35d 205
<> 135:176b8275d35d 206
<> 135:176b8275d35d 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 208 {
<> 135:176b8275d35d 209 uint32_t result;
<> 135:176b8275d35d 210
<> 135:176b8275d35d 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 212 return(result);
<> 135:176b8275d35d 213 }
<> 135:176b8275d35d 214
<> 135:176b8275d35d 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 216 {
<> 135:176b8275d35d 217 uint32_t result;
<> 135:176b8275d35d 218
<> 135:176b8275d35d 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 220 return(result);
<> 135:176b8275d35d 221 }
<> 135:176b8275d35d 222
<> 135:176b8275d35d 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 224 {
<> 135:176b8275d35d 225 uint32_t result;
<> 135:176b8275d35d 226
<> 135:176b8275d35d 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 228 return(result);
<> 135:176b8275d35d 229 }
<> 135:176b8275d35d 230
<> 135:176b8275d35d 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 232 {
<> 135:176b8275d35d 233 uint32_t result;
<> 135:176b8275d35d 234
<> 135:176b8275d35d 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 236 return(result);
<> 135:176b8275d35d 237 }
<> 135:176b8275d35d 238
<> 135:176b8275d35d 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 240 {
<> 135:176b8275d35d 241 uint32_t result;
<> 135:176b8275d35d 242
<> 135:176b8275d35d 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 244 return(result);
<> 135:176b8275d35d 245 }
<> 135:176b8275d35d 246
<> 135:176b8275d35d 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 248 {
<> 135:176b8275d35d 249 uint32_t result;
<> 135:176b8275d35d 250
<> 135:176b8275d35d 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 252 return(result);
<> 135:176b8275d35d 253 }
<> 135:176b8275d35d 254
<> 135:176b8275d35d 255
<> 135:176b8275d35d 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 257 {
<> 135:176b8275d35d 258 uint32_t result;
<> 135:176b8275d35d 259
<> 135:176b8275d35d 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 261 return(result);
<> 135:176b8275d35d 262 }
<> 135:176b8275d35d 263
<> 135:176b8275d35d 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 265 {
<> 135:176b8275d35d 266 uint32_t result;
<> 135:176b8275d35d 267
<> 135:176b8275d35d 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 269 return(result);
<> 135:176b8275d35d 270 }
<> 135:176b8275d35d 271
<> 135:176b8275d35d 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 273 {
<> 135:176b8275d35d 274 uint32_t result;
<> 135:176b8275d35d 275
<> 135:176b8275d35d 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 277 return(result);
<> 135:176b8275d35d 278 }
<> 135:176b8275d35d 279
<> 135:176b8275d35d 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 281 {
<> 135:176b8275d35d 282 uint32_t result;
<> 135:176b8275d35d 283
<> 135:176b8275d35d 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 285 return(result);
<> 135:176b8275d35d 286 }
<> 135:176b8275d35d 287
<> 135:176b8275d35d 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 289 {
<> 135:176b8275d35d 290 uint32_t result;
<> 135:176b8275d35d 291
<> 135:176b8275d35d 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 293 return(result);
<> 135:176b8275d35d 294 }
<> 135:176b8275d35d 295
<> 135:176b8275d35d 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 297 {
<> 135:176b8275d35d 298 uint32_t result;
<> 135:176b8275d35d 299
<> 135:176b8275d35d 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 301 return(result);
<> 135:176b8275d35d 302 }
<> 135:176b8275d35d 303
<> 135:176b8275d35d 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 305 {
<> 135:176b8275d35d 306 uint32_t result;
<> 135:176b8275d35d 307
<> 135:176b8275d35d 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 309 return(result);
<> 135:176b8275d35d 310 }
<> 135:176b8275d35d 311
<> 135:176b8275d35d 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 313 {
<> 135:176b8275d35d 314 uint32_t result;
<> 135:176b8275d35d 315
<> 135:176b8275d35d 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 317 return(result);
<> 135:176b8275d35d 318 }
<> 135:176b8275d35d 319
<> 135:176b8275d35d 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 321 {
<> 135:176b8275d35d 322 uint32_t result;
<> 135:176b8275d35d 323
<> 135:176b8275d35d 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 325 return(result);
<> 135:176b8275d35d 326 }
<> 135:176b8275d35d 327
<> 135:176b8275d35d 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 329 {
<> 135:176b8275d35d 330 uint32_t result;
<> 135:176b8275d35d 331
<> 135:176b8275d35d 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 333 return(result);
<> 135:176b8275d35d 334 }
<> 135:176b8275d35d 335
<> 135:176b8275d35d 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 337 {
<> 135:176b8275d35d 338 uint32_t result;
<> 135:176b8275d35d 339
<> 135:176b8275d35d 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 341 return(result);
<> 135:176b8275d35d 342 }
<> 135:176b8275d35d 343
<> 135:176b8275d35d 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 345 {
<> 135:176b8275d35d 346 uint32_t result;
<> 135:176b8275d35d 347
<> 135:176b8275d35d 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 349 return(result);
<> 135:176b8275d35d 350 }
<> 135:176b8275d35d 351
<> 135:176b8275d35d 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 353 {
<> 135:176b8275d35d 354 uint32_t result;
<> 135:176b8275d35d 355
<> 135:176b8275d35d 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 357 return(result);
<> 135:176b8275d35d 358 }
<> 135:176b8275d35d 359
<> 135:176b8275d35d 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 361 {
<> 135:176b8275d35d 362 uint32_t result;
<> 135:176b8275d35d 363
<> 135:176b8275d35d 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 365 return(result);
<> 135:176b8275d35d 366 }
<> 135:176b8275d35d 367
<> 135:176b8275d35d 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 369 {
<> 135:176b8275d35d 370 uint32_t result;
<> 135:176b8275d35d 371
<> 135:176b8275d35d 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 373 return(result);
<> 135:176b8275d35d 374 }
<> 135:176b8275d35d 375
<> 135:176b8275d35d 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 377 {
<> 135:176b8275d35d 378 uint32_t result;
<> 135:176b8275d35d 379
<> 135:176b8275d35d 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 381 return(result);
<> 135:176b8275d35d 382 }
<> 135:176b8275d35d 383
<> 135:176b8275d35d 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 385 {
<> 135:176b8275d35d 386 uint32_t result;
<> 135:176b8275d35d 387
<> 135:176b8275d35d 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 389 return(result);
<> 135:176b8275d35d 390 }
<> 135:176b8275d35d 391
<> 135:176b8275d35d 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 393 {
<> 135:176b8275d35d 394 uint32_t result;
<> 135:176b8275d35d 395
<> 135:176b8275d35d 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 397 return(result);
<> 135:176b8275d35d 398 }
<> 135:176b8275d35d 399
<> 135:176b8275d35d 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 401 {
<> 135:176b8275d35d 402 uint32_t result;
<> 135:176b8275d35d 403
<> 135:176b8275d35d 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 405 return(result);
<> 135:176b8275d35d 406 }
<> 135:176b8275d35d 407
<> 135:176b8275d35d 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 409 {
<> 135:176b8275d35d 410 uint32_t result;
<> 135:176b8275d35d 411
<> 135:176b8275d35d 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 413 return(result);
<> 135:176b8275d35d 414 }
<> 135:176b8275d35d 415
<> 135:176b8275d35d 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 417 {
<> 135:176b8275d35d 418 uint32_t result;
<> 135:176b8275d35d 419
<> 135:176b8275d35d 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 421 return(result);
<> 135:176b8275d35d 422 }
<> 135:176b8275d35d 423
<> 135:176b8275d35d 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 425 {
<> 135:176b8275d35d 426 uint32_t result;
<> 135:176b8275d35d 427
<> 135:176b8275d35d 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 429 return(result);
<> 135:176b8275d35d 430 }
<> 135:176b8275d35d 431
<> 135:176b8275d35d 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 433 {
<> 135:176b8275d35d 434 uint32_t result;
<> 135:176b8275d35d 435
<> 135:176b8275d35d 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 437 return(result);
<> 135:176b8275d35d 438 }
<> 135:176b8275d35d 439
<> 135:176b8275d35d 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 441 {
<> 135:176b8275d35d 442 uint32_t result;
<> 135:176b8275d35d 443
<> 135:176b8275d35d 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 445 return(result);
<> 135:176b8275d35d 446 }
<> 135:176b8275d35d 447
<> 135:176b8275d35d 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 449 {
<> 135:176b8275d35d 450 uint32_t result;
<> 135:176b8275d35d 451
<> 135:176b8275d35d 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 453 return(result);
<> 135:176b8275d35d 454 }
<> 135:176b8275d35d 455
<> 135:176b8275d35d 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 457 {
<> 135:176b8275d35d 458 uint32_t result;
<> 135:176b8275d35d 459
<> 135:176b8275d35d 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 461 return(result);
<> 135:176b8275d35d 462 }
<> 135:176b8275d35d 463
<> 135:176b8275d35d 464 #define __SSAT16(ARG1,ARG2) \
<> 135:176b8275d35d 465 ({ \
<> 135:176b8275d35d 466 uint32_t __RES, __ARG1 = (ARG1); \
<> 135:176b8275d35d 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 135:176b8275d35d 468 __RES; \
<> 135:176b8275d35d 469 })
<> 135:176b8275d35d 470
<> 135:176b8275d35d 471 #define __USAT16(ARG1,ARG2) \
<> 135:176b8275d35d 472 ({ \
<> 135:176b8275d35d 473 uint32_t __RES, __ARG1 = (ARG1); \
<> 135:176b8275d35d 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 135:176b8275d35d 475 __RES; \
<> 135:176b8275d35d 476 })
<> 135:176b8275d35d 477
<> 135:176b8275d35d 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
<> 135:176b8275d35d 479 {
<> 135:176b8275d35d 480 uint32_t result;
<> 135:176b8275d35d 481
<> 135:176b8275d35d 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 135:176b8275d35d 483 return(result);
<> 135:176b8275d35d 484 }
<> 135:176b8275d35d 485
<> 135:176b8275d35d 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 487 {
<> 135:176b8275d35d 488 uint32_t result;
<> 135:176b8275d35d 489
<> 135:176b8275d35d 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 491 return(result);
<> 135:176b8275d35d 492 }
<> 135:176b8275d35d 493
<> 135:176b8275d35d 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
<> 135:176b8275d35d 495 {
<> 135:176b8275d35d 496 uint32_t result;
<> 135:176b8275d35d 497
<> 135:176b8275d35d 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 135:176b8275d35d 499 return(result);
<> 135:176b8275d35d 500 }
<> 135:176b8275d35d 501
<> 135:176b8275d35d 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 503 {
<> 135:176b8275d35d 504 uint32_t result;
<> 135:176b8275d35d 505
<> 135:176b8275d35d 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 507 return(result);
<> 135:176b8275d35d 508 }
<> 135:176b8275d35d 509
<> 135:176b8275d35d 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 511 {
<> 135:176b8275d35d 512 uint32_t result;
<> 135:176b8275d35d 513
<> 135:176b8275d35d 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 515 return(result);
<> 135:176b8275d35d 516 }
<> 135:176b8275d35d 517
<> 135:176b8275d35d 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 519 {
<> 135:176b8275d35d 520 uint32_t result;
<> 135:176b8275d35d 521
<> 135:176b8275d35d 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 523 return(result);
<> 135:176b8275d35d 524 }
<> 135:176b8275d35d 525
<> 135:176b8275d35d 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 527 {
<> 135:176b8275d35d 528 uint32_t result;
<> 135:176b8275d35d 529
<> 135:176b8275d35d 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 531 return(result);
<> 135:176b8275d35d 532 }
<> 135:176b8275d35d 533
<> 135:176b8275d35d 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 535 {
<> 135:176b8275d35d 536 uint32_t result;
<> 135:176b8275d35d 537
<> 135:176b8275d35d 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 539 return(result);
<> 135:176b8275d35d 540 }
<> 135:176b8275d35d 541
<> 135:176b8275d35d 542 #define __SMLALD(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 543 ({ \
<> 135:176b8275d35d 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
<> 135:176b8275d35d 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 135:176b8275d35d 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 135:176b8275d35d 547 })
<> 135:176b8275d35d 548
<> 135:176b8275d35d 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 550 ({ \
<> 135:176b8275d35d 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
<> 135:176b8275d35d 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 135:176b8275d35d 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 135:176b8275d35d 554 })
<> 135:176b8275d35d 555
<> 135:176b8275d35d 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 557 {
<> 135:176b8275d35d 558 uint32_t result;
<> 135:176b8275d35d 559
<> 135:176b8275d35d 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 561 return(result);
<> 135:176b8275d35d 562 }
<> 135:176b8275d35d 563
<> 135:176b8275d35d 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 565 {
<> 135:176b8275d35d 566 uint32_t result;
<> 135:176b8275d35d 567
<> 135:176b8275d35d 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 569 return(result);
<> 135:176b8275d35d 570 }
<> 135:176b8275d35d 571
<> 135:176b8275d35d 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 573 {
<> 135:176b8275d35d 574 uint32_t result;
<> 135:176b8275d35d 575
<> 135:176b8275d35d 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 577 return(result);
<> 135:176b8275d35d 578 }
<> 135:176b8275d35d 579
<> 135:176b8275d35d 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 135:176b8275d35d 581 {
<> 135:176b8275d35d 582 uint32_t result;
<> 135:176b8275d35d 583
<> 135:176b8275d35d 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 585 return(result);
<> 135:176b8275d35d 586 }
<> 135:176b8275d35d 587
<> 135:176b8275d35d 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 589 ({ \
<> 135:176b8275d35d 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
<> 135:176b8275d35d 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 135:176b8275d35d 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 135:176b8275d35d 593 })
<> 135:176b8275d35d 594
<> 135:176b8275d35d 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 596 ({ \
<> 135:176b8275d35d 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
<> 135:176b8275d35d 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 135:176b8275d35d 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 135:176b8275d35d 600 })
<> 135:176b8275d35d 601
<> 135:176b8275d35d 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 603 {
<> 135:176b8275d35d 604 uint32_t result;
<> 135:176b8275d35d 605
<> 135:176b8275d35d 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 607 return(result);
<> 135:176b8275d35d 608 }
<> 135:176b8275d35d 609
<> 135:176b8275d35d 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 611 {
<> 135:176b8275d35d 612 uint32_t result;
<> 135:176b8275d35d 613
<> 135:176b8275d35d 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 615 return(result);
<> 135:176b8275d35d 616 }
<> 135:176b8275d35d 617
<> 135:176b8275d35d 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
<> 135:176b8275d35d 619 {
<> 135:176b8275d35d 620 uint32_t result;
<> 135:176b8275d35d 621
<> 135:176b8275d35d 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 135:176b8275d35d 623 return(result);
<> 135:176b8275d35d 624 }
<> 135:176b8275d35d 625
<> 135:176b8275d35d 626 #define __PKHBT(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 627 ({ \
<> 135:176b8275d35d 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 135:176b8275d35d 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 135:176b8275d35d 630 __RES; \
<> 135:176b8275d35d 631 })
<> 135:176b8275d35d 632
<> 135:176b8275d35d 633 #define __PKHTB(ARG1,ARG2,ARG3) \
<> 135:176b8275d35d 634 ({ \
<> 135:176b8275d35d 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 135:176b8275d35d 636 if (ARG3 == 0) \
<> 135:176b8275d35d 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
<> 135:176b8275d35d 638 else \
<> 135:176b8275d35d 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 135:176b8275d35d 640 __RES; \
<> 135:176b8275d35d 641 })
<> 135:176b8275d35d 642
<> 135:176b8275d35d 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
<> 135:176b8275d35d 644 {
<> 135:176b8275d35d 645 int32_t result;
<> 135:176b8275d35d 646
<> 135:176b8275d35d 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
<> 135:176b8275d35d 648 return(result);
<> 135:176b8275d35d 649 }
<> 135:176b8275d35d 650
<> 135:176b8275d35d 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 652
<> 135:176b8275d35d 653
<> 135:176b8275d35d 654
<> 135:176b8275d35d 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 135:176b8275d35d 656 /* TASKING carm specific functions */
<> 135:176b8275d35d 657
<> 135:176b8275d35d 658
<> 135:176b8275d35d 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 660 /* not yet supported */
<> 135:176b8275d35d 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 135:176b8275d35d 662
<> 135:176b8275d35d 663
<> 135:176b8275d35d 664 #endif
<> 135:176b8275d35d 665
<> 135:176b8275d35d 666 /*@} end of group CMSIS_SIMD_intrinsics */
<> 135:176b8275d35d 667
<> 135:176b8275d35d 668
<> 135:176b8275d35d 669 #endif /* __CORE_CM4_SIMD_H */
<> 135:176b8275d35d 670
<> 135:176b8275d35d 671 #ifdef __cplusplus
<> 135:176b8275d35d 672 }
<> 135:176b8275d35d 673 #endif