mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_cm0plus.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**************************************************************************//**
<> 135:176b8275d35d 2 * @file core_cm0plus.h
<> 135:176b8275d35d 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
<> 135:176b8275d35d 4 * @version V4.10
<> 135:176b8275d35d 5 * @date 18. March 2015
<> 135:176b8275d35d 6 *
<> 135:176b8275d35d 7 * @note
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 ******************************************************************************/
<> 135:176b8275d35d 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 135:176b8275d35d 11
<> 135:176b8275d35d 12 All rights reserved.
<> 135:176b8275d35d 13 Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 specific prior written permission.
<> 135:176b8275d35d 23 *
<> 135:176b8275d35d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37
<> 135:176b8275d35d 38 #if defined ( __ICCARM__ )
<> 135:176b8275d35d 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 135:176b8275d35d 40 #endif
<> 135:176b8275d35d 41
<> 135:176b8275d35d 42 #ifndef __CORE_CM0PLUS_H_GENERIC
<> 135:176b8275d35d 43 #define __CORE_CM0PLUS_H_GENERIC
<> 135:176b8275d35d 44
<> 135:176b8275d35d 45 #ifdef __cplusplus
<> 135:176b8275d35d 46 extern "C" {
<> 135:176b8275d35d 47 #endif
<> 135:176b8275d35d 48
<> 135:176b8275d35d 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 135:176b8275d35d 50 CMSIS violates the following MISRA-C:2004 rules:
<> 135:176b8275d35d 51
<> 135:176b8275d35d 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 135:176b8275d35d 53 Function definitions in header files are used to allow 'inlining'.
<> 135:176b8275d35d 54
<> 135:176b8275d35d 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 135:176b8275d35d 56 Unions are used for effective representation of core registers.
<> 135:176b8275d35d 57
<> 135:176b8275d35d 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 135:176b8275d35d 59 Function-like macros are used to allow more efficient code.
<> 135:176b8275d35d 60 */
<> 135:176b8275d35d 61
<> 135:176b8275d35d 62
<> 135:176b8275d35d 63 /*******************************************************************************
<> 135:176b8275d35d 64 * CMSIS definitions
<> 135:176b8275d35d 65 ******************************************************************************/
<> 135:176b8275d35d 66 /** \ingroup Cortex-M0+
<> 135:176b8275d35d 67 @{
<> 135:176b8275d35d 68 */
<> 135:176b8275d35d 69
<> 135:176b8275d35d 70 /* CMSIS CM0P definitions */
<> 135:176b8275d35d 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 135:176b8275d35d 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 135:176b8275d35d 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
<> 135:176b8275d35d 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
<> 135:176b8275d35d 75
<> 135:176b8275d35d 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
<> 135:176b8275d35d 77
<> 135:176b8275d35d 78
<> 135:176b8275d35d 79 #if defined ( __CC_ARM )
<> 135:176b8275d35d 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 135:176b8275d35d 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 135:176b8275d35d 82 #define __STATIC_INLINE static __inline
<> 135:176b8275d35d 83
<> 135:176b8275d35d 84 #elif defined ( __GNUC__ )
<> 135:176b8275d35d 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 135:176b8275d35d 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 135:176b8275d35d 87 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 88
<> 135:176b8275d35d 89 #elif defined ( __ICCARM__ )
<> 135:176b8275d35d 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 135:176b8275d35d 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 135:176b8275d35d 92 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 93
<> 135:176b8275d35d 94 #elif defined ( __TMS470__ )
<> 135:176b8275d35d 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 135:176b8275d35d 96 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 97
<> 135:176b8275d35d 98 #elif defined ( __TASKING__ )
<> 135:176b8275d35d 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 135:176b8275d35d 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 135:176b8275d35d 101 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 102
<> 135:176b8275d35d 103 #elif defined ( __CSMC__ )
<> 135:176b8275d35d 104 #define __packed
<> 135:176b8275d35d 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 135:176b8275d35d 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 135:176b8275d35d 107 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 108
<> 135:176b8275d35d 109 #endif
<> 135:176b8275d35d 110
<> 135:176b8275d35d 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 135:176b8275d35d 112 This core does not support an FPU at all
<> 135:176b8275d35d 113 */
<> 135:176b8275d35d 114 #define __FPU_USED 0
<> 135:176b8275d35d 115
<> 135:176b8275d35d 116 #if defined ( __CC_ARM )
<> 135:176b8275d35d 117 #if defined __TARGET_FPU_VFP
<> 135:176b8275d35d 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 119 #endif
<> 135:176b8275d35d 120
<> 135:176b8275d35d 121 #elif defined ( __GNUC__ )
<> 135:176b8275d35d 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 135:176b8275d35d 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 124 #endif
<> 135:176b8275d35d 125
<> 135:176b8275d35d 126 #elif defined ( __ICCARM__ )
<> 135:176b8275d35d 127 #if defined __ARMVFP__
<> 135:176b8275d35d 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 129 #endif
<> 135:176b8275d35d 130
<> 135:176b8275d35d 131 #elif defined ( __TMS470__ )
<> 135:176b8275d35d 132 #if defined __TI__VFP_SUPPORT____
<> 135:176b8275d35d 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 134 #endif
<> 135:176b8275d35d 135
<> 135:176b8275d35d 136 #elif defined ( __TASKING__ )
<> 135:176b8275d35d 137 #if defined __FPU_VFP__
<> 135:176b8275d35d 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 139 #endif
<> 135:176b8275d35d 140
<> 135:176b8275d35d 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 135:176b8275d35d 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 135:176b8275d35d 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 144 #endif
<> 135:176b8275d35d 145 #endif
<> 135:176b8275d35d 146
<> 135:176b8275d35d 147 #include <stdint.h> /* standard types definitions */
<> 135:176b8275d35d 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 135:176b8275d35d 149 #include <core_cmFunc.h> /* Core Function Access */
<> 135:176b8275d35d 150
<> 135:176b8275d35d 151 #ifdef __cplusplus
<> 135:176b8275d35d 152 }
<> 135:176b8275d35d 153 #endif
<> 135:176b8275d35d 154
<> 135:176b8275d35d 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
<> 135:176b8275d35d 156
<> 135:176b8275d35d 157 #ifndef __CMSIS_GENERIC
<> 135:176b8275d35d 158
<> 135:176b8275d35d 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
<> 135:176b8275d35d 160 #define __CORE_CM0PLUS_H_DEPENDANT
<> 135:176b8275d35d 161
<> 135:176b8275d35d 162 #ifdef __cplusplus
<> 135:176b8275d35d 163 extern "C" {
<> 135:176b8275d35d 164 #endif
<> 135:176b8275d35d 165
<> 135:176b8275d35d 166 /* check device defines and use defaults */
<> 135:176b8275d35d 167 #if defined __CHECK_DEVICE_DEFINES
<> 135:176b8275d35d 168 #ifndef __CM0PLUS_REV
<> 135:176b8275d35d 169 #define __CM0PLUS_REV 0x0000
<> 135:176b8275d35d 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
<> 135:176b8275d35d 171 #endif
<> 135:176b8275d35d 172
<> 135:176b8275d35d 173 #ifndef __MPU_PRESENT
<> 135:176b8275d35d 174 #define __MPU_PRESENT 0
<> 135:176b8275d35d 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 135:176b8275d35d 176 #endif
<> 135:176b8275d35d 177
<> 135:176b8275d35d 178 #ifndef __VTOR_PRESENT
<> 135:176b8275d35d 179 #define __VTOR_PRESENT 0
<> 135:176b8275d35d 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
<> 135:176b8275d35d 181 #endif
<> 135:176b8275d35d 182
<> 135:176b8275d35d 183 #ifndef __NVIC_PRIO_BITS
<> 135:176b8275d35d 184 #define __NVIC_PRIO_BITS 2
<> 135:176b8275d35d 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 135:176b8275d35d 186 #endif
<> 135:176b8275d35d 187
<> 135:176b8275d35d 188 #ifndef __Vendor_SysTickConfig
<> 135:176b8275d35d 189 #define __Vendor_SysTickConfig 0
<> 135:176b8275d35d 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 135:176b8275d35d 191 #endif
<> 135:176b8275d35d 192 #endif
<> 135:176b8275d35d 193
<> 135:176b8275d35d 194 /* IO definitions (access restrictions to peripheral registers) */
<> 135:176b8275d35d 195 /**
<> 135:176b8275d35d 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 135:176b8275d35d 197
<> 135:176b8275d35d 198 <strong>IO Type Qualifiers</strong> are used
<> 135:176b8275d35d 199 \li to specify the access to peripheral variables.
<> 135:176b8275d35d 200 \li for automatic generation of peripheral register debug information.
<> 135:176b8275d35d 201 */
<> 135:176b8275d35d 202 #ifdef __cplusplus
<> 135:176b8275d35d 203 #define __I volatile /*!< Defines 'read only' permissions */
<> 135:176b8275d35d 204 #else
<> 135:176b8275d35d 205 #define __I volatile const /*!< Defines 'read only' permissions */
<> 135:176b8275d35d 206 #endif
<> 135:176b8275d35d 207 #define __O volatile /*!< Defines 'write only' permissions */
<> 135:176b8275d35d 208 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 135:176b8275d35d 209
<> 135:176b8275d35d 210 #ifdef __cplusplus
<> 135:176b8275d35d 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 135:176b8275d35d 212 #else
<> 135:176b8275d35d 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 135:176b8275d35d 214 #endif
<> 135:176b8275d35d 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 135:176b8275d35d 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 135:176b8275d35d 217
<> 135:176b8275d35d 218 /*@} end of group Cortex-M0+ */
<> 135:176b8275d35d 219
<> 135:176b8275d35d 220
<> 135:176b8275d35d 221
<> 135:176b8275d35d 222 /*******************************************************************************
<> 135:176b8275d35d 223 * Register Abstraction
<> 135:176b8275d35d 224 Core Register contain:
<> 135:176b8275d35d 225 - Core Register
<> 135:176b8275d35d 226 - Core NVIC Register
<> 135:176b8275d35d 227 - Core SCB Register
<> 135:176b8275d35d 228 - Core SysTick Register
<> 135:176b8275d35d 229 - Core MPU Register
<> 135:176b8275d35d 230 ******************************************************************************/
<> 135:176b8275d35d 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 135:176b8275d35d 232 \brief Type definitions and defines for Cortex-M processor based devices.
<> 135:176b8275d35d 233 */
<> 135:176b8275d35d 234
<> 135:176b8275d35d 235 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 236 \defgroup CMSIS_CORE Status and Control Registers
<> 135:176b8275d35d 237 \brief Core Register type definitions.
<> 135:176b8275d35d 238 @{
<> 135:176b8275d35d 239 */
<> 135:176b8275d35d 240
<> 135:176b8275d35d 241 /** \brief Union type to access the Application Program Status Register (APSR).
<> 135:176b8275d35d 242 */
<> 135:176b8275d35d 243 typedef union
<> 135:176b8275d35d 244 {
<> 135:176b8275d35d 245 struct
<> 135:176b8275d35d 246 {
<> 135:176b8275d35d 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 135:176b8275d35d 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 135:176b8275d35d 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 135:176b8275d35d 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 135:176b8275d35d 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 135:176b8275d35d 252 } b; /*!< Structure used for bit access */
<> 135:176b8275d35d 253 uint32_t w; /*!< Type used for word access */
<> 135:176b8275d35d 254 } APSR_Type;
<> 135:176b8275d35d 255
<> 135:176b8275d35d 256 /* APSR Register Definitions */
<> 135:176b8275d35d 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 135:176b8275d35d 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 135:176b8275d35d 259
<> 135:176b8275d35d 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 135:176b8275d35d 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 135:176b8275d35d 262
<> 135:176b8275d35d 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 135:176b8275d35d 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 135:176b8275d35d 265
<> 135:176b8275d35d 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 135:176b8275d35d 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 135:176b8275d35d 268
<> 135:176b8275d35d 269
<> 135:176b8275d35d 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 135:176b8275d35d 271 */
<> 135:176b8275d35d 272 typedef union
<> 135:176b8275d35d 273 {
<> 135:176b8275d35d 274 struct
<> 135:176b8275d35d 275 {
<> 135:176b8275d35d 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 135:176b8275d35d 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 135:176b8275d35d 278 } b; /*!< Structure used for bit access */
<> 135:176b8275d35d 279 uint32_t w; /*!< Type used for word access */
<> 135:176b8275d35d 280 } IPSR_Type;
<> 135:176b8275d35d 281
<> 135:176b8275d35d 282 /* IPSR Register Definitions */
<> 135:176b8275d35d 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 135:176b8275d35d 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 135:176b8275d35d 285
<> 135:176b8275d35d 286
<> 135:176b8275d35d 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 135:176b8275d35d 288 */
<> 135:176b8275d35d 289 typedef union
<> 135:176b8275d35d 290 {
<> 135:176b8275d35d 291 struct
<> 135:176b8275d35d 292 {
<> 135:176b8275d35d 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 135:176b8275d35d 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 135:176b8275d35d 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 135:176b8275d35d 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 135:176b8275d35d 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 135:176b8275d35d 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 135:176b8275d35d 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 135:176b8275d35d 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 135:176b8275d35d 301 } b; /*!< Structure used for bit access */
<> 135:176b8275d35d 302 uint32_t w; /*!< Type used for word access */
<> 135:176b8275d35d 303 } xPSR_Type;
<> 135:176b8275d35d 304
<> 135:176b8275d35d 305 /* xPSR Register Definitions */
<> 135:176b8275d35d 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 135:176b8275d35d 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 135:176b8275d35d 308
<> 135:176b8275d35d 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 135:176b8275d35d 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 135:176b8275d35d 311
<> 135:176b8275d35d 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 135:176b8275d35d 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 135:176b8275d35d 314
<> 135:176b8275d35d 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 135:176b8275d35d 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 135:176b8275d35d 317
<> 135:176b8275d35d 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 135:176b8275d35d 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 135:176b8275d35d 320
<> 135:176b8275d35d 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 135:176b8275d35d 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 135:176b8275d35d 323
<> 135:176b8275d35d 324
<> 135:176b8275d35d 325 /** \brief Union type to access the Control Registers (CONTROL).
<> 135:176b8275d35d 326 */
<> 135:176b8275d35d 327 typedef union
<> 135:176b8275d35d 328 {
<> 135:176b8275d35d 329 struct
<> 135:176b8275d35d 330 {
<> 135:176b8275d35d 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 135:176b8275d35d 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 135:176b8275d35d 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 135:176b8275d35d 334 } b; /*!< Structure used for bit access */
<> 135:176b8275d35d 335 uint32_t w; /*!< Type used for word access */
<> 135:176b8275d35d 336 } CONTROL_Type;
<> 135:176b8275d35d 337
<> 135:176b8275d35d 338 /* CONTROL Register Definitions */
<> 135:176b8275d35d 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 135:176b8275d35d 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 135:176b8275d35d 341
<> 135:176b8275d35d 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 135:176b8275d35d 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 135:176b8275d35d 344
<> 135:176b8275d35d 345 /*@} end of group CMSIS_CORE */
<> 135:176b8275d35d 346
<> 135:176b8275d35d 347
<> 135:176b8275d35d 348 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 135:176b8275d35d 350 \brief Type definitions for the NVIC Registers
<> 135:176b8275d35d 351 @{
<> 135:176b8275d35d 352 */
<> 135:176b8275d35d 353
<> 135:176b8275d35d 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 135:176b8275d35d 355 */
<> 135:176b8275d35d 356 typedef struct
<> 135:176b8275d35d 357 {
<> 135:176b8275d35d 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 135:176b8275d35d 359 uint32_t RESERVED0[31];
<> 135:176b8275d35d 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 135:176b8275d35d 361 uint32_t RSERVED1[31];
<> 135:176b8275d35d 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 135:176b8275d35d 363 uint32_t RESERVED2[31];
<> 135:176b8275d35d 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 135:176b8275d35d 365 uint32_t RESERVED3[31];
<> 135:176b8275d35d 366 uint32_t RESERVED4[64];
<> 135:176b8275d35d 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 135:176b8275d35d 368 } NVIC_Type;
<> 135:176b8275d35d 369
<> 135:176b8275d35d 370 /*@} end of group CMSIS_NVIC */
<> 135:176b8275d35d 371
<> 135:176b8275d35d 372
<> 135:176b8275d35d 373 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 374 \defgroup CMSIS_SCB System Control Block (SCB)
<> 135:176b8275d35d 375 \brief Type definitions for the System Control Block Registers
<> 135:176b8275d35d 376 @{
<> 135:176b8275d35d 377 */
<> 135:176b8275d35d 378
<> 135:176b8275d35d 379 /** \brief Structure type to access the System Control Block (SCB).
<> 135:176b8275d35d 380 */
<> 135:176b8275d35d 381 typedef struct
<> 135:176b8275d35d 382 {
<> 135:176b8275d35d 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 135:176b8275d35d 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 135:176b8275d35d 385 #if (__VTOR_PRESENT == 1)
<> 135:176b8275d35d 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 135:176b8275d35d 387 #else
<> 135:176b8275d35d 388 uint32_t RESERVED0;
<> 135:176b8275d35d 389 #endif
<> 135:176b8275d35d 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 135:176b8275d35d 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 135:176b8275d35d 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 135:176b8275d35d 393 uint32_t RESERVED1;
<> 135:176b8275d35d 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 135:176b8275d35d 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 135:176b8275d35d 396 } SCB_Type;
<> 135:176b8275d35d 397
<> 135:176b8275d35d 398 /* SCB CPUID Register Definitions */
<> 135:176b8275d35d 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 135:176b8275d35d 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 135:176b8275d35d 401
<> 135:176b8275d35d 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 135:176b8275d35d 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 135:176b8275d35d 404
<> 135:176b8275d35d 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 135:176b8275d35d 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 135:176b8275d35d 407
<> 135:176b8275d35d 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 135:176b8275d35d 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 135:176b8275d35d 410
<> 135:176b8275d35d 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 135:176b8275d35d 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 135:176b8275d35d 413
<> 135:176b8275d35d 414 /* SCB Interrupt Control State Register Definitions */
<> 135:176b8275d35d 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 135:176b8275d35d 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 135:176b8275d35d 417
<> 135:176b8275d35d 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 135:176b8275d35d 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 135:176b8275d35d 420
<> 135:176b8275d35d 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 135:176b8275d35d 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 135:176b8275d35d 423
<> 135:176b8275d35d 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 135:176b8275d35d 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 135:176b8275d35d 426
<> 135:176b8275d35d 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 135:176b8275d35d 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 135:176b8275d35d 429
<> 135:176b8275d35d 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 135:176b8275d35d 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 135:176b8275d35d 432
<> 135:176b8275d35d 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 135:176b8275d35d 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 135:176b8275d35d 435
<> 135:176b8275d35d 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 135:176b8275d35d 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 135:176b8275d35d 438
<> 135:176b8275d35d 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 135:176b8275d35d 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 135:176b8275d35d 441
<> 135:176b8275d35d 442 #if (__VTOR_PRESENT == 1)
<> 135:176b8275d35d 443 /* SCB Interrupt Control State Register Definitions */
<> 135:176b8275d35d 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
<> 135:176b8275d35d 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 135:176b8275d35d 446 #endif
<> 135:176b8275d35d 447
<> 135:176b8275d35d 448 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 135:176b8275d35d 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 135:176b8275d35d 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 135:176b8275d35d 451
<> 135:176b8275d35d 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 135:176b8275d35d 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 135:176b8275d35d 454
<> 135:176b8275d35d 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 135:176b8275d35d 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 135:176b8275d35d 457
<> 135:176b8275d35d 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 135:176b8275d35d 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 135:176b8275d35d 460
<> 135:176b8275d35d 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 135:176b8275d35d 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 135:176b8275d35d 463
<> 135:176b8275d35d 464 /* SCB System Control Register Definitions */
<> 135:176b8275d35d 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 135:176b8275d35d 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 135:176b8275d35d 467
<> 135:176b8275d35d 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 135:176b8275d35d 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 135:176b8275d35d 470
<> 135:176b8275d35d 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 135:176b8275d35d 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 135:176b8275d35d 473
<> 135:176b8275d35d 474 /* SCB Configuration Control Register Definitions */
<> 135:176b8275d35d 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 135:176b8275d35d 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 135:176b8275d35d 477
<> 135:176b8275d35d 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 135:176b8275d35d 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 135:176b8275d35d 480
<> 135:176b8275d35d 481 /* SCB System Handler Control and State Register Definitions */
<> 135:176b8275d35d 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 135:176b8275d35d 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 135:176b8275d35d 484
<> 135:176b8275d35d 485 /*@} end of group CMSIS_SCB */
<> 135:176b8275d35d 486
<> 135:176b8275d35d 487
<> 135:176b8275d35d 488 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 135:176b8275d35d 490 \brief Type definitions for the System Timer Registers.
<> 135:176b8275d35d 491 @{
<> 135:176b8275d35d 492 */
<> 135:176b8275d35d 493
<> 135:176b8275d35d 494 /** \brief Structure type to access the System Timer (SysTick).
<> 135:176b8275d35d 495 */
<> 135:176b8275d35d 496 typedef struct
<> 135:176b8275d35d 497 {
<> 135:176b8275d35d 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 135:176b8275d35d 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 135:176b8275d35d 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 135:176b8275d35d 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 135:176b8275d35d 502 } SysTick_Type;
<> 135:176b8275d35d 503
<> 135:176b8275d35d 504 /* SysTick Control / Status Register Definitions */
<> 135:176b8275d35d 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 135:176b8275d35d 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 135:176b8275d35d 507
<> 135:176b8275d35d 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 135:176b8275d35d 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 135:176b8275d35d 510
<> 135:176b8275d35d 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 135:176b8275d35d 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 135:176b8275d35d 513
<> 135:176b8275d35d 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 135:176b8275d35d 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 135:176b8275d35d 516
<> 135:176b8275d35d 517 /* SysTick Reload Register Definitions */
<> 135:176b8275d35d 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 135:176b8275d35d 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 135:176b8275d35d 520
<> 135:176b8275d35d 521 /* SysTick Current Register Definitions */
<> 135:176b8275d35d 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 135:176b8275d35d 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 135:176b8275d35d 524
<> 135:176b8275d35d 525 /* SysTick Calibration Register Definitions */
<> 135:176b8275d35d 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 135:176b8275d35d 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 135:176b8275d35d 528
<> 135:176b8275d35d 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 135:176b8275d35d 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 135:176b8275d35d 531
<> 135:176b8275d35d 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 135:176b8275d35d 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 135:176b8275d35d 534
<> 135:176b8275d35d 535 /*@} end of group CMSIS_SysTick */
<> 135:176b8275d35d 536
<> 135:176b8275d35d 537 #if (__MPU_PRESENT == 1)
<> 135:176b8275d35d 538 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 135:176b8275d35d 540 \brief Type definitions for the Memory Protection Unit (MPU)
<> 135:176b8275d35d 541 @{
<> 135:176b8275d35d 542 */
<> 135:176b8275d35d 543
<> 135:176b8275d35d 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 135:176b8275d35d 545 */
<> 135:176b8275d35d 546 typedef struct
<> 135:176b8275d35d 547 {
<> 135:176b8275d35d 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 135:176b8275d35d 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 135:176b8275d35d 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 135:176b8275d35d 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 135:176b8275d35d 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 135:176b8275d35d 553 } MPU_Type;
<> 135:176b8275d35d 554
<> 135:176b8275d35d 555 /* MPU Type Register */
<> 135:176b8275d35d 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 135:176b8275d35d 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 135:176b8275d35d 558
<> 135:176b8275d35d 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 135:176b8275d35d 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 135:176b8275d35d 561
<> 135:176b8275d35d 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 135:176b8275d35d 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 135:176b8275d35d 564
<> 135:176b8275d35d 565 /* MPU Control Register */
<> 135:176b8275d35d 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 135:176b8275d35d 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 135:176b8275d35d 568
<> 135:176b8275d35d 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 135:176b8275d35d 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 135:176b8275d35d 571
<> 135:176b8275d35d 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 135:176b8275d35d 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 135:176b8275d35d 574
<> 135:176b8275d35d 575 /* MPU Region Number Register */
<> 135:176b8275d35d 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 135:176b8275d35d 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 135:176b8275d35d 578
<> 135:176b8275d35d 579 /* MPU Region Base Address Register */
<> 135:176b8275d35d 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
<> 135:176b8275d35d 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 135:176b8275d35d 582
<> 135:176b8275d35d 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 135:176b8275d35d 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 135:176b8275d35d 585
<> 135:176b8275d35d 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 135:176b8275d35d 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 135:176b8275d35d 588
<> 135:176b8275d35d 589 /* MPU Region Attribute and Size Register */
<> 135:176b8275d35d 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 135:176b8275d35d 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 135:176b8275d35d 592
<> 135:176b8275d35d 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 135:176b8275d35d 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 135:176b8275d35d 595
<> 135:176b8275d35d 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 135:176b8275d35d 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 135:176b8275d35d 598
<> 135:176b8275d35d 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 135:176b8275d35d 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 135:176b8275d35d 601
<> 135:176b8275d35d 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 135:176b8275d35d 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 135:176b8275d35d 604
<> 135:176b8275d35d 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 135:176b8275d35d 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 135:176b8275d35d 607
<> 135:176b8275d35d 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 135:176b8275d35d 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 135:176b8275d35d 610
<> 135:176b8275d35d 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 135:176b8275d35d 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 135:176b8275d35d 613
<> 135:176b8275d35d 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 135:176b8275d35d 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 135:176b8275d35d 616
<> 135:176b8275d35d 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 135:176b8275d35d 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 135:176b8275d35d 619
<> 135:176b8275d35d 620 /*@} end of group CMSIS_MPU */
<> 135:176b8275d35d 621 #endif
<> 135:176b8275d35d 622
<> 135:176b8275d35d 623
<> 135:176b8275d35d 624 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 135:176b8275d35d 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 135:176b8275d35d 627 are only accessible over DAP and not via processor. Therefore
<> 135:176b8275d35d 628 they are not covered by the Cortex-M0 header file.
<> 135:176b8275d35d 629 @{
<> 135:176b8275d35d 630 */
<> 135:176b8275d35d 631 /*@} end of group CMSIS_CoreDebug */
<> 135:176b8275d35d 632
<> 135:176b8275d35d 633
<> 135:176b8275d35d 634 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 635 \defgroup CMSIS_core_base Core Definitions
<> 135:176b8275d35d 636 \brief Definitions for base addresses, unions, and structures.
<> 135:176b8275d35d 637 @{
<> 135:176b8275d35d 638 */
<> 135:176b8275d35d 639
<> 135:176b8275d35d 640 /* Memory mapping of Cortex-M0+ Hardware */
<> 135:176b8275d35d 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 135:176b8275d35d 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 135:176b8275d35d 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 135:176b8275d35d 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 135:176b8275d35d 645
<> 135:176b8275d35d 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 135:176b8275d35d 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 135:176b8275d35d 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 135:176b8275d35d 649
<> 135:176b8275d35d 650 #if (__MPU_PRESENT == 1)
<> 135:176b8275d35d 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 135:176b8275d35d 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 135:176b8275d35d 653 #endif
<> 135:176b8275d35d 654
<> 135:176b8275d35d 655 /*@} */
<> 135:176b8275d35d 656
<> 135:176b8275d35d 657
<> 135:176b8275d35d 658
<> 135:176b8275d35d 659 /*******************************************************************************
<> 135:176b8275d35d 660 * Hardware Abstraction Layer
<> 135:176b8275d35d 661 Core Function Interface contains:
<> 135:176b8275d35d 662 - Core NVIC Functions
<> 135:176b8275d35d 663 - Core SysTick Functions
<> 135:176b8275d35d 664 - Core Register Access Functions
<> 135:176b8275d35d 665 ******************************************************************************/
<> 135:176b8275d35d 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 135:176b8275d35d 667 */
<> 135:176b8275d35d 668
<> 135:176b8275d35d 669
<> 135:176b8275d35d 670
<> 135:176b8275d35d 671 /* ########################## NVIC functions #################################### */
<> 135:176b8275d35d 672 /** \ingroup CMSIS_Core_FunctionInterface
<> 135:176b8275d35d 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 135:176b8275d35d 674 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 135:176b8275d35d 675 @{
<> 135:176b8275d35d 676 */
<> 135:176b8275d35d 677
<> 135:176b8275d35d 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 135:176b8275d35d 679 /* The following MACROS handle generation of the register offset and byte masks */
<> 135:176b8275d35d 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 135:176b8275d35d 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 135:176b8275d35d 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 135:176b8275d35d 683
<> 135:176b8275d35d 684
<> 135:176b8275d35d 685 /** \brief Enable External Interrupt
<> 135:176b8275d35d 686
<> 135:176b8275d35d 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 135:176b8275d35d 688
<> 135:176b8275d35d 689 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 135:176b8275d35d 690 */
<> 135:176b8275d35d 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 135:176b8275d35d 692 {
<> 135:176b8275d35d 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 135:176b8275d35d 694 }
<> 135:176b8275d35d 695
<> 135:176b8275d35d 696
<> 135:176b8275d35d 697 /** \brief Disable External Interrupt
<> 135:176b8275d35d 698
<> 135:176b8275d35d 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 135:176b8275d35d 700
<> 135:176b8275d35d 701 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 135:176b8275d35d 702 */
<> 135:176b8275d35d 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 135:176b8275d35d 704 {
<> 135:176b8275d35d 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 135:176b8275d35d 706 __DSB();
<> 135:176b8275d35d 707 __ISB();
<> 135:176b8275d35d 708 }
<> 135:176b8275d35d 709
<> 135:176b8275d35d 710
<> 135:176b8275d35d 711 /** \brief Get Pending Interrupt
<> 135:176b8275d35d 712
<> 135:176b8275d35d 713 The function reads the pending register in the NVIC and returns the pending bit
<> 135:176b8275d35d 714 for the specified interrupt.
<> 135:176b8275d35d 715
<> 135:176b8275d35d 716 \param [in] IRQn Interrupt number.
<> 135:176b8275d35d 717
<> 135:176b8275d35d 718 \return 0 Interrupt status is not pending.
<> 135:176b8275d35d 719 \return 1 Interrupt status is pending.
<> 135:176b8275d35d 720 */
<> 135:176b8275d35d 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 135:176b8275d35d 722 {
<> 135:176b8275d35d 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 135:176b8275d35d 724 }
<> 135:176b8275d35d 725
<> 135:176b8275d35d 726
<> 135:176b8275d35d 727 /** \brief Set Pending Interrupt
<> 135:176b8275d35d 728
<> 135:176b8275d35d 729 The function sets the pending bit of an external interrupt.
<> 135:176b8275d35d 730
<> 135:176b8275d35d 731 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 135:176b8275d35d 732 */
<> 135:176b8275d35d 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 135:176b8275d35d 734 {
<> 135:176b8275d35d 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 135:176b8275d35d 736 }
<> 135:176b8275d35d 737
<> 135:176b8275d35d 738
<> 135:176b8275d35d 739 /** \brief Clear Pending Interrupt
<> 135:176b8275d35d 740
<> 135:176b8275d35d 741 The function clears the pending bit of an external interrupt.
<> 135:176b8275d35d 742
<> 135:176b8275d35d 743 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 135:176b8275d35d 744 */
<> 135:176b8275d35d 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 135:176b8275d35d 746 {
<> 135:176b8275d35d 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 135:176b8275d35d 748 }
<> 135:176b8275d35d 749
<> 135:176b8275d35d 750
<> 135:176b8275d35d 751 /** \brief Set Interrupt Priority
<> 135:176b8275d35d 752
<> 135:176b8275d35d 753 The function sets the priority of an interrupt.
<> 135:176b8275d35d 754
<> 135:176b8275d35d 755 \note The priority cannot be set for every core interrupt.
<> 135:176b8275d35d 756
<> 135:176b8275d35d 757 \param [in] IRQn Interrupt number.
<> 135:176b8275d35d 758 \param [in] priority Priority to set.
<> 135:176b8275d35d 759 */
<> 135:176b8275d35d 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 135:176b8275d35d 761 {
<> 135:176b8275d35d 762 if((int32_t)(IRQn) < 0) {
<> 135:176b8275d35d 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 135:176b8275d35d 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 135:176b8275d35d 765 }
<> 135:176b8275d35d 766 else {
<> 135:176b8275d35d 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 135:176b8275d35d 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 135:176b8275d35d 769 }
<> 135:176b8275d35d 770 }
<> 135:176b8275d35d 771
<> 135:176b8275d35d 772
<> 135:176b8275d35d 773 /** \brief Get Interrupt Priority
<> 135:176b8275d35d 774
<> 135:176b8275d35d 775 The function reads the priority of an interrupt. The interrupt
<> 135:176b8275d35d 776 number can be positive to specify an external (device specific)
<> 135:176b8275d35d 777 interrupt, or negative to specify an internal (core) interrupt.
<> 135:176b8275d35d 778
<> 135:176b8275d35d 779
<> 135:176b8275d35d 780 \param [in] IRQn Interrupt number.
<> 135:176b8275d35d 781 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 135:176b8275d35d 782 priority bits of the microcontroller.
<> 135:176b8275d35d 783 */
<> 135:176b8275d35d 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 135:176b8275d35d 785 {
<> 135:176b8275d35d 786
<> 135:176b8275d35d 787 if((int32_t)(IRQn) < 0) {
<> 135:176b8275d35d 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 135:176b8275d35d 789 }
<> 135:176b8275d35d 790 else {
<> 135:176b8275d35d 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 135:176b8275d35d 792 }
<> 135:176b8275d35d 793 }
<> 135:176b8275d35d 794
<> 135:176b8275d35d 795
<> 135:176b8275d35d 796 /** \brief System Reset
<> 135:176b8275d35d 797
<> 135:176b8275d35d 798 The function initiates a system reset request to reset the MCU.
<> 135:176b8275d35d 799 */
<> 135:176b8275d35d 800 __STATIC_INLINE void NVIC_SystemReset(void)
<> 135:176b8275d35d 801 {
<> 135:176b8275d35d 802 __DSB(); /* Ensure all outstanding memory accesses included
<> 135:176b8275d35d 803 buffered write are completed before reset */
<> 135:176b8275d35d 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 135:176b8275d35d 805 SCB_AIRCR_SYSRESETREQ_Msk);
<> 135:176b8275d35d 806 __DSB(); /* Ensure completion of memory access */
<> 135:176b8275d35d 807 while(1) { __NOP(); } /* wait until reset */
<> 135:176b8275d35d 808 }
<> 135:176b8275d35d 809
<> 135:176b8275d35d 810 /*@} end of CMSIS_Core_NVICFunctions */
<> 135:176b8275d35d 811
<> 135:176b8275d35d 812
<> 135:176b8275d35d 813
<> 135:176b8275d35d 814 /* ################################## SysTick function ############################################ */
<> 135:176b8275d35d 815 /** \ingroup CMSIS_Core_FunctionInterface
<> 135:176b8275d35d 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 135:176b8275d35d 817 \brief Functions that configure the System.
<> 135:176b8275d35d 818 @{
<> 135:176b8275d35d 819 */
<> 135:176b8275d35d 820
<> 135:176b8275d35d 821 #if (__Vendor_SysTickConfig == 0)
<> 135:176b8275d35d 822
<> 135:176b8275d35d 823 /** \brief System Tick Configuration
<> 135:176b8275d35d 824
<> 135:176b8275d35d 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 135:176b8275d35d 826 Counter is in free running mode to generate periodic interrupts.
<> 135:176b8275d35d 827
<> 135:176b8275d35d 828 \param [in] ticks Number of ticks between two interrupts.
<> 135:176b8275d35d 829
<> 135:176b8275d35d 830 \return 0 Function succeeded.
<> 135:176b8275d35d 831 \return 1 Function failed.
<> 135:176b8275d35d 832
<> 135:176b8275d35d 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 135:176b8275d35d 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 135:176b8275d35d 835 must contain a vendor-specific implementation of this function.
<> 135:176b8275d35d 836
<> 135:176b8275d35d 837 */
<> 135:176b8275d35d 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 135:176b8275d35d 839 {
<> 135:176b8275d35d 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
<> 135:176b8275d35d 841
<> 135:176b8275d35d 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 135:176b8275d35d 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 135:176b8275d35d 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 135:176b8275d35d 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 135:176b8275d35d 846 SysTick_CTRL_TICKINT_Msk |
<> 135:176b8275d35d 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 135:176b8275d35d 848 return (0UL); /* Function successful */
<> 135:176b8275d35d 849 }
<> 135:176b8275d35d 850
<> 135:176b8275d35d 851 #endif
<> 135:176b8275d35d 852
<> 135:176b8275d35d 853 /*@} end of CMSIS_Core_SysTickFunctions */
<> 135:176b8275d35d 854
<> 135:176b8275d35d 855
<> 135:176b8275d35d 856
<> 135:176b8275d35d 857
<> 135:176b8275d35d 858 #ifdef __cplusplus
<> 135:176b8275d35d 859 }
<> 135:176b8275d35d 860 #endif
<> 135:176b8275d35d 861
<> 135:176b8275d35d 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
<> 135:176b8275d35d 863
<> 135:176b8275d35d 864 #endif /* __CMSIS_GENERIC */