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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_ca_mmu.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 ;/**************************************************************************//**
<> 135:176b8275d35d 2 ; * @file core_ca_mmu.h
<> 135:176b8275d35d 3 ; * @brief MMU Startup File for A9_MP Device Series
<> 135:176b8275d35d 4 ; * @version V1.01
<> 135:176b8275d35d 5 ; * @date 10 Sept 2014
<> 135:176b8275d35d 6 ; *
<> 135:176b8275d35d 7 ; * @note
<> 135:176b8275d35d 8 ; *
<> 135:176b8275d35d 9 ; ******************************************************************************/
<> 135:176b8275d35d 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
<> 135:176b8275d35d 11 ;
<> 135:176b8275d35d 12 ; All rights reserved.
<> 135:176b8275d35d 13 ; Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 ; modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 ; - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 ; notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 ; - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 ; notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 ; documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 ; - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 ; to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 ; specific prior written permission.
<> 135:176b8275d35d 23 ; *
<> 135:176b8275d35d 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 ; POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ; ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37 #ifdef __cplusplus
<> 135:176b8275d35d 38 extern "C" {
<> 135:176b8275d35d 39 #endif
<> 135:176b8275d35d 40
<> 135:176b8275d35d 41 #ifndef _MMU_FUNC_H
<> 135:176b8275d35d 42 #define _MMU_FUNC_H
<> 135:176b8275d35d 43
<> 135:176b8275d35d 44 #define SECTION_DESCRIPTOR (0x2)
<> 135:176b8275d35d 45 #define SECTION_MASK (0xFFFFFFFC)
<> 135:176b8275d35d 46
<> 135:176b8275d35d 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
<> 135:176b8275d35d 48 #define SECTION_B_SHIFT (2)
<> 135:176b8275d35d 49 #define SECTION_C_SHIFT (3)
<> 135:176b8275d35d 50 #define SECTION_TEX0_SHIFT (12)
<> 135:176b8275d35d 51 #define SECTION_TEX1_SHIFT (13)
<> 135:176b8275d35d 52 #define SECTION_TEX2_SHIFT (14)
<> 135:176b8275d35d 53
<> 135:176b8275d35d 54 #define SECTION_XN_MASK (0xFFFFFFEF)
<> 135:176b8275d35d 55 #define SECTION_XN_SHIFT (4)
<> 135:176b8275d35d 56
<> 135:176b8275d35d 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
<> 135:176b8275d35d 58 #define SECTION_DOMAIN_SHIFT (5)
<> 135:176b8275d35d 59
<> 135:176b8275d35d 60 #define SECTION_P_MASK (0xFFFFFDFF)
<> 135:176b8275d35d 61 #define SECTION_P_SHIFT (9)
<> 135:176b8275d35d 62
<> 135:176b8275d35d 63 #define SECTION_AP_MASK (0xFFFF73FF)
<> 135:176b8275d35d 64 #define SECTION_AP_SHIFT (10)
<> 135:176b8275d35d 65 #define SECTION_AP2_SHIFT (15)
<> 135:176b8275d35d 66
<> 135:176b8275d35d 67 #define SECTION_S_MASK (0xFFFEFFFF)
<> 135:176b8275d35d 68 #define SECTION_S_SHIFT (16)
<> 135:176b8275d35d 69
<> 135:176b8275d35d 70 #define SECTION_NG_MASK (0xFFFDFFFF)
<> 135:176b8275d35d 71 #define SECTION_NG_SHIFT (17)
<> 135:176b8275d35d 72
<> 135:176b8275d35d 73 #define SECTION_NS_MASK (0xFFF7FFFF)
<> 135:176b8275d35d 74 #define SECTION_NS_SHIFT (19)
<> 135:176b8275d35d 75
<> 135:176b8275d35d 76
<> 135:176b8275d35d 77 #define PAGE_L1_DESCRIPTOR (0x1)
<> 135:176b8275d35d 78 #define PAGE_L1_MASK (0xFFFFFFFC)
<> 135:176b8275d35d 79
<> 135:176b8275d35d 80 #define PAGE_L2_4K_DESC (0x2)
<> 135:176b8275d35d 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
<> 135:176b8275d35d 82
<> 135:176b8275d35d 83 #define PAGE_L2_64K_DESC (0x1)
<> 135:176b8275d35d 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
<> 135:176b8275d35d 85
<> 135:176b8275d35d 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
<> 135:176b8275d35d 87 #define PAGE_4K_B_SHIFT (2)
<> 135:176b8275d35d 88 #define PAGE_4K_C_SHIFT (3)
<> 135:176b8275d35d 89 #define PAGE_4K_TEX0_SHIFT (6)
<> 135:176b8275d35d 90 #define PAGE_4K_TEX1_SHIFT (7)
<> 135:176b8275d35d 91 #define PAGE_4K_TEX2_SHIFT (8)
<> 135:176b8275d35d 92
<> 135:176b8275d35d 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
<> 135:176b8275d35d 94 #define PAGE_64K_B_SHIFT (2)
<> 135:176b8275d35d 95 #define PAGE_64K_C_SHIFT (3)
<> 135:176b8275d35d 96 #define PAGE_64K_TEX0_SHIFT (12)
<> 135:176b8275d35d 97 #define PAGE_64K_TEX1_SHIFT (13)
<> 135:176b8275d35d 98 #define PAGE_64K_TEX2_SHIFT (14)
<> 135:176b8275d35d 99
<> 135:176b8275d35d 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
<> 135:176b8275d35d 101 #define PAGE_B_SHIFT (2)
<> 135:176b8275d35d 102 #define PAGE_C_SHIFT (3)
<> 135:176b8275d35d 103 #define PAGE_TEX_SHIFT (12)
<> 135:176b8275d35d 104
<> 135:176b8275d35d 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
<> 135:176b8275d35d 106 #define PAGE_XN_4K_SHIFT (0)
<> 135:176b8275d35d 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
<> 135:176b8275d35d 108 #define PAGE_XN_64K_SHIFT (15)
<> 135:176b8275d35d 109
<> 135:176b8275d35d 110
<> 135:176b8275d35d 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
<> 135:176b8275d35d 112 #define PAGE_DOMAIN_SHIFT (5)
<> 135:176b8275d35d 113
<> 135:176b8275d35d 114 #define PAGE_P_MASK (0xFFFFFDFF)
<> 135:176b8275d35d 115 #define PAGE_P_SHIFT (9)
<> 135:176b8275d35d 116
<> 135:176b8275d35d 117 #define PAGE_AP_MASK (0xFFFFFDCF)
<> 135:176b8275d35d 118 #define PAGE_AP_SHIFT (4)
<> 135:176b8275d35d 119 #define PAGE_AP2_SHIFT (9)
<> 135:176b8275d35d 120
<> 135:176b8275d35d 121 #define PAGE_S_MASK (0xFFFFFBFF)
<> 135:176b8275d35d 122 #define PAGE_S_SHIFT (10)
<> 135:176b8275d35d 123
<> 135:176b8275d35d 124 #define PAGE_NG_MASK (0xFFFFF7FF)
<> 135:176b8275d35d 125 #define PAGE_NG_SHIFT (11)
<> 135:176b8275d35d 126
<> 135:176b8275d35d 127 #define PAGE_NS_MASK (0xFFFFFFF7)
<> 135:176b8275d35d 128 #define PAGE_NS_SHIFT (3)
<> 135:176b8275d35d 129
<> 135:176b8275d35d 130 #define OFFSET_1M (0x00100000)
<> 135:176b8275d35d 131 #define OFFSET_64K (0x00010000)
<> 135:176b8275d35d 132 #define OFFSET_4K (0x00001000)
<> 135:176b8275d35d 133
<> 135:176b8275d35d 134 #define DESCRIPTOR_FAULT (0x00000000)
<> 135:176b8275d35d 135
<> 135:176b8275d35d 136 /* ########################### MMU Function Access ########################### */
<> 135:176b8275d35d 137 /** \ingroup MMU_FunctionInterface
<> 135:176b8275d35d 138 \defgroup MMU_Functions MMU Functions Interface
<> 135:176b8275d35d 139 @{
<> 135:176b8275d35d 140 */
<> 135:176b8275d35d 141
<> 135:176b8275d35d 142 /* Attributes enumerations */
<> 135:176b8275d35d 143
<> 135:176b8275d35d 144 /* Region size attributes */
<> 135:176b8275d35d 145 typedef enum
<> 135:176b8275d35d 146 {
<> 135:176b8275d35d 147 SECTION,
<> 135:176b8275d35d 148 PAGE_4k,
<> 135:176b8275d35d 149 PAGE_64k,
<> 135:176b8275d35d 150 } mmu_region_size_Type;
<> 135:176b8275d35d 151
<> 135:176b8275d35d 152 /* Region type attributes */
<> 135:176b8275d35d 153 typedef enum
<> 135:176b8275d35d 154 {
<> 135:176b8275d35d 155 NORMAL,
<> 135:176b8275d35d 156 DEVICE,
<> 135:176b8275d35d 157 SHARED_DEVICE,
<> 135:176b8275d35d 158 NON_SHARED_DEVICE,
<> 135:176b8275d35d 159 STRONGLY_ORDERED
<> 135:176b8275d35d 160 } mmu_memory_Type;
<> 135:176b8275d35d 161
<> 135:176b8275d35d 162 /* Region cacheability attributes */
<> 135:176b8275d35d 163 typedef enum
<> 135:176b8275d35d 164 {
<> 135:176b8275d35d 165 NON_CACHEABLE,
<> 135:176b8275d35d 166 WB_WA,
<> 135:176b8275d35d 167 WT,
<> 135:176b8275d35d 168 WB_NO_WA,
<> 135:176b8275d35d 169 } mmu_cacheability_Type;
<> 135:176b8275d35d 170
<> 135:176b8275d35d 171 /* Region parity check attributes */
<> 135:176b8275d35d 172 typedef enum
<> 135:176b8275d35d 173 {
<> 135:176b8275d35d 174 ECC_DISABLED,
<> 135:176b8275d35d 175 ECC_ENABLED,
<> 135:176b8275d35d 176 } mmu_ecc_check_Type;
<> 135:176b8275d35d 177
<> 135:176b8275d35d 178 /* Region execution attributes */
<> 135:176b8275d35d 179 typedef enum
<> 135:176b8275d35d 180 {
<> 135:176b8275d35d 181 EXECUTE,
<> 135:176b8275d35d 182 NON_EXECUTE,
<> 135:176b8275d35d 183 } mmu_execute_Type;
<> 135:176b8275d35d 184
<> 135:176b8275d35d 185 /* Region global attributes */
<> 135:176b8275d35d 186 typedef enum
<> 135:176b8275d35d 187 {
<> 135:176b8275d35d 188 GLOBAL,
<> 135:176b8275d35d 189 NON_GLOBAL,
<> 135:176b8275d35d 190 } mmu_global_Type;
<> 135:176b8275d35d 191
<> 135:176b8275d35d 192 /* Region shareability attributes */
<> 135:176b8275d35d 193 typedef enum
<> 135:176b8275d35d 194 {
<> 135:176b8275d35d 195 NON_SHARED,
<> 135:176b8275d35d 196 SHARED,
<> 135:176b8275d35d 197 } mmu_shared_Type;
<> 135:176b8275d35d 198
<> 135:176b8275d35d 199 /* Region security attributes */
<> 135:176b8275d35d 200 typedef enum
<> 135:176b8275d35d 201 {
<> 135:176b8275d35d 202 SECURE,
<> 135:176b8275d35d 203 NON_SECURE,
<> 135:176b8275d35d 204 } mmu_secure_Type;
<> 135:176b8275d35d 205
<> 135:176b8275d35d 206 /* Region access attributes */
<> 135:176b8275d35d 207 typedef enum
<> 135:176b8275d35d 208 {
<> 135:176b8275d35d 209 NO_ACCESS,
<> 135:176b8275d35d 210 RW,
<> 135:176b8275d35d 211 READ,
<> 135:176b8275d35d 212 } mmu_access_Type;
<> 135:176b8275d35d 213
<> 135:176b8275d35d 214 /* Memory Region definition */
<> 135:176b8275d35d 215 typedef struct RegionStruct {
<> 135:176b8275d35d 216 mmu_region_size_Type rg_t;
<> 135:176b8275d35d 217 mmu_memory_Type mem_t;
<> 135:176b8275d35d 218 uint8_t domain;
<> 135:176b8275d35d 219 mmu_cacheability_Type inner_norm_t;
<> 135:176b8275d35d 220 mmu_cacheability_Type outer_norm_t;
<> 135:176b8275d35d 221 mmu_ecc_check_Type e_t;
<> 135:176b8275d35d 222 mmu_execute_Type xn_t;
<> 135:176b8275d35d 223 mmu_global_Type g_t;
<> 135:176b8275d35d 224 mmu_secure_Type sec_t;
<> 135:176b8275d35d 225 mmu_access_Type priv_t;
<> 135:176b8275d35d 226 mmu_access_Type user_t;
<> 135:176b8275d35d 227 mmu_shared_Type sh_t;
<> 135:176b8275d35d 228
<> 135:176b8275d35d 229 } mmu_region_attributes_Type;
<> 135:176b8275d35d 230
<> 135:176b8275d35d 231 /** \brief Set section execution-never attribute
<> 135:176b8275d35d 232
<> 135:176b8275d35d 233 The function sets section execution-never attribute
<> 135:176b8275d35d 234
<> 135:176b8275d35d 235 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
<> 135:176b8275d35d 237
<> 135:176b8275d35d 238 \return 0
<> 135:176b8275d35d 239 */
<> 135:176b8275d35d 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
<> 135:176b8275d35d 241 {
<> 135:176b8275d35d 242 *descriptor_l1 &= SECTION_XN_MASK;
<> 135:176b8275d35d 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
<> 135:176b8275d35d 244 return 0;
<> 135:176b8275d35d 245 }
<> 135:176b8275d35d 246
<> 135:176b8275d35d 247 /** \brief Set section domain
<> 135:176b8275d35d 248
<> 135:176b8275d35d 249 The function sets section domain
<> 135:176b8275d35d 250
<> 135:176b8275d35d 251 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 252 \param [in] domain Section domain
<> 135:176b8275d35d 253
<> 135:176b8275d35d 254 \return 0
<> 135:176b8275d35d 255 */
<> 135:176b8275d35d 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
<> 135:176b8275d35d 257 {
<> 135:176b8275d35d 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
<> 135:176b8275d35d 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
<> 135:176b8275d35d 260 return 0;
<> 135:176b8275d35d 261 }
<> 135:176b8275d35d 262
<> 135:176b8275d35d 263 /** \brief Set section parity check
<> 135:176b8275d35d 264
<> 135:176b8275d35d 265 The function sets section parity check
<> 135:176b8275d35d 266
<> 135:176b8275d35d 267 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 135:176b8275d35d 269
<> 135:176b8275d35d 270 \return 0
<> 135:176b8275d35d 271 */
<> 135:176b8275d35d 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 135:176b8275d35d 273 {
<> 135:176b8275d35d 274 *descriptor_l1 &= SECTION_P_MASK;
<> 135:176b8275d35d 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 135:176b8275d35d 276 return 0;
<> 135:176b8275d35d 277 }
<> 135:176b8275d35d 278
<> 135:176b8275d35d 279 /** \brief Set section access privileges
<> 135:176b8275d35d 280
<> 135:176b8275d35d 281 The function sets section access privileges
<> 135:176b8275d35d 282
<> 135:176b8275d35d 283 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 135:176b8275d35d 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 135:176b8275d35d 286 \param [in] afe Access flag enable
<> 135:176b8275d35d 287
<> 135:176b8275d35d 288 \return 0
<> 135:176b8275d35d 289 */
<> 135:176b8275d35d 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 135:176b8275d35d 291 {
<> 135:176b8275d35d 292 uint32_t ap = 0;
<> 135:176b8275d35d 293
<> 135:176b8275d35d 294 if (afe == 0) { //full access
<> 135:176b8275d35d 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 135:176b8275d35d 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 135:176b8275d35d 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 135:176b8275d35d 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 135:176b8275d35d 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 135:176b8275d35d 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 135:176b8275d35d 301 }
<> 135:176b8275d35d 302
<> 135:176b8275d35d 303 else { //Simplified access
<> 135:176b8275d35d 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 135:176b8275d35d 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 135:176b8275d35d 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 135:176b8275d35d 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 135:176b8275d35d 308 }
<> 135:176b8275d35d 309
<> 135:176b8275d35d 310 *descriptor_l1 &= SECTION_AP_MASK;
<> 135:176b8275d35d 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
<> 135:176b8275d35d 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
<> 135:176b8275d35d 313
<> 135:176b8275d35d 314 return 0;
<> 135:176b8275d35d 315 }
<> 135:176b8275d35d 316
<> 135:176b8275d35d 317 /** \brief Set section shareability
<> 135:176b8275d35d 318
<> 135:176b8275d35d 319 The function sets section shareability
<> 135:176b8275d35d 320
<> 135:176b8275d35d 321 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
<> 135:176b8275d35d 323
<> 135:176b8275d35d 324 \return 0
<> 135:176b8275d35d 325 */
<> 135:176b8275d35d 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
<> 135:176b8275d35d 327 {
<> 135:176b8275d35d 328 *descriptor_l1 &= SECTION_S_MASK;
<> 135:176b8275d35d 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
<> 135:176b8275d35d 330 return 0;
<> 135:176b8275d35d 331 }
<> 135:176b8275d35d 332
<> 135:176b8275d35d 333 /** \brief Set section Global attribute
<> 135:176b8275d35d 334
<> 135:176b8275d35d 335 The function sets section Global attribute
<> 135:176b8275d35d 336
<> 135:176b8275d35d 337 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
<> 135:176b8275d35d 339
<> 135:176b8275d35d 340 \return 0
<> 135:176b8275d35d 341 */
<> 135:176b8275d35d 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
<> 135:176b8275d35d 343 {
<> 135:176b8275d35d 344 *descriptor_l1 &= SECTION_NG_MASK;
<> 135:176b8275d35d 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
<> 135:176b8275d35d 346 return 0;
<> 135:176b8275d35d 347 }
<> 135:176b8275d35d 348
<> 135:176b8275d35d 349 /** \brief Set section Security attribute
<> 135:176b8275d35d 350
<> 135:176b8275d35d 351 The function sets section Global attribute
<> 135:176b8275d35d 352
<> 135:176b8275d35d 353 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
<> 135:176b8275d35d 355
<> 135:176b8275d35d 356 \return 0
<> 135:176b8275d35d 357 */
<> 135:176b8275d35d 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 135:176b8275d35d 359 {
<> 135:176b8275d35d 360 *descriptor_l1 &= SECTION_NS_MASK;
<> 135:176b8275d35d 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
<> 135:176b8275d35d 362 return 0;
<> 135:176b8275d35d 363 }
<> 135:176b8275d35d 364
<> 135:176b8275d35d 365 /* Page 4k or 64k */
<> 135:176b8275d35d 366 /** \brief Set 4k/64k page execution-never attribute
<> 135:176b8275d35d 367
<> 135:176b8275d35d 368 The function sets 4k/64k page execution-never attribute
<> 135:176b8275d35d 369
<> 135:176b8275d35d 370 \param [out] descriptor_l2 L2 descriptor.
<> 135:176b8275d35d 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
<> 135:176b8275d35d 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
<> 135:176b8275d35d 373
<> 135:176b8275d35d 374 \return 0
<> 135:176b8275d35d 375 */
<> 135:176b8275d35d 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
<> 135:176b8275d35d 377 {
<> 135:176b8275d35d 378 if (page == PAGE_4k)
<> 135:176b8275d35d 379 {
<> 135:176b8275d35d 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
<> 135:176b8275d35d 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
<> 135:176b8275d35d 382 }
<> 135:176b8275d35d 383 else
<> 135:176b8275d35d 384 {
<> 135:176b8275d35d 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
<> 135:176b8275d35d 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
<> 135:176b8275d35d 387 }
<> 135:176b8275d35d 388 return 0;
<> 135:176b8275d35d 389 }
<> 135:176b8275d35d 390
<> 135:176b8275d35d 391 /** \brief Set 4k/64k page domain
<> 135:176b8275d35d 392
<> 135:176b8275d35d 393 The function sets 4k/64k page domain
<> 135:176b8275d35d 394
<> 135:176b8275d35d 395 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 396 \param [in] domain Page domain
<> 135:176b8275d35d 397
<> 135:176b8275d35d 398 \return 0
<> 135:176b8275d35d 399 */
<> 135:176b8275d35d 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
<> 135:176b8275d35d 401 {
<> 135:176b8275d35d 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
<> 135:176b8275d35d 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
<> 135:176b8275d35d 404 return 0;
<> 135:176b8275d35d 405 }
<> 135:176b8275d35d 406
<> 135:176b8275d35d 407 /** \brief Set 4k/64k page parity check
<> 135:176b8275d35d 408
<> 135:176b8275d35d 409 The function sets 4k/64k page parity check
<> 135:176b8275d35d 410
<> 135:176b8275d35d 411 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 135:176b8275d35d 413
<> 135:176b8275d35d 414 \return 0
<> 135:176b8275d35d 415 */
<> 135:176b8275d35d 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 135:176b8275d35d 417 {
<> 135:176b8275d35d 418 *descriptor_l1 &= SECTION_P_MASK;
<> 135:176b8275d35d 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 135:176b8275d35d 420 return 0;
<> 135:176b8275d35d 421 }
<> 135:176b8275d35d 422
<> 135:176b8275d35d 423 /** \brief Set 4k/64k page access privileges
<> 135:176b8275d35d 424
<> 135:176b8275d35d 425 The function sets 4k/64k page access privileges
<> 135:176b8275d35d 426
<> 135:176b8275d35d 427 \param [out] descriptor_l2 L2 descriptor.
<> 135:176b8275d35d 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 135:176b8275d35d 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 135:176b8275d35d 430 \param [in] afe Access flag enable
<> 135:176b8275d35d 431
<> 135:176b8275d35d 432 \return 0
<> 135:176b8275d35d 433 */
<> 135:176b8275d35d 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 135:176b8275d35d 435 {
<> 135:176b8275d35d 436 uint32_t ap = 0;
<> 135:176b8275d35d 437
<> 135:176b8275d35d 438 if (afe == 0) { //full access
<> 135:176b8275d35d 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 135:176b8275d35d 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 135:176b8275d35d 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 135:176b8275d35d 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 135:176b8275d35d 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 135:176b8275d35d 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
<> 135:176b8275d35d 445 }
<> 135:176b8275d35d 446
<> 135:176b8275d35d 447 else { //Simplified access
<> 135:176b8275d35d 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 135:176b8275d35d 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 135:176b8275d35d 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 135:176b8275d35d 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 135:176b8275d35d 452 }
<> 135:176b8275d35d 453
<> 135:176b8275d35d 454 *descriptor_l2 &= PAGE_AP_MASK;
<> 135:176b8275d35d 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
<> 135:176b8275d35d 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
<> 135:176b8275d35d 457
<> 135:176b8275d35d 458 return 0;
<> 135:176b8275d35d 459 }
<> 135:176b8275d35d 460
<> 135:176b8275d35d 461 /** \brief Set 4k/64k page shareability
<> 135:176b8275d35d 462
<> 135:176b8275d35d 463 The function sets 4k/64k page shareability
<> 135:176b8275d35d 464
<> 135:176b8275d35d 465 \param [out] descriptor_l2 L2 descriptor.
<> 135:176b8275d35d 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
<> 135:176b8275d35d 467
<> 135:176b8275d35d 468 \return 0
<> 135:176b8275d35d 469 */
<> 135:176b8275d35d 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
<> 135:176b8275d35d 471 {
<> 135:176b8275d35d 472 *descriptor_l2 &= PAGE_S_MASK;
<> 135:176b8275d35d 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
<> 135:176b8275d35d 474 return 0;
<> 135:176b8275d35d 475 }
<> 135:176b8275d35d 476
<> 135:176b8275d35d 477 /** \brief Set 4k/64k page Global attribute
<> 135:176b8275d35d 478
<> 135:176b8275d35d 479 The function sets 4k/64k page Global attribute
<> 135:176b8275d35d 480
<> 135:176b8275d35d 481 \param [out] descriptor_l2 L2 descriptor.
<> 135:176b8275d35d 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
<> 135:176b8275d35d 483
<> 135:176b8275d35d 484 \return 0
<> 135:176b8275d35d 485 */
<> 135:176b8275d35d 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
<> 135:176b8275d35d 487 {
<> 135:176b8275d35d 488 *descriptor_l2 &= PAGE_NG_MASK;
<> 135:176b8275d35d 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
<> 135:176b8275d35d 490 return 0;
<> 135:176b8275d35d 491 }
<> 135:176b8275d35d 492
<> 135:176b8275d35d 493 /** \brief Set 4k/64k page Security attribute
<> 135:176b8275d35d 494
<> 135:176b8275d35d 495 The function sets 4k/64k page Global attribute
<> 135:176b8275d35d 496
<> 135:176b8275d35d 497 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
<> 135:176b8275d35d 499
<> 135:176b8275d35d 500 \return 0
<> 135:176b8275d35d 501 */
<> 135:176b8275d35d 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 135:176b8275d35d 503 {
<> 135:176b8275d35d 504 *descriptor_l1 &= PAGE_NS_MASK;
<> 135:176b8275d35d 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
<> 135:176b8275d35d 506 return 0;
<> 135:176b8275d35d 507 }
<> 135:176b8275d35d 508
<> 135:176b8275d35d 509
<> 135:176b8275d35d 510 /** \brief Set Section memory attributes
<> 135:176b8275d35d 511
<> 135:176b8275d35d 512 The function sets section memory attributes
<> 135:176b8275d35d 513
<> 135:176b8275d35d 514 \param [out] descriptor_l1 L1 descriptor.
<> 135:176b8275d35d 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 135:176b8275d35d 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 135:176b8275d35d 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 135:176b8275d35d 518
<> 135:176b8275d35d 519 \return 0
<> 135:176b8275d35d 520 */
<> 135:176b8275d35d 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
<> 135:176b8275d35d 522 {
<> 135:176b8275d35d 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
<> 135:176b8275d35d 524
<> 135:176b8275d35d 525 if (STRONGLY_ORDERED == mem)
<> 135:176b8275d35d 526 {
<> 135:176b8275d35d 527 return 0;
<> 135:176b8275d35d 528 }
<> 135:176b8275d35d 529 else if (SHARED_DEVICE == mem)
<> 135:176b8275d35d 530 {
<> 135:176b8275d35d 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 135:176b8275d35d 532 }
<> 135:176b8275d35d 533 else if (NON_SHARED_DEVICE == mem)
<> 135:176b8275d35d 534 {
<> 135:176b8275d35d 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
<> 135:176b8275d35d 536 }
<> 135:176b8275d35d 537 else if (NORMAL == mem)
<> 135:176b8275d35d 538 {
<> 135:176b8275d35d 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
<> 135:176b8275d35d 540 switch(inner)
<> 135:176b8275d35d 541 {
<> 135:176b8275d35d 542 case NON_CACHEABLE:
<> 135:176b8275d35d 543 break;
<> 135:176b8275d35d 544 case WB_WA:
<> 135:176b8275d35d 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 135:176b8275d35d 546 break;
<> 135:176b8275d35d 547 case WT:
<> 135:176b8275d35d 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
<> 135:176b8275d35d 549 break;
<> 135:176b8275d35d 550 case WB_NO_WA:
<> 135:176b8275d35d 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
<> 135:176b8275d35d 552 break;
<> 135:176b8275d35d 553 }
<> 135:176b8275d35d 554 switch(outer)
<> 135:176b8275d35d 555 {
<> 135:176b8275d35d 556 case NON_CACHEABLE:
<> 135:176b8275d35d 557 break;
<> 135:176b8275d35d 558 case WB_WA:
<> 135:176b8275d35d 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
<> 135:176b8275d35d 560 break;
<> 135:176b8275d35d 561 case WT:
<> 135:176b8275d35d 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
<> 135:176b8275d35d 563 break;
<> 135:176b8275d35d 564 case WB_NO_WA:
<> 135:176b8275d35d 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
<> 135:176b8275d35d 566 break;
<> 135:176b8275d35d 567 }
<> 135:176b8275d35d 568 }
<> 135:176b8275d35d 569
<> 135:176b8275d35d 570 return 0;
<> 135:176b8275d35d 571 }
<> 135:176b8275d35d 572
<> 135:176b8275d35d 573 /** \brief Set 4k/64k page memory attributes
<> 135:176b8275d35d 574
<> 135:176b8275d35d 575 The function sets 4k/64k page memory attributes
<> 135:176b8275d35d 576
<> 135:176b8275d35d 577 \param [out] descriptor_l2 L2 descriptor.
<> 135:176b8275d35d 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 135:176b8275d35d 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 135:176b8275d35d 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 135:176b8275d35d 581
<> 135:176b8275d35d 582 \return 0
<> 135:176b8275d35d 583 */
<> 135:176b8275d35d 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
<> 135:176b8275d35d 585 {
<> 135:176b8275d35d 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
<> 135:176b8275d35d 587
<> 135:176b8275d35d 588 if (page == PAGE_64k)
<> 135:176b8275d35d 589 {
<> 135:176b8275d35d 590 //same as section
<> 135:176b8275d35d 591 __memory_section(descriptor_l2, mem, outer, inner);
<> 135:176b8275d35d 592 }
<> 135:176b8275d35d 593 else
<> 135:176b8275d35d 594 {
<> 135:176b8275d35d 595 if (STRONGLY_ORDERED == mem)
<> 135:176b8275d35d 596 {
<> 135:176b8275d35d 597 return 0;
<> 135:176b8275d35d 598 }
<> 135:176b8275d35d 599 else if (SHARED_DEVICE == mem)
<> 135:176b8275d35d 600 {
<> 135:176b8275d35d 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 135:176b8275d35d 602 }
<> 135:176b8275d35d 603 else if (NON_SHARED_DEVICE == mem)
<> 135:176b8275d35d 604 {
<> 135:176b8275d35d 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
<> 135:176b8275d35d 606 }
<> 135:176b8275d35d 607 else if (NORMAL == mem)
<> 135:176b8275d35d 608 {
<> 135:176b8275d35d 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
<> 135:176b8275d35d 610 switch(inner)
<> 135:176b8275d35d 611 {
<> 135:176b8275d35d 612 case NON_CACHEABLE:
<> 135:176b8275d35d 613 break;
<> 135:176b8275d35d 614 case WB_WA:
<> 135:176b8275d35d 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 135:176b8275d35d 616 break;
<> 135:176b8275d35d 617 case WT:
<> 135:176b8275d35d 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
<> 135:176b8275d35d 619 break;
<> 135:176b8275d35d 620 case WB_NO_WA:
<> 135:176b8275d35d 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
<> 135:176b8275d35d 622 break;
<> 135:176b8275d35d 623 }
<> 135:176b8275d35d 624 switch(outer)
<> 135:176b8275d35d 625 {
<> 135:176b8275d35d 626 case NON_CACHEABLE:
<> 135:176b8275d35d 627 break;
<> 135:176b8275d35d 628 case WB_WA:
<> 135:176b8275d35d 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
<> 135:176b8275d35d 630 break;
<> 135:176b8275d35d 631 case WT:
<> 135:176b8275d35d 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
<> 135:176b8275d35d 633 break;
<> 135:176b8275d35d 634 case WB_NO_WA:
<> 135:176b8275d35d 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
<> 135:176b8275d35d 636 break;
<> 135:176b8275d35d 637 }
<> 135:176b8275d35d 638 }
<> 135:176b8275d35d 639 }
<> 135:176b8275d35d 640
<> 135:176b8275d35d 641 return 0;
<> 135:176b8275d35d 642 }
<> 135:176b8275d35d 643
<> 135:176b8275d35d 644 /** \brief Create a L1 section descriptor
<> 135:176b8275d35d 645
<> 135:176b8275d35d 646 The function creates a section descriptor.
<> 135:176b8275d35d 647
<> 135:176b8275d35d 648 Assumptions:
<> 135:176b8275d35d 649 - 16MB super sections not supported
<> 135:176b8275d35d 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 135:176b8275d35d 651 - Functions always return 0
<> 135:176b8275d35d 652
<> 135:176b8275d35d 653 \param [out] descriptor L1 descriptor
<> 135:176b8275d35d 654 \param [out] descriptor2 L2 descriptor
<> 135:176b8275d35d 655 \param [in] reg Section attributes
<> 135:176b8275d35d 656
<> 135:176b8275d35d 657 \return 0
<> 135:176b8275d35d 658 */
<> 135:176b8275d35d 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
<> 135:176b8275d35d 660 {
<> 135:176b8275d35d 661 *descriptor = 0;
<> 135:176b8275d35d 662
<> 135:176b8275d35d 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
<> 135:176b8275d35d 664 __xn_section(descriptor,reg.xn_t);
<> 135:176b8275d35d 665 __domain_section(descriptor, reg.domain);
<> 135:176b8275d35d 666 __p_section(descriptor, reg.e_t);
<> 135:176b8275d35d 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
<> 135:176b8275d35d 668 __shared_section(descriptor,reg.sh_t);
<> 135:176b8275d35d 669 __global_section(descriptor,reg.g_t);
<> 135:176b8275d35d 670 __secure_section(descriptor,reg.sec_t);
<> 135:176b8275d35d 671 *descriptor &= SECTION_MASK;
<> 135:176b8275d35d 672 *descriptor |= SECTION_DESCRIPTOR;
<> 135:176b8275d35d 673
<> 135:176b8275d35d 674 return 0;
<> 135:176b8275d35d 675
<> 135:176b8275d35d 676 }
<> 135:176b8275d35d 677
<> 135:176b8275d35d 678
<> 135:176b8275d35d 679 /** \brief Create a L1 and L2 4k/64k page descriptor
<> 135:176b8275d35d 680
<> 135:176b8275d35d 681 The function creates a 4k/64k page descriptor.
<> 135:176b8275d35d 682 Assumptions:
<> 135:176b8275d35d 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 135:176b8275d35d 684 - Functions always return 0
<> 135:176b8275d35d 685
<> 135:176b8275d35d 686 \param [out] descriptor L1 descriptor
<> 135:176b8275d35d 687 \param [out] descriptor2 L2 descriptor
<> 135:176b8275d35d 688 \param [in] reg 4k/64k page attributes
<> 135:176b8275d35d 689
<> 135:176b8275d35d 690 \return 0
<> 135:176b8275d35d 691 */
<> 135:176b8275d35d 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
<> 135:176b8275d35d 693 {
<> 135:176b8275d35d 694 *descriptor = 0;
<> 135:176b8275d35d 695 *descriptor2 = 0;
<> 135:176b8275d35d 696
<> 135:176b8275d35d 697 switch (reg.rg_t)
<> 135:176b8275d35d 698 {
<> 135:176b8275d35d 699 case PAGE_4k:
<> 135:176b8275d35d 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
<> 135:176b8275d35d 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
<> 135:176b8275d35d 702 __domain_page(descriptor, reg.domain);
<> 135:176b8275d35d 703 __p_page(descriptor, reg.e_t);
<> 135:176b8275d35d 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 135:176b8275d35d 705 __shared_page(descriptor2,reg.sh_t);
<> 135:176b8275d35d 706 __global_page(descriptor2,reg.g_t);
<> 135:176b8275d35d 707 __secure_page(descriptor,reg.sec_t);
<> 135:176b8275d35d 708 *descriptor &= PAGE_L1_MASK;
<> 135:176b8275d35d 709 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 135:176b8275d35d 710 *descriptor2 &= PAGE_L2_4K_MASK;
<> 135:176b8275d35d 711 *descriptor2 |= PAGE_L2_4K_DESC;
<> 135:176b8275d35d 712 break;
<> 135:176b8275d35d 713
<> 135:176b8275d35d 714 case PAGE_64k:
<> 135:176b8275d35d 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
<> 135:176b8275d35d 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
<> 135:176b8275d35d 717 __domain_page(descriptor, reg.domain);
<> 135:176b8275d35d 718 __p_page(descriptor, reg.e_t);
<> 135:176b8275d35d 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 135:176b8275d35d 720 __shared_page(descriptor2,reg.sh_t);
<> 135:176b8275d35d 721 __global_page(descriptor2,reg.g_t);
<> 135:176b8275d35d 722 __secure_page(descriptor,reg.sec_t);
<> 135:176b8275d35d 723 *descriptor &= PAGE_L1_MASK;
<> 135:176b8275d35d 724 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 135:176b8275d35d 725 *descriptor2 &= PAGE_L2_64K_MASK;
<> 135:176b8275d35d 726 *descriptor2 |= PAGE_L2_64K_DESC;
<> 135:176b8275d35d 727 break;
<> 135:176b8275d35d 728
<> 135:176b8275d35d 729 case SECTION:
<> 135:176b8275d35d 730 //error
<> 135:176b8275d35d 731 break;
<> 135:176b8275d35d 732
<> 135:176b8275d35d 733 }
<> 135:176b8275d35d 734
<> 135:176b8275d35d 735 return 0;
<> 135:176b8275d35d 736
<> 135:176b8275d35d 737 }
<> 135:176b8275d35d 738
<> 135:176b8275d35d 739 /** \brief Create a 1MB Section
<> 135:176b8275d35d 740
<> 135:176b8275d35d 741 \param [in] ttb Translation table base address
<> 135:176b8275d35d 742 \param [in] base_address Section base address
<> 135:176b8275d35d 743 \param [in] count Number of sections to create
<> 135:176b8275d35d 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 135:176b8275d35d 745
<> 135:176b8275d35d 746 */
<> 135:176b8275d35d 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
<> 135:176b8275d35d 748 {
<> 135:176b8275d35d 749 uint32_t offset;
<> 135:176b8275d35d 750 uint32_t entry;
<> 135:176b8275d35d 751 uint32_t i;
<> 135:176b8275d35d 752
<> 135:176b8275d35d 753 offset = base_address >> 20;
<> 135:176b8275d35d 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
<> 135:176b8275d35d 755
<> 135:176b8275d35d 756 //4 bytes aligned
<> 135:176b8275d35d 757 ttb = ttb + offset;
<> 135:176b8275d35d 758
<> 135:176b8275d35d 759 for (i = 0; i < count; i++ )
<> 135:176b8275d35d 760 {
<> 135:176b8275d35d 761 //4 bytes aligned
<> 135:176b8275d35d 762 *ttb++ = entry;
<> 135:176b8275d35d 763 entry += OFFSET_1M;
<> 135:176b8275d35d 764 }
<> 135:176b8275d35d 765 }
<> 135:176b8275d35d 766
<> 135:176b8275d35d 767 /** \brief Create a 4k page entry
<> 135:176b8275d35d 768
<> 135:176b8275d35d 769 \param [in] ttb L1 table base address
<> 135:176b8275d35d 770 \param [in] base_address 4k base address
<> 135:176b8275d35d 771 \param [in] count Number of 4k pages to create
<> 135:176b8275d35d 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 135:176b8275d35d 773 \param [in] ttb_l2 L2 table base address
<> 135:176b8275d35d 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 135:176b8275d35d 775
<> 135:176b8275d35d 776 */
<> 135:176b8275d35d 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 135:176b8275d35d 778 {
<> 135:176b8275d35d 779
<> 135:176b8275d35d 780 uint32_t offset, offset2;
<> 135:176b8275d35d 781 uint32_t entry, entry2;
<> 135:176b8275d35d 782 uint32_t i;
<> 135:176b8275d35d 783
<> 135:176b8275d35d 784
<> 135:176b8275d35d 785 offset = base_address >> 20;
<> 135:176b8275d35d 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 135:176b8275d35d 787
<> 135:176b8275d35d 788 //4 bytes aligned
<> 135:176b8275d35d 789 ttb += offset;
<> 135:176b8275d35d 790 //create l1_entry
<> 135:176b8275d35d 791 *ttb = entry;
<> 135:176b8275d35d 792
<> 135:176b8275d35d 793 offset2 = (base_address & 0xff000) >> 12;
<> 135:176b8275d35d 794 ttb_l2 += offset2;
<> 135:176b8275d35d 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
<> 135:176b8275d35d 796 for (i = 0; i < count; i++ )
<> 135:176b8275d35d 797 {
<> 135:176b8275d35d 798 //4 bytes aligned
<> 135:176b8275d35d 799 *ttb_l2++ = entry2;
<> 135:176b8275d35d 800 entry2 += OFFSET_4K;
<> 135:176b8275d35d 801 }
<> 135:176b8275d35d 802 }
<> 135:176b8275d35d 803
<> 135:176b8275d35d 804 /** \brief Create a 64k page entry
<> 135:176b8275d35d 805
<> 135:176b8275d35d 806 \param [in] ttb L1 table base address
<> 135:176b8275d35d 807 \param [in] base_address 64k base address
<> 135:176b8275d35d 808 \param [in] count Number of 64k pages to create
<> 135:176b8275d35d 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 135:176b8275d35d 810 \param [in] ttb_l2 L2 table base address
<> 135:176b8275d35d 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 135:176b8275d35d 812
<> 135:176b8275d35d 813 */
<> 135:176b8275d35d 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 135:176b8275d35d 815 {
<> 135:176b8275d35d 816 uint32_t offset, offset2;
<> 135:176b8275d35d 817 uint32_t entry, entry2;
<> 135:176b8275d35d 818 uint32_t i,j;
<> 135:176b8275d35d 819
<> 135:176b8275d35d 820
<> 135:176b8275d35d 821 offset = base_address >> 20;
<> 135:176b8275d35d 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 135:176b8275d35d 823
<> 135:176b8275d35d 824 //4 bytes aligned
<> 135:176b8275d35d 825 ttb += offset;
<> 135:176b8275d35d 826 //create l1_entry
<> 135:176b8275d35d 827 *ttb = entry;
<> 135:176b8275d35d 828
<> 135:176b8275d35d 829 offset2 = (base_address & 0xff000) >> 12;
<> 135:176b8275d35d 830 ttb_l2 += offset2;
<> 135:176b8275d35d 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
<> 135:176b8275d35d 832 for (i = 0; i < count; i++ )
<> 135:176b8275d35d 833 {
<> 135:176b8275d35d 834 //create 16 entries
<> 135:176b8275d35d 835 for (j = 0; j < 16; j++)
<> 135:176b8275d35d 836 //4 bytes aligned
<> 135:176b8275d35d 837 *ttb_l2++ = entry2;
<> 135:176b8275d35d 838 entry2 += OFFSET_64K;
<> 135:176b8275d35d 839 }
<> 135:176b8275d35d 840 }
<> 135:176b8275d35d 841
<> 135:176b8275d35d 842 /*@} end of MMU_Functions */
<> 135:176b8275d35d 843 #endif
<> 135:176b8275d35d 844
<> 135:176b8275d35d 845 #ifdef __cplusplus
<> 135:176b8275d35d 846 }
<> 135:176b8275d35d 847 #endif