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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_caFunc.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**************************************************************************//**
<> 135:176b8275d35d 2 * @file core_caFunc.h
<> 135:176b8275d35d 3 * @brief CMSIS Cortex-A Core Function Access Header File
<> 135:176b8275d35d 4 * @version V3.10
<> 135:176b8275d35d 5 * @date 30 Oct 2013
<> 135:176b8275d35d 6 *
<> 135:176b8275d35d 7 * @note
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 ******************************************************************************/
<> 135:176b8275d35d 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
<> 135:176b8275d35d 11
<> 135:176b8275d35d 12 All rights reserved.
<> 135:176b8275d35d 13 Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 specific prior written permission.
<> 135:176b8275d35d 23 *
<> 135:176b8275d35d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37
<> 135:176b8275d35d 38 #ifndef __CORE_CAFUNC_H__
<> 135:176b8275d35d 39 #define __CORE_CAFUNC_H__
<> 135:176b8275d35d 40
<> 135:176b8275d35d 41
<> 135:176b8275d35d 42 /* ########################### Core Function Access ########################### */
<> 135:176b8275d35d 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 135:176b8275d35d 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 135:176b8275d35d 45 @{
<> 135:176b8275d35d 46 */
<> 135:176b8275d35d 47
<> 135:176b8275d35d 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 135:176b8275d35d 49 /* ARM armcc specific functions */
<> 135:176b8275d35d 50
<> 135:176b8275d35d 51 #if (__ARMCC_VERSION < 400677)
<> 135:176b8275d35d 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 135:176b8275d35d 53 #endif
<> 135:176b8275d35d 54
<> 135:176b8275d35d 55 #define MODE_USR 0x10
<> 135:176b8275d35d 56 #define MODE_FIQ 0x11
<> 135:176b8275d35d 57 #define MODE_IRQ 0x12
<> 135:176b8275d35d 58 #define MODE_SVC 0x13
<> 135:176b8275d35d 59 #define MODE_MON 0x16
<> 135:176b8275d35d 60 #define MODE_ABT 0x17
<> 135:176b8275d35d 61 #define MODE_HYP 0x1A
<> 135:176b8275d35d 62 #define MODE_UND 0x1B
<> 135:176b8275d35d 63 #define MODE_SYS 0x1F
<> 135:176b8275d35d 64
<> 135:176b8275d35d 65 /** \brief Get APSR Register
<> 135:176b8275d35d 66
<> 135:176b8275d35d 67 This function returns the content of the APSR Register.
<> 135:176b8275d35d 68
<> 135:176b8275d35d 69 \return APSR Register value
<> 135:176b8275d35d 70 */
<> 135:176b8275d35d 71 __STATIC_INLINE uint32_t __get_APSR(void)
<> 135:176b8275d35d 72 {
<> 135:176b8275d35d 73 register uint32_t __regAPSR __ASM("apsr");
<> 135:176b8275d35d 74 return(__regAPSR);
<> 135:176b8275d35d 75 }
<> 135:176b8275d35d 76
<> 135:176b8275d35d 77
<> 135:176b8275d35d 78 /** \brief Get CPSR Register
<> 135:176b8275d35d 79
<> 135:176b8275d35d 80 This function returns the content of the CPSR Register.
<> 135:176b8275d35d 81
<> 135:176b8275d35d 82 \return CPSR Register value
<> 135:176b8275d35d 83 */
<> 135:176b8275d35d 84 __STATIC_INLINE uint32_t __get_CPSR(void)
<> 135:176b8275d35d 85 {
<> 135:176b8275d35d 86 register uint32_t __regCPSR __ASM("cpsr");
<> 135:176b8275d35d 87 return(__regCPSR);
<> 135:176b8275d35d 88 }
<> 135:176b8275d35d 89
<> 135:176b8275d35d 90 /** \brief Set Stack Pointer
<> 135:176b8275d35d 91
<> 135:176b8275d35d 92 This function assigns the given value to the current stack pointer.
<> 135:176b8275d35d 93
<> 135:176b8275d35d 94 \param [in] topOfStack Stack Pointer value to set
<> 135:176b8275d35d 95 */
<> 135:176b8275d35d 96 register uint32_t __regSP __ASM("sp");
<> 135:176b8275d35d 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
<> 135:176b8275d35d 98 {
<> 135:176b8275d35d 99 __regSP = topOfStack;
<> 135:176b8275d35d 100 }
<> 135:176b8275d35d 101
<> 135:176b8275d35d 102
<> 135:176b8275d35d 103 /** \brief Get link register
<> 135:176b8275d35d 104
<> 135:176b8275d35d 105 This function returns the value of the link register
<> 135:176b8275d35d 106
<> 135:176b8275d35d 107 \return Value of link register
<> 135:176b8275d35d 108 */
<> 135:176b8275d35d 109 register uint32_t __reglr __ASM("lr");
<> 135:176b8275d35d 110 __STATIC_INLINE uint32_t __get_LR(void)
<> 135:176b8275d35d 111 {
<> 135:176b8275d35d 112 return(__reglr);
<> 135:176b8275d35d 113 }
<> 135:176b8275d35d 114
<> 135:176b8275d35d 115 /** \brief Set link register
<> 135:176b8275d35d 116
<> 135:176b8275d35d 117 This function sets the value of the link register
<> 135:176b8275d35d 118
<> 135:176b8275d35d 119 \param [in] lr LR value to set
<> 135:176b8275d35d 120 */
<> 135:176b8275d35d 121 __STATIC_INLINE void __set_LR(uint32_t lr)
<> 135:176b8275d35d 122 {
<> 135:176b8275d35d 123 __reglr = lr;
<> 135:176b8275d35d 124 }
<> 135:176b8275d35d 125
<> 135:176b8275d35d 126 /** \brief Set Process Stack Pointer
<> 135:176b8275d35d 127
<> 135:176b8275d35d 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 135:176b8275d35d 129
<> 135:176b8275d35d 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 135:176b8275d35d 131 */
<> 135:176b8275d35d 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
<> 135:176b8275d35d 133 {
<> 135:176b8275d35d 134 ARM
<> 135:176b8275d35d 135 PRESERVE8
<> 135:176b8275d35d 136
<> 135:176b8275d35d 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
<> 135:176b8275d35d 138 MRS R1, CPSR
<> 135:176b8275d35d 139 CPS #MODE_SYS ;no effect in USR mode
<> 135:176b8275d35d 140 MOV SP, R0
<> 135:176b8275d35d 141 MSR CPSR_c, R1 ;no effect in USR mode
<> 135:176b8275d35d 142 ISB
<> 135:176b8275d35d 143 BX LR
<> 135:176b8275d35d 144
<> 135:176b8275d35d 145 }
<> 135:176b8275d35d 146
<> 135:176b8275d35d 147 /** \brief Set User Mode
<> 135:176b8275d35d 148
<> 135:176b8275d35d 149 This function changes the processor state to User Mode
<> 135:176b8275d35d 150 */
<> 135:176b8275d35d 151 __STATIC_ASM void __set_CPS_USR(void)
<> 135:176b8275d35d 152 {
<> 135:176b8275d35d 153 ARM
<> 135:176b8275d35d 154
<> 135:176b8275d35d 155 CPS #MODE_USR
<> 135:176b8275d35d 156 BX LR
<> 135:176b8275d35d 157 }
<> 135:176b8275d35d 158
<> 135:176b8275d35d 159
<> 135:176b8275d35d 160 /** \brief Enable FIQ
<> 135:176b8275d35d 161
<> 135:176b8275d35d 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 135:176b8275d35d 163 Can only be executed in Privileged modes.
<> 135:176b8275d35d 164 */
<> 135:176b8275d35d 165 #define __enable_fault_irq __enable_fiq
<> 135:176b8275d35d 166
<> 135:176b8275d35d 167
<> 135:176b8275d35d 168 /** \brief Disable FIQ
<> 135:176b8275d35d 169
<> 135:176b8275d35d 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 135:176b8275d35d 171 Can only be executed in Privileged modes.
<> 135:176b8275d35d 172 */
<> 135:176b8275d35d 173 #define __disable_fault_irq __disable_fiq
<> 135:176b8275d35d 174
<> 135:176b8275d35d 175
<> 135:176b8275d35d 176 /** \brief Get FPSCR
<> 135:176b8275d35d 177
<> 135:176b8275d35d 178 This function returns the current value of the Floating Point Status/Control register.
<> 135:176b8275d35d 179
<> 135:176b8275d35d 180 \return Floating Point Status/Control register value
<> 135:176b8275d35d 181 */
<> 135:176b8275d35d 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 135:176b8275d35d 183 {
<> 135:176b8275d35d 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 185 register uint32_t __regfpscr __ASM("fpscr");
<> 135:176b8275d35d 186 return(__regfpscr);
<> 135:176b8275d35d 187 #else
<> 135:176b8275d35d 188 return(0);
<> 135:176b8275d35d 189 #endif
<> 135:176b8275d35d 190 }
<> 135:176b8275d35d 191
<> 135:176b8275d35d 192
<> 135:176b8275d35d 193 /** \brief Set FPSCR
<> 135:176b8275d35d 194
<> 135:176b8275d35d 195 This function assigns the given value to the Floating Point Status/Control register.
<> 135:176b8275d35d 196
<> 135:176b8275d35d 197 \param [in] fpscr Floating Point Status/Control value to set
<> 135:176b8275d35d 198 */
<> 135:176b8275d35d 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 135:176b8275d35d 200 {
<> 135:176b8275d35d 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 202 register uint32_t __regfpscr __ASM("fpscr");
<> 135:176b8275d35d 203 __regfpscr = (fpscr);
<> 135:176b8275d35d 204 #endif
<> 135:176b8275d35d 205 }
<> 135:176b8275d35d 206
<> 135:176b8275d35d 207 /** \brief Get FPEXC
<> 135:176b8275d35d 208
<> 135:176b8275d35d 209 This function returns the current value of the Floating Point Exception Control register.
<> 135:176b8275d35d 210
<> 135:176b8275d35d 211 \return Floating Point Exception Control register value
<> 135:176b8275d35d 212 */
<> 135:176b8275d35d 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
<> 135:176b8275d35d 214 {
<> 135:176b8275d35d 215 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 216 register uint32_t __regfpexc __ASM("fpexc");
<> 135:176b8275d35d 217 return(__regfpexc);
<> 135:176b8275d35d 218 #else
<> 135:176b8275d35d 219 return(0);
<> 135:176b8275d35d 220 #endif
<> 135:176b8275d35d 221 }
<> 135:176b8275d35d 222
<> 135:176b8275d35d 223
<> 135:176b8275d35d 224 /** \brief Set FPEXC
<> 135:176b8275d35d 225
<> 135:176b8275d35d 226 This function assigns the given value to the Floating Point Exception Control register.
<> 135:176b8275d35d 227
<> 135:176b8275d35d 228 \param [in] fpscr Floating Point Exception Control value to set
<> 135:176b8275d35d 229 */
<> 135:176b8275d35d 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
<> 135:176b8275d35d 231 {
<> 135:176b8275d35d 232 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 233 register uint32_t __regfpexc __ASM("fpexc");
<> 135:176b8275d35d 234 __regfpexc = (fpexc);
<> 135:176b8275d35d 235 #endif
<> 135:176b8275d35d 236 }
<> 135:176b8275d35d 237
<> 135:176b8275d35d 238 /** \brief Get CPACR
<> 135:176b8275d35d 239
<> 135:176b8275d35d 240 This function returns the current value of the Coprocessor Access Control register.
<> 135:176b8275d35d 241
<> 135:176b8275d35d 242 \return Coprocessor Access Control register value
<> 135:176b8275d35d 243 */
<> 135:176b8275d35d 244 __STATIC_INLINE uint32_t __get_CPACR(void)
<> 135:176b8275d35d 245 {
<> 135:176b8275d35d 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 135:176b8275d35d 247 return __regCPACR;
<> 135:176b8275d35d 248 }
<> 135:176b8275d35d 249
<> 135:176b8275d35d 250 /** \brief Set CPACR
<> 135:176b8275d35d 251
<> 135:176b8275d35d 252 This function assigns the given value to the Coprocessor Access Control register.
<> 135:176b8275d35d 253
<> 135:176b8275d35d 254 \param [in] cpacr Coprocessor Acccess Control value to set
<> 135:176b8275d35d 255 */
<> 135:176b8275d35d 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
<> 135:176b8275d35d 257 {
<> 135:176b8275d35d 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 135:176b8275d35d 259 __regCPACR = cpacr;
<> 135:176b8275d35d 260 __ISB();
<> 135:176b8275d35d 261 }
<> 135:176b8275d35d 262
<> 135:176b8275d35d 263 /** \brief Get CBAR
<> 135:176b8275d35d 264
<> 135:176b8275d35d 265 This function returns the value of the Configuration Base Address register.
<> 135:176b8275d35d 266
<> 135:176b8275d35d 267 \return Configuration Base Address register value
<> 135:176b8275d35d 268 */
<> 135:176b8275d35d 269 __STATIC_INLINE uint32_t __get_CBAR() {
<> 135:176b8275d35d 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
<> 135:176b8275d35d 271 return(__regCBAR);
<> 135:176b8275d35d 272 }
<> 135:176b8275d35d 273
<> 135:176b8275d35d 274 /** \brief Get TTBR0
<> 135:176b8275d35d 275
<> 135:176b8275d35d 276 This function returns the value of the Translation Table Base Register 0.
<> 135:176b8275d35d 277
<> 135:176b8275d35d 278 \return Translation Table Base Register 0 value
<> 135:176b8275d35d 279 */
<> 135:176b8275d35d 280 __STATIC_INLINE uint32_t __get_TTBR0() {
<> 135:176b8275d35d 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 135:176b8275d35d 282 return(__regTTBR0);
<> 135:176b8275d35d 283 }
<> 135:176b8275d35d 284
<> 135:176b8275d35d 285 /** \brief Set TTBR0
<> 135:176b8275d35d 286
<> 135:176b8275d35d 287 This function assigns the given value to the Translation Table Base Register 0.
<> 135:176b8275d35d 288
<> 135:176b8275d35d 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 135:176b8275d35d 290 */
<> 135:176b8275d35d 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 135:176b8275d35d 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 135:176b8275d35d 293 __regTTBR0 = ttbr0;
<> 135:176b8275d35d 294 __ISB();
<> 135:176b8275d35d 295 }
<> 135:176b8275d35d 296
<> 135:176b8275d35d 297 /** \brief Get DACR
<> 135:176b8275d35d 298
<> 135:176b8275d35d 299 This function returns the value of the Domain Access Control Register.
<> 135:176b8275d35d 300
<> 135:176b8275d35d 301 \return Domain Access Control Register value
<> 135:176b8275d35d 302 */
<> 135:176b8275d35d 303 __STATIC_INLINE uint32_t __get_DACR() {
<> 135:176b8275d35d 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 135:176b8275d35d 305 return(__regDACR);
<> 135:176b8275d35d 306 }
<> 135:176b8275d35d 307
<> 135:176b8275d35d 308 /** \brief Set DACR
<> 135:176b8275d35d 309
<> 135:176b8275d35d 310 This function assigns the given value to the Domain Access Control Register.
<> 135:176b8275d35d 311
<> 135:176b8275d35d 312 \param [in] dacr Domain Access Control Register value to set
<> 135:176b8275d35d 313 */
<> 135:176b8275d35d 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 135:176b8275d35d 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 135:176b8275d35d 316 __regDACR = dacr;
<> 135:176b8275d35d 317 __ISB();
<> 135:176b8275d35d 318 }
<> 135:176b8275d35d 319
<> 135:176b8275d35d 320 /******************************** Cache and BTAC enable ****************************************************/
<> 135:176b8275d35d 321
<> 135:176b8275d35d 322 /** \brief Set SCTLR
<> 135:176b8275d35d 323
<> 135:176b8275d35d 324 This function assigns the given value to the System Control Register.
<> 135:176b8275d35d 325
<> 135:176b8275d35d 326 \param [in] sctlr System Control Register value to set
<> 135:176b8275d35d 327 */
<> 135:176b8275d35d 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
<> 135:176b8275d35d 329 {
<> 135:176b8275d35d 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 135:176b8275d35d 331 __regSCTLR = sctlr;
<> 135:176b8275d35d 332 }
<> 135:176b8275d35d 333
<> 135:176b8275d35d 334 /** \brief Get SCTLR
<> 135:176b8275d35d 335
<> 135:176b8275d35d 336 This function returns the value of the System Control Register.
<> 135:176b8275d35d 337
<> 135:176b8275d35d 338 \return System Control Register value
<> 135:176b8275d35d 339 */
<> 135:176b8275d35d 340 __STATIC_INLINE uint32_t __get_SCTLR() {
<> 135:176b8275d35d 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 135:176b8275d35d 342 return(__regSCTLR);
<> 135:176b8275d35d 343 }
<> 135:176b8275d35d 344
<> 135:176b8275d35d 345 /** \brief Enable Caches
<> 135:176b8275d35d 346
<> 135:176b8275d35d 347 Enable Caches
<> 135:176b8275d35d 348 */
<> 135:176b8275d35d 349 __STATIC_INLINE void __enable_caches(void) {
<> 135:176b8275d35d 350 // Set I bit 12 to enable I Cache
<> 135:176b8275d35d 351 // Set C bit 2 to enable D Cache
<> 135:176b8275d35d 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 135:176b8275d35d 353 }
<> 135:176b8275d35d 354
<> 135:176b8275d35d 355 /** \brief Disable Caches
<> 135:176b8275d35d 356
<> 135:176b8275d35d 357 Disable Caches
<> 135:176b8275d35d 358 */
<> 135:176b8275d35d 359 __STATIC_INLINE void __disable_caches(void) {
<> 135:176b8275d35d 360 // Clear I bit 12 to disable I Cache
<> 135:176b8275d35d 361 // Clear C bit 2 to disable D Cache
<> 135:176b8275d35d 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
<> 135:176b8275d35d 363 __ISB();
<> 135:176b8275d35d 364 }
<> 135:176b8275d35d 365
<> 135:176b8275d35d 366 /** \brief Enable BTAC
<> 135:176b8275d35d 367
<> 135:176b8275d35d 368 Enable BTAC
<> 135:176b8275d35d 369 */
<> 135:176b8275d35d 370 __STATIC_INLINE void __enable_btac(void) {
<> 135:176b8275d35d 371 // Set Z bit 11 to enable branch prediction
<> 135:176b8275d35d 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 135:176b8275d35d 373 __ISB();
<> 135:176b8275d35d 374 }
<> 135:176b8275d35d 375
<> 135:176b8275d35d 376 /** \brief Disable BTAC
<> 135:176b8275d35d 377
<> 135:176b8275d35d 378 Disable BTAC
<> 135:176b8275d35d 379 */
<> 135:176b8275d35d 380 __STATIC_INLINE void __disable_btac(void) {
<> 135:176b8275d35d 381 // Clear Z bit 11 to disable branch prediction
<> 135:176b8275d35d 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
<> 135:176b8275d35d 383 }
<> 135:176b8275d35d 384
<> 135:176b8275d35d 385
<> 135:176b8275d35d 386 /** \brief Enable MMU
<> 135:176b8275d35d 387
<> 135:176b8275d35d 388 Enable MMU
<> 135:176b8275d35d 389 */
<> 135:176b8275d35d 390 __STATIC_INLINE void __enable_mmu(void) {
<> 135:176b8275d35d 391 // Set M bit 0 to enable the MMU
<> 135:176b8275d35d 392 // Set AFE bit to enable simplified access permissions model
<> 135:176b8275d35d 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 135:176b8275d35d 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 135:176b8275d35d 395 __ISB();
<> 135:176b8275d35d 396 }
<> 135:176b8275d35d 397
<> 135:176b8275d35d 398 /** \brief Disable MMU
<> 135:176b8275d35d 399
<> 135:176b8275d35d 400 Disable MMU
<> 135:176b8275d35d 401 */
<> 135:176b8275d35d 402 __STATIC_INLINE void __disable_mmu(void) {
<> 135:176b8275d35d 403 // Clear M bit 0 to disable the MMU
<> 135:176b8275d35d 404 __set_SCTLR( __get_SCTLR() & ~1);
<> 135:176b8275d35d 405 __ISB();
<> 135:176b8275d35d 406 }
<> 135:176b8275d35d 407
<> 135:176b8275d35d 408 /******************************** TLB maintenance operations ************************************************/
<> 135:176b8275d35d 409 /** \brief Invalidate the whole tlb
<> 135:176b8275d35d 410
<> 135:176b8275d35d 411 TLBIALL. Invalidate the whole tlb
<> 135:176b8275d35d 412 */
<> 135:176b8275d35d 413
<> 135:176b8275d35d 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 135:176b8275d35d 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
<> 135:176b8275d35d 416 __TLBIALL = 0;
<> 135:176b8275d35d 417 __DSB();
<> 135:176b8275d35d 418 __ISB();
<> 135:176b8275d35d 419 }
<> 135:176b8275d35d 420
<> 135:176b8275d35d 421 /******************************** BTB maintenance operations ************************************************/
<> 135:176b8275d35d 422 /** \brief Invalidate entire branch predictor array
<> 135:176b8275d35d 423
<> 135:176b8275d35d 424 BPIALL. Branch Predictor Invalidate All.
<> 135:176b8275d35d 425 */
<> 135:176b8275d35d 426
<> 135:176b8275d35d 427 __STATIC_INLINE void __v7_inv_btac(void) {
<> 135:176b8275d35d 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
<> 135:176b8275d35d 429 __BPIALL = 0;
<> 135:176b8275d35d 430 __DSB(); //ensure completion of the invalidation
<> 135:176b8275d35d 431 __ISB(); //ensure instruction fetch path sees new state
<> 135:176b8275d35d 432 }
<> 135:176b8275d35d 433
<> 135:176b8275d35d 434
<> 135:176b8275d35d 435 /******************************** L1 cache operations ******************************************************/
<> 135:176b8275d35d 436
<> 135:176b8275d35d 437 /** \brief Invalidate the whole I$
<> 135:176b8275d35d 438
<> 135:176b8275d35d 439 ICIALLU. Instruction Cache Invalidate All to PoU
<> 135:176b8275d35d 440 */
<> 135:176b8275d35d 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 135:176b8275d35d 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
<> 135:176b8275d35d 443 __ICIALLU = 0;
<> 135:176b8275d35d 444 __DSB(); //ensure completion of the invalidation
<> 135:176b8275d35d 445 __ISB(); //ensure instruction fetch path sees new I cache state
<> 135:176b8275d35d 446 }
<> 135:176b8275d35d 447
<> 135:176b8275d35d 448 /** \brief Clean D$ by MVA
<> 135:176b8275d35d 449
<> 135:176b8275d35d 450 DCCMVAC. Data cache clean by MVA to PoC
<> 135:176b8275d35d 451 */
<> 135:176b8275d35d 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
<> 135:176b8275d35d 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
<> 135:176b8275d35d 454 __DCCMVAC = (uint32_t)va;
<> 135:176b8275d35d 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 135:176b8275d35d 456 }
<> 135:176b8275d35d 457
<> 135:176b8275d35d 458 /** \brief Invalidate D$ by MVA
<> 135:176b8275d35d 459
<> 135:176b8275d35d 460 DCIMVAC. Data cache invalidate by MVA to PoC
<> 135:176b8275d35d 461 */
<> 135:176b8275d35d 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
<> 135:176b8275d35d 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
<> 135:176b8275d35d 464 __DCIMVAC = (uint32_t)va;
<> 135:176b8275d35d 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 135:176b8275d35d 466 }
<> 135:176b8275d35d 467
<> 135:176b8275d35d 468 /** \brief Clean and Invalidate D$ by MVA
<> 135:176b8275d35d 469
<> 135:176b8275d35d 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 135:176b8275d35d 471 */
<> 135:176b8275d35d 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 135:176b8275d35d 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
<> 135:176b8275d35d 474 __DCCIMVAC = (uint32_t)va;
<> 135:176b8275d35d 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 135:176b8275d35d 476 }
<> 135:176b8275d35d 477
<> 135:176b8275d35d 478 /** \brief Clean and Invalidate the entire data or unified cache
<> 135:176b8275d35d 479
<> 135:176b8275d35d 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
<> 135:176b8275d35d 481 */
<> 135:176b8275d35d 482 #pragma push
<> 135:176b8275d35d 483 #pragma arm
<> 135:176b8275d35d 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
<> 135:176b8275d35d 485 ARM
<> 135:176b8275d35d 486
<> 135:176b8275d35d 487 PUSH {R4-R11}
<> 135:176b8275d35d 488
<> 135:176b8275d35d 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
<> 135:176b8275d35d 490 ANDS R3, R6, #0x07000000 // Extract coherency level
<> 135:176b8275d35d 491 MOV R3, R3, LSR #23 // Total cache levels << 1
<> 135:176b8275d35d 492 BEQ Finished // If 0, no need to clean
<> 135:176b8275d35d 493
<> 135:176b8275d35d 494 MOV R10, #0 // R10 holds current cache level << 1
<> 135:176b8275d35d 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
<> 135:176b8275d35d 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
<> 135:176b8275d35d 497 AND R1, R1, #7 // Isolate those lower 3 bits
<> 135:176b8275d35d 498 CMP R1, #2
<> 135:176b8275d35d 499 BLT Skip // No cache or only instruction cache at this level
<> 135:176b8275d35d 500
<> 135:176b8275d35d 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
<> 135:176b8275d35d 502 ISB // ISB to sync the change to the CacheSizeID reg
<> 135:176b8275d35d 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
<> 135:176b8275d35d 504 AND R2, R1, #7 // Extract the line length field
<> 135:176b8275d35d 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
<> 135:176b8275d35d 506 LDR R4, =0x3FF
<> 135:176b8275d35d 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
<> 135:176b8275d35d 508 CLZ R5, R4 // R5 is the bit position of the way size increment
<> 135:176b8275d35d 509 LDR R7, =0x7FFF
<> 135:176b8275d35d 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
<> 135:176b8275d35d 511
<> 135:176b8275d35d 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
<> 135:176b8275d35d 513
<> 135:176b8275d35d 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
<> 135:176b8275d35d 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
<> 135:176b8275d35d 516 CMP R0, #0
<> 135:176b8275d35d 517 BNE Dccsw
<> 135:176b8275d35d 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
<> 135:176b8275d35d 519 B cont
<> 135:176b8275d35d 520 Dccsw CMP R0, #1
<> 135:176b8275d35d 521 BNE Dccisw
<> 135:176b8275d35d 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
<> 135:176b8275d35d 523 B cont
<> 135:176b8275d35d 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
<> 135:176b8275d35d 525 cont SUBS R9, R9, #1 // Decrement the Way number
<> 135:176b8275d35d 526 BGE Loop3
<> 135:176b8275d35d 527 SUBS R7, R7, #1 // Decrement the Set number
<> 135:176b8275d35d 528 BGE Loop2
<> 135:176b8275d35d 529 Skip ADD R10, R10, #2 // Increment the cache number
<> 135:176b8275d35d 530 CMP R3, R10
<> 135:176b8275d35d 531 BGT Loop1
<> 135:176b8275d35d 532
<> 135:176b8275d35d 533 Finished
<> 135:176b8275d35d 534 DSB
<> 135:176b8275d35d 535 POP {R4-R11}
<> 135:176b8275d35d 536 BX lr
<> 135:176b8275d35d 537
<> 135:176b8275d35d 538 }
<> 135:176b8275d35d 539 #pragma pop
<> 135:176b8275d35d 540
<> 135:176b8275d35d 541
<> 135:176b8275d35d 542 /** \brief Invalidate the whole D$
<> 135:176b8275d35d 543
<> 135:176b8275d35d 544 DCISW. Invalidate by Set/Way
<> 135:176b8275d35d 545 */
<> 135:176b8275d35d 546
<> 135:176b8275d35d 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 135:176b8275d35d 548 __v7_all_cache(0);
<> 135:176b8275d35d 549 }
<> 135:176b8275d35d 550
<> 135:176b8275d35d 551 /** \brief Clean the whole D$
<> 135:176b8275d35d 552
<> 135:176b8275d35d 553 DCCSW. Clean by Set/Way
<> 135:176b8275d35d 554 */
<> 135:176b8275d35d 555
<> 135:176b8275d35d 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 135:176b8275d35d 557 __v7_all_cache(1);
<> 135:176b8275d35d 558 }
<> 135:176b8275d35d 559
<> 135:176b8275d35d 560 /** \brief Clean and invalidate the whole D$
<> 135:176b8275d35d 561
<> 135:176b8275d35d 562 DCCISW. Clean and Invalidate by Set/Way
<> 135:176b8275d35d 563 */
<> 135:176b8275d35d 564
<> 135:176b8275d35d 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 135:176b8275d35d 566 __v7_all_cache(2);
<> 135:176b8275d35d 567 }
<> 135:176b8275d35d 568
<> 135:176b8275d35d 569 #include "core_ca_mmu.h"
<> 135:176b8275d35d 570
<> 135:176b8275d35d 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
<> 135:176b8275d35d 572
<> 135:176b8275d35d 573 #define __inline inline
<> 135:176b8275d35d 574
<> 135:176b8275d35d 575 inline static uint32_t __disable_irq_iar() {
<> 135:176b8275d35d 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
<> 135:176b8275d35d 577 __disable_irq();
<> 135:176b8275d35d 578 return irq_dis;
<> 135:176b8275d35d 579 }
<> 135:176b8275d35d 580
<> 135:176b8275d35d 581 #define MODE_USR 0x10
<> 135:176b8275d35d 582 #define MODE_FIQ 0x11
<> 135:176b8275d35d 583 #define MODE_IRQ 0x12
<> 135:176b8275d35d 584 #define MODE_SVC 0x13
<> 135:176b8275d35d 585 #define MODE_MON 0x16
<> 135:176b8275d35d 586 #define MODE_ABT 0x17
<> 135:176b8275d35d 587 #define MODE_HYP 0x1A
<> 135:176b8275d35d 588 #define MODE_UND 0x1B
<> 135:176b8275d35d 589 #define MODE_SYS 0x1F
<> 135:176b8275d35d 590
<> 135:176b8275d35d 591 /** \brief Set Process Stack Pointer
<> 135:176b8275d35d 592
<> 135:176b8275d35d 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 135:176b8275d35d 594
<> 135:176b8275d35d 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 135:176b8275d35d 596 */
<> 135:176b8275d35d 597 // from rt_CMSIS.c
<> 135:176b8275d35d 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
<> 135:176b8275d35d 599 __asm(
<> 135:176b8275d35d 600 " ARM\n"
<> 135:176b8275d35d 601 // " PRESERVE8\n"
<> 135:176b8275d35d 602
<> 135:176b8275d35d 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
<> 135:176b8275d35d 604 " MRS R1, CPSR \n"
<> 135:176b8275d35d 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
<> 135:176b8275d35d 606 " MOV SP, R0 \n"
<> 135:176b8275d35d 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
<> 135:176b8275d35d 608 " ISB \n"
<> 135:176b8275d35d 609 " BX LR \n");
<> 135:176b8275d35d 610 }
<> 135:176b8275d35d 611
<> 135:176b8275d35d 612 /** \brief Set User Mode
<> 135:176b8275d35d 613
<> 135:176b8275d35d 614 This function changes the processor state to User Mode
<> 135:176b8275d35d 615 */
<> 135:176b8275d35d 616 // from rt_CMSIS.c
<> 135:176b8275d35d 617 __arm static inline void __set_CPS_USR(void) {
<> 135:176b8275d35d 618 __asm(
<> 135:176b8275d35d 619 " ARM \n"
<> 135:176b8275d35d 620
<> 135:176b8275d35d 621 " CPS #0x10 \n" // MODE_USR
<> 135:176b8275d35d 622 " BX LR\n");
<> 135:176b8275d35d 623 }
<> 135:176b8275d35d 624
<> 135:176b8275d35d 625 /** \brief Set TTBR0
<> 135:176b8275d35d 626
<> 135:176b8275d35d 627 This function assigns the given value to the Translation Table Base Register 0.
<> 135:176b8275d35d 628
<> 135:176b8275d35d 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 135:176b8275d35d 630 */
<> 135:176b8275d35d 631 // from mmu_Renesas_RZ_A1.c
<> 135:176b8275d35d 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 135:176b8275d35d 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
<> 135:176b8275d35d 634 __ISB();
<> 135:176b8275d35d 635 }
<> 135:176b8275d35d 636
<> 135:176b8275d35d 637 /** \brief Set DACR
<> 135:176b8275d35d 638
<> 135:176b8275d35d 639 This function assigns the given value to the Domain Access Control Register.
<> 135:176b8275d35d 640
<> 135:176b8275d35d 641 \param [in] dacr Domain Access Control Register value to set
<> 135:176b8275d35d 642 */
<> 135:176b8275d35d 643 // from mmu_Renesas_RZ_A1.c
<> 135:176b8275d35d 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 135:176b8275d35d 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
<> 135:176b8275d35d 646 __ISB();
<> 135:176b8275d35d 647 }
<> 135:176b8275d35d 648
<> 135:176b8275d35d 649
<> 135:176b8275d35d 650 /******************************** Cache and BTAC enable ****************************************************/
<> 135:176b8275d35d 651 /** \brief Set SCTLR
<> 135:176b8275d35d 652
<> 135:176b8275d35d 653 This function assigns the given value to the System Control Register.
<> 135:176b8275d35d 654
<> 135:176b8275d35d 655 \param [in] sctlr System Control Register value to set
<> 135:176b8275d35d 656 */
<> 135:176b8275d35d 657 // from __enable_mmu()
<> 135:176b8275d35d 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
<> 135:176b8275d35d 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
<> 135:176b8275d35d 660 }
<> 135:176b8275d35d 661
<> 135:176b8275d35d 662 /** \brief Get SCTLR
<> 135:176b8275d35d 663
<> 135:176b8275d35d 664 This function returns the value of the System Control Register.
<> 135:176b8275d35d 665
<> 135:176b8275d35d 666 \return System Control Register value
<> 135:176b8275d35d 667 */
<> 135:176b8275d35d 668 // from __enable_mmu()
<> 135:176b8275d35d 669 __STATIC_INLINE uint32_t __get_SCTLR() {
<> 135:176b8275d35d 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
<> 135:176b8275d35d 671 return __regSCTLR;
<> 135:176b8275d35d 672 }
<> 135:176b8275d35d 673
<> 135:176b8275d35d 674 /** \brief Enable Caches
<> 135:176b8275d35d 675
<> 135:176b8275d35d 676 Enable Caches
<> 135:176b8275d35d 677 */
<> 135:176b8275d35d 678 // from system_Renesas_RZ_A1.c
<> 135:176b8275d35d 679 __STATIC_INLINE void __enable_caches(void) {
<> 135:176b8275d35d 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 135:176b8275d35d 681 }
<> 135:176b8275d35d 682
<> 135:176b8275d35d 683 /** \brief Enable BTAC
<> 135:176b8275d35d 684
<> 135:176b8275d35d 685 Enable BTAC
<> 135:176b8275d35d 686 */
<> 135:176b8275d35d 687 // from system_Renesas_RZ_A1.c
<> 135:176b8275d35d 688 __STATIC_INLINE void __enable_btac(void) {
<> 135:176b8275d35d 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 135:176b8275d35d 690 __ISB();
<> 135:176b8275d35d 691 }
<> 135:176b8275d35d 692
<> 135:176b8275d35d 693 /** \brief Enable MMU
<> 135:176b8275d35d 694
<> 135:176b8275d35d 695 Enable MMU
<> 135:176b8275d35d 696 */
<> 135:176b8275d35d 697 // from system_Renesas_RZ_A1.c
<> 135:176b8275d35d 698 __STATIC_INLINE void __enable_mmu(void) {
<> 135:176b8275d35d 699 // Set M bit 0 to enable the MMU
<> 135:176b8275d35d 700 // Set AFE bit to enable simplified access permissions model
<> 135:176b8275d35d 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 135:176b8275d35d 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 135:176b8275d35d 703 __ISB();
<> 135:176b8275d35d 704 }
<> 135:176b8275d35d 705
<> 135:176b8275d35d 706 /******************************** TLB maintenance operations ************************************************/
<> 135:176b8275d35d 707 /** \brief Invalidate the whole tlb
<> 135:176b8275d35d 708
<> 135:176b8275d35d 709 TLBIALL. Invalidate the whole tlb
<> 135:176b8275d35d 710 */
<> 135:176b8275d35d 711 // from system_Renesas_RZ_A1.c
<> 135:176b8275d35d 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 135:176b8275d35d 713 uint32_t val = 0;
<> 135:176b8275d35d 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
<> 135:176b8275d35d 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
<> 135:176b8275d35d 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
<> 135:176b8275d35d 717 __DSB();
<> 135:176b8275d35d 718 __ISB();
<> 135:176b8275d35d 719 }
<> 135:176b8275d35d 720
<> 135:176b8275d35d 721 /******************************** BTB maintenance operations ************************************************/
<> 135:176b8275d35d 722 /** \brief Invalidate entire branch predictor array
<> 135:176b8275d35d 723
<> 135:176b8275d35d 724 BPIALL. Branch Predictor Invalidate All.
<> 135:176b8275d35d 725 */
<> 135:176b8275d35d 726 // from system_Renesas_RZ_A1.c
<> 135:176b8275d35d 727 __STATIC_INLINE void __v7_inv_btac(void) {
<> 135:176b8275d35d 728 uint32_t val = 0;
<> 135:176b8275d35d 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
<> 135:176b8275d35d 730 __DSB(); //ensure completion of the invalidation
<> 135:176b8275d35d 731 __ISB(); //ensure instruction fetch path sees new state
<> 135:176b8275d35d 732 }
<> 135:176b8275d35d 733
<> 135:176b8275d35d 734
<> 135:176b8275d35d 735 /******************************** L1 cache operations ******************************************************/
<> 135:176b8275d35d 736
<> 135:176b8275d35d 737 /** \brief Invalidate the whole I$
<> 135:176b8275d35d 738
<> 135:176b8275d35d 739 ICIALLU. Instruction Cache Invalidate All to PoU
<> 135:176b8275d35d 740 */
<> 135:176b8275d35d 741 // from system_Renesas_RZ_A1.c
<> 135:176b8275d35d 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 135:176b8275d35d 743 uint32_t val = 0;
<> 135:176b8275d35d 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
<> 135:176b8275d35d 745 __DSB(); //ensure completion of the invalidation
<> 135:176b8275d35d 746 __ISB(); //ensure instruction fetch path sees new I cache state
<> 135:176b8275d35d 747 }
<> 135:176b8275d35d 748
<> 135:176b8275d35d 749 // from __v7_inv_dcache_all()
<> 135:176b8275d35d 750 __arm static inline void __v7_all_cache(uint32_t op) {
<> 135:176b8275d35d 751 __asm(
<> 135:176b8275d35d 752 " ARM \n"
<> 135:176b8275d35d 753
<> 135:176b8275d35d 754 " PUSH {R4-R11} \n"
<> 135:176b8275d35d 755
<> 135:176b8275d35d 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
<> 135:176b8275d35d 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
<> 135:176b8275d35d 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
<> 135:176b8275d35d 759 " BEQ Finished\n" // If 0, no need to clean
<> 135:176b8275d35d 760
<> 135:176b8275d35d 761 " MOV R10, #0\n" // R10 holds current cache level << 1
<> 135:176b8275d35d 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
<> 135:176b8275d35d 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
<> 135:176b8275d35d 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
<> 135:176b8275d35d 765 " CMP R1, #2 \n"
<> 135:176b8275d35d 766 " BLT Skip \n" // No cache or only instruction cache at this level
<> 135:176b8275d35d 767
<> 135:176b8275d35d 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
<> 135:176b8275d35d 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
<> 135:176b8275d35d 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
<> 135:176b8275d35d 771 " AND R2, R1, #7 \n" // Extract the line length field
<> 135:176b8275d35d 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
<> 135:176b8275d35d 773 " movw R4, #0x3FF \n"
<> 135:176b8275d35d 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
<> 135:176b8275d35d 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
<> 135:176b8275d35d 776 " movw R7, #0x7FFF \n"
<> 135:176b8275d35d 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
<> 135:176b8275d35d 778
<> 135:176b8275d35d 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
<> 135:176b8275d35d 780
<> 135:176b8275d35d 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
<> 135:176b8275d35d 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
<> 135:176b8275d35d 783 " CMP R0, #0 \n"
<> 135:176b8275d35d 784 " BNE Dccsw \n"
<> 135:176b8275d35d 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
<> 135:176b8275d35d 786 " B cont \n"
<> 135:176b8275d35d 787 "Dccsw: CMP R0, #1 \n"
<> 135:176b8275d35d 788 " BNE Dccisw \n"
<> 135:176b8275d35d 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
<> 135:176b8275d35d 790 " B cont \n"
<> 135:176b8275d35d 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
<> 135:176b8275d35d 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
<> 135:176b8275d35d 793 " BGE Loop3 \n"
<> 135:176b8275d35d 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
<> 135:176b8275d35d 795 " BGE Loop2 \n"
<> 135:176b8275d35d 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
<> 135:176b8275d35d 797 " CMP R3, R10 \n"
<> 135:176b8275d35d 798 " BGT Loop1 \n"
<> 135:176b8275d35d 799
<> 135:176b8275d35d 800 "Finished: \n"
<> 135:176b8275d35d 801 " DSB \n"
<> 135:176b8275d35d 802 " POP {R4-R11} \n"
<> 135:176b8275d35d 803 " BX lr \n" );
<> 135:176b8275d35d 804 }
<> 135:176b8275d35d 805
<> 135:176b8275d35d 806 /** \brief Invalidate the whole D$
<> 135:176b8275d35d 807
<> 135:176b8275d35d 808 DCISW. Invalidate by Set/Way
<> 135:176b8275d35d 809 */
<> 135:176b8275d35d 810 // from system_Renesas_RZ_A1.c
<> 135:176b8275d35d 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 135:176b8275d35d 812 __v7_all_cache(0);
<> 135:176b8275d35d 813 }
<> 135:176b8275d35d 814 /** \brief Clean the whole D$
<> 135:176b8275d35d 815
<> 135:176b8275d35d 816 DCCSW. Clean by Set/Way
<> 135:176b8275d35d 817 */
<> 135:176b8275d35d 818
<> 135:176b8275d35d 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 135:176b8275d35d 820 __v7_all_cache(1);
<> 135:176b8275d35d 821 }
<> 135:176b8275d35d 822
<> 135:176b8275d35d 823 /** \brief Clean and invalidate the whole D$
<> 135:176b8275d35d 824
<> 135:176b8275d35d 825 DCCISW. Clean and Invalidate by Set/Way
<> 135:176b8275d35d 826 */
<> 135:176b8275d35d 827
<> 135:176b8275d35d 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 135:176b8275d35d 829 __v7_all_cache(2);
<> 135:176b8275d35d 830 }
<> 135:176b8275d35d 831 /** \brief Clean and Invalidate D$ by MVA
<> 135:176b8275d35d 832
<> 135:176b8275d35d 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 135:176b8275d35d 834 */
<> 135:176b8275d35d 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 135:176b8275d35d 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
<> 135:176b8275d35d 837 __DMB();
<> 135:176b8275d35d 838 }
<> 135:176b8275d35d 839
<> 135:176b8275d35d 840 #include "core_ca_mmu.h"
<> 135:176b8275d35d 841
<> 135:176b8275d35d 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
<> 135:176b8275d35d 843 /* GNU gcc specific functions */
<> 135:176b8275d35d 844
<> 135:176b8275d35d 845 #define MODE_USR 0x10
<> 135:176b8275d35d 846 #define MODE_FIQ 0x11
<> 135:176b8275d35d 847 #define MODE_IRQ 0x12
<> 135:176b8275d35d 848 #define MODE_SVC 0x13
<> 135:176b8275d35d 849 #define MODE_MON 0x16
<> 135:176b8275d35d 850 #define MODE_ABT 0x17
<> 135:176b8275d35d 851 #define MODE_HYP 0x1A
<> 135:176b8275d35d 852 #define MODE_UND 0x1B
<> 135:176b8275d35d 853 #define MODE_SYS 0x1F
<> 135:176b8275d35d 854
<> 135:176b8275d35d 855
<> 135:176b8275d35d 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 135:176b8275d35d 857 {
<> 135:176b8275d35d 858 __ASM volatile ("cpsie i");
<> 135:176b8275d35d 859 }
<> 135:176b8275d35d 860
<> 135:176b8275d35d 861 /** \brief Disable IRQ Interrupts
<> 135:176b8275d35d 862
<> 135:176b8275d35d 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 135:176b8275d35d 864 Can only be executed in Privileged modes.
<> 135:176b8275d35d 865 */
<> 135:176b8275d35d 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
<> 135:176b8275d35d 867 {
<> 135:176b8275d35d 868 uint32_t result;
<> 135:176b8275d35d 869
<> 135:176b8275d35d 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
<> 135:176b8275d35d 871 __ASM volatile ("cpsid i");
<> 135:176b8275d35d 872 return(result & 0x80);
<> 135:176b8275d35d 873 }
<> 135:176b8275d35d 874
<> 135:176b8275d35d 875
<> 135:176b8275d35d 876 /** \brief Get APSR Register
<> 135:176b8275d35d 877
<> 135:176b8275d35d 878 This function returns the content of the APSR Register.
<> 135:176b8275d35d 879
<> 135:176b8275d35d 880 \return APSR Register value
<> 135:176b8275d35d 881 */
<> 135:176b8275d35d 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 135:176b8275d35d 883 {
<> 135:176b8275d35d 884 #if 1
<> 135:176b8275d35d 885 register uint32_t __regAPSR;
<> 135:176b8275d35d 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
<> 135:176b8275d35d 887 #else
<> 135:176b8275d35d 888 register uint32_t __regAPSR __ASM("apsr");
<> 135:176b8275d35d 889 #endif
<> 135:176b8275d35d 890 return(__regAPSR);
<> 135:176b8275d35d 891 }
<> 135:176b8275d35d 892
<> 135:176b8275d35d 893
<> 135:176b8275d35d 894 /** \brief Get CPSR Register
<> 135:176b8275d35d 895
<> 135:176b8275d35d 896 This function returns the content of the CPSR Register.
<> 135:176b8275d35d 897
<> 135:176b8275d35d 898 \return CPSR Register value
<> 135:176b8275d35d 899 */
<> 135:176b8275d35d 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
<> 135:176b8275d35d 901 {
<> 135:176b8275d35d 902 #if 1
<> 135:176b8275d35d 903 register uint32_t __regCPSR;
<> 135:176b8275d35d 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
<> 135:176b8275d35d 905 #else
<> 135:176b8275d35d 906 register uint32_t __regCPSR __ASM("cpsr");
<> 135:176b8275d35d 907 #endif
<> 135:176b8275d35d 908 return(__regCPSR);
<> 135:176b8275d35d 909 }
<> 135:176b8275d35d 910
<> 135:176b8275d35d 911 #if 0
<> 135:176b8275d35d 912 /** \brief Set Stack Pointer
<> 135:176b8275d35d 913
<> 135:176b8275d35d 914 This function assigns the given value to the current stack pointer.
<> 135:176b8275d35d 915
<> 135:176b8275d35d 916 \param [in] topOfStack Stack Pointer value to set
<> 135:176b8275d35d 917 */
<> 135:176b8275d35d 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
<> 135:176b8275d35d 919 {
<> 135:176b8275d35d 920 register uint32_t __regSP __ASM("sp");
<> 135:176b8275d35d 921 __regSP = topOfStack;
<> 135:176b8275d35d 922 }
<> 135:176b8275d35d 923 #endif
<> 135:176b8275d35d 924
<> 135:176b8275d35d 925 /** \brief Get link register
<> 135:176b8275d35d 926
<> 135:176b8275d35d 927 This function returns the value of the link register
<> 135:176b8275d35d 928
<> 135:176b8275d35d 929 \return Value of link register
<> 135:176b8275d35d 930 */
<> 135:176b8275d35d 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
<> 135:176b8275d35d 932 {
<> 135:176b8275d35d 933 register uint32_t __reglr __ASM("lr");
<> 135:176b8275d35d 934 return(__reglr);
<> 135:176b8275d35d 935 }
<> 135:176b8275d35d 936
<> 135:176b8275d35d 937 #if 0
<> 135:176b8275d35d 938 /** \brief Set link register
<> 135:176b8275d35d 939
<> 135:176b8275d35d 940 This function sets the value of the link register
<> 135:176b8275d35d 941
<> 135:176b8275d35d 942 \param [in] lr LR value to set
<> 135:176b8275d35d 943 */
<> 135:176b8275d35d 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
<> 135:176b8275d35d 945 {
<> 135:176b8275d35d 946 register uint32_t __reglr __ASM("lr");
<> 135:176b8275d35d 947 __reglr = lr;
<> 135:176b8275d35d 948 }
<> 135:176b8275d35d 949 #endif
<> 135:176b8275d35d 950
<> 135:176b8275d35d 951 /** \brief Set Process Stack Pointer
<> 135:176b8275d35d 952
<> 135:176b8275d35d 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 135:176b8275d35d 954
<> 135:176b8275d35d 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 135:176b8275d35d 956 */
<> 135:176b8275d35d 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 135:176b8275d35d 958 {
<> 135:176b8275d35d 959 __asm__ volatile (
<> 135:176b8275d35d 960 ".ARM;"
<> 135:176b8275d35d 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
<> 135:176b8275d35d 962
<> 135:176b8275d35d 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
<> 135:176b8275d35d 964 "MRS R1, CPSR;"
<> 135:176b8275d35d 965 "CPS %0;" /* ;no effect in USR mode */
<> 135:176b8275d35d 966 "MOV SP, R0;"
<> 135:176b8275d35d 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
<> 135:176b8275d35d 968 "ISB;"
<> 135:176b8275d35d 969 //"BX LR;"
<> 135:176b8275d35d 970 :
<> 135:176b8275d35d 971 : "i"(MODE_SYS)
<> 135:176b8275d35d 972 : "r0", "r1");
<> 135:176b8275d35d 973 return;
<> 135:176b8275d35d 974 }
<> 135:176b8275d35d 975
<> 135:176b8275d35d 976 /** \brief Set User Mode
<> 135:176b8275d35d 977
<> 135:176b8275d35d 978 This function changes the processor state to User Mode
<> 135:176b8275d35d 979 */
<> 135:176b8275d35d 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
<> 135:176b8275d35d 981 {
<> 135:176b8275d35d 982 __asm__ volatile (
<> 135:176b8275d35d 983 ".ARM;"
<> 135:176b8275d35d 984
<> 135:176b8275d35d 985 "CPS %0;"
<> 135:176b8275d35d 986 //"BX LR;"
<> 135:176b8275d35d 987 :
<> 135:176b8275d35d 988 : "i"(MODE_USR)
<> 135:176b8275d35d 989 : );
<> 135:176b8275d35d 990 return;
<> 135:176b8275d35d 991 }
<> 135:176b8275d35d 992
<> 135:176b8275d35d 993
<> 135:176b8275d35d 994 /** \brief Enable FIQ
<> 135:176b8275d35d 995
<> 135:176b8275d35d 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 135:176b8275d35d 997 Can only be executed in Privileged modes.
<> 135:176b8275d35d 998 */
<> 135:176b8275d35d 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
<> 135:176b8275d35d 1000
<> 135:176b8275d35d 1001
<> 135:176b8275d35d 1002 /** \brief Disable FIQ
<> 135:176b8275d35d 1003
<> 135:176b8275d35d 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 135:176b8275d35d 1005 Can only be executed in Privileged modes.
<> 135:176b8275d35d 1006 */
<> 135:176b8275d35d 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
<> 135:176b8275d35d 1008
<> 135:176b8275d35d 1009
<> 135:176b8275d35d 1010 /** \brief Get FPSCR
<> 135:176b8275d35d 1011
<> 135:176b8275d35d 1012 This function returns the current value of the Floating Point Status/Control register.
<> 135:176b8275d35d 1013
<> 135:176b8275d35d 1014 \return Floating Point Status/Control register value
<> 135:176b8275d35d 1015 */
<> 135:176b8275d35d 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 135:176b8275d35d 1017 {
<> 135:176b8275d35d 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 1019 #if 1
<> 135:176b8275d35d 1020 uint32_t result;
<> 135:176b8275d35d 1021
<> 135:176b8275d35d 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
<> 135:176b8275d35d 1023 return (result);
<> 135:176b8275d35d 1024 #else
<> 135:176b8275d35d 1025 register uint32_t __regfpscr __ASM("fpscr");
<> 135:176b8275d35d 1026 return(__regfpscr);
<> 135:176b8275d35d 1027 #endif
<> 135:176b8275d35d 1028 #else
<> 135:176b8275d35d 1029 return(0);
<> 135:176b8275d35d 1030 #endif
<> 135:176b8275d35d 1031 }
<> 135:176b8275d35d 1032
<> 135:176b8275d35d 1033
<> 135:176b8275d35d 1034 /** \brief Set FPSCR
<> 135:176b8275d35d 1035
<> 135:176b8275d35d 1036 This function assigns the given value to the Floating Point Status/Control register.
<> 135:176b8275d35d 1037
<> 135:176b8275d35d 1038 \param [in] fpscr Floating Point Status/Control value to set
<> 135:176b8275d35d 1039 */
<> 135:176b8275d35d 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 135:176b8275d35d 1041 {
<> 135:176b8275d35d 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 1043 #if 1
<> 135:176b8275d35d 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
<> 135:176b8275d35d 1045 #else
<> 135:176b8275d35d 1046 register uint32_t __regfpscr __ASM("fpscr");
<> 135:176b8275d35d 1047 __regfpscr = (fpscr);
<> 135:176b8275d35d 1048 #endif
<> 135:176b8275d35d 1049 #endif
<> 135:176b8275d35d 1050 }
<> 135:176b8275d35d 1051
<> 135:176b8275d35d 1052 /** \brief Get FPEXC
<> 135:176b8275d35d 1053
<> 135:176b8275d35d 1054 This function returns the current value of the Floating Point Exception Control register.
<> 135:176b8275d35d 1055
<> 135:176b8275d35d 1056 \return Floating Point Exception Control register value
<> 135:176b8275d35d 1057 */
<> 135:176b8275d35d 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
<> 135:176b8275d35d 1059 {
<> 135:176b8275d35d 1060 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 1061 #if 1
<> 135:176b8275d35d 1062 uint32_t result;
<> 135:176b8275d35d 1063
<> 135:176b8275d35d 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
<> 135:176b8275d35d 1065 return (result);
<> 135:176b8275d35d 1066 #else
<> 135:176b8275d35d 1067 register uint32_t __regfpexc __ASM("fpexc");
<> 135:176b8275d35d 1068 return(__regfpexc);
<> 135:176b8275d35d 1069 #endif
<> 135:176b8275d35d 1070 #else
<> 135:176b8275d35d 1071 return(0);
<> 135:176b8275d35d 1072 #endif
<> 135:176b8275d35d 1073 }
<> 135:176b8275d35d 1074
<> 135:176b8275d35d 1075
<> 135:176b8275d35d 1076 /** \brief Set FPEXC
<> 135:176b8275d35d 1077
<> 135:176b8275d35d 1078 This function assigns the given value to the Floating Point Exception Control register.
<> 135:176b8275d35d 1079
<> 135:176b8275d35d 1080 \param [in] fpscr Floating Point Exception Control value to set
<> 135:176b8275d35d 1081 */
<> 135:176b8275d35d 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
<> 135:176b8275d35d 1083 {
<> 135:176b8275d35d 1084 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 1085 #if 1
<> 135:176b8275d35d 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
<> 135:176b8275d35d 1087 #else
<> 135:176b8275d35d 1088 register uint32_t __regfpexc __ASM("fpexc");
<> 135:176b8275d35d 1089 __regfpexc = (fpexc);
<> 135:176b8275d35d 1090 #endif
<> 135:176b8275d35d 1091 #endif
<> 135:176b8275d35d 1092 }
<> 135:176b8275d35d 1093
<> 135:176b8275d35d 1094 /** \brief Get CPACR
<> 135:176b8275d35d 1095
<> 135:176b8275d35d 1096 This function returns the current value of the Coprocessor Access Control register.
<> 135:176b8275d35d 1097
<> 135:176b8275d35d 1098 \return Coprocessor Access Control register value
<> 135:176b8275d35d 1099 */
<> 135:176b8275d35d 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
<> 135:176b8275d35d 1101 {
<> 135:176b8275d35d 1102 #if 1
<> 135:176b8275d35d 1103 register uint32_t __regCPACR;
<> 135:176b8275d35d 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
<> 135:176b8275d35d 1105 #else
<> 135:176b8275d35d 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 135:176b8275d35d 1107 #endif
<> 135:176b8275d35d 1108 return __regCPACR;
<> 135:176b8275d35d 1109 }
<> 135:176b8275d35d 1110
<> 135:176b8275d35d 1111 /** \brief Set CPACR
<> 135:176b8275d35d 1112
<> 135:176b8275d35d 1113 This function assigns the given value to the Coprocessor Access Control register.
<> 135:176b8275d35d 1114
<> 135:176b8275d35d 1115 \param [in] cpacr Coprocessor Acccess Control value to set
<> 135:176b8275d35d 1116 */
<> 135:176b8275d35d 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
<> 135:176b8275d35d 1118 {
<> 135:176b8275d35d 1119 #if 1
<> 135:176b8275d35d 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
<> 135:176b8275d35d 1121 #else
<> 135:176b8275d35d 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 135:176b8275d35d 1123 __regCPACR = cpacr;
<> 135:176b8275d35d 1124 #endif
<> 135:176b8275d35d 1125 __ISB();
<> 135:176b8275d35d 1126 }
<> 135:176b8275d35d 1127
<> 135:176b8275d35d 1128 /** \brief Get CBAR
<> 135:176b8275d35d 1129
<> 135:176b8275d35d 1130 This function returns the value of the Configuration Base Address register.
<> 135:176b8275d35d 1131
<> 135:176b8275d35d 1132 \return Configuration Base Address register value
<> 135:176b8275d35d 1133 */
<> 135:176b8275d35d 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
<> 135:176b8275d35d 1135 #if 1
<> 135:176b8275d35d 1136 register uint32_t __regCBAR;
<> 135:176b8275d35d 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
<> 135:176b8275d35d 1138 #else
<> 135:176b8275d35d 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
<> 135:176b8275d35d 1140 #endif
<> 135:176b8275d35d 1141 return(__regCBAR);
<> 135:176b8275d35d 1142 }
<> 135:176b8275d35d 1143
<> 135:176b8275d35d 1144 /** \brief Get TTBR0
<> 135:176b8275d35d 1145
<> 135:176b8275d35d 1146 This function returns the value of the Translation Table Base Register 0.
<> 135:176b8275d35d 1147
<> 135:176b8275d35d 1148 \return Translation Table Base Register 0 value
<> 135:176b8275d35d 1149 */
<> 135:176b8275d35d 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
<> 135:176b8275d35d 1151 #if 1
<> 135:176b8275d35d 1152 register uint32_t __regTTBR0;
<> 135:176b8275d35d 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
<> 135:176b8275d35d 1154 #else
<> 135:176b8275d35d 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 135:176b8275d35d 1156 #endif
<> 135:176b8275d35d 1157 return(__regTTBR0);
<> 135:176b8275d35d 1158 }
<> 135:176b8275d35d 1159
<> 135:176b8275d35d 1160 /** \brief Set TTBR0
<> 135:176b8275d35d 1161
<> 135:176b8275d35d 1162 This function assigns the given value to the Translation Table Base Register 0.
<> 135:176b8275d35d 1163
<> 135:176b8275d35d 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 135:176b8275d35d 1165 */
<> 135:176b8275d35d 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 135:176b8275d35d 1167 #if 1
<> 135:176b8275d35d 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
<> 135:176b8275d35d 1169 #else
<> 135:176b8275d35d 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 135:176b8275d35d 1171 __regTTBR0 = ttbr0;
<> 135:176b8275d35d 1172 #endif
<> 135:176b8275d35d 1173 __ISB();
<> 135:176b8275d35d 1174 }
<> 135:176b8275d35d 1175
<> 135:176b8275d35d 1176 /** \brief Get DACR
<> 135:176b8275d35d 1177
<> 135:176b8275d35d 1178 This function returns the value of the Domain Access Control Register.
<> 135:176b8275d35d 1179
<> 135:176b8275d35d 1180 \return Domain Access Control Register value
<> 135:176b8275d35d 1181 */
<> 135:176b8275d35d 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
<> 135:176b8275d35d 1183 #if 1
<> 135:176b8275d35d 1184 register uint32_t __regDACR;
<> 135:176b8275d35d 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
<> 135:176b8275d35d 1186 #else
<> 135:176b8275d35d 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 135:176b8275d35d 1188 #endif
<> 135:176b8275d35d 1189 return(__regDACR);
<> 135:176b8275d35d 1190 }
<> 135:176b8275d35d 1191
<> 135:176b8275d35d 1192 /** \brief Set DACR
<> 135:176b8275d35d 1193
<> 135:176b8275d35d 1194 This function assigns the given value to the Domain Access Control Register.
<> 135:176b8275d35d 1195
<> 135:176b8275d35d 1196 \param [in] dacr Domain Access Control Register value to set
<> 135:176b8275d35d 1197 */
<> 135:176b8275d35d 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 135:176b8275d35d 1199 #if 1
<> 135:176b8275d35d 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
<> 135:176b8275d35d 1201 #else
<> 135:176b8275d35d 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 135:176b8275d35d 1203 __regDACR = dacr;
<> 135:176b8275d35d 1204 #endif
<> 135:176b8275d35d 1205 __ISB();
<> 135:176b8275d35d 1206 }
<> 135:176b8275d35d 1207
<> 135:176b8275d35d 1208 /******************************** Cache and BTAC enable ****************************************************/
<> 135:176b8275d35d 1209
<> 135:176b8275d35d 1210 /** \brief Set SCTLR
<> 135:176b8275d35d 1211
<> 135:176b8275d35d 1212 This function assigns the given value to the System Control Register.
<> 135:176b8275d35d 1213
<> 135:176b8275d35d 1214 \param [in] sctlr System Control Register value to set
<> 135:176b8275d35d 1215 */
<> 135:176b8275d35d 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
<> 135:176b8275d35d 1217 {
<> 135:176b8275d35d 1218 #if 1
<> 135:176b8275d35d 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
<> 135:176b8275d35d 1220 #else
<> 135:176b8275d35d 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 135:176b8275d35d 1222 __regSCTLR = sctlr;
<> 135:176b8275d35d 1223 #endif
<> 135:176b8275d35d 1224 }
<> 135:176b8275d35d 1225
<> 135:176b8275d35d 1226 /** \brief Get SCTLR
<> 135:176b8275d35d 1227
<> 135:176b8275d35d 1228 This function returns the value of the System Control Register.
<> 135:176b8275d35d 1229
<> 135:176b8275d35d 1230 \return System Control Register value
<> 135:176b8275d35d 1231 */
<> 135:176b8275d35d 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
<> 135:176b8275d35d 1233 #if 1
<> 135:176b8275d35d 1234 register uint32_t __regSCTLR;
<> 135:176b8275d35d 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
<> 135:176b8275d35d 1236 #else
<> 135:176b8275d35d 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 135:176b8275d35d 1238 #endif
<> 135:176b8275d35d 1239 return(__regSCTLR);
<> 135:176b8275d35d 1240 }
<> 135:176b8275d35d 1241
<> 135:176b8275d35d 1242 /** \brief Enable Caches
<> 135:176b8275d35d 1243
<> 135:176b8275d35d 1244 Enable Caches
<> 135:176b8275d35d 1245 */
<> 135:176b8275d35d 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
<> 135:176b8275d35d 1247 // Set I bit 12 to enable I Cache
<> 135:176b8275d35d 1248 // Set C bit 2 to enable D Cache
<> 135:176b8275d35d 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 135:176b8275d35d 1250 }
<> 135:176b8275d35d 1251
<> 135:176b8275d35d 1252 /** \brief Disable Caches
<> 135:176b8275d35d 1253
<> 135:176b8275d35d 1254 Disable Caches
<> 135:176b8275d35d 1255 */
<> 135:176b8275d35d 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
<> 135:176b8275d35d 1257 // Clear I bit 12 to disable I Cache
<> 135:176b8275d35d 1258 // Clear C bit 2 to disable D Cache
<> 135:176b8275d35d 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
<> 135:176b8275d35d 1260 __ISB();
<> 135:176b8275d35d 1261 }
<> 135:176b8275d35d 1262
<> 135:176b8275d35d 1263 /** \brief Enable BTAC
<> 135:176b8275d35d 1264
<> 135:176b8275d35d 1265 Enable BTAC
<> 135:176b8275d35d 1266 */
<> 135:176b8275d35d 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
<> 135:176b8275d35d 1268 // Set Z bit 11 to enable branch prediction
<> 135:176b8275d35d 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 135:176b8275d35d 1270 __ISB();
<> 135:176b8275d35d 1271 }
<> 135:176b8275d35d 1272
<> 135:176b8275d35d 1273 /** \brief Disable BTAC
<> 135:176b8275d35d 1274
<> 135:176b8275d35d 1275 Disable BTAC
<> 135:176b8275d35d 1276 */
<> 135:176b8275d35d 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
<> 135:176b8275d35d 1278 // Clear Z bit 11 to disable branch prediction
<> 135:176b8275d35d 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
<> 135:176b8275d35d 1280 }
<> 135:176b8275d35d 1281
<> 135:176b8275d35d 1282
<> 135:176b8275d35d 1283 /** \brief Enable MMU
<> 135:176b8275d35d 1284
<> 135:176b8275d35d 1285 Enable MMU
<> 135:176b8275d35d 1286 */
<> 135:176b8275d35d 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
<> 135:176b8275d35d 1288 // Set M bit 0 to enable the MMU
<> 135:176b8275d35d 1289 // Set AFE bit to enable simplified access permissions model
<> 135:176b8275d35d 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 135:176b8275d35d 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 135:176b8275d35d 1292 __ISB();
<> 135:176b8275d35d 1293 }
<> 135:176b8275d35d 1294
<> 135:176b8275d35d 1295 /** \brief Disable MMU
<> 135:176b8275d35d 1296
<> 135:176b8275d35d 1297 Disable MMU
<> 135:176b8275d35d 1298 */
<> 135:176b8275d35d 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
<> 135:176b8275d35d 1300 // Clear M bit 0 to disable the MMU
<> 135:176b8275d35d 1301 __set_SCTLR( __get_SCTLR() & ~1);
<> 135:176b8275d35d 1302 __ISB();
<> 135:176b8275d35d 1303 }
<> 135:176b8275d35d 1304
<> 135:176b8275d35d 1305 /******************************** TLB maintenance operations ************************************************/
<> 135:176b8275d35d 1306 /** \brief Invalidate the whole tlb
<> 135:176b8275d35d 1307
<> 135:176b8275d35d 1308 TLBIALL. Invalidate the whole tlb
<> 135:176b8275d35d 1309 */
<> 135:176b8275d35d 1310
<> 135:176b8275d35d 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 135:176b8275d35d 1312 #if 1
<> 135:176b8275d35d 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
<> 135:176b8275d35d 1314 #else
<> 135:176b8275d35d 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
<> 135:176b8275d35d 1316 __TLBIALL = 0;
<> 135:176b8275d35d 1317 #endif
<> 135:176b8275d35d 1318 __DSB();
<> 135:176b8275d35d 1319 __ISB();
<> 135:176b8275d35d 1320 }
<> 135:176b8275d35d 1321
<> 135:176b8275d35d 1322 /******************************** BTB maintenance operations ************************************************/
<> 135:176b8275d35d 1323 /** \brief Invalidate entire branch predictor array
<> 135:176b8275d35d 1324
<> 135:176b8275d35d 1325 BPIALL. Branch Predictor Invalidate All.
<> 135:176b8275d35d 1326 */
<> 135:176b8275d35d 1327
<> 135:176b8275d35d 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
<> 135:176b8275d35d 1329 #if 1
<> 135:176b8275d35d 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
<> 135:176b8275d35d 1331 #else
<> 135:176b8275d35d 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
<> 135:176b8275d35d 1333 __BPIALL = 0;
<> 135:176b8275d35d 1334 #endif
<> 135:176b8275d35d 1335 __DSB(); //ensure completion of the invalidation
<> 135:176b8275d35d 1336 __ISB(); //ensure instruction fetch path sees new state
<> 135:176b8275d35d 1337 }
<> 135:176b8275d35d 1338
<> 135:176b8275d35d 1339
<> 135:176b8275d35d 1340 /******************************** L1 cache operations ******************************************************/
<> 135:176b8275d35d 1341
<> 135:176b8275d35d 1342 /** \brief Invalidate the whole I$
<> 135:176b8275d35d 1343
<> 135:176b8275d35d 1344 ICIALLU. Instruction Cache Invalidate All to PoU
<> 135:176b8275d35d 1345 */
<> 135:176b8275d35d 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 135:176b8275d35d 1347 #if 1
<> 135:176b8275d35d 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
<> 135:176b8275d35d 1349 #else
<> 135:176b8275d35d 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
<> 135:176b8275d35d 1351 __ICIALLU = 0;
<> 135:176b8275d35d 1352 #endif
<> 135:176b8275d35d 1353 __DSB(); //ensure completion of the invalidation
<> 135:176b8275d35d 1354 __ISB(); //ensure instruction fetch path sees new I cache state
<> 135:176b8275d35d 1355 }
<> 135:176b8275d35d 1356
<> 135:176b8275d35d 1357 /** \brief Clean D$ by MVA
<> 135:176b8275d35d 1358
<> 135:176b8275d35d 1359 DCCMVAC. Data cache clean by MVA to PoC
<> 135:176b8275d35d 1360 */
<> 135:176b8275d35d 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
<> 135:176b8275d35d 1362 #if 1
<> 135:176b8275d35d 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
<> 135:176b8275d35d 1364 #else
<> 135:176b8275d35d 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
<> 135:176b8275d35d 1366 __DCCMVAC = (uint32_t)va;
<> 135:176b8275d35d 1367 #endif
<> 135:176b8275d35d 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 135:176b8275d35d 1369 }
<> 135:176b8275d35d 1370
<> 135:176b8275d35d 1371 /** \brief Invalidate D$ by MVA
<> 135:176b8275d35d 1372
<> 135:176b8275d35d 1373 DCIMVAC. Data cache invalidate by MVA to PoC
<> 135:176b8275d35d 1374 */
<> 135:176b8275d35d 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
<> 135:176b8275d35d 1376 #if 1
<> 135:176b8275d35d 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
<> 135:176b8275d35d 1378 #else
<> 135:176b8275d35d 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
<> 135:176b8275d35d 1380 __DCIMVAC = (uint32_t)va;
<> 135:176b8275d35d 1381 #endif
<> 135:176b8275d35d 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 135:176b8275d35d 1383 }
<> 135:176b8275d35d 1384
<> 135:176b8275d35d 1385 /** \brief Clean and Invalidate D$ by MVA
<> 135:176b8275d35d 1386
<> 135:176b8275d35d 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 135:176b8275d35d 1388 */
<> 135:176b8275d35d 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 135:176b8275d35d 1390 #if 1
<> 135:176b8275d35d 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
<> 135:176b8275d35d 1392 #else
<> 135:176b8275d35d 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
<> 135:176b8275d35d 1394 __DCCIMVAC = (uint32_t)va;
<> 135:176b8275d35d 1395 #endif
<> 135:176b8275d35d 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 135:176b8275d35d 1397 }
<> 135:176b8275d35d 1398
<> 135:176b8275d35d 1399 /** \brief Clean and Invalidate the entire data or unified cache
<> 135:176b8275d35d 1400
<> 135:176b8275d35d 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
<> 135:176b8275d35d 1402 */
<> 135:176b8275d35d 1403 extern void __v7_all_cache(uint32_t op);
<> 135:176b8275d35d 1404
<> 135:176b8275d35d 1405
<> 135:176b8275d35d 1406 /** \brief Invalidate the whole D$
<> 135:176b8275d35d 1407
<> 135:176b8275d35d 1408 DCISW. Invalidate by Set/Way
<> 135:176b8275d35d 1409 */
<> 135:176b8275d35d 1410
<> 135:176b8275d35d 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 135:176b8275d35d 1412 __v7_all_cache(0);
<> 135:176b8275d35d 1413 }
<> 135:176b8275d35d 1414
<> 135:176b8275d35d 1415 /** \brief Clean the whole D$
<> 135:176b8275d35d 1416
<> 135:176b8275d35d 1417 DCCSW. Clean by Set/Way
<> 135:176b8275d35d 1418 */
<> 135:176b8275d35d 1419
<> 135:176b8275d35d 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 135:176b8275d35d 1421 __v7_all_cache(1);
<> 135:176b8275d35d 1422 }
<> 135:176b8275d35d 1423
<> 135:176b8275d35d 1424 /** \brief Clean and invalidate the whole D$
<> 135:176b8275d35d 1425
<> 135:176b8275d35d 1426 DCCISW. Clean and Invalidate by Set/Way
<> 135:176b8275d35d 1427 */
<> 135:176b8275d35d 1428
<> 135:176b8275d35d 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 135:176b8275d35d 1430 __v7_all_cache(2);
<> 135:176b8275d35d 1431 }
<> 135:176b8275d35d 1432
<> 135:176b8275d35d 1433 #include "core_ca_mmu.h"
<> 135:176b8275d35d 1434
<> 135:176b8275d35d 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
<> 135:176b8275d35d 1436
<> 135:176b8275d35d 1437 #error TASKING Compiler support not implemented for Cortex-A
<> 135:176b8275d35d 1438
<> 135:176b8275d35d 1439 #endif
<> 135:176b8275d35d 1440
<> 135:176b8275d35d 1441 /*@} end of CMSIS_Core_RegAccFunctions */
<> 135:176b8275d35d 1442
<> 135:176b8275d35d 1443
<> 135:176b8275d35d 1444 #endif /* __CORE_CAFUNC_H__ */