mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC1549/core_cm4_simd.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
79:0c05e21ae27e 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 79:0c05e21ae27e 1 /**************************************************************************//**
emilmont 79:0c05e21ae27e 2 * @file core_cm4_simd.h
emilmont 79:0c05e21ae27e 3 * @brief CMSIS Cortex-M4 SIMD Header File
emilmont 79:0c05e21ae27e 4 * @version V3.20
emilmont 79:0c05e21ae27e 5 * @date 25. February 2013
emilmont 79:0c05e21ae27e 6 *
emilmont 79:0c05e21ae27e 7 * @note
emilmont 79:0c05e21ae27e 8 *
emilmont 79:0c05e21ae27e 9 ******************************************************************************/
emilmont 79:0c05e21ae27e 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 79:0c05e21ae27e 11
emilmont 79:0c05e21ae27e 12 All rights reserved.
emilmont 79:0c05e21ae27e 13 Redistribution and use in source and binary forms, with or without
emilmont 79:0c05e21ae27e 14 modification, are permitted provided that the following conditions are met:
emilmont 79:0c05e21ae27e 15 - Redistributions of source code must retain the above copyright
emilmont 79:0c05e21ae27e 16 notice, this list of conditions and the following disclaimer.
emilmont 79:0c05e21ae27e 17 - Redistributions in binary form must reproduce the above copyright
emilmont 79:0c05e21ae27e 18 notice, this list of conditions and the following disclaimer in the
emilmont 79:0c05e21ae27e 19 documentation and/or other materials provided with the distribution.
emilmont 79:0c05e21ae27e 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 79:0c05e21ae27e 21 to endorse or promote products derived from this software without
emilmont 79:0c05e21ae27e 22 specific prior written permission.
emilmont 79:0c05e21ae27e 23 *
emilmont 79:0c05e21ae27e 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 79:0c05e21ae27e 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 79:0c05e21ae27e 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 79:0c05e21ae27e 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 79:0c05e21ae27e 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 79:0c05e21ae27e 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 79:0c05e21ae27e 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 79:0c05e21ae27e 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 79:0c05e21ae27e 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 79:0c05e21ae27e 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 79:0c05e21ae27e 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 79:0c05e21ae27e 35 ---------------------------------------------------------------------------*/
emilmont 79:0c05e21ae27e 36
emilmont 79:0c05e21ae27e 37
emilmont 79:0c05e21ae27e 38 #ifdef __cplusplus
emilmont 79:0c05e21ae27e 39 extern "C" {
emilmont 79:0c05e21ae27e 40 #endif
emilmont 79:0c05e21ae27e 41
emilmont 79:0c05e21ae27e 42 #ifndef __CORE_CM4_SIMD_H
emilmont 79:0c05e21ae27e 43 #define __CORE_CM4_SIMD_H
emilmont 79:0c05e21ae27e 44
emilmont 79:0c05e21ae27e 45
emilmont 79:0c05e21ae27e 46 /*******************************************************************************
emilmont 79:0c05e21ae27e 47 * Hardware Abstraction Layer
emilmont 79:0c05e21ae27e 48 ******************************************************************************/
emilmont 79:0c05e21ae27e 49
emilmont 79:0c05e21ae27e 50
emilmont 79:0c05e21ae27e 51 /* ################### Compiler specific Intrinsics ########################### */
emilmont 79:0c05e21ae27e 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
emilmont 79:0c05e21ae27e 53 Access to dedicated SIMD instructions
emilmont 79:0c05e21ae27e 54 @{
emilmont 79:0c05e21ae27e 55 */
emilmont 79:0c05e21ae27e 56
emilmont 79:0c05e21ae27e 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 79:0c05e21ae27e 58 /* ARM armcc specific functions */
emilmont 79:0c05e21ae27e 59
emilmont 79:0c05e21ae27e 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 61 #define __SADD8 __sadd8
emilmont 79:0c05e21ae27e 62 #define __QADD8 __qadd8
emilmont 79:0c05e21ae27e 63 #define __SHADD8 __shadd8
emilmont 79:0c05e21ae27e 64 #define __UADD8 __uadd8
emilmont 79:0c05e21ae27e 65 #define __UQADD8 __uqadd8
emilmont 79:0c05e21ae27e 66 #define __UHADD8 __uhadd8
emilmont 79:0c05e21ae27e 67 #define __SSUB8 __ssub8
emilmont 79:0c05e21ae27e 68 #define __QSUB8 __qsub8
emilmont 79:0c05e21ae27e 69 #define __SHSUB8 __shsub8
emilmont 79:0c05e21ae27e 70 #define __USUB8 __usub8
emilmont 79:0c05e21ae27e 71 #define __UQSUB8 __uqsub8
emilmont 79:0c05e21ae27e 72 #define __UHSUB8 __uhsub8
emilmont 79:0c05e21ae27e 73 #define __SADD16 __sadd16
emilmont 79:0c05e21ae27e 74 #define __QADD16 __qadd16
emilmont 79:0c05e21ae27e 75 #define __SHADD16 __shadd16
emilmont 79:0c05e21ae27e 76 #define __UADD16 __uadd16
emilmont 79:0c05e21ae27e 77 #define __UQADD16 __uqadd16
emilmont 79:0c05e21ae27e 78 #define __UHADD16 __uhadd16
emilmont 79:0c05e21ae27e 79 #define __SSUB16 __ssub16
emilmont 79:0c05e21ae27e 80 #define __QSUB16 __qsub16
emilmont 79:0c05e21ae27e 81 #define __SHSUB16 __shsub16
emilmont 79:0c05e21ae27e 82 #define __USUB16 __usub16
emilmont 79:0c05e21ae27e 83 #define __UQSUB16 __uqsub16
emilmont 79:0c05e21ae27e 84 #define __UHSUB16 __uhsub16
emilmont 79:0c05e21ae27e 85 #define __SASX __sasx
emilmont 79:0c05e21ae27e 86 #define __QASX __qasx
emilmont 79:0c05e21ae27e 87 #define __SHASX __shasx
emilmont 79:0c05e21ae27e 88 #define __UASX __uasx
emilmont 79:0c05e21ae27e 89 #define __UQASX __uqasx
emilmont 79:0c05e21ae27e 90 #define __UHASX __uhasx
emilmont 79:0c05e21ae27e 91 #define __SSAX __ssax
emilmont 79:0c05e21ae27e 92 #define __QSAX __qsax
emilmont 79:0c05e21ae27e 93 #define __SHSAX __shsax
emilmont 79:0c05e21ae27e 94 #define __USAX __usax
emilmont 79:0c05e21ae27e 95 #define __UQSAX __uqsax
emilmont 79:0c05e21ae27e 96 #define __UHSAX __uhsax
emilmont 79:0c05e21ae27e 97 #define __USAD8 __usad8
emilmont 79:0c05e21ae27e 98 #define __USADA8 __usada8
emilmont 79:0c05e21ae27e 99 #define __SSAT16 __ssat16
emilmont 79:0c05e21ae27e 100 #define __USAT16 __usat16
emilmont 79:0c05e21ae27e 101 #define __UXTB16 __uxtb16
emilmont 79:0c05e21ae27e 102 #define __UXTAB16 __uxtab16
emilmont 79:0c05e21ae27e 103 #define __SXTB16 __sxtb16
emilmont 79:0c05e21ae27e 104 #define __SXTAB16 __sxtab16
emilmont 79:0c05e21ae27e 105 #define __SMUAD __smuad
emilmont 79:0c05e21ae27e 106 #define __SMUADX __smuadx
emilmont 79:0c05e21ae27e 107 #define __SMLAD __smlad
emilmont 79:0c05e21ae27e 108 #define __SMLADX __smladx
emilmont 79:0c05e21ae27e 109 #define __SMLALD __smlald
emilmont 79:0c05e21ae27e 110 #define __SMLALDX __smlaldx
emilmont 79:0c05e21ae27e 111 #define __SMUSD __smusd
emilmont 79:0c05e21ae27e 112 #define __SMUSDX __smusdx
emilmont 79:0c05e21ae27e 113 #define __SMLSD __smlsd
emilmont 79:0c05e21ae27e 114 #define __SMLSDX __smlsdx
emilmont 79:0c05e21ae27e 115 #define __SMLSLD __smlsld
emilmont 79:0c05e21ae27e 116 #define __SMLSLDX __smlsldx
emilmont 79:0c05e21ae27e 117 #define __SEL __sel
emilmont 79:0c05e21ae27e 118 #define __QADD __qadd
emilmont 79:0c05e21ae27e 119 #define __QSUB __qsub
emilmont 79:0c05e21ae27e 120
emilmont 79:0c05e21ae27e 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
emilmont 79:0c05e21ae27e 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
emilmont 79:0c05e21ae27e 123
emilmont 79:0c05e21ae27e 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
emilmont 79:0c05e21ae27e 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
emilmont 79:0c05e21ae27e 126
emilmont 79:0c05e21ae27e 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
emilmont 79:0c05e21ae27e 128 ((int64_t)(ARG3) << 32) ) >> 32))
emilmont 79:0c05e21ae27e 129
emilmont 79:0c05e21ae27e 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 131
emilmont 79:0c05e21ae27e 132
emilmont 79:0c05e21ae27e 133
emilmont 79:0c05e21ae27e 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 79:0c05e21ae27e 135 /* IAR iccarm specific functions */
emilmont 79:0c05e21ae27e 136
emilmont 79:0c05e21ae27e 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 138 #include <cmsis_iar.h>
emilmont 79:0c05e21ae27e 139
emilmont 79:0c05e21ae27e 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 141
emilmont 79:0c05e21ae27e 142
emilmont 79:0c05e21ae27e 143
emilmont 79:0c05e21ae27e 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 79:0c05e21ae27e 145 /* TI CCS specific functions */
emilmont 79:0c05e21ae27e 146
emilmont 79:0c05e21ae27e 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 148 #include <cmsis_ccs.h>
emilmont 79:0c05e21ae27e 149
emilmont 79:0c05e21ae27e 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 151
emilmont 79:0c05e21ae27e 152
emilmont 79:0c05e21ae27e 153
emilmont 79:0c05e21ae27e 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 79:0c05e21ae27e 155 /* GNU gcc specific functions */
emilmont 79:0c05e21ae27e 156
emilmont 79:0c05e21ae27e 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 159 {
emilmont 79:0c05e21ae27e 160 uint32_t result;
emilmont 79:0c05e21ae27e 161
emilmont 79:0c05e21ae27e 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 163 return(result);
emilmont 79:0c05e21ae27e 164 }
emilmont 79:0c05e21ae27e 165
emilmont 79:0c05e21ae27e 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 167 {
emilmont 79:0c05e21ae27e 168 uint32_t result;
emilmont 79:0c05e21ae27e 169
emilmont 79:0c05e21ae27e 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 171 return(result);
emilmont 79:0c05e21ae27e 172 }
emilmont 79:0c05e21ae27e 173
emilmont 79:0c05e21ae27e 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 175 {
emilmont 79:0c05e21ae27e 176 uint32_t result;
emilmont 79:0c05e21ae27e 177
emilmont 79:0c05e21ae27e 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 179 return(result);
emilmont 79:0c05e21ae27e 180 }
emilmont 79:0c05e21ae27e 181
emilmont 79:0c05e21ae27e 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 183 {
emilmont 79:0c05e21ae27e 184 uint32_t result;
emilmont 79:0c05e21ae27e 185
emilmont 79:0c05e21ae27e 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 187 return(result);
emilmont 79:0c05e21ae27e 188 }
emilmont 79:0c05e21ae27e 189
emilmont 79:0c05e21ae27e 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 191 {
emilmont 79:0c05e21ae27e 192 uint32_t result;
emilmont 79:0c05e21ae27e 193
emilmont 79:0c05e21ae27e 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 195 return(result);
emilmont 79:0c05e21ae27e 196 }
emilmont 79:0c05e21ae27e 197
emilmont 79:0c05e21ae27e 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 199 {
emilmont 79:0c05e21ae27e 200 uint32_t result;
emilmont 79:0c05e21ae27e 201
emilmont 79:0c05e21ae27e 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 203 return(result);
emilmont 79:0c05e21ae27e 204 }
emilmont 79:0c05e21ae27e 205
emilmont 79:0c05e21ae27e 206
emilmont 79:0c05e21ae27e 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 208 {
emilmont 79:0c05e21ae27e 209 uint32_t result;
emilmont 79:0c05e21ae27e 210
emilmont 79:0c05e21ae27e 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 212 return(result);
emilmont 79:0c05e21ae27e 213 }
emilmont 79:0c05e21ae27e 214
emilmont 79:0c05e21ae27e 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 216 {
emilmont 79:0c05e21ae27e 217 uint32_t result;
emilmont 79:0c05e21ae27e 218
emilmont 79:0c05e21ae27e 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 220 return(result);
emilmont 79:0c05e21ae27e 221 }
emilmont 79:0c05e21ae27e 222
emilmont 79:0c05e21ae27e 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 224 {
emilmont 79:0c05e21ae27e 225 uint32_t result;
emilmont 79:0c05e21ae27e 226
emilmont 79:0c05e21ae27e 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 228 return(result);
emilmont 79:0c05e21ae27e 229 }
emilmont 79:0c05e21ae27e 230
emilmont 79:0c05e21ae27e 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 232 {
emilmont 79:0c05e21ae27e 233 uint32_t result;
emilmont 79:0c05e21ae27e 234
emilmont 79:0c05e21ae27e 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 236 return(result);
emilmont 79:0c05e21ae27e 237 }
emilmont 79:0c05e21ae27e 238
emilmont 79:0c05e21ae27e 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 240 {
emilmont 79:0c05e21ae27e 241 uint32_t result;
emilmont 79:0c05e21ae27e 242
emilmont 79:0c05e21ae27e 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 244 return(result);
emilmont 79:0c05e21ae27e 245 }
emilmont 79:0c05e21ae27e 246
emilmont 79:0c05e21ae27e 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 248 {
emilmont 79:0c05e21ae27e 249 uint32_t result;
emilmont 79:0c05e21ae27e 250
emilmont 79:0c05e21ae27e 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 252 return(result);
emilmont 79:0c05e21ae27e 253 }
emilmont 79:0c05e21ae27e 254
emilmont 79:0c05e21ae27e 255
emilmont 79:0c05e21ae27e 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 257 {
emilmont 79:0c05e21ae27e 258 uint32_t result;
emilmont 79:0c05e21ae27e 259
emilmont 79:0c05e21ae27e 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 261 return(result);
emilmont 79:0c05e21ae27e 262 }
emilmont 79:0c05e21ae27e 263
emilmont 79:0c05e21ae27e 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 265 {
emilmont 79:0c05e21ae27e 266 uint32_t result;
emilmont 79:0c05e21ae27e 267
emilmont 79:0c05e21ae27e 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 269 return(result);
emilmont 79:0c05e21ae27e 270 }
emilmont 79:0c05e21ae27e 271
emilmont 79:0c05e21ae27e 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 273 {
emilmont 79:0c05e21ae27e 274 uint32_t result;
emilmont 79:0c05e21ae27e 275
emilmont 79:0c05e21ae27e 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 277 return(result);
emilmont 79:0c05e21ae27e 278 }
emilmont 79:0c05e21ae27e 279
emilmont 79:0c05e21ae27e 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 281 {
emilmont 79:0c05e21ae27e 282 uint32_t result;
emilmont 79:0c05e21ae27e 283
emilmont 79:0c05e21ae27e 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 285 return(result);
emilmont 79:0c05e21ae27e 286 }
emilmont 79:0c05e21ae27e 287
emilmont 79:0c05e21ae27e 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 289 {
emilmont 79:0c05e21ae27e 290 uint32_t result;
emilmont 79:0c05e21ae27e 291
emilmont 79:0c05e21ae27e 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 293 return(result);
emilmont 79:0c05e21ae27e 294 }
emilmont 79:0c05e21ae27e 295
emilmont 79:0c05e21ae27e 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 297 {
emilmont 79:0c05e21ae27e 298 uint32_t result;
emilmont 79:0c05e21ae27e 299
emilmont 79:0c05e21ae27e 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 301 return(result);
emilmont 79:0c05e21ae27e 302 }
emilmont 79:0c05e21ae27e 303
emilmont 79:0c05e21ae27e 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 305 {
emilmont 79:0c05e21ae27e 306 uint32_t result;
emilmont 79:0c05e21ae27e 307
emilmont 79:0c05e21ae27e 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 309 return(result);
emilmont 79:0c05e21ae27e 310 }
emilmont 79:0c05e21ae27e 311
emilmont 79:0c05e21ae27e 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 313 {
emilmont 79:0c05e21ae27e 314 uint32_t result;
emilmont 79:0c05e21ae27e 315
emilmont 79:0c05e21ae27e 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 317 return(result);
emilmont 79:0c05e21ae27e 318 }
emilmont 79:0c05e21ae27e 319
emilmont 79:0c05e21ae27e 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 321 {
emilmont 79:0c05e21ae27e 322 uint32_t result;
emilmont 79:0c05e21ae27e 323
emilmont 79:0c05e21ae27e 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 325 return(result);
emilmont 79:0c05e21ae27e 326 }
emilmont 79:0c05e21ae27e 327
emilmont 79:0c05e21ae27e 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 329 {
emilmont 79:0c05e21ae27e 330 uint32_t result;
emilmont 79:0c05e21ae27e 331
emilmont 79:0c05e21ae27e 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 333 return(result);
emilmont 79:0c05e21ae27e 334 }
emilmont 79:0c05e21ae27e 335
emilmont 79:0c05e21ae27e 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 337 {
emilmont 79:0c05e21ae27e 338 uint32_t result;
emilmont 79:0c05e21ae27e 339
emilmont 79:0c05e21ae27e 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 341 return(result);
emilmont 79:0c05e21ae27e 342 }
emilmont 79:0c05e21ae27e 343
emilmont 79:0c05e21ae27e 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 345 {
emilmont 79:0c05e21ae27e 346 uint32_t result;
emilmont 79:0c05e21ae27e 347
emilmont 79:0c05e21ae27e 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 349 return(result);
emilmont 79:0c05e21ae27e 350 }
emilmont 79:0c05e21ae27e 351
emilmont 79:0c05e21ae27e 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 353 {
emilmont 79:0c05e21ae27e 354 uint32_t result;
emilmont 79:0c05e21ae27e 355
emilmont 79:0c05e21ae27e 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 357 return(result);
emilmont 79:0c05e21ae27e 358 }
emilmont 79:0c05e21ae27e 359
emilmont 79:0c05e21ae27e 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 361 {
emilmont 79:0c05e21ae27e 362 uint32_t result;
emilmont 79:0c05e21ae27e 363
emilmont 79:0c05e21ae27e 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 365 return(result);
emilmont 79:0c05e21ae27e 366 }
emilmont 79:0c05e21ae27e 367
emilmont 79:0c05e21ae27e 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 369 {
emilmont 79:0c05e21ae27e 370 uint32_t result;
emilmont 79:0c05e21ae27e 371
emilmont 79:0c05e21ae27e 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 373 return(result);
emilmont 79:0c05e21ae27e 374 }
emilmont 79:0c05e21ae27e 375
emilmont 79:0c05e21ae27e 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 377 {
emilmont 79:0c05e21ae27e 378 uint32_t result;
emilmont 79:0c05e21ae27e 379
emilmont 79:0c05e21ae27e 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 381 return(result);
emilmont 79:0c05e21ae27e 382 }
emilmont 79:0c05e21ae27e 383
emilmont 79:0c05e21ae27e 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 385 {
emilmont 79:0c05e21ae27e 386 uint32_t result;
emilmont 79:0c05e21ae27e 387
emilmont 79:0c05e21ae27e 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 389 return(result);
emilmont 79:0c05e21ae27e 390 }
emilmont 79:0c05e21ae27e 391
emilmont 79:0c05e21ae27e 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 393 {
emilmont 79:0c05e21ae27e 394 uint32_t result;
emilmont 79:0c05e21ae27e 395
emilmont 79:0c05e21ae27e 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 397 return(result);
emilmont 79:0c05e21ae27e 398 }
emilmont 79:0c05e21ae27e 399
emilmont 79:0c05e21ae27e 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 401 {
emilmont 79:0c05e21ae27e 402 uint32_t result;
emilmont 79:0c05e21ae27e 403
emilmont 79:0c05e21ae27e 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 405 return(result);
emilmont 79:0c05e21ae27e 406 }
emilmont 79:0c05e21ae27e 407
emilmont 79:0c05e21ae27e 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 409 {
emilmont 79:0c05e21ae27e 410 uint32_t result;
emilmont 79:0c05e21ae27e 411
emilmont 79:0c05e21ae27e 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 413 return(result);
emilmont 79:0c05e21ae27e 414 }
emilmont 79:0c05e21ae27e 415
emilmont 79:0c05e21ae27e 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 417 {
emilmont 79:0c05e21ae27e 418 uint32_t result;
emilmont 79:0c05e21ae27e 419
emilmont 79:0c05e21ae27e 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 421 return(result);
emilmont 79:0c05e21ae27e 422 }
emilmont 79:0c05e21ae27e 423
emilmont 79:0c05e21ae27e 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 425 {
emilmont 79:0c05e21ae27e 426 uint32_t result;
emilmont 79:0c05e21ae27e 427
emilmont 79:0c05e21ae27e 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 429 return(result);
emilmont 79:0c05e21ae27e 430 }
emilmont 79:0c05e21ae27e 431
emilmont 79:0c05e21ae27e 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 433 {
emilmont 79:0c05e21ae27e 434 uint32_t result;
emilmont 79:0c05e21ae27e 435
emilmont 79:0c05e21ae27e 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 437 return(result);
emilmont 79:0c05e21ae27e 438 }
emilmont 79:0c05e21ae27e 439
emilmont 79:0c05e21ae27e 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 441 {
emilmont 79:0c05e21ae27e 442 uint32_t result;
emilmont 79:0c05e21ae27e 443
emilmont 79:0c05e21ae27e 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 445 return(result);
emilmont 79:0c05e21ae27e 446 }
emilmont 79:0c05e21ae27e 447
emilmont 79:0c05e21ae27e 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 449 {
emilmont 79:0c05e21ae27e 450 uint32_t result;
emilmont 79:0c05e21ae27e 451
emilmont 79:0c05e21ae27e 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 453 return(result);
emilmont 79:0c05e21ae27e 454 }
emilmont 79:0c05e21ae27e 455
emilmont 79:0c05e21ae27e 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 79:0c05e21ae27e 457 {
emilmont 79:0c05e21ae27e 458 uint32_t result;
emilmont 79:0c05e21ae27e 459
emilmont 79:0c05e21ae27e 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 79:0c05e21ae27e 461 return(result);
emilmont 79:0c05e21ae27e 462 }
emilmont 79:0c05e21ae27e 463
emilmont 79:0c05e21ae27e 464 #define __SSAT16(ARG1,ARG2) \
emilmont 79:0c05e21ae27e 465 ({ \
emilmont 79:0c05e21ae27e 466 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 79:0c05e21ae27e 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 79:0c05e21ae27e 468 __RES; \
emilmont 79:0c05e21ae27e 469 })
emilmont 79:0c05e21ae27e 470
emilmont 79:0c05e21ae27e 471 #define __USAT16(ARG1,ARG2) \
emilmont 79:0c05e21ae27e 472 ({ \
emilmont 79:0c05e21ae27e 473 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 79:0c05e21ae27e 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 79:0c05e21ae27e 475 __RES; \
emilmont 79:0c05e21ae27e 476 })
emilmont 79:0c05e21ae27e 477
emilmont 79:0c05e21ae27e 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
emilmont 79:0c05e21ae27e 479 {
emilmont 79:0c05e21ae27e 480 uint32_t result;
emilmont 79:0c05e21ae27e 481
emilmont 79:0c05e21ae27e 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
emilmont 79:0c05e21ae27e 483 return(result);
emilmont 79:0c05e21ae27e 484 }
emilmont 79:0c05e21ae27e 485
emilmont 79:0c05e21ae27e 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 487 {
emilmont 79:0c05e21ae27e 488 uint32_t result;
emilmont 79:0c05e21ae27e 489
emilmont 79:0c05e21ae27e 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 491 return(result);
emilmont 79:0c05e21ae27e 492 }
emilmont 79:0c05e21ae27e 493
emilmont 79:0c05e21ae27e 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
emilmont 79:0c05e21ae27e 495 {
emilmont 79:0c05e21ae27e 496 uint32_t result;
emilmont 79:0c05e21ae27e 497
emilmont 79:0c05e21ae27e 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
emilmont 79:0c05e21ae27e 499 return(result);
emilmont 79:0c05e21ae27e 500 }
emilmont 79:0c05e21ae27e 501
emilmont 79:0c05e21ae27e 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 503 {
emilmont 79:0c05e21ae27e 504 uint32_t result;
emilmont 79:0c05e21ae27e 505
emilmont 79:0c05e21ae27e 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 507 return(result);
emilmont 79:0c05e21ae27e 508 }
emilmont 79:0c05e21ae27e 509
emilmont 79:0c05e21ae27e 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 511 {
emilmont 79:0c05e21ae27e 512 uint32_t result;
emilmont 79:0c05e21ae27e 513
emilmont 79:0c05e21ae27e 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 515 return(result);
emilmont 79:0c05e21ae27e 516 }
emilmont 79:0c05e21ae27e 517
emilmont 79:0c05e21ae27e 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 519 {
emilmont 79:0c05e21ae27e 520 uint32_t result;
emilmont 79:0c05e21ae27e 521
emilmont 79:0c05e21ae27e 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 523 return(result);
emilmont 79:0c05e21ae27e 524 }
emilmont 79:0c05e21ae27e 525
emilmont 79:0c05e21ae27e 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 79:0c05e21ae27e 527 {
emilmont 79:0c05e21ae27e 528 uint32_t result;
emilmont 79:0c05e21ae27e 529
emilmont 79:0c05e21ae27e 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 79:0c05e21ae27e 531 return(result);
emilmont 79:0c05e21ae27e 532 }
emilmont 79:0c05e21ae27e 533
emilmont 79:0c05e21ae27e 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 79:0c05e21ae27e 535 {
emilmont 79:0c05e21ae27e 536 uint32_t result;
emilmont 79:0c05e21ae27e 537
emilmont 79:0c05e21ae27e 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 79:0c05e21ae27e 539 return(result);
emilmont 79:0c05e21ae27e 540 }
emilmont 79:0c05e21ae27e 541
emilmont 79:0c05e21ae27e 542 #define __SMLALD(ARG1,ARG2,ARG3) \
emilmont 79:0c05e21ae27e 543 ({ \
emilmont 79:0c05e21ae27e 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
emilmont 79:0c05e21ae27e 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 79:0c05e21ae27e 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 79:0c05e21ae27e 547 })
emilmont 79:0c05e21ae27e 548
emilmont 79:0c05e21ae27e 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
emilmont 79:0c05e21ae27e 550 ({ \
emilmont 79:0c05e21ae27e 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
emilmont 79:0c05e21ae27e 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 79:0c05e21ae27e 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 79:0c05e21ae27e 554 })
emilmont 79:0c05e21ae27e 555
emilmont 79:0c05e21ae27e 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 557 {
emilmont 79:0c05e21ae27e 558 uint32_t result;
emilmont 79:0c05e21ae27e 559
emilmont 79:0c05e21ae27e 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 561 return(result);
emilmont 79:0c05e21ae27e 562 }
emilmont 79:0c05e21ae27e 563
emilmont 79:0c05e21ae27e 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 565 {
emilmont 79:0c05e21ae27e 566 uint32_t result;
emilmont 79:0c05e21ae27e 567
emilmont 79:0c05e21ae27e 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 569 return(result);
emilmont 79:0c05e21ae27e 570 }
emilmont 79:0c05e21ae27e 571
emilmont 79:0c05e21ae27e 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 79:0c05e21ae27e 573 {
emilmont 79:0c05e21ae27e 574 uint32_t result;
emilmont 79:0c05e21ae27e 575
emilmont 79:0c05e21ae27e 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 79:0c05e21ae27e 577 return(result);
emilmont 79:0c05e21ae27e 578 }
emilmont 79:0c05e21ae27e 579
emilmont 79:0c05e21ae27e 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 79:0c05e21ae27e 581 {
emilmont 79:0c05e21ae27e 582 uint32_t result;
emilmont 79:0c05e21ae27e 583
emilmont 79:0c05e21ae27e 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 79:0c05e21ae27e 585 return(result);
emilmont 79:0c05e21ae27e 586 }
emilmont 79:0c05e21ae27e 587
emilmont 79:0c05e21ae27e 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
emilmont 79:0c05e21ae27e 589 ({ \
emilmont 79:0c05e21ae27e 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
emilmont 79:0c05e21ae27e 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 79:0c05e21ae27e 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 79:0c05e21ae27e 593 })
emilmont 79:0c05e21ae27e 594
emilmont 79:0c05e21ae27e 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
emilmont 79:0c05e21ae27e 596 ({ \
emilmont 79:0c05e21ae27e 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
emilmont 79:0c05e21ae27e 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 79:0c05e21ae27e 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 79:0c05e21ae27e 600 })
emilmont 79:0c05e21ae27e 601
emilmont 79:0c05e21ae27e 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 603 {
emilmont 79:0c05e21ae27e 604 uint32_t result;
emilmont 79:0c05e21ae27e 605
emilmont 79:0c05e21ae27e 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 607 return(result);
emilmont 79:0c05e21ae27e 608 }
emilmont 79:0c05e21ae27e 609
emilmont 79:0c05e21ae27e 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 611 {
emilmont 79:0c05e21ae27e 612 uint32_t result;
emilmont 79:0c05e21ae27e 613
emilmont 79:0c05e21ae27e 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 615 return(result);
emilmont 79:0c05e21ae27e 616 }
emilmont 79:0c05e21ae27e 617
emilmont 79:0c05e21ae27e 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
emilmont 79:0c05e21ae27e 619 {
emilmont 79:0c05e21ae27e 620 uint32_t result;
emilmont 79:0c05e21ae27e 621
emilmont 79:0c05e21ae27e 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 79:0c05e21ae27e 623 return(result);
emilmont 79:0c05e21ae27e 624 }
emilmont 79:0c05e21ae27e 625
emilmont 79:0c05e21ae27e 626 #define __PKHBT(ARG1,ARG2,ARG3) \
emilmont 79:0c05e21ae27e 627 ({ \
emilmont 79:0c05e21ae27e 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
emilmont 79:0c05e21ae27e 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
emilmont 79:0c05e21ae27e 630 __RES; \
emilmont 79:0c05e21ae27e 631 })
emilmont 79:0c05e21ae27e 632
emilmont 79:0c05e21ae27e 633 #define __PKHTB(ARG1,ARG2,ARG3) \
emilmont 79:0c05e21ae27e 634 ({ \
emilmont 79:0c05e21ae27e 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
emilmont 79:0c05e21ae27e 636 if (ARG3 == 0) \
emilmont 79:0c05e21ae27e 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
emilmont 79:0c05e21ae27e 638 else \
emilmont 79:0c05e21ae27e 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
emilmont 79:0c05e21ae27e 640 __RES; \
emilmont 79:0c05e21ae27e 641 })
emilmont 79:0c05e21ae27e 642
emilmont 79:0c05e21ae27e 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
emilmont 79:0c05e21ae27e 644 {
emilmont 79:0c05e21ae27e 645 int32_t result;
emilmont 79:0c05e21ae27e 646
emilmont 79:0c05e21ae27e 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
emilmont 79:0c05e21ae27e 648 return(result);
emilmont 79:0c05e21ae27e 649 }
emilmont 79:0c05e21ae27e 650
emilmont 79:0c05e21ae27e 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 652
emilmont 79:0c05e21ae27e 653
emilmont 79:0c05e21ae27e 654
emilmont 79:0c05e21ae27e 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 79:0c05e21ae27e 656 /* TASKING carm specific functions */
emilmont 79:0c05e21ae27e 657
emilmont 79:0c05e21ae27e 658
emilmont 79:0c05e21ae27e 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 660 /* not yet supported */
emilmont 79:0c05e21ae27e 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 79:0c05e21ae27e 662
emilmont 79:0c05e21ae27e 663
emilmont 79:0c05e21ae27e 664 #endif
emilmont 79:0c05e21ae27e 665
emilmont 79:0c05e21ae27e 666 /*@} end of group CMSIS_SIMD_intrinsics */
emilmont 79:0c05e21ae27e 667
emilmont 79:0c05e21ae27e 668
emilmont 79:0c05e21ae27e 669 #endif /* __CORE_CM4_SIMD_H */
emilmont 79:0c05e21ae27e 670
emilmont 79:0c05e21ae27e 671 #ifdef __cplusplus
emilmont 79:0c05e21ae27e 672 }
emilmont 79:0c05e21ae27e 673 #endif