mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC1549/core_cm4.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:: <>
Date:: Tue Mar 14 16:20:51 2017 +0000
Revision:: 138:093f2bd7b9eb
Parent:: 131:faff56e089b2
Child:: 145:64910690c574

Release 138 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	79:0c05e21ae27e	1	/************************************************************************//
emilmont	79:0c05e21ae27e	2	* @file core_cm4.h
emilmont	79:0c05e21ae27e	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Kojto	110:165afa46840b	4	* @version V4.10
Kojto	110:165afa46840b	5	* @date 18. March 2015
emilmont	79:0c05e21ae27e	6	*
emilmont	79:0c05e21ae27e	7	* @note
emilmont	79:0c05e21ae27e	8	*
emilmont	79:0c05e21ae27e	9	******************************************************************************/
Kojto	110:165afa46840b	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont	79:0c05e21ae27e	11
emilmont	79:0c05e21ae27e	12	All rights reserved.
emilmont	79:0c05e21ae27e	13	Redistribution and use in source and binary forms, with or without
emilmont	79:0c05e21ae27e	14	modification, are permitted provided that the following conditions are met:
emilmont	79:0c05e21ae27e	15	- Redistributions of source code must retain the above copyright
emilmont	79:0c05e21ae27e	16	notice, this list of conditions and the following disclaimer.
emilmont	79:0c05e21ae27e	17	- Redistributions in binary form must reproduce the above copyright
emilmont	79:0c05e21ae27e	18	notice, this list of conditions and the following disclaimer in the
emilmont	79:0c05e21ae27e	19	documentation and/or other materials provided with the distribution.
emilmont	79:0c05e21ae27e	20	- Neither the name of ARM nor the names of its contributors may be used
emilmont	79:0c05e21ae27e	21	to endorse or promote products derived from this software without
emilmont	79:0c05e21ae27e	22	specific prior written permission.
emilmont	79:0c05e21ae27e	23	*
emilmont	79:0c05e21ae27e	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	79:0c05e21ae27e	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	79:0c05e21ae27e	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont	79:0c05e21ae27e	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont	79:0c05e21ae27e	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont	79:0c05e21ae27e	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont	79:0c05e21ae27e	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont	79:0c05e21ae27e	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont	79:0c05e21ae27e	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont	79:0c05e21ae27e	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont	79:0c05e21ae27e	34	POSSIBILITY OF SUCH DAMAGE.
emilmont	79:0c05e21ae27e	35	---------------------------------------------------------------------------*/
emilmont	79:0c05e21ae27e	36
emilmont	79:0c05e21ae27e	37
emilmont	79:0c05e21ae27e	38	#if defined ( __ICCARM__ )
emilmont	79:0c05e21ae27e	39	#pragma system_include /* treat file as system include file for MISRA check */
emilmont	79:0c05e21ae27e	40	#endif
emilmont	79:0c05e21ae27e	41
Kojto	110:165afa46840b	42	#ifndef __CORE_CM4_H_GENERIC
Kojto	110:165afa46840b	43	#define __CORE_CM4_H_GENERIC
Kojto	110:165afa46840b	44
emilmont	79:0c05e21ae27e	45	#ifdef __cplusplus
emilmont	79:0c05e21ae27e	46	extern "C" {
emilmont	79:0c05e21ae27e	47	#endif
emilmont	79:0c05e21ae27e	48
emilmont	79:0c05e21ae27e	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont	79:0c05e21ae27e	50	CMSIS violates the following MISRA-C:2004 rules:
emilmont	79:0c05e21ae27e	51
emilmont	79:0c05e21ae27e	52	\li Required Rule 8.5, object/function definition in header file.<br>
emilmont	79:0c05e21ae27e	53	Function definitions in header files are used to allow 'inlining'.
emilmont	79:0c05e21ae27e	54
emilmont	79:0c05e21ae27e	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont	79:0c05e21ae27e	56	Unions are used for effective representation of core registers.
emilmont	79:0c05e21ae27e	57
emilmont	79:0c05e21ae27e	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont	79:0c05e21ae27e	59	Function-like macros are used to allow more efficient code.
emilmont	79:0c05e21ae27e	60	*/
emilmont	79:0c05e21ae27e	61
emilmont	79:0c05e21ae27e	62
emilmont	79:0c05e21ae27e	63	/*******************************************************************************
emilmont	79:0c05e21ae27e	64	* CMSIS definitions
emilmont	79:0c05e21ae27e	65	******************************************************************************/
emilmont	79:0c05e21ae27e	66	/** \ingroup Cortex_M4
emilmont	79:0c05e21ae27e	67	@{
emilmont	79:0c05e21ae27e	68	*/
emilmont	79:0c05e21ae27e	69
emilmont	79:0c05e21ae27e	70	/* CMSIS CM4 definitions */
Kojto	110:165afa46840b	71	#define __CM4_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Kojto	110:165afa46840b	72	#define __CM4_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
emilmont	79:0c05e21ae27e	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
emilmont	79:0c05e21ae27e	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
emilmont	79:0c05e21ae27e	75
emilmont	79:0c05e21ae27e	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
emilmont	79:0c05e21ae27e	77
emilmont	79:0c05e21ae27e	78
emilmont	79:0c05e21ae27e	79	#if defined ( __CC_ARM )
emilmont	79:0c05e21ae27e	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
emilmont	79:0c05e21ae27e	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
emilmont	79:0c05e21ae27e	82	#define __STATIC_INLINE static __inline
emilmont	79:0c05e21ae27e	83
Kojto	110:165afa46840b	84	#elif defined ( __GNUC__ )
Kojto	110:165afa46840b	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	110:165afa46840b	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	110:165afa46840b	87	#define __STATIC_INLINE static inline
Kojto	110:165afa46840b	88
emilmont	79:0c05e21ae27e	89	#elif defined ( __ICCARM__ )
emilmont	79:0c05e21ae27e	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
emilmont	79:0c05e21ae27e	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
emilmont	79:0c05e21ae27e	92	#define __STATIC_INLINE static inline
emilmont	79:0c05e21ae27e	93
emilmont	79:0c05e21ae27e	94	#elif defined ( __TMS470__ )
emilmont	79:0c05e21ae27e	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
emilmont	79:0c05e21ae27e	96	#define __STATIC_INLINE static inline
emilmont	79:0c05e21ae27e	97
emilmont	79:0c05e21ae27e	98	#elif defined ( __TASKING__ )
emilmont	79:0c05e21ae27e	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
emilmont	79:0c05e21ae27e	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
emilmont	79:0c05e21ae27e	101	#define __STATIC_INLINE static inline
emilmont	79:0c05e21ae27e	102
Kojto	110:165afa46840b	103	#elif defined ( __CSMC__ )
Kojto	110:165afa46840b	104	#define __packed
Kojto	110:165afa46840b	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Kojto	110:165afa46840b	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Kojto	110:165afa46840b	107	#define __STATIC_INLINE static inline
Kojto	110:165afa46840b	108
emilmont	79:0c05e21ae27e	109	#endif
emilmont	79:0c05e21ae27e	110
Kojto	110:165afa46840b	111	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	110:165afa46840b	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
emilmont	79:0c05e21ae27e	113	*/
emilmont	79:0c05e21ae27e	114	#if defined ( __CC_ARM )
emilmont	79:0c05e21ae27e	115	#if defined __TARGET_FPU_VFP
emilmont	79:0c05e21ae27e	116	#if (__FPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	117	#define __FPU_USED 1
emilmont	79:0c05e21ae27e	118	#else
emilmont	79:0c05e21ae27e	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	120	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	121	#endif
emilmont	79:0c05e21ae27e	122	#else
emilmont	79:0c05e21ae27e	123	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	124	#endif
emilmont	79:0c05e21ae27e	125
Kojto	110:165afa46840b	126	#elif defined ( __GNUC__ )
Kojto	110:165afa46840b	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	110:165afa46840b	128	#if (__FPU_PRESENT == 1)
Kojto	110:165afa46840b	129	#define __FPU_USED 1
Kojto	110:165afa46840b	130	#else
Kojto	110:165afa46840b	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	110:165afa46840b	132	#define __FPU_USED 0
Kojto	110:165afa46840b	133	#endif
Kojto	110:165afa46840b	134	#else
Kojto	110:165afa46840b	135	#define __FPU_USED 0
Kojto	110:165afa46840b	136	#endif
Kojto	110:165afa46840b	137
emilmont	79:0c05e21ae27e	138	#elif defined ( __ICCARM__ )
emilmont	79:0c05e21ae27e	139	#if defined __ARMVFP__
emilmont	79:0c05e21ae27e	140	#if (__FPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	141	#define __FPU_USED 1
emilmont	79:0c05e21ae27e	142	#else
emilmont	79:0c05e21ae27e	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	144	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	145	#endif
emilmont	79:0c05e21ae27e	146	#else
emilmont	79:0c05e21ae27e	147	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	148	#endif
emilmont	79:0c05e21ae27e	149
emilmont	79:0c05e21ae27e	150	#elif defined ( __TMS470__ )
emilmont	79:0c05e21ae27e	151	#if defined __TI_VFP_SUPPORT__
emilmont	79:0c05e21ae27e	152	#if (__FPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	153	#define __FPU_USED 1
emilmont	79:0c05e21ae27e	154	#else
emilmont	79:0c05e21ae27e	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	156	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	157	#endif
emilmont	79:0c05e21ae27e	158	#else
emilmont	79:0c05e21ae27e	159	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	160	#endif
emilmont	79:0c05e21ae27e	161
Kojto	110:165afa46840b	162	#elif defined ( __TASKING__ )
Kojto	110:165afa46840b	163	#if defined __FPU_VFP__
emilmont	79:0c05e21ae27e	164	#if (__FPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	165	#define __FPU_USED 1
emilmont	79:0c05e21ae27e	166	#else
Kojto	110:165afa46840b	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	168	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	169	#endif
emilmont	79:0c05e21ae27e	170	#else
emilmont	79:0c05e21ae27e	171	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	172	#endif
emilmont	79:0c05e21ae27e	173
Kojto	110:165afa46840b	174	#elif defined ( __CSMC__ ) /* Cosmic */
Kojto	110:165afa46840b	175	#if ( __CSMC__ & 0x400) // FPU present for parser
emilmont	79:0c05e21ae27e	176	#if (__FPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	177	#define __FPU_USED 1
emilmont	79:0c05e21ae27e	178	#else
emilmont	79:0c05e21ae27e	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	79:0c05e21ae27e	180	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	181	#endif
emilmont	79:0c05e21ae27e	182	#else
emilmont	79:0c05e21ae27e	183	#define __FPU_USED 0
emilmont	79:0c05e21ae27e	184	#endif
emilmont	79:0c05e21ae27e	185	#endif
emilmont	79:0c05e21ae27e	186
emilmont	79:0c05e21ae27e	187	#include <stdint.h> /* standard types definitions */
emilmont	79:0c05e21ae27e	188	#include <core_cmInstr.h> /* Core Instruction Access */
emilmont	79:0c05e21ae27e	189	#include <core_cmFunc.h> /* Core Function Access */
Kojto	110:165afa46840b	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto	110:165afa46840b	191
Kojto	110:165afa46840b	192	#ifdef __cplusplus
Kojto	110:165afa46840b	193	}
Kojto	110:165afa46840b	194	#endif
emilmont	79:0c05e21ae27e	195
emilmont	79:0c05e21ae27e	196	#endif /* __CORE_CM4_H_GENERIC */
emilmont	79:0c05e21ae27e	197
emilmont	79:0c05e21ae27e	198	#ifndef __CMSIS_GENERIC
emilmont	79:0c05e21ae27e	199
emilmont	79:0c05e21ae27e	200	#ifndef __CORE_CM4_H_DEPENDANT
emilmont	79:0c05e21ae27e	201	#define __CORE_CM4_H_DEPENDANT
emilmont	79:0c05e21ae27e	202
Kojto	110:165afa46840b	203	#ifdef __cplusplus
Kojto	110:165afa46840b	204	extern "C" {
Kojto	110:165afa46840b	205	#endif
Kojto	110:165afa46840b	206
emilmont	79:0c05e21ae27e	207	/* check device defines and use defaults */
emilmont	79:0c05e21ae27e	208	#if defined __CHECK_DEVICE_DEFINES
emilmont	79:0c05e21ae27e	209	#ifndef __CM4_REV
emilmont	79:0c05e21ae27e	210	#define __CM4_REV 0x0000
emilmont	79:0c05e21ae27e	211	#warning "__CM4_REV not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	212	#endif
emilmont	79:0c05e21ae27e	213
emilmont	79:0c05e21ae27e	214	#ifndef __FPU_PRESENT
emilmont	79:0c05e21ae27e	215	#define __FPU_PRESENT 0
emilmont	79:0c05e21ae27e	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	217	#endif
emilmont	79:0c05e21ae27e	218
emilmont	79:0c05e21ae27e	219	#ifndef __MPU_PRESENT
emilmont	79:0c05e21ae27e	220	#define __MPU_PRESENT 0
emilmont	79:0c05e21ae27e	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	222	#endif
emilmont	79:0c05e21ae27e	223
emilmont	79:0c05e21ae27e	224	#ifndef __NVIC_PRIO_BITS
emilmont	79:0c05e21ae27e	225	#define __NVIC_PRIO_BITS 4
emilmont	79:0c05e21ae27e	226	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	227	#endif
emilmont	79:0c05e21ae27e	228
emilmont	79:0c05e21ae27e	229	#ifndef __Vendor_SysTickConfig
emilmont	79:0c05e21ae27e	230	#define __Vendor_SysTickConfig 0
emilmont	79:0c05e21ae27e	231	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont	79:0c05e21ae27e	232	#endif
emilmont	79:0c05e21ae27e	233	#endif
emilmont	79:0c05e21ae27e	234
emilmont	79:0c05e21ae27e	235	/* IO definitions (access restrictions to peripheral registers) */
emilmont	79:0c05e21ae27e	236	/**
emilmont	79:0c05e21ae27e	237	\defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont	79:0c05e21ae27e	238
emilmont	79:0c05e21ae27e	239	<strong>IO Type Qualifiers</strong> are used
emilmont	79:0c05e21ae27e	240	\li to specify the access to peripheral variables.
emilmont	79:0c05e21ae27e	241	\li for automatic generation of peripheral register debug information.
emilmont	79:0c05e21ae27e	242	*/
emilmont	79:0c05e21ae27e	243	#ifdef __cplusplus
emilmont	79:0c05e21ae27e	244	#define __I volatile /!< Defines 'read only' permissions /
emilmont	79:0c05e21ae27e	245	#else
emilmont	79:0c05e21ae27e	246	#define __I volatile const /!< Defines 'read only' permissions /
emilmont	79:0c05e21ae27e	247	#endif
emilmont	79:0c05e21ae27e	248	#define __O volatile /!< Defines 'write only' permissions /
emilmont	79:0c05e21ae27e	249	#define __IO volatile /!< Defines 'read / write' permissions /
emilmont	79:0c05e21ae27e	250
<>	128:9bcdf88f62b0	251	#ifdef __cplusplus
<>	128:9bcdf88f62b0	252	#define __IM volatile /!< Defines 'read only' permissions /
<>	128:9bcdf88f62b0	253	#else
<>	128:9bcdf88f62b0	254	#define __IM volatile const /!< Defines 'read only' permissions /
<>	128:9bcdf88f62b0	255	#endif
<>	128:9bcdf88f62b0	256	#define __OM volatile /!< Defines 'write only' permissions /
<>	128:9bcdf88f62b0	257	#define __IOM volatile /!< Defines 'read / write' permissions /
<>	128:9bcdf88f62b0	258
emilmont	79:0c05e21ae27e	259	/@} end of group Cortex_M4 /
emilmont	79:0c05e21ae27e	260
emilmont	79:0c05e21ae27e	261
emilmont	79:0c05e21ae27e	262
emilmont	79:0c05e21ae27e	263	/*******************************************************************************
emilmont	79:0c05e21ae27e	264	* Register Abstraction
emilmont	79:0c05e21ae27e	265	Core Register contain:
emilmont	79:0c05e21ae27e	266	- Core Register
emilmont	79:0c05e21ae27e	267	- Core NVIC Register
emilmont	79:0c05e21ae27e	268	- Core SCB Register
emilmont	79:0c05e21ae27e	269	- Core SysTick Register
emilmont	79:0c05e21ae27e	270	- Core Debug Register
emilmont	79:0c05e21ae27e	271	- Core MPU Register
emilmont	79:0c05e21ae27e	272	- Core FPU Register
emilmont	79:0c05e21ae27e	273	******************************************************************************/
emilmont	79:0c05e21ae27e	274	/** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont	79:0c05e21ae27e	275	\brief Type definitions and defines for Cortex-M processor based devices.
emilmont	79:0c05e21ae27e	276	*/
emilmont	79:0c05e21ae27e	277
emilmont	79:0c05e21ae27e	278	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	279	\defgroup CMSIS_CORE Status and Control Registers
emilmont	79:0c05e21ae27e	280	\brief Core Register type definitions.
emilmont	79:0c05e21ae27e	281	@{
emilmont	79:0c05e21ae27e	282	*/
emilmont	79:0c05e21ae27e	283
emilmont	79:0c05e21ae27e	284	/** \brief Union type to access the Application Program Status Register (APSR).
emilmont	79:0c05e21ae27e	285	*/
emilmont	79:0c05e21ae27e	286	typedef union
emilmont	79:0c05e21ae27e	287	{
emilmont	79:0c05e21ae27e	288	struct
emilmont	79:0c05e21ae27e	289	{
emilmont	79:0c05e21ae27e	290	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
emilmont	79:0c05e21ae27e	291	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	79:0c05e21ae27e	292	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
emilmont	79:0c05e21ae27e	293	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	79:0c05e21ae27e	294	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	79:0c05e21ae27e	295	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	79:0c05e21ae27e	296	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	79:0c05e21ae27e	297	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	79:0c05e21ae27e	298	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	299	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	300	} APSR_Type;
emilmont	79:0c05e21ae27e	301
Kojto	110:165afa46840b	302	/* APSR Register Definitions */
Kojto	110:165afa46840b	303	#define APSR_N_Pos 31 /!< APSR: N Position /
Kojto	110:165afa46840b	304	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	110:165afa46840b	305
Kojto	110:165afa46840b	306	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Kojto	110:165afa46840b	307	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	110:165afa46840b	308
Kojto	110:165afa46840b	309	#define APSR_C_Pos 29 /!< APSR: C Position /
Kojto	110:165afa46840b	310	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	110:165afa46840b	311
Kojto	110:165afa46840b	312	#define APSR_V_Pos 28 /!< APSR: V Position /
Kojto	110:165afa46840b	313	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	110:165afa46840b	314
Kojto	110:165afa46840b	315	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Kojto	110:165afa46840b	316	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	110:165afa46840b	317
Kojto	110:165afa46840b	318	#define APSR_GE_Pos 16 /!< APSR: GE Position /
Kojto	110:165afa46840b	319	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Kojto	110:165afa46840b	320
emilmont	79:0c05e21ae27e	321
emilmont	79:0c05e21ae27e	322	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont	79:0c05e21ae27e	323	*/
emilmont	79:0c05e21ae27e	324	typedef union
emilmont	79:0c05e21ae27e	325	{
emilmont	79:0c05e21ae27e	326	struct
emilmont	79:0c05e21ae27e	327	{
emilmont	79:0c05e21ae27e	328	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	79:0c05e21ae27e	329	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
emilmont	79:0c05e21ae27e	330	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	331	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	332	} IPSR_Type;
emilmont	79:0c05e21ae27e	333
Kojto	110:165afa46840b	334	/* IPSR Register Definitions */
Kojto	110:165afa46840b	335	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Kojto	110:165afa46840b	336	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	110:165afa46840b	337
emilmont	79:0c05e21ae27e	338
emilmont	79:0c05e21ae27e	339	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont	79:0c05e21ae27e	340	*/
emilmont	79:0c05e21ae27e	341	typedef union
emilmont	79:0c05e21ae27e	342	{
emilmont	79:0c05e21ae27e	343	struct
emilmont	79:0c05e21ae27e	344	{
emilmont	79:0c05e21ae27e	345	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	79:0c05e21ae27e	346	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
emilmont	79:0c05e21ae27e	347	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	79:0c05e21ae27e	348	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
emilmont	79:0c05e21ae27e	349	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
emilmont	79:0c05e21ae27e	350	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
emilmont	79:0c05e21ae27e	351	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	79:0c05e21ae27e	352	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	79:0c05e21ae27e	353	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	79:0c05e21ae27e	354	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	79:0c05e21ae27e	355	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	79:0c05e21ae27e	356	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	357	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	358	} xPSR_Type;
emilmont	79:0c05e21ae27e	359
Kojto	110:165afa46840b	360	/* xPSR Register Definitions */
Kojto	110:165afa46840b	361	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Kojto	110:165afa46840b	362	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	110:165afa46840b	363
Kojto	110:165afa46840b	364	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Kojto	110:165afa46840b	365	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	110:165afa46840b	366
Kojto	110:165afa46840b	367	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Kojto	110:165afa46840b	368	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	110:165afa46840b	369
Kojto	110:165afa46840b	370	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Kojto	110:165afa46840b	371	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	110:165afa46840b	372
Kojto	110:165afa46840b	373	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Kojto	110:165afa46840b	374	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	110:165afa46840b	375
Kojto	110:165afa46840b	376	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Kojto	110:165afa46840b	377	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	110:165afa46840b	378
Kojto	110:165afa46840b	379	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Kojto	110:165afa46840b	380	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	110:165afa46840b	381
Kojto	110:165afa46840b	382	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
Kojto	110:165afa46840b	383	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Kojto	110:165afa46840b	384
Kojto	110:165afa46840b	385	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Kojto	110:165afa46840b	386	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	110:165afa46840b	387
emilmont	79:0c05e21ae27e	388
emilmont	79:0c05e21ae27e	389	/** \brief Union type to access the Control Registers (CONTROL).
emilmont	79:0c05e21ae27e	390	*/
emilmont	79:0c05e21ae27e	391	typedef union
emilmont	79:0c05e21ae27e	392	{
emilmont	79:0c05e21ae27e	393	struct
emilmont	79:0c05e21ae27e	394	{
emilmont	79:0c05e21ae27e	395	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
emilmont	79:0c05e21ae27e	396	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
emilmont	79:0c05e21ae27e	397	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
emilmont	79:0c05e21ae27e	398	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
emilmont	79:0c05e21ae27e	399	} b; /!< Structure used for bit access /
emilmont	79:0c05e21ae27e	400	uint32_t w; /!< Type used for word access /
emilmont	79:0c05e21ae27e	401	} CONTROL_Type;
emilmont	79:0c05e21ae27e	402
Kojto	110:165afa46840b	403	/* CONTROL Register Definitions */
Kojto	110:165afa46840b	404	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
Kojto	110:165afa46840b	405	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Kojto	110:165afa46840b	406
Kojto	110:165afa46840b	407	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Kojto	110:165afa46840b	408	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	110:165afa46840b	409
Kojto	110:165afa46840b	410	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Kojto	110:165afa46840b	411	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	110:165afa46840b	412
emilmont	79:0c05e21ae27e	413	/@} end of group CMSIS_CORE /
emilmont	79:0c05e21ae27e	414
emilmont	79:0c05e21ae27e	415
emilmont	79:0c05e21ae27e	416	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	417	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont	79:0c05e21ae27e	418	\brief Type definitions for the NVIC Registers
emilmont	79:0c05e21ae27e	419	@{
emilmont	79:0c05e21ae27e	420	*/
emilmont	79:0c05e21ae27e	421
emilmont	79:0c05e21ae27e	422	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont	79:0c05e21ae27e	423	*/
emilmont	79:0c05e21ae27e	424	typedef struct
emilmont	79:0c05e21ae27e	425	{
emilmont	79:0c05e21ae27e	426	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
emilmont	79:0c05e21ae27e	427	uint32_t RESERVED0[24];
emilmont	79:0c05e21ae27e	428	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
emilmont	79:0c05e21ae27e	429	uint32_t RSERVED1[24];
emilmont	79:0c05e21ae27e	430	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
emilmont	79:0c05e21ae27e	431	uint32_t RESERVED2[24];
emilmont	79:0c05e21ae27e	432	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
emilmont	79:0c05e21ae27e	433	uint32_t RESERVED3[24];
emilmont	79:0c05e21ae27e	434	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
emilmont	79:0c05e21ae27e	435	uint32_t RESERVED4[56];
emilmont	79:0c05e21ae27e	436	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
emilmont	79:0c05e21ae27e	437	uint32_t RESERVED5[644];
emilmont	79:0c05e21ae27e	438	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
emilmont	79:0c05e21ae27e	439	} NVIC_Type;
emilmont	79:0c05e21ae27e	440
emilmont	79:0c05e21ae27e	441	/* Software Triggered Interrupt Register Definitions */
emilmont	79:0c05e21ae27e	442	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	110:165afa46840b	443	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
emilmont	79:0c05e21ae27e	444
emilmont	79:0c05e21ae27e	445	/@} end of group CMSIS_NVIC /
emilmont	79:0c05e21ae27e	446
emilmont	79:0c05e21ae27e	447
emilmont	79:0c05e21ae27e	448	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	449	\defgroup CMSIS_SCB System Control Block (SCB)
emilmont	79:0c05e21ae27e	450	\brief Type definitions for the System Control Block Registers
emilmont	79:0c05e21ae27e	451	@{
emilmont	79:0c05e21ae27e	452	*/
emilmont	79:0c05e21ae27e	453
emilmont	79:0c05e21ae27e	454	/** \brief Structure type to access the System Control Block (SCB).
emilmont	79:0c05e21ae27e	455	*/
emilmont	79:0c05e21ae27e	456	typedef struct
emilmont	79:0c05e21ae27e	457	{
emilmont	79:0c05e21ae27e	458	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
emilmont	79:0c05e21ae27e	459	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
emilmont	79:0c05e21ae27e	460	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
emilmont	79:0c05e21ae27e	461	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
emilmont	79:0c05e21ae27e	462	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
emilmont	79:0c05e21ae27e	463	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
emilmont	79:0c05e21ae27e	464	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
emilmont	79:0c05e21ae27e	465	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
emilmont	79:0c05e21ae27e	466	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
emilmont	79:0c05e21ae27e	467	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
emilmont	79:0c05e21ae27e	468	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
emilmont	79:0c05e21ae27e	469	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
emilmont	79:0c05e21ae27e	470	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
emilmont	79:0c05e21ae27e	471	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
emilmont	79:0c05e21ae27e	472	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
emilmont	79:0c05e21ae27e	473	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
emilmont	79:0c05e21ae27e	474	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
emilmont	79:0c05e21ae27e	475	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
emilmont	79:0c05e21ae27e	476	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
emilmont	79:0c05e21ae27e	477	uint32_t RESERVED0[5];
emilmont	79:0c05e21ae27e	478	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
emilmont	79:0c05e21ae27e	479	} SCB_Type;
emilmont	79:0c05e21ae27e	480
emilmont	79:0c05e21ae27e	481	/* SCB CPUID Register Definitions */
emilmont	79:0c05e21ae27e	482	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
emilmont	79:0c05e21ae27e	483	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
emilmont	79:0c05e21ae27e	484
emilmont	79:0c05e21ae27e	485	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
emilmont	79:0c05e21ae27e	486	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
emilmont	79:0c05e21ae27e	487
emilmont	79:0c05e21ae27e	488	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
emilmont	79:0c05e21ae27e	489	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
emilmont	79:0c05e21ae27e	490
emilmont	79:0c05e21ae27e	491	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
emilmont	79:0c05e21ae27e	492	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
emilmont	79:0c05e21ae27e	493
emilmont	79:0c05e21ae27e	494	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	110:165afa46840b	495	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
emilmont	79:0c05e21ae27e	496
emilmont	79:0c05e21ae27e	497	/* SCB Interrupt Control State Register Definitions */
emilmont	79:0c05e21ae27e	498	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
emilmont	79:0c05e21ae27e	499	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
emilmont	79:0c05e21ae27e	500
emilmont	79:0c05e21ae27e	501	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
emilmont	79:0c05e21ae27e	502	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
emilmont	79:0c05e21ae27e	503
emilmont	79:0c05e21ae27e	504	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
emilmont	79:0c05e21ae27e	505	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
emilmont	79:0c05e21ae27e	506
emilmont	79:0c05e21ae27e	507	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
emilmont	79:0c05e21ae27e	508	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
emilmont	79:0c05e21ae27e	509
emilmont	79:0c05e21ae27e	510	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
emilmont	79:0c05e21ae27e	511	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
emilmont	79:0c05e21ae27e	512
emilmont	79:0c05e21ae27e	513	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
emilmont	79:0c05e21ae27e	514	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
emilmont	79:0c05e21ae27e	515
emilmont	79:0c05e21ae27e	516	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
emilmont	79:0c05e21ae27e	517	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
emilmont	79:0c05e21ae27e	518
emilmont	79:0c05e21ae27e	519	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
emilmont	79:0c05e21ae27e	520	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
emilmont	79:0c05e21ae27e	521
emilmont	79:0c05e21ae27e	522	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
emilmont	79:0c05e21ae27e	523	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
emilmont	79:0c05e21ae27e	524
emilmont	79:0c05e21ae27e	525	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	110:165afa46840b	526	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
emilmont	79:0c05e21ae27e	527
emilmont	79:0c05e21ae27e	528	/* SCB Vector Table Offset Register Definitions */
emilmont	79:0c05e21ae27e	529	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	79:0c05e21ae27e	530	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	79:0c05e21ae27e	531
emilmont	79:0c05e21ae27e	532	/* SCB Application Interrupt and Reset Control Register Definitions */
emilmont	79:0c05e21ae27e	533	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
emilmont	79:0c05e21ae27e	534	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
emilmont	79:0c05e21ae27e	535
emilmont	79:0c05e21ae27e	536	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
emilmont	79:0c05e21ae27e	537	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
emilmont	79:0c05e21ae27e	538
emilmont	79:0c05e21ae27e	539	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
emilmont	79:0c05e21ae27e	540	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
emilmont	79:0c05e21ae27e	541
emilmont	79:0c05e21ae27e	542	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
emilmont	79:0c05e21ae27e	543	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
emilmont	79:0c05e21ae27e	544
emilmont	79:0c05e21ae27e	545	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
emilmont	79:0c05e21ae27e	546	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
emilmont	79:0c05e21ae27e	547
emilmont	79:0c05e21ae27e	548	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
emilmont	79:0c05e21ae27e	549	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
emilmont	79:0c05e21ae27e	550
emilmont	79:0c05e21ae27e	551	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	110:165afa46840b	552	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
emilmont	79:0c05e21ae27e	553
emilmont	79:0c05e21ae27e	554	/* SCB System Control Register Definitions */
emilmont	79:0c05e21ae27e	555	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
emilmont	79:0c05e21ae27e	556	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
emilmont	79:0c05e21ae27e	557
emilmont	79:0c05e21ae27e	558	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
emilmont	79:0c05e21ae27e	559	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
emilmont	79:0c05e21ae27e	560
emilmont	79:0c05e21ae27e	561	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
emilmont	79:0c05e21ae27e	562	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
emilmont	79:0c05e21ae27e	563
emilmont	79:0c05e21ae27e	564	/* SCB Configuration Control Register Definitions */
emilmont	79:0c05e21ae27e	565	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
emilmont	79:0c05e21ae27e	566	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
emilmont	79:0c05e21ae27e	567
emilmont	79:0c05e21ae27e	568	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
emilmont	79:0c05e21ae27e	569	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
emilmont	79:0c05e21ae27e	570
emilmont	79:0c05e21ae27e	571	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
emilmont	79:0c05e21ae27e	572	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
emilmont	79:0c05e21ae27e	573
emilmont	79:0c05e21ae27e	574	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
emilmont	79:0c05e21ae27e	575	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
emilmont	79:0c05e21ae27e	576
emilmont	79:0c05e21ae27e	577	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
emilmont	79:0c05e21ae27e	578	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
emilmont	79:0c05e21ae27e	579
emilmont	79:0c05e21ae27e	580	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	110:165afa46840b	581	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
emilmont	79:0c05e21ae27e	582
emilmont	79:0c05e21ae27e	583	/* SCB System Handler Control and State Register Definitions */
emilmont	79:0c05e21ae27e	584	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
emilmont	79:0c05e21ae27e	585	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
emilmont	79:0c05e21ae27e	586
emilmont	79:0c05e21ae27e	587	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
emilmont	79:0c05e21ae27e	588	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
emilmont	79:0c05e21ae27e	589
emilmont	79:0c05e21ae27e	590	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
emilmont	79:0c05e21ae27e	591	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
emilmont	79:0c05e21ae27e	592
emilmont	79:0c05e21ae27e	593	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
emilmont	79:0c05e21ae27e	594	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
emilmont	79:0c05e21ae27e	595
emilmont	79:0c05e21ae27e	596	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
emilmont	79:0c05e21ae27e	597	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
emilmont	79:0c05e21ae27e	598
emilmont	79:0c05e21ae27e	599	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
emilmont	79:0c05e21ae27e	600	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
emilmont	79:0c05e21ae27e	601
emilmont	79:0c05e21ae27e	602	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
emilmont	79:0c05e21ae27e	603	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
emilmont	79:0c05e21ae27e	604
emilmont	79:0c05e21ae27e	605	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
emilmont	79:0c05e21ae27e	606	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
emilmont	79:0c05e21ae27e	607
emilmont	79:0c05e21ae27e	608	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
emilmont	79:0c05e21ae27e	609	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
emilmont	79:0c05e21ae27e	610
emilmont	79:0c05e21ae27e	611	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
emilmont	79:0c05e21ae27e	612	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
emilmont	79:0c05e21ae27e	613
emilmont	79:0c05e21ae27e	614	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
emilmont	79:0c05e21ae27e	615	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
emilmont	79:0c05e21ae27e	616
emilmont	79:0c05e21ae27e	617	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
emilmont	79:0c05e21ae27e	618	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
emilmont	79:0c05e21ae27e	619
emilmont	79:0c05e21ae27e	620	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
emilmont	79:0c05e21ae27e	621	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
emilmont	79:0c05e21ae27e	622
emilmont	79:0c05e21ae27e	623	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	110:165afa46840b	624	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
emilmont	79:0c05e21ae27e	625
emilmont	79:0c05e21ae27e	626	/* SCB Configurable Fault Status Registers Definitions */
emilmont	79:0c05e21ae27e	627	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
emilmont	79:0c05e21ae27e	628	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
emilmont	79:0c05e21ae27e	629
emilmont	79:0c05e21ae27e	630	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
emilmont	79:0c05e21ae27e	631	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
emilmont	79:0c05e21ae27e	632
emilmont	79:0c05e21ae27e	633	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	110:165afa46840b	634	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
emilmont	79:0c05e21ae27e	635
emilmont	79:0c05e21ae27e	636	/* SCB Hard Fault Status Registers Definitions */
emilmont	79:0c05e21ae27e	637	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
emilmont	79:0c05e21ae27e	638	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
emilmont	79:0c05e21ae27e	639
emilmont	79:0c05e21ae27e	640	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
emilmont	79:0c05e21ae27e	641	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
emilmont	79:0c05e21ae27e	642
emilmont	79:0c05e21ae27e	643	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
emilmont	79:0c05e21ae27e	644	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
emilmont	79:0c05e21ae27e	645
emilmont	79:0c05e21ae27e	646	/* SCB Debug Fault Status Register Definitions */
emilmont	79:0c05e21ae27e	647	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
emilmont	79:0c05e21ae27e	648	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
emilmont	79:0c05e21ae27e	649
emilmont	79:0c05e21ae27e	650	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
emilmont	79:0c05e21ae27e	651	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
emilmont	79:0c05e21ae27e	652
emilmont	79:0c05e21ae27e	653	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
emilmont	79:0c05e21ae27e	654	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
emilmont	79:0c05e21ae27e	655
emilmont	79:0c05e21ae27e	656	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
emilmont	79:0c05e21ae27e	657	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
emilmont	79:0c05e21ae27e	658
emilmont	79:0c05e21ae27e	659	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	110:165afa46840b	660	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
emilmont	79:0c05e21ae27e	661
emilmont	79:0c05e21ae27e	662	/@} end of group CMSIS_SCB /
emilmont	79:0c05e21ae27e	663
emilmont	79:0c05e21ae27e	664
emilmont	79:0c05e21ae27e	665	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	666	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont	79:0c05e21ae27e	667	\brief Type definitions for the System Control and ID Register not in the SCB
emilmont	79:0c05e21ae27e	668	@{
emilmont	79:0c05e21ae27e	669	*/
emilmont	79:0c05e21ae27e	670
emilmont	79:0c05e21ae27e	671	/** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont	79:0c05e21ae27e	672	*/
emilmont	79:0c05e21ae27e	673	typedef struct
emilmont	79:0c05e21ae27e	674	{
emilmont	79:0c05e21ae27e	675	uint32_t RESERVED0[1];
emilmont	79:0c05e21ae27e	676	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
emilmont	79:0c05e21ae27e	677	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
emilmont	79:0c05e21ae27e	678	} SCnSCB_Type;
emilmont	79:0c05e21ae27e	679
emilmont	79:0c05e21ae27e	680	/* Interrupt Controller Type Register Definitions */
emilmont	79:0c05e21ae27e	681	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	110:165afa46840b	682	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
emilmont	79:0c05e21ae27e	683
emilmont	79:0c05e21ae27e	684	/* Auxiliary Control Register Definitions */
emilmont	79:0c05e21ae27e	685	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
emilmont	79:0c05e21ae27e	686	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
emilmont	79:0c05e21ae27e	687
emilmont	79:0c05e21ae27e	688	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
emilmont	79:0c05e21ae27e	689	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
emilmont	79:0c05e21ae27e	690
emilmont	79:0c05e21ae27e	691	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
emilmont	79:0c05e21ae27e	692	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
emilmont	79:0c05e21ae27e	693
emilmont	79:0c05e21ae27e	694	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
emilmont	79:0c05e21ae27e	695	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
emilmont	79:0c05e21ae27e	696
emilmont	79:0c05e21ae27e	697	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	110:165afa46840b	698	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
emilmont	79:0c05e21ae27e	699
emilmont	79:0c05e21ae27e	700	/@} end of group CMSIS_SCnotSCB /
emilmont	79:0c05e21ae27e	701
emilmont	79:0c05e21ae27e	702
emilmont	79:0c05e21ae27e	703	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	704	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont	79:0c05e21ae27e	705	\brief Type definitions for the System Timer Registers.
emilmont	79:0c05e21ae27e	706	@{
emilmont	79:0c05e21ae27e	707	*/
emilmont	79:0c05e21ae27e	708
emilmont	79:0c05e21ae27e	709	/** \brief Structure type to access the System Timer (SysTick).
emilmont	79:0c05e21ae27e	710	*/
emilmont	79:0c05e21ae27e	711	typedef struct
emilmont	79:0c05e21ae27e	712	{
emilmont	79:0c05e21ae27e	713	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
emilmont	79:0c05e21ae27e	714	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
emilmont	79:0c05e21ae27e	715	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
emilmont	79:0c05e21ae27e	716	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
emilmont	79:0c05e21ae27e	717	} SysTick_Type;
emilmont	79:0c05e21ae27e	718
emilmont	79:0c05e21ae27e	719	/* SysTick Control / Status Register Definitions */
emilmont	79:0c05e21ae27e	720	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
emilmont	79:0c05e21ae27e	721	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
emilmont	79:0c05e21ae27e	722
emilmont	79:0c05e21ae27e	723	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
emilmont	79:0c05e21ae27e	724	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
emilmont	79:0c05e21ae27e	725
emilmont	79:0c05e21ae27e	726	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
emilmont	79:0c05e21ae27e	727	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
emilmont	79:0c05e21ae27e	728
emilmont	79:0c05e21ae27e	729	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	110:165afa46840b	730	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
emilmont	79:0c05e21ae27e	731
emilmont	79:0c05e21ae27e	732	/* SysTick Reload Register Definitions */
emilmont	79:0c05e21ae27e	733	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	110:165afa46840b	734	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
emilmont	79:0c05e21ae27e	735
emilmont	79:0c05e21ae27e	736	/* SysTick Current Register Definitions */
emilmont	79:0c05e21ae27e	737	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	110:165afa46840b	738	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
emilmont	79:0c05e21ae27e	739
emilmont	79:0c05e21ae27e	740	/* SysTick Calibration Register Definitions */
emilmont	79:0c05e21ae27e	741	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
emilmont	79:0c05e21ae27e	742	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
emilmont	79:0c05e21ae27e	743
emilmont	79:0c05e21ae27e	744	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
emilmont	79:0c05e21ae27e	745	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
emilmont	79:0c05e21ae27e	746
emilmont	79:0c05e21ae27e	747	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	110:165afa46840b	748	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
emilmont	79:0c05e21ae27e	749
emilmont	79:0c05e21ae27e	750	/@} end of group CMSIS_SysTick /
emilmont	79:0c05e21ae27e	751
emilmont	79:0c05e21ae27e	752
emilmont	79:0c05e21ae27e	753	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	754	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont	79:0c05e21ae27e	755	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont	79:0c05e21ae27e	756	@{
emilmont	79:0c05e21ae27e	757	*/
emilmont	79:0c05e21ae27e	758
emilmont	79:0c05e21ae27e	759	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont	79:0c05e21ae27e	760	*/
emilmont	79:0c05e21ae27e	761	typedef struct
emilmont	79:0c05e21ae27e	762	{
emilmont	79:0c05e21ae27e	763	__O union
emilmont	79:0c05e21ae27e	764	{
emilmont	79:0c05e21ae27e	765	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
emilmont	79:0c05e21ae27e	766	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
emilmont	79:0c05e21ae27e	767	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
emilmont	79:0c05e21ae27e	768	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
emilmont	79:0c05e21ae27e	769	uint32_t RESERVED0[864];
emilmont	79:0c05e21ae27e	770	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
emilmont	79:0c05e21ae27e	771	uint32_t RESERVED1[15];
emilmont	79:0c05e21ae27e	772	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
emilmont	79:0c05e21ae27e	773	uint32_t RESERVED2[15];
emilmont	79:0c05e21ae27e	774	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
emilmont	79:0c05e21ae27e	775	uint32_t RESERVED3[29];
emilmont	79:0c05e21ae27e	776	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
emilmont	79:0c05e21ae27e	777	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
emilmont	79:0c05e21ae27e	778	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
emilmont	79:0c05e21ae27e	779	uint32_t RESERVED4[43];
emilmont	79:0c05e21ae27e	780	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
emilmont	79:0c05e21ae27e	781	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
emilmont	79:0c05e21ae27e	782	uint32_t RESERVED5[6];
emilmont	79:0c05e21ae27e	783	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
emilmont	79:0c05e21ae27e	784	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
emilmont	79:0c05e21ae27e	785	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
emilmont	79:0c05e21ae27e	786	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
emilmont	79:0c05e21ae27e	787	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
emilmont	79:0c05e21ae27e	788	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
emilmont	79:0c05e21ae27e	789	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
emilmont	79:0c05e21ae27e	790	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
emilmont	79:0c05e21ae27e	791	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
emilmont	79:0c05e21ae27e	792	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
emilmont	79:0c05e21ae27e	793	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
emilmont	79:0c05e21ae27e	794	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
emilmont	79:0c05e21ae27e	795	} ITM_Type;
emilmont	79:0c05e21ae27e	796
emilmont	79:0c05e21ae27e	797	/* ITM Trace Privilege Register Definitions */
emilmont	79:0c05e21ae27e	798	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	110:165afa46840b	799	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
emilmont	79:0c05e21ae27e	800
emilmont	79:0c05e21ae27e	801	/* ITM Trace Control Register Definitions */
emilmont	79:0c05e21ae27e	802	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
emilmont	79:0c05e21ae27e	803	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
emilmont	79:0c05e21ae27e	804
emilmont	79:0c05e21ae27e	805	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
emilmont	79:0c05e21ae27e	806	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
emilmont	79:0c05e21ae27e	807
emilmont	79:0c05e21ae27e	808	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
emilmont	79:0c05e21ae27e	809	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
emilmont	79:0c05e21ae27e	810
emilmont	79:0c05e21ae27e	811	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
emilmont	79:0c05e21ae27e	812	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
emilmont	79:0c05e21ae27e	813
emilmont	79:0c05e21ae27e	814	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
emilmont	79:0c05e21ae27e	815	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
emilmont	79:0c05e21ae27e	816
emilmont	79:0c05e21ae27e	817	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
emilmont	79:0c05e21ae27e	818	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
emilmont	79:0c05e21ae27e	819
emilmont	79:0c05e21ae27e	820	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
emilmont	79:0c05e21ae27e	821	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
emilmont	79:0c05e21ae27e	822
emilmont	79:0c05e21ae27e	823	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
emilmont	79:0c05e21ae27e	824	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
emilmont	79:0c05e21ae27e	825
emilmont	79:0c05e21ae27e	826	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	110:165afa46840b	827	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
emilmont	79:0c05e21ae27e	828
emilmont	79:0c05e21ae27e	829	/* ITM Integration Write Register Definitions */
emilmont	79:0c05e21ae27e	830	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	110:165afa46840b	831	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
emilmont	79:0c05e21ae27e	832
emilmont	79:0c05e21ae27e	833	/* ITM Integration Read Register Definitions */
emilmont	79:0c05e21ae27e	834	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	110:165afa46840b	835	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
emilmont	79:0c05e21ae27e	836
emilmont	79:0c05e21ae27e	837	/* ITM Integration Mode Control Register Definitions */
emilmont	79:0c05e21ae27e	838	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	110:165afa46840b	839	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
emilmont	79:0c05e21ae27e	840
emilmont	79:0c05e21ae27e	841	/* ITM Lock Status Register Definitions */
emilmont	79:0c05e21ae27e	842	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
emilmont	79:0c05e21ae27e	843	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
emilmont	79:0c05e21ae27e	844
emilmont	79:0c05e21ae27e	845	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
emilmont	79:0c05e21ae27e	846	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
emilmont	79:0c05e21ae27e	847
emilmont	79:0c05e21ae27e	848	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	110:165afa46840b	849	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
emilmont	79:0c05e21ae27e	850
emilmont	79:0c05e21ae27e	851	/@}/ /* end of group CMSIS_ITM */
emilmont	79:0c05e21ae27e	852
emilmont	79:0c05e21ae27e	853
emilmont	79:0c05e21ae27e	854	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	855	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont	79:0c05e21ae27e	856	\brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont	79:0c05e21ae27e	857	@{
emilmont	79:0c05e21ae27e	858	*/
emilmont	79:0c05e21ae27e	859
emilmont	79:0c05e21ae27e	860	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont	79:0c05e21ae27e	861	*/
emilmont	79:0c05e21ae27e	862	typedef struct
emilmont	79:0c05e21ae27e	863	{
emilmont	79:0c05e21ae27e	864	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
emilmont	79:0c05e21ae27e	865	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
emilmont	79:0c05e21ae27e	866	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
emilmont	79:0c05e21ae27e	867	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
emilmont	79:0c05e21ae27e	868	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
emilmont	79:0c05e21ae27e	869	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
emilmont	79:0c05e21ae27e	870	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
emilmont	79:0c05e21ae27e	871	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
emilmont	79:0c05e21ae27e	872	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
emilmont	79:0c05e21ae27e	873	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
emilmont	79:0c05e21ae27e	874	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
emilmont	79:0c05e21ae27e	875	uint32_t RESERVED0[1];
emilmont	79:0c05e21ae27e	876	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
emilmont	79:0c05e21ae27e	877	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
emilmont	79:0c05e21ae27e	878	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
emilmont	79:0c05e21ae27e	879	uint32_t RESERVED1[1];
emilmont	79:0c05e21ae27e	880	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
emilmont	79:0c05e21ae27e	881	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
emilmont	79:0c05e21ae27e	882	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
emilmont	79:0c05e21ae27e	883	uint32_t RESERVED2[1];
emilmont	79:0c05e21ae27e	884	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
emilmont	79:0c05e21ae27e	885	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
emilmont	79:0c05e21ae27e	886	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
emilmont	79:0c05e21ae27e	887	} DWT_Type;
emilmont	79:0c05e21ae27e	888
emilmont	79:0c05e21ae27e	889	/* DWT Control Register Definitions */
emilmont	79:0c05e21ae27e	890	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
emilmont	79:0c05e21ae27e	891	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
emilmont	79:0c05e21ae27e	892
emilmont	79:0c05e21ae27e	893	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
emilmont	79:0c05e21ae27e	894	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
emilmont	79:0c05e21ae27e	895
emilmont	79:0c05e21ae27e	896	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
emilmont	79:0c05e21ae27e	897	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
emilmont	79:0c05e21ae27e	898
emilmont	79:0c05e21ae27e	899	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
emilmont	79:0c05e21ae27e	900	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
emilmont	79:0c05e21ae27e	901
emilmont	79:0c05e21ae27e	902	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
emilmont	79:0c05e21ae27e	903	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
emilmont	79:0c05e21ae27e	904
emilmont	79:0c05e21ae27e	905	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
emilmont	79:0c05e21ae27e	906	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
emilmont	79:0c05e21ae27e	907
emilmont	79:0c05e21ae27e	908	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
emilmont	79:0c05e21ae27e	909	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
emilmont	79:0c05e21ae27e	910
emilmont	79:0c05e21ae27e	911	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
emilmont	79:0c05e21ae27e	912	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
emilmont	79:0c05e21ae27e	913
emilmont	79:0c05e21ae27e	914	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
emilmont	79:0c05e21ae27e	915	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
emilmont	79:0c05e21ae27e	916
emilmont	79:0c05e21ae27e	917	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
emilmont	79:0c05e21ae27e	918	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
emilmont	79:0c05e21ae27e	919
emilmont	79:0c05e21ae27e	920	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
emilmont	79:0c05e21ae27e	921	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
emilmont	79:0c05e21ae27e	922
emilmont	79:0c05e21ae27e	923	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
emilmont	79:0c05e21ae27e	924	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
emilmont	79:0c05e21ae27e	925
emilmont	79:0c05e21ae27e	926	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
emilmont	79:0c05e21ae27e	927	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
emilmont	79:0c05e21ae27e	928
emilmont	79:0c05e21ae27e	929	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
emilmont	79:0c05e21ae27e	930	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
emilmont	79:0c05e21ae27e	931
emilmont	79:0c05e21ae27e	932	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
emilmont	79:0c05e21ae27e	933	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
emilmont	79:0c05e21ae27e	934
emilmont	79:0c05e21ae27e	935	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
emilmont	79:0c05e21ae27e	936	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
emilmont	79:0c05e21ae27e	937
emilmont	79:0c05e21ae27e	938	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
emilmont	79:0c05e21ae27e	939	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
emilmont	79:0c05e21ae27e	940
emilmont	79:0c05e21ae27e	941	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	110:165afa46840b	942	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
emilmont	79:0c05e21ae27e	943
emilmont	79:0c05e21ae27e	944	/* DWT CPI Count Register Definitions */
emilmont	79:0c05e21ae27e	945	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	110:165afa46840b	946	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
emilmont	79:0c05e21ae27e	947
emilmont	79:0c05e21ae27e	948	/* DWT Exception Overhead Count Register Definitions */
emilmont	79:0c05e21ae27e	949	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	110:165afa46840b	950	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
emilmont	79:0c05e21ae27e	951
emilmont	79:0c05e21ae27e	952	/* DWT Sleep Count Register Definitions */
emilmont	79:0c05e21ae27e	953	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	110:165afa46840b	954	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
emilmont	79:0c05e21ae27e	955
emilmont	79:0c05e21ae27e	956	/* DWT LSU Count Register Definitions */
emilmont	79:0c05e21ae27e	957	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	110:165afa46840b	958	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
emilmont	79:0c05e21ae27e	959
emilmont	79:0c05e21ae27e	960	/* DWT Folded-instruction Count Register Definitions */
emilmont	79:0c05e21ae27e	961	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	110:165afa46840b	962	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
emilmont	79:0c05e21ae27e	963
emilmont	79:0c05e21ae27e	964	/* DWT Comparator Mask Register Definitions */
emilmont	79:0c05e21ae27e	965	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	110:165afa46840b	966	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
emilmont	79:0c05e21ae27e	967
emilmont	79:0c05e21ae27e	968	/* DWT Comparator Function Register Definitions */
emilmont	79:0c05e21ae27e	969	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
emilmont	79:0c05e21ae27e	970	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
emilmont	79:0c05e21ae27e	971
emilmont	79:0c05e21ae27e	972	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
emilmont	79:0c05e21ae27e	973	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
emilmont	79:0c05e21ae27e	974
emilmont	79:0c05e21ae27e	975	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
emilmont	79:0c05e21ae27e	976	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
emilmont	79:0c05e21ae27e	977
emilmont	79:0c05e21ae27e	978	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
emilmont	79:0c05e21ae27e	979	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
emilmont	79:0c05e21ae27e	980
emilmont	79:0c05e21ae27e	981	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
emilmont	79:0c05e21ae27e	982	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
emilmont	79:0c05e21ae27e	983
emilmont	79:0c05e21ae27e	984	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
emilmont	79:0c05e21ae27e	985	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
emilmont	79:0c05e21ae27e	986
emilmont	79:0c05e21ae27e	987	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
emilmont	79:0c05e21ae27e	988	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
emilmont	79:0c05e21ae27e	989
emilmont	79:0c05e21ae27e	990	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
emilmont	79:0c05e21ae27e	991	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
emilmont	79:0c05e21ae27e	992
emilmont	79:0c05e21ae27e	993	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	110:165afa46840b	994	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
emilmont	79:0c05e21ae27e	995
emilmont	79:0c05e21ae27e	996	/@}/ /* end of group CMSIS_DWT */
emilmont	79:0c05e21ae27e	997
emilmont	79:0c05e21ae27e	998
emilmont	79:0c05e21ae27e	999	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1000	\defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont	79:0c05e21ae27e	1001	\brief Type definitions for the Trace Port Interface (TPI)
emilmont	79:0c05e21ae27e	1002	@{
emilmont	79:0c05e21ae27e	1003	*/
emilmont	79:0c05e21ae27e	1004
emilmont	79:0c05e21ae27e	1005	/** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont	79:0c05e21ae27e	1006	*/
emilmont	79:0c05e21ae27e	1007	typedef struct
emilmont	79:0c05e21ae27e	1008	{
emilmont	79:0c05e21ae27e	1009	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
emilmont	79:0c05e21ae27e	1010	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
emilmont	79:0c05e21ae27e	1011	uint32_t RESERVED0[2];
emilmont	79:0c05e21ae27e	1012	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
emilmont	79:0c05e21ae27e	1013	uint32_t RESERVED1[55];
emilmont	79:0c05e21ae27e	1014	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
emilmont	79:0c05e21ae27e	1015	uint32_t RESERVED2[131];
emilmont	79:0c05e21ae27e	1016	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
emilmont	79:0c05e21ae27e	1017	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
emilmont	79:0c05e21ae27e	1018	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
emilmont	79:0c05e21ae27e	1019	uint32_t RESERVED3[759];
emilmont	79:0c05e21ae27e	1020	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
emilmont	79:0c05e21ae27e	1021	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
emilmont	79:0c05e21ae27e	1022	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
emilmont	79:0c05e21ae27e	1023	uint32_t RESERVED4[1];
emilmont	79:0c05e21ae27e	1024	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
emilmont	79:0c05e21ae27e	1025	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
emilmont	79:0c05e21ae27e	1026	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
emilmont	79:0c05e21ae27e	1027	uint32_t RESERVED5[39];
emilmont	79:0c05e21ae27e	1028	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
emilmont	79:0c05e21ae27e	1029	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
emilmont	79:0c05e21ae27e	1030	uint32_t RESERVED7[8];
emilmont	79:0c05e21ae27e	1031	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
emilmont	79:0c05e21ae27e	1032	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
emilmont	79:0c05e21ae27e	1033	} TPI_Type;
emilmont	79:0c05e21ae27e	1034
emilmont	79:0c05e21ae27e	1035	/* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont	79:0c05e21ae27e	1036	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	110:165afa46840b	1037	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
emilmont	79:0c05e21ae27e	1038
emilmont	79:0c05e21ae27e	1039	/* TPI Selected Pin Protocol Register Definitions */
emilmont	79:0c05e21ae27e	1040	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	110:165afa46840b	1041	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
emilmont	79:0c05e21ae27e	1042
emilmont	79:0c05e21ae27e	1043	/* TPI Formatter and Flush Status Register Definitions */
emilmont	79:0c05e21ae27e	1044	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
emilmont	79:0c05e21ae27e	1045	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
emilmont	79:0c05e21ae27e	1046
emilmont	79:0c05e21ae27e	1047	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
emilmont	79:0c05e21ae27e	1048	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
emilmont	79:0c05e21ae27e	1049
emilmont	79:0c05e21ae27e	1050	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
emilmont	79:0c05e21ae27e	1051	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
emilmont	79:0c05e21ae27e	1052
emilmont	79:0c05e21ae27e	1053	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	110:165afa46840b	1054	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
emilmont	79:0c05e21ae27e	1055
emilmont	79:0c05e21ae27e	1056	/* TPI Formatter and Flush Control Register Definitions */
emilmont	79:0c05e21ae27e	1057	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
emilmont	79:0c05e21ae27e	1058	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
emilmont	79:0c05e21ae27e	1059
emilmont	79:0c05e21ae27e	1060	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
emilmont	79:0c05e21ae27e	1061	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
emilmont	79:0c05e21ae27e	1062
emilmont	79:0c05e21ae27e	1063	/* TPI TRIGGER Register Definitions */
emilmont	79:0c05e21ae27e	1064	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	110:165afa46840b	1065	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
emilmont	79:0c05e21ae27e	1066
emilmont	79:0c05e21ae27e	1067	/* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont	79:0c05e21ae27e	1068	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
emilmont	79:0c05e21ae27e	1069	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1070
emilmont	79:0c05e21ae27e	1071	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
emilmont	79:0c05e21ae27e	1072	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
emilmont	79:0c05e21ae27e	1073
emilmont	79:0c05e21ae27e	1074	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
emilmont	79:0c05e21ae27e	1075	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1076
emilmont	79:0c05e21ae27e	1077	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
emilmont	79:0c05e21ae27e	1078	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
emilmont	79:0c05e21ae27e	1079
emilmont	79:0c05e21ae27e	1080	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
emilmont	79:0c05e21ae27e	1081	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
emilmont	79:0c05e21ae27e	1082
emilmont	79:0c05e21ae27e	1083	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
emilmont	79:0c05e21ae27e	1084	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
emilmont	79:0c05e21ae27e	1085
emilmont	79:0c05e21ae27e	1086	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	110:165afa46840b	1087	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
emilmont	79:0c05e21ae27e	1088
emilmont	79:0c05e21ae27e	1089	/* TPI ITATBCTR2 Register Definitions */
emilmont	79:0c05e21ae27e	1090	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	110:165afa46840b	1091	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
emilmont	79:0c05e21ae27e	1092
emilmont	79:0c05e21ae27e	1093	/* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont	79:0c05e21ae27e	1094	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
emilmont	79:0c05e21ae27e	1095	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1096
emilmont	79:0c05e21ae27e	1097	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
emilmont	79:0c05e21ae27e	1098	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
emilmont	79:0c05e21ae27e	1099
emilmont	79:0c05e21ae27e	1100	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
emilmont	79:0c05e21ae27e	1101	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
emilmont	79:0c05e21ae27e	1102
emilmont	79:0c05e21ae27e	1103	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
emilmont	79:0c05e21ae27e	1104	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
emilmont	79:0c05e21ae27e	1105
emilmont	79:0c05e21ae27e	1106	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
emilmont	79:0c05e21ae27e	1107	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
emilmont	79:0c05e21ae27e	1108
emilmont	79:0c05e21ae27e	1109	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
emilmont	79:0c05e21ae27e	1110	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
emilmont	79:0c05e21ae27e	1111
emilmont	79:0c05e21ae27e	1112	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	110:165afa46840b	1113	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
emilmont	79:0c05e21ae27e	1114
emilmont	79:0c05e21ae27e	1115	/* TPI ITATBCTR0 Register Definitions */
emilmont	79:0c05e21ae27e	1116	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	110:165afa46840b	1117	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
emilmont	79:0c05e21ae27e	1118
emilmont	79:0c05e21ae27e	1119	/* TPI Integration Mode Control Register Definitions */
emilmont	79:0c05e21ae27e	1120	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	110:165afa46840b	1121	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
emilmont	79:0c05e21ae27e	1122
emilmont	79:0c05e21ae27e	1123	/* TPI DEVID Register Definitions */
emilmont	79:0c05e21ae27e	1124	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
emilmont	79:0c05e21ae27e	1125	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
emilmont	79:0c05e21ae27e	1126
emilmont	79:0c05e21ae27e	1127	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
emilmont	79:0c05e21ae27e	1128	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
emilmont	79:0c05e21ae27e	1129
emilmont	79:0c05e21ae27e	1130	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
emilmont	79:0c05e21ae27e	1131	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
emilmont	79:0c05e21ae27e	1132
emilmont	79:0c05e21ae27e	1133	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
emilmont	79:0c05e21ae27e	1134	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
emilmont	79:0c05e21ae27e	1135
emilmont	79:0c05e21ae27e	1136	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
emilmont	79:0c05e21ae27e	1137	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
emilmont	79:0c05e21ae27e	1138
emilmont	79:0c05e21ae27e	1139	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	110:165afa46840b	1140	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
emilmont	79:0c05e21ae27e	1141
emilmont	79:0c05e21ae27e	1142	/* TPI DEVTYPE Register Definitions */
emilmont	79:0c05e21ae27e	1143	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
emilmont	79:0c05e21ae27e	1144	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
emilmont	79:0c05e21ae27e	1145
Kojto	110:165afa46840b	1146	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	110:165afa46840b	1147	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	110:165afa46840b	1148
emilmont	79:0c05e21ae27e	1149	/@}/ /* end of group CMSIS_TPI */
emilmont	79:0c05e21ae27e	1150
emilmont	79:0c05e21ae27e	1151
emilmont	79:0c05e21ae27e	1152	#if (__MPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	1153	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1154	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont	79:0c05e21ae27e	1155	\brief Type definitions for the Memory Protection Unit (MPU)
emilmont	79:0c05e21ae27e	1156	@{
emilmont	79:0c05e21ae27e	1157	*/
emilmont	79:0c05e21ae27e	1158
emilmont	79:0c05e21ae27e	1159	/** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont	79:0c05e21ae27e	1160	*/
emilmont	79:0c05e21ae27e	1161	typedef struct
emilmont	79:0c05e21ae27e	1162	{
emilmont	79:0c05e21ae27e	1163	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
emilmont	79:0c05e21ae27e	1164	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
emilmont	79:0c05e21ae27e	1165	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
emilmont	79:0c05e21ae27e	1166	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
emilmont	79:0c05e21ae27e	1167	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1168	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
emilmont	79:0c05e21ae27e	1169	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1170	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
emilmont	79:0c05e21ae27e	1171	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1172	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
emilmont	79:0c05e21ae27e	1173	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
emilmont	79:0c05e21ae27e	1174	} MPU_Type;
emilmont	79:0c05e21ae27e	1175
emilmont	79:0c05e21ae27e	1176	/* MPU Type Register */
emilmont	79:0c05e21ae27e	1177	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
emilmont	79:0c05e21ae27e	1178	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
emilmont	79:0c05e21ae27e	1179
emilmont	79:0c05e21ae27e	1180	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
emilmont	79:0c05e21ae27e	1181	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
emilmont	79:0c05e21ae27e	1182
emilmont	79:0c05e21ae27e	1183	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	110:165afa46840b	1184	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
emilmont	79:0c05e21ae27e	1185
emilmont	79:0c05e21ae27e	1186	/* MPU Control Register */
emilmont	79:0c05e21ae27e	1187	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
emilmont	79:0c05e21ae27e	1188	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
emilmont	79:0c05e21ae27e	1189
emilmont	79:0c05e21ae27e	1190	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
emilmont	79:0c05e21ae27e	1191	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
emilmont	79:0c05e21ae27e	1192
emilmont	79:0c05e21ae27e	1193	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	110:165afa46840b	1194	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
emilmont	79:0c05e21ae27e	1195
emilmont	79:0c05e21ae27e	1196	/* MPU Region Number Register */
emilmont	79:0c05e21ae27e	1197	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	110:165afa46840b	1198	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
emilmont	79:0c05e21ae27e	1199
emilmont	79:0c05e21ae27e	1200	/* MPU Region Base Address Register */
emilmont	79:0c05e21ae27e	1201	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
emilmont	79:0c05e21ae27e	1202	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
emilmont	79:0c05e21ae27e	1203
emilmont	79:0c05e21ae27e	1204	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
emilmont	79:0c05e21ae27e	1205	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
emilmont	79:0c05e21ae27e	1206
emilmont	79:0c05e21ae27e	1207	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	110:165afa46840b	1208	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
emilmont	79:0c05e21ae27e	1209
emilmont	79:0c05e21ae27e	1210	/* MPU Region Attribute and Size Register */
emilmont	79:0c05e21ae27e	1211	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
emilmont	79:0c05e21ae27e	1212	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
emilmont	79:0c05e21ae27e	1213
emilmont	79:0c05e21ae27e	1214	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
emilmont	79:0c05e21ae27e	1215	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
emilmont	79:0c05e21ae27e	1216
emilmont	79:0c05e21ae27e	1217	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
emilmont	79:0c05e21ae27e	1218	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
emilmont	79:0c05e21ae27e	1219
emilmont	79:0c05e21ae27e	1220	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
emilmont	79:0c05e21ae27e	1221	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
emilmont	79:0c05e21ae27e	1222
emilmont	79:0c05e21ae27e	1223	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
emilmont	79:0c05e21ae27e	1224	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
emilmont	79:0c05e21ae27e	1225
emilmont	79:0c05e21ae27e	1226	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
emilmont	79:0c05e21ae27e	1227	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
emilmont	79:0c05e21ae27e	1228
emilmont	79:0c05e21ae27e	1229	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
emilmont	79:0c05e21ae27e	1230	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
emilmont	79:0c05e21ae27e	1231
emilmont	79:0c05e21ae27e	1232	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
emilmont	79:0c05e21ae27e	1233	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
emilmont	79:0c05e21ae27e	1234
emilmont	79:0c05e21ae27e	1235	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
emilmont	79:0c05e21ae27e	1236	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
emilmont	79:0c05e21ae27e	1237
emilmont	79:0c05e21ae27e	1238	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	110:165afa46840b	1239	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
emilmont	79:0c05e21ae27e	1240
emilmont	79:0c05e21ae27e	1241	/@} end of group CMSIS_MPU /
emilmont	79:0c05e21ae27e	1242	#endif
emilmont	79:0c05e21ae27e	1243
emilmont	79:0c05e21ae27e	1244
emilmont	79:0c05e21ae27e	1245	#if (__FPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	1246	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1247	\defgroup CMSIS_FPU Floating Point Unit (FPU)
emilmont	79:0c05e21ae27e	1248	\brief Type definitions for the Floating Point Unit (FPU)
emilmont	79:0c05e21ae27e	1249	@{
emilmont	79:0c05e21ae27e	1250	*/
emilmont	79:0c05e21ae27e	1251
emilmont	79:0c05e21ae27e	1252	/** \brief Structure type to access the Floating Point Unit (FPU).
emilmont	79:0c05e21ae27e	1253	*/
emilmont	79:0c05e21ae27e	1254	typedef struct
emilmont	79:0c05e21ae27e	1255	{
emilmont	79:0c05e21ae27e	1256	uint32_t RESERVED0[1];
emilmont	79:0c05e21ae27e	1257	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
emilmont	79:0c05e21ae27e	1258	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
emilmont	79:0c05e21ae27e	1259	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
emilmont	79:0c05e21ae27e	1260	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
emilmont	79:0c05e21ae27e	1261	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
emilmont	79:0c05e21ae27e	1262	} FPU_Type;
emilmont	79:0c05e21ae27e	1263
emilmont	79:0c05e21ae27e	1264	/* Floating-Point Context Control Register */
emilmont	79:0c05e21ae27e	1265	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
emilmont	79:0c05e21ae27e	1266	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
emilmont	79:0c05e21ae27e	1267
emilmont	79:0c05e21ae27e	1268	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
emilmont	79:0c05e21ae27e	1269	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
emilmont	79:0c05e21ae27e	1270
emilmont	79:0c05e21ae27e	1271	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
emilmont	79:0c05e21ae27e	1272	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
emilmont	79:0c05e21ae27e	1273
emilmont	79:0c05e21ae27e	1274	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
emilmont	79:0c05e21ae27e	1275	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
emilmont	79:0c05e21ae27e	1276
emilmont	79:0c05e21ae27e	1277	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
emilmont	79:0c05e21ae27e	1278	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
emilmont	79:0c05e21ae27e	1279
emilmont	79:0c05e21ae27e	1280	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
emilmont	79:0c05e21ae27e	1281	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
emilmont	79:0c05e21ae27e	1282
emilmont	79:0c05e21ae27e	1283	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
emilmont	79:0c05e21ae27e	1284	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
emilmont	79:0c05e21ae27e	1285
emilmont	79:0c05e21ae27e	1286	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
emilmont	79:0c05e21ae27e	1287	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
emilmont	79:0c05e21ae27e	1288
emilmont	79:0c05e21ae27e	1289	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Kojto	110:165afa46840b	1290	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
emilmont	79:0c05e21ae27e	1291
emilmont	79:0c05e21ae27e	1292	/* Floating-Point Context Address Register */
emilmont	79:0c05e21ae27e	1293	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
emilmont	79:0c05e21ae27e	1294	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
emilmont	79:0c05e21ae27e	1295
emilmont	79:0c05e21ae27e	1296	/* Floating-Point Default Status Control Register */
emilmont	79:0c05e21ae27e	1297	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
emilmont	79:0c05e21ae27e	1298	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
emilmont	79:0c05e21ae27e	1299
emilmont	79:0c05e21ae27e	1300	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
emilmont	79:0c05e21ae27e	1301	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
emilmont	79:0c05e21ae27e	1302
emilmont	79:0c05e21ae27e	1303	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
emilmont	79:0c05e21ae27e	1304	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
emilmont	79:0c05e21ae27e	1305
emilmont	79:0c05e21ae27e	1306	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
emilmont	79:0c05e21ae27e	1307	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
emilmont	79:0c05e21ae27e	1308
emilmont	79:0c05e21ae27e	1309	/* Media and FP Feature Register 0 */
emilmont	79:0c05e21ae27e	1310	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
emilmont	79:0c05e21ae27e	1311	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
emilmont	79:0c05e21ae27e	1312
emilmont	79:0c05e21ae27e	1313	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
emilmont	79:0c05e21ae27e	1314	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
emilmont	79:0c05e21ae27e	1315
emilmont	79:0c05e21ae27e	1316	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
emilmont	79:0c05e21ae27e	1317	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
emilmont	79:0c05e21ae27e	1318
emilmont	79:0c05e21ae27e	1319	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
emilmont	79:0c05e21ae27e	1320	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
emilmont	79:0c05e21ae27e	1321
emilmont	79:0c05e21ae27e	1322	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
emilmont	79:0c05e21ae27e	1323	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
emilmont	79:0c05e21ae27e	1324
emilmont	79:0c05e21ae27e	1325	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
emilmont	79:0c05e21ae27e	1326	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
emilmont	79:0c05e21ae27e	1327
emilmont	79:0c05e21ae27e	1328	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
emilmont	79:0c05e21ae27e	1329	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
emilmont	79:0c05e21ae27e	1330
emilmont	79:0c05e21ae27e	1331	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Kojto	110:165afa46840b	1332	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
emilmont	79:0c05e21ae27e	1333
emilmont	79:0c05e21ae27e	1334	/* Media and FP Feature Register 1 */
emilmont	79:0c05e21ae27e	1335	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
emilmont	79:0c05e21ae27e	1336	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
emilmont	79:0c05e21ae27e	1337
emilmont	79:0c05e21ae27e	1338	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
emilmont	79:0c05e21ae27e	1339	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
emilmont	79:0c05e21ae27e	1340
emilmont	79:0c05e21ae27e	1341	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
emilmont	79:0c05e21ae27e	1342	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
emilmont	79:0c05e21ae27e	1343
emilmont	79:0c05e21ae27e	1344	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Kojto	110:165afa46840b	1345	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
emilmont	79:0c05e21ae27e	1346
emilmont	79:0c05e21ae27e	1347	/@} end of group CMSIS_FPU /
emilmont	79:0c05e21ae27e	1348	#endif
emilmont	79:0c05e21ae27e	1349
emilmont	79:0c05e21ae27e	1350
emilmont	79:0c05e21ae27e	1351	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1352	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont	79:0c05e21ae27e	1353	\brief Type definitions for the Core Debug Registers
emilmont	79:0c05e21ae27e	1354	@{
emilmont	79:0c05e21ae27e	1355	*/
emilmont	79:0c05e21ae27e	1356
emilmont	79:0c05e21ae27e	1357	/** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont	79:0c05e21ae27e	1358	*/
emilmont	79:0c05e21ae27e	1359	typedef struct
emilmont	79:0c05e21ae27e	1360	{
emilmont	79:0c05e21ae27e	1361	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
emilmont	79:0c05e21ae27e	1362	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
emilmont	79:0c05e21ae27e	1363	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
emilmont	79:0c05e21ae27e	1364	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
emilmont	79:0c05e21ae27e	1365	} CoreDebug_Type;
emilmont	79:0c05e21ae27e	1366
emilmont	79:0c05e21ae27e	1367	/* Debug Halting Control and Status Register */
emilmont	79:0c05e21ae27e	1368	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
emilmont	79:0c05e21ae27e	1369	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
emilmont	79:0c05e21ae27e	1370
emilmont	79:0c05e21ae27e	1371	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
emilmont	79:0c05e21ae27e	1372	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
emilmont	79:0c05e21ae27e	1373
emilmont	79:0c05e21ae27e	1374	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
emilmont	79:0c05e21ae27e	1375	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
emilmont	79:0c05e21ae27e	1376
emilmont	79:0c05e21ae27e	1377	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
emilmont	79:0c05e21ae27e	1378	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
emilmont	79:0c05e21ae27e	1379
emilmont	79:0c05e21ae27e	1380	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
emilmont	79:0c05e21ae27e	1381	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
emilmont	79:0c05e21ae27e	1382
emilmont	79:0c05e21ae27e	1383	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
emilmont	79:0c05e21ae27e	1384	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
emilmont	79:0c05e21ae27e	1385
emilmont	79:0c05e21ae27e	1386	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
emilmont	79:0c05e21ae27e	1387	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
emilmont	79:0c05e21ae27e	1388
emilmont	79:0c05e21ae27e	1389	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
emilmont	79:0c05e21ae27e	1390	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
emilmont	79:0c05e21ae27e	1391
emilmont	79:0c05e21ae27e	1392	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
emilmont	79:0c05e21ae27e	1393	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
emilmont	79:0c05e21ae27e	1394
emilmont	79:0c05e21ae27e	1395	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
emilmont	79:0c05e21ae27e	1396	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
emilmont	79:0c05e21ae27e	1397
emilmont	79:0c05e21ae27e	1398	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
emilmont	79:0c05e21ae27e	1399	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
emilmont	79:0c05e21ae27e	1400
emilmont	79:0c05e21ae27e	1401	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	110:165afa46840b	1402	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
emilmont	79:0c05e21ae27e	1403
emilmont	79:0c05e21ae27e	1404	/* Debug Core Register Selector Register */
emilmont	79:0c05e21ae27e	1405	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
emilmont	79:0c05e21ae27e	1406	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
emilmont	79:0c05e21ae27e	1407
emilmont	79:0c05e21ae27e	1408	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	110:165afa46840b	1409	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
emilmont	79:0c05e21ae27e	1410
emilmont	79:0c05e21ae27e	1411	/* Debug Exception and Monitor Control Register */
emilmont	79:0c05e21ae27e	1412	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
emilmont	79:0c05e21ae27e	1413	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
emilmont	79:0c05e21ae27e	1414
emilmont	79:0c05e21ae27e	1415	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
emilmont	79:0c05e21ae27e	1416	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
emilmont	79:0c05e21ae27e	1417
emilmont	79:0c05e21ae27e	1418	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
emilmont	79:0c05e21ae27e	1419	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
emilmont	79:0c05e21ae27e	1420
emilmont	79:0c05e21ae27e	1421	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
emilmont	79:0c05e21ae27e	1422	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
emilmont	79:0c05e21ae27e	1423
emilmont	79:0c05e21ae27e	1424	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
emilmont	79:0c05e21ae27e	1425	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
emilmont	79:0c05e21ae27e	1426
emilmont	79:0c05e21ae27e	1427	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
emilmont	79:0c05e21ae27e	1428	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
emilmont	79:0c05e21ae27e	1429
emilmont	79:0c05e21ae27e	1430	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
emilmont	79:0c05e21ae27e	1431	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
emilmont	79:0c05e21ae27e	1432
emilmont	79:0c05e21ae27e	1433	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
emilmont	79:0c05e21ae27e	1434	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
emilmont	79:0c05e21ae27e	1435
emilmont	79:0c05e21ae27e	1436	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
emilmont	79:0c05e21ae27e	1437	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
emilmont	79:0c05e21ae27e	1438
emilmont	79:0c05e21ae27e	1439	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
emilmont	79:0c05e21ae27e	1440	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
emilmont	79:0c05e21ae27e	1441
emilmont	79:0c05e21ae27e	1442	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
emilmont	79:0c05e21ae27e	1443	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
emilmont	79:0c05e21ae27e	1444
emilmont	79:0c05e21ae27e	1445	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
emilmont	79:0c05e21ae27e	1446	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
emilmont	79:0c05e21ae27e	1447
emilmont	79:0c05e21ae27e	1448	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	110:165afa46840b	1449	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
emilmont	79:0c05e21ae27e	1450
emilmont	79:0c05e21ae27e	1451	/@} end of group CMSIS_CoreDebug /
emilmont	79:0c05e21ae27e	1452
emilmont	79:0c05e21ae27e	1453
emilmont	79:0c05e21ae27e	1454	/** \ingroup CMSIS_core_register
emilmont	79:0c05e21ae27e	1455	\defgroup CMSIS_core_base Core Definitions
emilmont	79:0c05e21ae27e	1456	\brief Definitions for base addresses, unions, and structures.
emilmont	79:0c05e21ae27e	1457	@{
emilmont	79:0c05e21ae27e	1458	*/
emilmont	79:0c05e21ae27e	1459
emilmont	79:0c05e21ae27e	1460	/* Memory mapping of Cortex-M4 Hardware */
emilmont	79:0c05e21ae27e	1461	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
emilmont	79:0c05e21ae27e	1462	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
emilmont	79:0c05e21ae27e	1463	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
emilmont	79:0c05e21ae27e	1464	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
emilmont	79:0c05e21ae27e	1465	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
emilmont	79:0c05e21ae27e	1466	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
emilmont	79:0c05e21ae27e	1467	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
emilmont	79:0c05e21ae27e	1468	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
emilmont	79:0c05e21ae27e	1469
emilmont	79:0c05e21ae27e	1470	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
emilmont	79:0c05e21ae27e	1471	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
emilmont	79:0c05e21ae27e	1472	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
emilmont	79:0c05e21ae27e	1473	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
emilmont	79:0c05e21ae27e	1474	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
emilmont	79:0c05e21ae27e	1475	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
emilmont	79:0c05e21ae27e	1476	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
emilmont	79:0c05e21ae27e	1477	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
emilmont	79:0c05e21ae27e	1478
emilmont	79:0c05e21ae27e	1479	#if (__MPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	1480	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
emilmont	79:0c05e21ae27e	1481	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
emilmont	79:0c05e21ae27e	1482	#endif
emilmont	79:0c05e21ae27e	1483
emilmont	79:0c05e21ae27e	1484	#if (__FPU_PRESENT == 1)
emilmont	79:0c05e21ae27e	1485	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
emilmont	79:0c05e21ae27e	1486	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
emilmont	79:0c05e21ae27e	1487	#endif
emilmont	79:0c05e21ae27e	1488
emilmont	79:0c05e21ae27e	1489	/@} /
emilmont	79:0c05e21ae27e	1490
emilmont	79:0c05e21ae27e	1491
emilmont	79:0c05e21ae27e	1492
emilmont	79:0c05e21ae27e	1493	/*******************************************************************************
emilmont	79:0c05e21ae27e	1494	* Hardware Abstraction Layer
emilmont	79:0c05e21ae27e	1495	Core Function Interface contains:
emilmont	79:0c05e21ae27e	1496	- Core NVIC Functions
emilmont	79:0c05e21ae27e	1497	- Core SysTick Functions
emilmont	79:0c05e21ae27e	1498	- Core Debug Functions
emilmont	79:0c05e21ae27e	1499	- Core Register Access Functions
emilmont	79:0c05e21ae27e	1500	******************************************************************************/
emilmont	79:0c05e21ae27e	1501	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont	79:0c05e21ae27e	1502	*/
emilmont	79:0c05e21ae27e	1503
emilmont	79:0c05e21ae27e	1504
emilmont	79:0c05e21ae27e	1505
emilmont	79:0c05e21ae27e	1506	/* ########################## NVIC functions #################################### */
emilmont	79:0c05e21ae27e	1507	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	79:0c05e21ae27e	1508	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont	79:0c05e21ae27e	1509	\brief Functions that manage interrupts and exceptions via the NVIC.
emilmont	79:0c05e21ae27e	1510	@{
emilmont	79:0c05e21ae27e	1511	*/
emilmont	79:0c05e21ae27e	1512
Kojto	122:f9eeca106725	1513	#ifdef CMSIS_NVIC_VIRTUAL
Kojto	122:f9eeca106725	1514	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1515	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Kojto	122:f9eeca106725	1516	#endif
Kojto	122:f9eeca106725	1517	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1518	#else
Kojto	122:f9eeca106725	1519	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Kojto	122:f9eeca106725	1520	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Kojto	122:f9eeca106725	1521	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Kojto	122:f9eeca106725	1522	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Kojto	122:f9eeca106725	1523	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Kojto	122:f9eeca106725	1524	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Kojto	122:f9eeca106725	1525	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Kojto	122:f9eeca106725	1526	#define NVIC_GetActive __NVIC_GetActive
Kojto	122:f9eeca106725	1527	#define NVIC_SetPriority __NVIC_SetPriority
Kojto	122:f9eeca106725	1528	#define NVIC_GetPriority __NVIC_GetPriority
<>	128:9bcdf88f62b0	1529	#define NVIC_SystemReset __NVIC_SystemReset
Kojto	122:f9eeca106725	1530	#endif /* CMSIS_NVIC_VIRTUAL */
Kojto	122:f9eeca106725	1531
Kojto	122:f9eeca106725	1532	#ifdef CMSIS_VECTAB_VIRTUAL
Kojto	122:f9eeca106725	1533	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1534	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Kojto	122:f9eeca106725	1535	#endif
Kojto	122:f9eeca106725	1536	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1537	#else
Kojto	122:f9eeca106725	1538	#define NVIC_SetVector __NVIC_SetVector
Kojto	122:f9eeca106725	1539	#define NVIC_GetVector __NVIC_GetVector
Kojto	122:f9eeca106725	1540	#endif /* CMSIS_VECTAB_VIRTUAL */
Kojto	122:f9eeca106725	1541
Kojto	122:f9eeca106725	1542
emilmont	79:0c05e21ae27e	1543	/** \brief Set Priority Grouping
emilmont	79:0c05e21ae27e	1544
emilmont	79:0c05e21ae27e	1545	The function sets the priority grouping field using the required unlock sequence.
emilmont	79:0c05e21ae27e	1546	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont	79:0c05e21ae27e	1547	Only values from 0..7 are used.
emilmont	79:0c05e21ae27e	1548	In case of a conflict between priority grouping and available
emilmont	79:0c05e21ae27e	1549	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont	79:0c05e21ae27e	1550
emilmont	79:0c05e21ae27e	1551	\param [in] PriorityGroup Priority grouping field.
emilmont	79:0c05e21ae27e	1552	*/
Kojto	122:f9eeca106725	1553	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont	79:0c05e21ae27e	1554	{
emilmont	79:0c05e21ae27e	1555	uint32_t reg_value;
Kojto	110:165afa46840b	1556	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont	79:0c05e21ae27e	1557
emilmont	79:0c05e21ae27e	1558	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	110:165afa46840b	1559	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	110:165afa46840b	1560	reg_value = (reg_value \|
Kojto	110:165afa46840b	1561	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	110:165afa46840b	1562	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
emilmont	79:0c05e21ae27e	1563	SCB->AIRCR = reg_value;
emilmont	79:0c05e21ae27e	1564	}
emilmont	79:0c05e21ae27e	1565
emilmont	79:0c05e21ae27e	1566
emilmont	79:0c05e21ae27e	1567	/** \brief Get Priority Grouping
emilmont	79:0c05e21ae27e	1568
emilmont	79:0c05e21ae27e	1569	The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont	79:0c05e21ae27e	1570
emilmont	79:0c05e21ae27e	1571	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont	79:0c05e21ae27e	1572	*/
Kojto	122:f9eeca106725	1573	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
emilmont	79:0c05e21ae27e	1574	{
Kojto	110:165afa46840b	1575	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
emilmont	79:0c05e21ae27e	1576	}
emilmont	79:0c05e21ae27e	1577
emilmont	79:0c05e21ae27e	1578
emilmont	79:0c05e21ae27e	1579	/** \brief Enable External Interrupt
emilmont	79:0c05e21ae27e	1580
emilmont	79:0c05e21ae27e	1581	The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont	79:0c05e21ae27e	1582
emilmont	79:0c05e21ae27e	1583	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1584	*/
Kojto	122:f9eeca106725	1585	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1586	{
Kojto	110:165afa46840b	1587	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont	79:0c05e21ae27e	1588	}
emilmont	79:0c05e21ae27e	1589
emilmont	79:0c05e21ae27e	1590
emilmont	79:0c05e21ae27e	1591	/** \brief Disable External Interrupt
emilmont	79:0c05e21ae27e	1592
emilmont	79:0c05e21ae27e	1593	The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont	79:0c05e21ae27e	1594
emilmont	79:0c05e21ae27e	1595	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1596	*/
Kojto	122:f9eeca106725	1597	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1598	{
Kojto	110:165afa46840b	1599	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	131:faff56e089b2	1600	__DSB();
<>	131:faff56e089b2	1601	__ISB();
emilmont	79:0c05e21ae27e	1602	}
emilmont	79:0c05e21ae27e	1603
emilmont	79:0c05e21ae27e	1604
emilmont	79:0c05e21ae27e	1605	/** \brief Get Pending Interrupt
emilmont	79:0c05e21ae27e	1606
emilmont	79:0c05e21ae27e	1607	The function reads the pending register in the NVIC and returns the pending bit
emilmont	79:0c05e21ae27e	1608	for the specified interrupt.
emilmont	79:0c05e21ae27e	1609
emilmont	79:0c05e21ae27e	1610	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1611
emilmont	79:0c05e21ae27e	1612	\return 0 Interrupt status is not pending.
emilmont	79:0c05e21ae27e	1613	\return 1 Interrupt status is pending.
emilmont	79:0c05e21ae27e	1614	*/
Kojto	122:f9eeca106725	1615	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1616	{
Kojto	110:165afa46840b	1617	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont	79:0c05e21ae27e	1618	}
emilmont	79:0c05e21ae27e	1619
emilmont	79:0c05e21ae27e	1620
emilmont	79:0c05e21ae27e	1621	/** \brief Set Pending Interrupt
emilmont	79:0c05e21ae27e	1622
emilmont	79:0c05e21ae27e	1623	The function sets the pending bit of an external interrupt.
emilmont	79:0c05e21ae27e	1624
emilmont	79:0c05e21ae27e	1625	\param [in] IRQn Interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1626	*/
Kojto	122:f9eeca106725	1627	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1628	{
Kojto	110:165afa46840b	1629	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont	79:0c05e21ae27e	1630	}
emilmont	79:0c05e21ae27e	1631
emilmont	79:0c05e21ae27e	1632
emilmont	79:0c05e21ae27e	1633	/** \brief Clear Pending Interrupt
emilmont	79:0c05e21ae27e	1634
emilmont	79:0c05e21ae27e	1635	The function clears the pending bit of an external interrupt.
emilmont	79:0c05e21ae27e	1636
emilmont	79:0c05e21ae27e	1637	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	79:0c05e21ae27e	1638	*/
Kojto	122:f9eeca106725	1639	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1640	{
Kojto	110:165afa46840b	1641	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont	79:0c05e21ae27e	1642	}
emilmont	79:0c05e21ae27e	1643
emilmont	79:0c05e21ae27e	1644
emilmont	79:0c05e21ae27e	1645	/** \brief Get Active Interrupt
emilmont	79:0c05e21ae27e	1646
emilmont	79:0c05e21ae27e	1647	The function reads the active register in NVIC and returns the active bit.
emilmont	79:0c05e21ae27e	1648
emilmont	79:0c05e21ae27e	1649	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1650
emilmont	79:0c05e21ae27e	1651	\return 0 Interrupt status is not active.
emilmont	79:0c05e21ae27e	1652	\return 1 Interrupt status is active.
emilmont	79:0c05e21ae27e	1653	*/
Kojto	122:f9eeca106725	1654	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1655	{
Kojto	110:165afa46840b	1656	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont	79:0c05e21ae27e	1657	}
emilmont	79:0c05e21ae27e	1658
emilmont	79:0c05e21ae27e	1659
emilmont	79:0c05e21ae27e	1660	/** \brief Set Interrupt Priority
emilmont	79:0c05e21ae27e	1661
emilmont	79:0c05e21ae27e	1662	The function sets the priority of an interrupt.
emilmont	79:0c05e21ae27e	1663
emilmont	79:0c05e21ae27e	1664	\note The priority cannot be set for every core interrupt.
emilmont	79:0c05e21ae27e	1665
emilmont	79:0c05e21ae27e	1666	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1667	\param [in] priority Priority to set.
emilmont	79:0c05e21ae27e	1668	*/
Kojto	122:f9eeca106725	1669	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont	79:0c05e21ae27e	1670	{
Kojto	110:165afa46840b	1671	if((int32_t)IRQn < 0) {
Kojto	110:165afa46840b	1672	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	110:165afa46840b	1673	}
emilmont	79:0c05e21ae27e	1674	else {
Kojto	110:165afa46840b	1675	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	110:165afa46840b	1676	}
emilmont	79:0c05e21ae27e	1677	}
emilmont	79:0c05e21ae27e	1678
emilmont	79:0c05e21ae27e	1679
emilmont	79:0c05e21ae27e	1680	/** \brief Get Interrupt Priority
emilmont	79:0c05e21ae27e	1681
emilmont	79:0c05e21ae27e	1682	The function reads the priority of an interrupt. The interrupt
emilmont	79:0c05e21ae27e	1683	number can be positive to specify an external (device specific)
emilmont	79:0c05e21ae27e	1684	interrupt, or negative to specify an internal (core) interrupt.
emilmont	79:0c05e21ae27e	1685
emilmont	79:0c05e21ae27e	1686
emilmont	79:0c05e21ae27e	1687	\param [in] IRQn Interrupt number.
emilmont	79:0c05e21ae27e	1688	\return Interrupt Priority. Value is aligned automatically to the implemented
emilmont	79:0c05e21ae27e	1689	priority bits of the microcontroller.
emilmont	79:0c05e21ae27e	1690	*/
Kojto	122:f9eeca106725	1691	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
emilmont	79:0c05e21ae27e	1692	{
emilmont	79:0c05e21ae27e	1693
Kojto	110:165afa46840b	1694	if((int32_t)IRQn < 0) {
Kojto	110:165afa46840b	1695	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto	110:165afa46840b	1696	}
emilmont	79:0c05e21ae27e	1697	else {
Kojto	110:165afa46840b	1698	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto	110:165afa46840b	1699	}
emilmont	79:0c05e21ae27e	1700	}
emilmont	79:0c05e21ae27e	1701
emilmont	79:0c05e21ae27e	1702
emilmont	79:0c05e21ae27e	1703	/** \brief Encode Priority
emilmont	79:0c05e21ae27e	1704
emilmont	79:0c05e21ae27e	1705	The function encodes the priority for an interrupt with the given priority group,
emilmont	79:0c05e21ae27e	1706	preemptive priority value, and subpriority value.
emilmont	79:0c05e21ae27e	1707	In case of a conflict between priority grouping and available
Kojto	110:165afa46840b	1708	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont	79:0c05e21ae27e	1709
emilmont	79:0c05e21ae27e	1710	\param [in] PriorityGroup Used priority group.
emilmont	79:0c05e21ae27e	1711	\param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont	79:0c05e21ae27e	1712	\param [in] SubPriority Subpriority value (starting from 0).
emilmont	79:0c05e21ae27e	1713	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont	79:0c05e21ae27e	1714	*/
emilmont	79:0c05e21ae27e	1715	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont	79:0c05e21ae27e	1716	{
Kojto	110:165afa46840b	1717	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont	79:0c05e21ae27e	1718	uint32_t PreemptPriorityBits;
emilmont	79:0c05e21ae27e	1719	uint32_t SubPriorityBits;
emilmont	79:0c05e21ae27e	1720
Kojto	110:165afa46840b	1721	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	110:165afa46840b	1722	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont	79:0c05e21ae27e	1723
emilmont	79:0c05e21ae27e	1724	return (
Kojto	110:165afa46840b	1725	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	110:165afa46840b	1726	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
emilmont	79:0c05e21ae27e	1727	);
emilmont	79:0c05e21ae27e	1728	}
emilmont	79:0c05e21ae27e	1729
emilmont	79:0c05e21ae27e	1730
emilmont	79:0c05e21ae27e	1731	/** \brief Decode Priority
emilmont	79:0c05e21ae27e	1732
emilmont	79:0c05e21ae27e	1733	The function decodes an interrupt priority value with a given priority group to
emilmont	79:0c05e21ae27e	1734	preemptive priority value and subpriority value.
emilmont	79:0c05e21ae27e	1735	In case of a conflict between priority grouping and available
Kojto	110:165afa46840b	1736	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
emilmont	79:0c05e21ae27e	1737
emilmont	79:0c05e21ae27e	1738	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont	79:0c05e21ae27e	1739	\param [in] PriorityGroup Used priority group.
emilmont	79:0c05e21ae27e	1740	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont	79:0c05e21ae27e	1741	\param [out] pSubPriority Subpriority value (starting from 0).
emilmont	79:0c05e21ae27e	1742	*/
emilmont	79:0c05e21ae27e	1743	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont	79:0c05e21ae27e	1744	{
Kojto	110:165afa46840b	1745	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont	79:0c05e21ae27e	1746	uint32_t PreemptPriorityBits;
emilmont	79:0c05e21ae27e	1747	uint32_t SubPriorityBits;
emilmont	79:0c05e21ae27e	1748
Kojto	110:165afa46840b	1749	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	110:165afa46840b	1750	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont	79:0c05e21ae27e	1751
Kojto	110:165afa46840b	1752	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	110:165afa46840b	1753	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
emilmont	79:0c05e21ae27e	1754	}
emilmont	79:0c05e21ae27e	1755
emilmont	79:0c05e21ae27e	1756
emilmont	79:0c05e21ae27e	1757	/** \brief System Reset
emilmont	79:0c05e21ae27e	1758
emilmont	79:0c05e21ae27e	1759	The function initiates a system reset request to reset the MCU.
emilmont	79:0c05e21ae27e	1760	*/
<>	128:9bcdf88f62b0	1761	__STATIC_INLINE void __NVIC_SystemReset(void)
emilmont	79:0c05e21ae27e	1762	{
Kojto	110:165afa46840b	1763	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	110:165afa46840b	1764	buffered write are completed before reset */
Kojto	110:165afa46840b	1765	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	110:165afa46840b	1766	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	110:165afa46840b	1767	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	110:165afa46840b	1768	__DSB(); /* Ensure completion of memory access */
Kojto	110:165afa46840b	1769	while(1) { __NOP(); } /* wait until reset */
emilmont	79:0c05e21ae27e	1770	}
emilmont	79:0c05e21ae27e	1771
emilmont	79:0c05e21ae27e	1772	/@} end of CMSIS_Core_NVICFunctions /
emilmont	79:0c05e21ae27e	1773
emilmont	79:0c05e21ae27e	1774
emilmont	79:0c05e21ae27e	1775
emilmont	79:0c05e21ae27e	1776	/* ################################## SysTick function ############################################ */
emilmont	79:0c05e21ae27e	1777	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	79:0c05e21ae27e	1778	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont	79:0c05e21ae27e	1779	\brief Functions that configure the System.
emilmont	79:0c05e21ae27e	1780	@{
emilmont	79:0c05e21ae27e	1781	*/
emilmont	79:0c05e21ae27e	1782
emilmont	79:0c05e21ae27e	1783	#if (__Vendor_SysTickConfig == 0)
emilmont	79:0c05e21ae27e	1784
emilmont	79:0c05e21ae27e	1785	/** \brief System Tick Configuration
emilmont	79:0c05e21ae27e	1786
emilmont	79:0c05e21ae27e	1787	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont	79:0c05e21ae27e	1788	Counter is in free running mode to generate periodic interrupts.
emilmont	79:0c05e21ae27e	1789
emilmont	79:0c05e21ae27e	1790	\param [in] ticks Number of ticks between two interrupts.
emilmont	79:0c05e21ae27e	1791
emilmont	79:0c05e21ae27e	1792	\return 0 Function succeeded.
emilmont	79:0c05e21ae27e	1793	\return 1 Function failed.
emilmont	79:0c05e21ae27e	1794
emilmont	79:0c05e21ae27e	1795	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont	79:0c05e21ae27e	1796	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont	79:0c05e21ae27e	1797	must contain a vendor-specific implementation of this function.
emilmont	79:0c05e21ae27e	1798
emilmont	79:0c05e21ae27e	1799	*/
emilmont	79:0c05e21ae27e	1800	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont	79:0c05e21ae27e	1801	{
Kojto	110:165afa46840b	1802	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
emilmont	79:0c05e21ae27e	1803
Kojto	110:165afa46840b	1804	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	110:165afa46840b	1805	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	110:165afa46840b	1806	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont	79:0c05e21ae27e	1807	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
emilmont	79:0c05e21ae27e	1808	SysTick_CTRL_TICKINT_Msk \|
Kojto	110:165afa46840b	1809	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	110:165afa46840b	1810	return (0UL); /* Function successful */
emilmont	79:0c05e21ae27e	1811	}
emilmont	79:0c05e21ae27e	1812
emilmont	79:0c05e21ae27e	1813	#endif
emilmont	79:0c05e21ae27e	1814
emilmont	79:0c05e21ae27e	1815	/@} end of CMSIS_Core_SysTickFunctions /
emilmont	79:0c05e21ae27e	1816
emilmont	79:0c05e21ae27e	1817
emilmont	79:0c05e21ae27e	1818
emilmont	79:0c05e21ae27e	1819	/* ##################################### Debug In/Output function ########################################### */
emilmont	79:0c05e21ae27e	1820	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	79:0c05e21ae27e	1821	\defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont	79:0c05e21ae27e	1822	\brief Functions that access the ITM debug interface.
emilmont	79:0c05e21ae27e	1823	@{
emilmont	79:0c05e21ae27e	1824	*/
emilmont	79:0c05e21ae27e	1825
emilmont	79:0c05e21ae27e	1826	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
emilmont	79:0c05e21ae27e	1827	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
emilmont	79:0c05e21ae27e	1828
emilmont	79:0c05e21ae27e	1829
emilmont	79:0c05e21ae27e	1830	/** \brief ITM Send Character
emilmont	79:0c05e21ae27e	1831
emilmont	79:0c05e21ae27e	1832	The function transmits a character via the ITM channel 0, and
emilmont	79:0c05e21ae27e	1833	\li Just returns when no debugger is connected that has booked the output.
emilmont	79:0c05e21ae27e	1834	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont	79:0c05e21ae27e	1835
emilmont	79:0c05e21ae27e	1836	\param [in] ch Character to transmit.
emilmont	79:0c05e21ae27e	1837
emilmont	79:0c05e21ae27e	1838	\returns Character to transmit.
emilmont	79:0c05e21ae27e	1839	*/
emilmont	79:0c05e21ae27e	1840	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont	79:0c05e21ae27e	1841	{
Kojto	110:165afa46840b	1842	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	110:165afa46840b	1843	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
emilmont	79:0c05e21ae27e	1844	{
Kojto	110:165afa46840b	1845	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto	110:165afa46840b	1846	ITM->PORT[0].u8 = (uint8_t)ch;
emilmont	79:0c05e21ae27e	1847	}
emilmont	79:0c05e21ae27e	1848	return (ch);
emilmont	79:0c05e21ae27e	1849	}
emilmont	79:0c05e21ae27e	1850
emilmont	79:0c05e21ae27e	1851
emilmont	79:0c05e21ae27e	1852	/** \brief ITM Receive Character
emilmont	79:0c05e21ae27e	1853
emilmont	79:0c05e21ae27e	1854	The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont	79:0c05e21ae27e	1855
emilmont	79:0c05e21ae27e	1856	\return Received character.
emilmont	79:0c05e21ae27e	1857	\return -1 No character pending.
emilmont	79:0c05e21ae27e	1858	*/
emilmont	79:0c05e21ae27e	1859	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont	79:0c05e21ae27e	1860	int32_t ch = -1; /* no character available */
emilmont	79:0c05e21ae27e	1861
emilmont	79:0c05e21ae27e	1862	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont	79:0c05e21ae27e	1863	ch = ITM_RxBuffer;
emilmont	79:0c05e21ae27e	1864	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont	79:0c05e21ae27e	1865	}
emilmont	79:0c05e21ae27e	1866
emilmont	79:0c05e21ae27e	1867	return (ch);
emilmont	79:0c05e21ae27e	1868	}
emilmont	79:0c05e21ae27e	1869
emilmont	79:0c05e21ae27e	1870
emilmont	79:0c05e21ae27e	1871	/** \brief ITM Check Character
emilmont	79:0c05e21ae27e	1872
emilmont	79:0c05e21ae27e	1873	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont	79:0c05e21ae27e	1874
emilmont	79:0c05e21ae27e	1875	\return 0 No character available.
emilmont	79:0c05e21ae27e	1876	\return 1 Character available.
emilmont	79:0c05e21ae27e	1877	*/
emilmont	79:0c05e21ae27e	1878	__STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont	79:0c05e21ae27e	1879
emilmont	79:0c05e21ae27e	1880	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont	79:0c05e21ae27e	1881	return (0); /* no character available */
emilmont	79:0c05e21ae27e	1882	} else {
emilmont	79:0c05e21ae27e	1883	return (1); /* character available */
emilmont	79:0c05e21ae27e	1884	}
emilmont	79:0c05e21ae27e	1885	}
emilmont	79:0c05e21ae27e	1886
emilmont	79:0c05e21ae27e	1887	/@} end of CMSIS_core_DebugFunctions /
emilmont	79:0c05e21ae27e	1888
emilmont	79:0c05e21ae27e	1889
Kojto	110:165afa46840b	1890
emilmont	79:0c05e21ae27e	1891
emilmont	79:0c05e21ae27e	1892	#ifdef __cplusplus
emilmont	79:0c05e21ae27e	1893	}
emilmont	79:0c05e21ae27e	1894	#endif
Kojto	110:165afa46840b	1895
Kojto	110:165afa46840b	1896	#endif /* __CORE_CM4_H_DEPENDANT */
Kojto	110:165afa46840b	1897
Kojto	110:165afa46840b	1898	#endif /* __CMSIS_GENERIC */