mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC11U35_401/core_cm4_simd.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
74:a842253909c9 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 74:a842253909c9 1 /**************************************************************************//**
bogdanm 74:a842253909c9 2 * @file core_cm4_simd.h
bogdanm 74:a842253909c9 3 * @brief CMSIS Cortex-M4 SIMD Header File
bogdanm 74:a842253909c9 4 * @version V3.20
bogdanm 74:a842253909c9 5 * @date 25. February 2013
bogdanm 74:a842253909c9 6 *
bogdanm 74:a842253909c9 7 * @note
bogdanm 74:a842253909c9 8 *
bogdanm 74:a842253909c9 9 ******************************************************************************/
bogdanm 74:a842253909c9 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 74:a842253909c9 11
bogdanm 74:a842253909c9 12 All rights reserved.
bogdanm 74:a842253909c9 13 Redistribution and use in source and binary forms, with or without
bogdanm 74:a842253909c9 14 modification, are permitted provided that the following conditions are met:
bogdanm 74:a842253909c9 15 - Redistributions of source code must retain the above copyright
bogdanm 74:a842253909c9 16 notice, this list of conditions and the following disclaimer.
bogdanm 74:a842253909c9 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 74:a842253909c9 18 notice, this list of conditions and the following disclaimer in the
bogdanm 74:a842253909c9 19 documentation and/or other materials provided with the distribution.
bogdanm 74:a842253909c9 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 74:a842253909c9 21 to endorse or promote products derived from this software without
bogdanm 74:a842253909c9 22 specific prior written permission.
bogdanm 74:a842253909c9 23 *
bogdanm 74:a842253909c9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 74:a842253909c9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 74:a842253909c9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 74:a842253909c9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 74:a842253909c9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 74:a842253909c9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 74:a842253909c9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 74:a842253909c9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 74:a842253909c9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 74:a842253909c9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 74:a842253909c9 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 74:a842253909c9 35 ---------------------------------------------------------------------------*/
bogdanm 74:a842253909c9 36
bogdanm 74:a842253909c9 37
bogdanm 74:a842253909c9 38 #ifdef __cplusplus
bogdanm 74:a842253909c9 39 extern "C" {
bogdanm 74:a842253909c9 40 #endif
bogdanm 74:a842253909c9 41
bogdanm 74:a842253909c9 42 #ifndef __CORE_CM4_SIMD_H
bogdanm 74:a842253909c9 43 #define __CORE_CM4_SIMD_H
bogdanm 74:a842253909c9 44
bogdanm 74:a842253909c9 45
bogdanm 74:a842253909c9 46 /*******************************************************************************
bogdanm 74:a842253909c9 47 * Hardware Abstraction Layer
bogdanm 74:a842253909c9 48 ******************************************************************************/
bogdanm 74:a842253909c9 49
bogdanm 74:a842253909c9 50
bogdanm 74:a842253909c9 51 /* ################### Compiler specific Intrinsics ########################### */
bogdanm 74:a842253909c9 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
bogdanm 74:a842253909c9 53 Access to dedicated SIMD instructions
bogdanm 74:a842253909c9 54 @{
bogdanm 74:a842253909c9 55 */
bogdanm 74:a842253909c9 56
bogdanm 74:a842253909c9 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 74:a842253909c9 58 /* ARM armcc specific functions */
bogdanm 74:a842253909c9 59
bogdanm 74:a842253909c9 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 61 #define __SADD8 __sadd8
bogdanm 74:a842253909c9 62 #define __QADD8 __qadd8
bogdanm 74:a842253909c9 63 #define __SHADD8 __shadd8
bogdanm 74:a842253909c9 64 #define __UADD8 __uadd8
bogdanm 74:a842253909c9 65 #define __UQADD8 __uqadd8
bogdanm 74:a842253909c9 66 #define __UHADD8 __uhadd8
bogdanm 74:a842253909c9 67 #define __SSUB8 __ssub8
bogdanm 74:a842253909c9 68 #define __QSUB8 __qsub8
bogdanm 74:a842253909c9 69 #define __SHSUB8 __shsub8
bogdanm 74:a842253909c9 70 #define __USUB8 __usub8
bogdanm 74:a842253909c9 71 #define __UQSUB8 __uqsub8
bogdanm 74:a842253909c9 72 #define __UHSUB8 __uhsub8
bogdanm 74:a842253909c9 73 #define __SADD16 __sadd16
bogdanm 74:a842253909c9 74 #define __QADD16 __qadd16
bogdanm 74:a842253909c9 75 #define __SHADD16 __shadd16
bogdanm 74:a842253909c9 76 #define __UADD16 __uadd16
bogdanm 74:a842253909c9 77 #define __UQADD16 __uqadd16
bogdanm 74:a842253909c9 78 #define __UHADD16 __uhadd16
bogdanm 74:a842253909c9 79 #define __SSUB16 __ssub16
bogdanm 74:a842253909c9 80 #define __QSUB16 __qsub16
bogdanm 74:a842253909c9 81 #define __SHSUB16 __shsub16
bogdanm 74:a842253909c9 82 #define __USUB16 __usub16
bogdanm 74:a842253909c9 83 #define __UQSUB16 __uqsub16
bogdanm 74:a842253909c9 84 #define __UHSUB16 __uhsub16
bogdanm 74:a842253909c9 85 #define __SASX __sasx
bogdanm 74:a842253909c9 86 #define __QASX __qasx
bogdanm 74:a842253909c9 87 #define __SHASX __shasx
bogdanm 74:a842253909c9 88 #define __UASX __uasx
bogdanm 74:a842253909c9 89 #define __UQASX __uqasx
bogdanm 74:a842253909c9 90 #define __UHASX __uhasx
bogdanm 74:a842253909c9 91 #define __SSAX __ssax
bogdanm 74:a842253909c9 92 #define __QSAX __qsax
bogdanm 74:a842253909c9 93 #define __SHSAX __shsax
bogdanm 74:a842253909c9 94 #define __USAX __usax
bogdanm 74:a842253909c9 95 #define __UQSAX __uqsax
bogdanm 74:a842253909c9 96 #define __UHSAX __uhsax
bogdanm 74:a842253909c9 97 #define __USAD8 __usad8
bogdanm 74:a842253909c9 98 #define __USADA8 __usada8
bogdanm 74:a842253909c9 99 #define __SSAT16 __ssat16
bogdanm 74:a842253909c9 100 #define __USAT16 __usat16
bogdanm 74:a842253909c9 101 #define __UXTB16 __uxtb16
bogdanm 74:a842253909c9 102 #define __UXTAB16 __uxtab16
bogdanm 74:a842253909c9 103 #define __SXTB16 __sxtb16
bogdanm 74:a842253909c9 104 #define __SXTAB16 __sxtab16
bogdanm 74:a842253909c9 105 #define __SMUAD __smuad
bogdanm 74:a842253909c9 106 #define __SMUADX __smuadx
bogdanm 74:a842253909c9 107 #define __SMLAD __smlad
bogdanm 74:a842253909c9 108 #define __SMLADX __smladx
bogdanm 74:a842253909c9 109 #define __SMLALD __smlald
bogdanm 74:a842253909c9 110 #define __SMLALDX __smlaldx
bogdanm 74:a842253909c9 111 #define __SMUSD __smusd
bogdanm 74:a842253909c9 112 #define __SMUSDX __smusdx
bogdanm 74:a842253909c9 113 #define __SMLSD __smlsd
bogdanm 74:a842253909c9 114 #define __SMLSDX __smlsdx
bogdanm 74:a842253909c9 115 #define __SMLSLD __smlsld
bogdanm 74:a842253909c9 116 #define __SMLSLDX __smlsldx
bogdanm 74:a842253909c9 117 #define __SEL __sel
bogdanm 74:a842253909c9 118 #define __QADD __qadd
bogdanm 74:a842253909c9 119 #define __QSUB __qsub
bogdanm 74:a842253909c9 120
bogdanm 74:a842253909c9 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
bogdanm 74:a842253909c9 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
bogdanm 74:a842253909c9 123
bogdanm 74:a842253909c9 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
bogdanm 74:a842253909c9 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
bogdanm 74:a842253909c9 126
bogdanm 74:a842253909c9 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
bogdanm 74:a842253909c9 128 ((int64_t)(ARG3) << 32) ) >> 32))
bogdanm 74:a842253909c9 129
bogdanm 74:a842253909c9 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 131
bogdanm 74:a842253909c9 132
bogdanm 74:a842253909c9 133
bogdanm 74:a842253909c9 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
bogdanm 74:a842253909c9 135 /* IAR iccarm specific functions */
bogdanm 74:a842253909c9 136
bogdanm 74:a842253909c9 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 138 #include <cmsis_iar.h>
bogdanm 74:a842253909c9 139
bogdanm 74:a842253909c9 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 141
bogdanm 74:a842253909c9 142
bogdanm 74:a842253909c9 143
bogdanm 74:a842253909c9 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
bogdanm 74:a842253909c9 145 /* TI CCS specific functions */
bogdanm 74:a842253909c9 146
bogdanm 74:a842253909c9 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 148 #include <cmsis_ccs.h>
bogdanm 74:a842253909c9 149
bogdanm 74:a842253909c9 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 151
bogdanm 74:a842253909c9 152
bogdanm 74:a842253909c9 153
bogdanm 74:a842253909c9 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
bogdanm 74:a842253909c9 155 /* GNU gcc specific functions */
bogdanm 74:a842253909c9 156
bogdanm 74:a842253909c9 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 159 {
bogdanm 74:a842253909c9 160 uint32_t result;
bogdanm 74:a842253909c9 161
bogdanm 74:a842253909c9 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 163 return(result);
bogdanm 74:a842253909c9 164 }
bogdanm 74:a842253909c9 165
bogdanm 74:a842253909c9 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 167 {
bogdanm 74:a842253909c9 168 uint32_t result;
bogdanm 74:a842253909c9 169
bogdanm 74:a842253909c9 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 171 return(result);
bogdanm 74:a842253909c9 172 }
bogdanm 74:a842253909c9 173
bogdanm 74:a842253909c9 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 175 {
bogdanm 74:a842253909c9 176 uint32_t result;
bogdanm 74:a842253909c9 177
bogdanm 74:a842253909c9 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 179 return(result);
bogdanm 74:a842253909c9 180 }
bogdanm 74:a842253909c9 181
bogdanm 74:a842253909c9 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 183 {
bogdanm 74:a842253909c9 184 uint32_t result;
bogdanm 74:a842253909c9 185
bogdanm 74:a842253909c9 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 187 return(result);
bogdanm 74:a842253909c9 188 }
bogdanm 74:a842253909c9 189
bogdanm 74:a842253909c9 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 191 {
bogdanm 74:a842253909c9 192 uint32_t result;
bogdanm 74:a842253909c9 193
bogdanm 74:a842253909c9 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 195 return(result);
bogdanm 74:a842253909c9 196 }
bogdanm 74:a842253909c9 197
bogdanm 74:a842253909c9 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 199 {
bogdanm 74:a842253909c9 200 uint32_t result;
bogdanm 74:a842253909c9 201
bogdanm 74:a842253909c9 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 203 return(result);
bogdanm 74:a842253909c9 204 }
bogdanm 74:a842253909c9 205
bogdanm 74:a842253909c9 206
bogdanm 74:a842253909c9 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 208 {
bogdanm 74:a842253909c9 209 uint32_t result;
bogdanm 74:a842253909c9 210
bogdanm 74:a842253909c9 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 212 return(result);
bogdanm 74:a842253909c9 213 }
bogdanm 74:a842253909c9 214
bogdanm 74:a842253909c9 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 216 {
bogdanm 74:a842253909c9 217 uint32_t result;
bogdanm 74:a842253909c9 218
bogdanm 74:a842253909c9 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 220 return(result);
bogdanm 74:a842253909c9 221 }
bogdanm 74:a842253909c9 222
bogdanm 74:a842253909c9 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 224 {
bogdanm 74:a842253909c9 225 uint32_t result;
bogdanm 74:a842253909c9 226
bogdanm 74:a842253909c9 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 228 return(result);
bogdanm 74:a842253909c9 229 }
bogdanm 74:a842253909c9 230
bogdanm 74:a842253909c9 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 232 {
bogdanm 74:a842253909c9 233 uint32_t result;
bogdanm 74:a842253909c9 234
bogdanm 74:a842253909c9 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 236 return(result);
bogdanm 74:a842253909c9 237 }
bogdanm 74:a842253909c9 238
bogdanm 74:a842253909c9 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 240 {
bogdanm 74:a842253909c9 241 uint32_t result;
bogdanm 74:a842253909c9 242
bogdanm 74:a842253909c9 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 244 return(result);
bogdanm 74:a842253909c9 245 }
bogdanm 74:a842253909c9 246
bogdanm 74:a842253909c9 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 248 {
bogdanm 74:a842253909c9 249 uint32_t result;
bogdanm 74:a842253909c9 250
bogdanm 74:a842253909c9 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 252 return(result);
bogdanm 74:a842253909c9 253 }
bogdanm 74:a842253909c9 254
bogdanm 74:a842253909c9 255
bogdanm 74:a842253909c9 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 257 {
bogdanm 74:a842253909c9 258 uint32_t result;
bogdanm 74:a842253909c9 259
bogdanm 74:a842253909c9 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 261 return(result);
bogdanm 74:a842253909c9 262 }
bogdanm 74:a842253909c9 263
bogdanm 74:a842253909c9 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 265 {
bogdanm 74:a842253909c9 266 uint32_t result;
bogdanm 74:a842253909c9 267
bogdanm 74:a842253909c9 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 269 return(result);
bogdanm 74:a842253909c9 270 }
bogdanm 74:a842253909c9 271
bogdanm 74:a842253909c9 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 273 {
bogdanm 74:a842253909c9 274 uint32_t result;
bogdanm 74:a842253909c9 275
bogdanm 74:a842253909c9 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 277 return(result);
bogdanm 74:a842253909c9 278 }
bogdanm 74:a842253909c9 279
bogdanm 74:a842253909c9 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 281 {
bogdanm 74:a842253909c9 282 uint32_t result;
bogdanm 74:a842253909c9 283
bogdanm 74:a842253909c9 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 285 return(result);
bogdanm 74:a842253909c9 286 }
bogdanm 74:a842253909c9 287
bogdanm 74:a842253909c9 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 289 {
bogdanm 74:a842253909c9 290 uint32_t result;
bogdanm 74:a842253909c9 291
bogdanm 74:a842253909c9 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 293 return(result);
bogdanm 74:a842253909c9 294 }
bogdanm 74:a842253909c9 295
bogdanm 74:a842253909c9 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 297 {
bogdanm 74:a842253909c9 298 uint32_t result;
bogdanm 74:a842253909c9 299
bogdanm 74:a842253909c9 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 301 return(result);
bogdanm 74:a842253909c9 302 }
bogdanm 74:a842253909c9 303
bogdanm 74:a842253909c9 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 305 {
bogdanm 74:a842253909c9 306 uint32_t result;
bogdanm 74:a842253909c9 307
bogdanm 74:a842253909c9 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 309 return(result);
bogdanm 74:a842253909c9 310 }
bogdanm 74:a842253909c9 311
bogdanm 74:a842253909c9 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 313 {
bogdanm 74:a842253909c9 314 uint32_t result;
bogdanm 74:a842253909c9 315
bogdanm 74:a842253909c9 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 317 return(result);
bogdanm 74:a842253909c9 318 }
bogdanm 74:a842253909c9 319
bogdanm 74:a842253909c9 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 321 {
bogdanm 74:a842253909c9 322 uint32_t result;
bogdanm 74:a842253909c9 323
bogdanm 74:a842253909c9 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 325 return(result);
bogdanm 74:a842253909c9 326 }
bogdanm 74:a842253909c9 327
bogdanm 74:a842253909c9 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 329 {
bogdanm 74:a842253909c9 330 uint32_t result;
bogdanm 74:a842253909c9 331
bogdanm 74:a842253909c9 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 333 return(result);
bogdanm 74:a842253909c9 334 }
bogdanm 74:a842253909c9 335
bogdanm 74:a842253909c9 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 337 {
bogdanm 74:a842253909c9 338 uint32_t result;
bogdanm 74:a842253909c9 339
bogdanm 74:a842253909c9 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 341 return(result);
bogdanm 74:a842253909c9 342 }
bogdanm 74:a842253909c9 343
bogdanm 74:a842253909c9 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 345 {
bogdanm 74:a842253909c9 346 uint32_t result;
bogdanm 74:a842253909c9 347
bogdanm 74:a842253909c9 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 349 return(result);
bogdanm 74:a842253909c9 350 }
bogdanm 74:a842253909c9 351
bogdanm 74:a842253909c9 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 353 {
bogdanm 74:a842253909c9 354 uint32_t result;
bogdanm 74:a842253909c9 355
bogdanm 74:a842253909c9 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 357 return(result);
bogdanm 74:a842253909c9 358 }
bogdanm 74:a842253909c9 359
bogdanm 74:a842253909c9 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 361 {
bogdanm 74:a842253909c9 362 uint32_t result;
bogdanm 74:a842253909c9 363
bogdanm 74:a842253909c9 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 365 return(result);
bogdanm 74:a842253909c9 366 }
bogdanm 74:a842253909c9 367
bogdanm 74:a842253909c9 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 369 {
bogdanm 74:a842253909c9 370 uint32_t result;
bogdanm 74:a842253909c9 371
bogdanm 74:a842253909c9 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 373 return(result);
bogdanm 74:a842253909c9 374 }
bogdanm 74:a842253909c9 375
bogdanm 74:a842253909c9 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 377 {
bogdanm 74:a842253909c9 378 uint32_t result;
bogdanm 74:a842253909c9 379
bogdanm 74:a842253909c9 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 381 return(result);
bogdanm 74:a842253909c9 382 }
bogdanm 74:a842253909c9 383
bogdanm 74:a842253909c9 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 385 {
bogdanm 74:a842253909c9 386 uint32_t result;
bogdanm 74:a842253909c9 387
bogdanm 74:a842253909c9 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 389 return(result);
bogdanm 74:a842253909c9 390 }
bogdanm 74:a842253909c9 391
bogdanm 74:a842253909c9 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 393 {
bogdanm 74:a842253909c9 394 uint32_t result;
bogdanm 74:a842253909c9 395
bogdanm 74:a842253909c9 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 397 return(result);
bogdanm 74:a842253909c9 398 }
bogdanm 74:a842253909c9 399
bogdanm 74:a842253909c9 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 401 {
bogdanm 74:a842253909c9 402 uint32_t result;
bogdanm 74:a842253909c9 403
bogdanm 74:a842253909c9 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 405 return(result);
bogdanm 74:a842253909c9 406 }
bogdanm 74:a842253909c9 407
bogdanm 74:a842253909c9 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 409 {
bogdanm 74:a842253909c9 410 uint32_t result;
bogdanm 74:a842253909c9 411
bogdanm 74:a842253909c9 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 413 return(result);
bogdanm 74:a842253909c9 414 }
bogdanm 74:a842253909c9 415
bogdanm 74:a842253909c9 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 417 {
bogdanm 74:a842253909c9 418 uint32_t result;
bogdanm 74:a842253909c9 419
bogdanm 74:a842253909c9 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 421 return(result);
bogdanm 74:a842253909c9 422 }
bogdanm 74:a842253909c9 423
bogdanm 74:a842253909c9 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 425 {
bogdanm 74:a842253909c9 426 uint32_t result;
bogdanm 74:a842253909c9 427
bogdanm 74:a842253909c9 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 429 return(result);
bogdanm 74:a842253909c9 430 }
bogdanm 74:a842253909c9 431
bogdanm 74:a842253909c9 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 433 {
bogdanm 74:a842253909c9 434 uint32_t result;
bogdanm 74:a842253909c9 435
bogdanm 74:a842253909c9 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 437 return(result);
bogdanm 74:a842253909c9 438 }
bogdanm 74:a842253909c9 439
bogdanm 74:a842253909c9 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 441 {
bogdanm 74:a842253909c9 442 uint32_t result;
bogdanm 74:a842253909c9 443
bogdanm 74:a842253909c9 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 445 return(result);
bogdanm 74:a842253909c9 446 }
bogdanm 74:a842253909c9 447
bogdanm 74:a842253909c9 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 449 {
bogdanm 74:a842253909c9 450 uint32_t result;
bogdanm 74:a842253909c9 451
bogdanm 74:a842253909c9 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 453 return(result);
bogdanm 74:a842253909c9 454 }
bogdanm 74:a842253909c9 455
bogdanm 74:a842253909c9 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 74:a842253909c9 457 {
bogdanm 74:a842253909c9 458 uint32_t result;
bogdanm 74:a842253909c9 459
bogdanm 74:a842253909c9 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 74:a842253909c9 461 return(result);
bogdanm 74:a842253909c9 462 }
bogdanm 74:a842253909c9 463
bogdanm 74:a842253909c9 464 #define __SSAT16(ARG1,ARG2) \
bogdanm 74:a842253909c9 465 ({ \
bogdanm 74:a842253909c9 466 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 74:a842253909c9 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 74:a842253909c9 468 __RES; \
bogdanm 74:a842253909c9 469 })
bogdanm 74:a842253909c9 470
bogdanm 74:a842253909c9 471 #define __USAT16(ARG1,ARG2) \
bogdanm 74:a842253909c9 472 ({ \
bogdanm 74:a842253909c9 473 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 74:a842253909c9 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 74:a842253909c9 475 __RES; \
bogdanm 74:a842253909c9 476 })
bogdanm 74:a842253909c9 477
bogdanm 74:a842253909c9 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
bogdanm 74:a842253909c9 479 {
bogdanm 74:a842253909c9 480 uint32_t result;
bogdanm 74:a842253909c9 481
bogdanm 74:a842253909c9 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
bogdanm 74:a842253909c9 483 return(result);
bogdanm 74:a842253909c9 484 }
bogdanm 74:a842253909c9 485
bogdanm 74:a842253909c9 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 487 {
bogdanm 74:a842253909c9 488 uint32_t result;
bogdanm 74:a842253909c9 489
bogdanm 74:a842253909c9 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 491 return(result);
bogdanm 74:a842253909c9 492 }
bogdanm 74:a842253909c9 493
bogdanm 74:a842253909c9 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
bogdanm 74:a842253909c9 495 {
bogdanm 74:a842253909c9 496 uint32_t result;
bogdanm 74:a842253909c9 497
bogdanm 74:a842253909c9 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
bogdanm 74:a842253909c9 499 return(result);
bogdanm 74:a842253909c9 500 }
bogdanm 74:a842253909c9 501
bogdanm 74:a842253909c9 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 503 {
bogdanm 74:a842253909c9 504 uint32_t result;
bogdanm 74:a842253909c9 505
bogdanm 74:a842253909c9 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 507 return(result);
bogdanm 74:a842253909c9 508 }
bogdanm 74:a842253909c9 509
bogdanm 74:a842253909c9 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 511 {
bogdanm 74:a842253909c9 512 uint32_t result;
bogdanm 74:a842253909c9 513
bogdanm 74:a842253909c9 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 515 return(result);
bogdanm 74:a842253909c9 516 }
bogdanm 74:a842253909c9 517
bogdanm 74:a842253909c9 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 519 {
bogdanm 74:a842253909c9 520 uint32_t result;
bogdanm 74:a842253909c9 521
bogdanm 74:a842253909c9 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 523 return(result);
bogdanm 74:a842253909c9 524 }
bogdanm 74:a842253909c9 525
bogdanm 74:a842253909c9 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 74:a842253909c9 527 {
bogdanm 74:a842253909c9 528 uint32_t result;
bogdanm 74:a842253909c9 529
bogdanm 74:a842253909c9 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 74:a842253909c9 531 return(result);
bogdanm 74:a842253909c9 532 }
bogdanm 74:a842253909c9 533
bogdanm 74:a842253909c9 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 74:a842253909c9 535 {
bogdanm 74:a842253909c9 536 uint32_t result;
bogdanm 74:a842253909c9 537
bogdanm 74:a842253909c9 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 74:a842253909c9 539 return(result);
bogdanm 74:a842253909c9 540 }
bogdanm 74:a842253909c9 541
bogdanm 74:a842253909c9 542 #define __SMLALD(ARG1,ARG2,ARG3) \
bogdanm 74:a842253909c9 543 ({ \
bogdanm 74:a842253909c9 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
bogdanm 74:a842253909c9 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 74:a842253909c9 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 74:a842253909c9 547 })
bogdanm 74:a842253909c9 548
bogdanm 74:a842253909c9 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
bogdanm 74:a842253909c9 550 ({ \
bogdanm 74:a842253909c9 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
bogdanm 74:a842253909c9 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 74:a842253909c9 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 74:a842253909c9 554 })
bogdanm 74:a842253909c9 555
bogdanm 74:a842253909c9 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 557 {
bogdanm 74:a842253909c9 558 uint32_t result;
bogdanm 74:a842253909c9 559
bogdanm 74:a842253909c9 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 561 return(result);
bogdanm 74:a842253909c9 562 }
bogdanm 74:a842253909c9 563
bogdanm 74:a842253909c9 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 565 {
bogdanm 74:a842253909c9 566 uint32_t result;
bogdanm 74:a842253909c9 567
bogdanm 74:a842253909c9 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 569 return(result);
bogdanm 74:a842253909c9 570 }
bogdanm 74:a842253909c9 571
bogdanm 74:a842253909c9 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 74:a842253909c9 573 {
bogdanm 74:a842253909c9 574 uint32_t result;
bogdanm 74:a842253909c9 575
bogdanm 74:a842253909c9 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 74:a842253909c9 577 return(result);
bogdanm 74:a842253909c9 578 }
bogdanm 74:a842253909c9 579
bogdanm 74:a842253909c9 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 74:a842253909c9 581 {
bogdanm 74:a842253909c9 582 uint32_t result;
bogdanm 74:a842253909c9 583
bogdanm 74:a842253909c9 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 74:a842253909c9 585 return(result);
bogdanm 74:a842253909c9 586 }
bogdanm 74:a842253909c9 587
bogdanm 74:a842253909c9 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
bogdanm 74:a842253909c9 589 ({ \
bogdanm 74:a842253909c9 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
bogdanm 74:a842253909c9 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 74:a842253909c9 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 74:a842253909c9 593 })
bogdanm 74:a842253909c9 594
bogdanm 74:a842253909c9 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
bogdanm 74:a842253909c9 596 ({ \
bogdanm 74:a842253909c9 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
bogdanm 74:a842253909c9 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 74:a842253909c9 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 74:a842253909c9 600 })
bogdanm 74:a842253909c9 601
bogdanm 74:a842253909c9 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 603 {
bogdanm 74:a842253909c9 604 uint32_t result;
bogdanm 74:a842253909c9 605
bogdanm 74:a842253909c9 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 607 return(result);
bogdanm 74:a842253909c9 608 }
bogdanm 74:a842253909c9 609
bogdanm 74:a842253909c9 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 611 {
bogdanm 74:a842253909c9 612 uint32_t result;
bogdanm 74:a842253909c9 613
bogdanm 74:a842253909c9 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 615 return(result);
bogdanm 74:a842253909c9 616 }
bogdanm 74:a842253909c9 617
bogdanm 74:a842253909c9 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
bogdanm 74:a842253909c9 619 {
bogdanm 74:a842253909c9 620 uint32_t result;
bogdanm 74:a842253909c9 621
bogdanm 74:a842253909c9 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 74:a842253909c9 623 return(result);
bogdanm 74:a842253909c9 624 }
bogdanm 74:a842253909c9 625
bogdanm 74:a842253909c9 626 #define __PKHBT(ARG1,ARG2,ARG3) \
bogdanm 74:a842253909c9 627 ({ \
bogdanm 74:a842253909c9 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
bogdanm 74:a842253909c9 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
bogdanm 74:a842253909c9 630 __RES; \
bogdanm 74:a842253909c9 631 })
bogdanm 74:a842253909c9 632
bogdanm 74:a842253909c9 633 #define __PKHTB(ARG1,ARG2,ARG3) \
bogdanm 74:a842253909c9 634 ({ \
bogdanm 74:a842253909c9 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
bogdanm 74:a842253909c9 636 if (ARG3 == 0) \
bogdanm 74:a842253909c9 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
bogdanm 74:a842253909c9 638 else \
bogdanm 74:a842253909c9 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
bogdanm 74:a842253909c9 640 __RES; \
bogdanm 74:a842253909c9 641 })
bogdanm 74:a842253909c9 642
bogdanm 74:a842253909c9 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
bogdanm 74:a842253909c9 644 {
bogdanm 74:a842253909c9 645 int32_t result;
bogdanm 74:a842253909c9 646
bogdanm 74:a842253909c9 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
bogdanm 74:a842253909c9 648 return(result);
bogdanm 74:a842253909c9 649 }
bogdanm 74:a842253909c9 650
bogdanm 74:a842253909c9 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 652
bogdanm 74:a842253909c9 653
bogdanm 74:a842253909c9 654
bogdanm 74:a842253909c9 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
bogdanm 74:a842253909c9 656 /* TASKING carm specific functions */
bogdanm 74:a842253909c9 657
bogdanm 74:a842253909c9 658
bogdanm 74:a842253909c9 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 660 /* not yet supported */
bogdanm 74:a842253909c9 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 74:a842253909c9 662
bogdanm 74:a842253909c9 663
bogdanm 74:a842253909c9 664 #endif
bogdanm 74:a842253909c9 665
bogdanm 74:a842253909c9 666 /*@} end of group CMSIS_SIMD_intrinsics */
bogdanm 74:a842253909c9 667
bogdanm 74:a842253909c9 668
bogdanm 74:a842253909c9 669 #endif /* __CORE_CM4_SIMD_H */
bogdanm 74:a842253909c9 670
bogdanm 74:a842253909c9 671 #ifdef __cplusplus
bogdanm 74:a842253909c9 672 }
bogdanm 74:a842253909c9 673 #endif