mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_KL27Z/core_cm0plus.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 120:7c328cabac7e 1 /**************************************************************************//**
Kojto 120:7c328cabac7e 2 * @file core_cm0plus.h
Kojto 120:7c328cabac7e 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 120:7c328cabac7e 4 * @version V4.10
Kojto 120:7c328cabac7e 5 * @date 18. March 2015
Kojto 120:7c328cabac7e 6 *
Kojto 120:7c328cabac7e 7 * @note
Kojto 120:7c328cabac7e 8 *
Kojto 120:7c328cabac7e 9 ******************************************************************************/
Kojto 120:7c328cabac7e 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 120:7c328cabac7e 11
Kojto 120:7c328cabac7e 12 All rights reserved.
Kojto 120:7c328cabac7e 13 Redistribution and use in source and binary forms, with or without
Kojto 120:7c328cabac7e 14 modification, are permitted provided that the following conditions are met:
Kojto 120:7c328cabac7e 15 - Redistributions of source code must retain the above copyright
Kojto 120:7c328cabac7e 16 notice, this list of conditions and the following disclaimer.
Kojto 120:7c328cabac7e 17 - Redistributions in binary form must reproduce the above copyright
Kojto 120:7c328cabac7e 18 notice, this list of conditions and the following disclaimer in the
Kojto 120:7c328cabac7e 19 documentation and/or other materials provided with the distribution.
Kojto 120:7c328cabac7e 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 120:7c328cabac7e 21 to endorse or promote products derived from this software without
Kojto 120:7c328cabac7e 22 specific prior written permission.
Kojto 120:7c328cabac7e 23 *
Kojto 120:7c328cabac7e 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 120:7c328cabac7e 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 120:7c328cabac7e 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 120:7c328cabac7e 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 120:7c328cabac7e 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 120:7c328cabac7e 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 120:7c328cabac7e 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 120:7c328cabac7e 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 120:7c328cabac7e 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 120:7c328cabac7e 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 120:7c328cabac7e 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 120:7c328cabac7e 35 ---------------------------------------------------------------------------*/
Kojto 120:7c328cabac7e 36
Kojto 120:7c328cabac7e 37
Kojto 120:7c328cabac7e 38 #if defined ( __ICCARM__ )
Kojto 120:7c328cabac7e 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 120:7c328cabac7e 40 #endif
Kojto 120:7c328cabac7e 41
Kojto 120:7c328cabac7e 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 120:7c328cabac7e 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 120:7c328cabac7e 44
Kojto 120:7c328cabac7e 45 #ifdef __cplusplus
Kojto 120:7c328cabac7e 46 extern "C" {
Kojto 120:7c328cabac7e 47 #endif
Kojto 120:7c328cabac7e 48
Kojto 120:7c328cabac7e 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 120:7c328cabac7e 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 120:7c328cabac7e 51
Kojto 120:7c328cabac7e 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 120:7c328cabac7e 53 Function definitions in header files are used to allow 'inlining'.
Kojto 120:7c328cabac7e 54
Kojto 120:7c328cabac7e 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 120:7c328cabac7e 56 Unions are used for effective representation of core registers.
Kojto 120:7c328cabac7e 57
Kojto 120:7c328cabac7e 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 120:7c328cabac7e 59 Function-like macros are used to allow more efficient code.
Kojto 120:7c328cabac7e 60 */
Kojto 120:7c328cabac7e 61
Kojto 120:7c328cabac7e 62
Kojto 120:7c328cabac7e 63 /*******************************************************************************
Kojto 120:7c328cabac7e 64 * CMSIS definitions
Kojto 120:7c328cabac7e 65 ******************************************************************************/
Kojto 120:7c328cabac7e 66 /** \ingroup Cortex-M0+
Kojto 120:7c328cabac7e 67 @{
Kojto 120:7c328cabac7e 68 */
Kojto 120:7c328cabac7e 69
Kojto 120:7c328cabac7e 70 /* CMSIS CM0P definitions */
Kojto 120:7c328cabac7e 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 120:7c328cabac7e 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 120:7c328cabac7e 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 120:7c328cabac7e 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 120:7c328cabac7e 75
Kojto 120:7c328cabac7e 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 120:7c328cabac7e 77
Kojto 120:7c328cabac7e 78
Kojto 120:7c328cabac7e 79 #if defined ( __CC_ARM )
Kojto 120:7c328cabac7e 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 120:7c328cabac7e 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 120:7c328cabac7e 82 #define __STATIC_INLINE static __inline
Kojto 120:7c328cabac7e 83
Kojto 120:7c328cabac7e 84 #elif defined ( __GNUC__ )
Kojto 120:7c328cabac7e 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 120:7c328cabac7e 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 120:7c328cabac7e 87 #define __STATIC_INLINE static inline
Kojto 120:7c328cabac7e 88
Kojto 120:7c328cabac7e 89 #elif defined ( __ICCARM__ )
Kojto 120:7c328cabac7e 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 120:7c328cabac7e 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 120:7c328cabac7e 92 #define __STATIC_INLINE static inline
Kojto 120:7c328cabac7e 93
Kojto 120:7c328cabac7e 94 #elif defined ( __TMS470__ )
Kojto 120:7c328cabac7e 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 120:7c328cabac7e 96 #define __STATIC_INLINE static inline
Kojto 120:7c328cabac7e 97
Kojto 120:7c328cabac7e 98 #elif defined ( __TASKING__ )
Kojto 120:7c328cabac7e 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 120:7c328cabac7e 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 120:7c328cabac7e 101 #define __STATIC_INLINE static inline
Kojto 120:7c328cabac7e 102
Kojto 120:7c328cabac7e 103 #elif defined ( __CSMC__ )
Kojto 120:7c328cabac7e 104 #define __packed
Kojto 120:7c328cabac7e 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 120:7c328cabac7e 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 120:7c328cabac7e 107 #define __STATIC_INLINE static inline
Kojto 120:7c328cabac7e 108
Kojto 120:7c328cabac7e 109 #endif
Kojto 120:7c328cabac7e 110
Kojto 120:7c328cabac7e 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 120:7c328cabac7e 112 This core does not support an FPU at all
Kojto 120:7c328cabac7e 113 */
Kojto 120:7c328cabac7e 114 #define __FPU_USED 0
Kojto 120:7c328cabac7e 115
Kojto 120:7c328cabac7e 116 #if defined ( __CC_ARM )
Kojto 120:7c328cabac7e 117 #if defined __TARGET_FPU_VFP
Kojto 120:7c328cabac7e 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 120:7c328cabac7e 119 #endif
Kojto 120:7c328cabac7e 120
Kojto 120:7c328cabac7e 121 #elif defined ( __GNUC__ )
Kojto 120:7c328cabac7e 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 120:7c328cabac7e 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 120:7c328cabac7e 124 #endif
Kojto 120:7c328cabac7e 125
Kojto 120:7c328cabac7e 126 #elif defined ( __ICCARM__ )
Kojto 120:7c328cabac7e 127 #if defined __ARMVFP__
Kojto 120:7c328cabac7e 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 120:7c328cabac7e 129 #endif
Kojto 120:7c328cabac7e 130
Kojto 120:7c328cabac7e 131 #elif defined ( __TMS470__ )
Kojto 120:7c328cabac7e 132 #if defined __TI__VFP_SUPPORT____
Kojto 120:7c328cabac7e 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 120:7c328cabac7e 134 #endif
Kojto 120:7c328cabac7e 135
Kojto 120:7c328cabac7e 136 #elif defined ( __TASKING__ )
Kojto 120:7c328cabac7e 137 #if defined __FPU_VFP__
Kojto 120:7c328cabac7e 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 120:7c328cabac7e 139 #endif
Kojto 120:7c328cabac7e 140
Kojto 120:7c328cabac7e 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 120:7c328cabac7e 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 120:7c328cabac7e 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 120:7c328cabac7e 144 #endif
Kojto 120:7c328cabac7e 145 #endif
Kojto 120:7c328cabac7e 146
Kojto 120:7c328cabac7e 147 #include <stdint.h> /* standard types definitions */
Kojto 120:7c328cabac7e 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 120:7c328cabac7e 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 120:7c328cabac7e 150
Kojto 120:7c328cabac7e 151 #ifdef __cplusplus
Kojto 120:7c328cabac7e 152 }
Kojto 120:7c328cabac7e 153 #endif
Kojto 120:7c328cabac7e 154
Kojto 120:7c328cabac7e 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 120:7c328cabac7e 156
Kojto 120:7c328cabac7e 157 #ifndef __CMSIS_GENERIC
Kojto 120:7c328cabac7e 158
Kojto 120:7c328cabac7e 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 120:7c328cabac7e 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 120:7c328cabac7e 161
Kojto 120:7c328cabac7e 162 #ifdef __cplusplus
Kojto 120:7c328cabac7e 163 extern "C" {
Kojto 120:7c328cabac7e 164 #endif
Kojto 120:7c328cabac7e 165
Kojto 120:7c328cabac7e 166 /* check device defines and use defaults */
Kojto 120:7c328cabac7e 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 120:7c328cabac7e 168 #ifndef __CM0PLUS_REV
Kojto 120:7c328cabac7e 169 #define __CM0PLUS_REV 0x0000
Kojto 120:7c328cabac7e 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 120:7c328cabac7e 171 #endif
Kojto 120:7c328cabac7e 172
Kojto 120:7c328cabac7e 173 #ifndef __MPU_PRESENT
Kojto 120:7c328cabac7e 174 #define __MPU_PRESENT 0
Kojto 120:7c328cabac7e 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 120:7c328cabac7e 176 #endif
Kojto 120:7c328cabac7e 177
Kojto 120:7c328cabac7e 178 #ifndef __VTOR_PRESENT
Kojto 120:7c328cabac7e 179 #define __VTOR_PRESENT 0
Kojto 120:7c328cabac7e 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 120:7c328cabac7e 181 #endif
Kojto 120:7c328cabac7e 182
Kojto 120:7c328cabac7e 183 #ifndef __NVIC_PRIO_BITS
Kojto 120:7c328cabac7e 184 #define __NVIC_PRIO_BITS 2
Kojto 120:7c328cabac7e 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 120:7c328cabac7e 186 #endif
Kojto 120:7c328cabac7e 187
Kojto 120:7c328cabac7e 188 #ifndef __Vendor_SysTickConfig
Kojto 120:7c328cabac7e 189 #define __Vendor_SysTickConfig 0
Kojto 120:7c328cabac7e 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 120:7c328cabac7e 191 #endif
Kojto 120:7c328cabac7e 192 #endif
Kojto 120:7c328cabac7e 193
Kojto 120:7c328cabac7e 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 120:7c328cabac7e 195 /**
Kojto 120:7c328cabac7e 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 120:7c328cabac7e 197
Kojto 120:7c328cabac7e 198 <strong>IO Type Qualifiers</strong> are used
Kojto 120:7c328cabac7e 199 \li to specify the access to peripheral variables.
Kojto 120:7c328cabac7e 200 \li for automatic generation of peripheral register debug information.
Kojto 120:7c328cabac7e 201 */
Kojto 120:7c328cabac7e 202 #ifdef __cplusplus
Kojto 120:7c328cabac7e 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 120:7c328cabac7e 204 #else
Kojto 120:7c328cabac7e 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 120:7c328cabac7e 206 #endif
Kojto 120:7c328cabac7e 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 120:7c328cabac7e 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 120:7c328cabac7e 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 120:7c328cabac7e 218 /*@} end of group Cortex-M0+ */
Kojto 120:7c328cabac7e 219
Kojto 120:7c328cabac7e 220
Kojto 120:7c328cabac7e 221
Kojto 120:7c328cabac7e 222 /*******************************************************************************
Kojto 120:7c328cabac7e 223 * Register Abstraction
Kojto 120:7c328cabac7e 224 Core Register contain:
Kojto 120:7c328cabac7e 225 - Core Register
Kojto 120:7c328cabac7e 226 - Core NVIC Register
Kojto 120:7c328cabac7e 227 - Core SCB Register
Kojto 120:7c328cabac7e 228 - Core SysTick Register
Kojto 120:7c328cabac7e 229 - Core MPU Register
Kojto 120:7c328cabac7e 230 ******************************************************************************/
Kojto 120:7c328cabac7e 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 120:7c328cabac7e 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 120:7c328cabac7e 233 */
Kojto 120:7c328cabac7e 234
Kojto 120:7c328cabac7e 235 /** \ingroup CMSIS_core_register
Kojto 120:7c328cabac7e 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 120:7c328cabac7e 237 \brief Core Register type definitions.
Kojto 120:7c328cabac7e 238 @{
Kojto 120:7c328cabac7e 239 */
Kojto 120:7c328cabac7e 240
Kojto 120:7c328cabac7e 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 120:7c328cabac7e 242 */
Kojto 120:7c328cabac7e 243 typedef union
Kojto 120:7c328cabac7e 244 {
Kojto 120:7c328cabac7e 245 struct
Kojto 120:7c328cabac7e 246 {
Kojto 120:7c328cabac7e 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 120:7c328cabac7e 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 120:7c328cabac7e 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 120:7c328cabac7e 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 120:7c328cabac7e 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 120:7c328cabac7e 252 } b; /*!< Structure used for bit access */
Kojto 120:7c328cabac7e 253 uint32_t w; /*!< Type used for word access */
Kojto 120:7c328cabac7e 254 } APSR_Type;
Kojto 120:7c328cabac7e 255
Kojto 120:7c328cabac7e 256 /* APSR Register Definitions */
Kojto 120:7c328cabac7e 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 120:7c328cabac7e 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 120:7c328cabac7e 259
Kojto 120:7c328cabac7e 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 120:7c328cabac7e 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 120:7c328cabac7e 262
Kojto 120:7c328cabac7e 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 120:7c328cabac7e 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 120:7c328cabac7e 265
Kojto 120:7c328cabac7e 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 120:7c328cabac7e 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 120:7c328cabac7e 268
Kojto 120:7c328cabac7e 269
Kojto 120:7c328cabac7e 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 120:7c328cabac7e 271 */
Kojto 120:7c328cabac7e 272 typedef union
Kojto 120:7c328cabac7e 273 {
Kojto 120:7c328cabac7e 274 struct
Kojto 120:7c328cabac7e 275 {
Kojto 120:7c328cabac7e 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 120:7c328cabac7e 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 120:7c328cabac7e 278 } b; /*!< Structure used for bit access */
Kojto 120:7c328cabac7e 279 uint32_t w; /*!< Type used for word access */
Kojto 120:7c328cabac7e 280 } IPSR_Type;
Kojto 120:7c328cabac7e 281
Kojto 120:7c328cabac7e 282 /* IPSR Register Definitions */
Kojto 120:7c328cabac7e 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 120:7c328cabac7e 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 120:7c328cabac7e 285
Kojto 120:7c328cabac7e 286
Kojto 120:7c328cabac7e 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 120:7c328cabac7e 288 */
Kojto 120:7c328cabac7e 289 typedef union
Kojto 120:7c328cabac7e 290 {
Kojto 120:7c328cabac7e 291 struct
Kojto 120:7c328cabac7e 292 {
Kojto 120:7c328cabac7e 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 120:7c328cabac7e 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 120:7c328cabac7e 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 120:7c328cabac7e 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 120:7c328cabac7e 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 120:7c328cabac7e 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 120:7c328cabac7e 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 120:7c328cabac7e 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 120:7c328cabac7e 301 } b; /*!< Structure used for bit access */
Kojto 120:7c328cabac7e 302 uint32_t w; /*!< Type used for word access */
Kojto 120:7c328cabac7e 303 } xPSR_Type;
Kojto 120:7c328cabac7e 304
Kojto 120:7c328cabac7e 305 /* xPSR Register Definitions */
Kojto 120:7c328cabac7e 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 120:7c328cabac7e 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 120:7c328cabac7e 308
Kojto 120:7c328cabac7e 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 120:7c328cabac7e 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 120:7c328cabac7e 311
Kojto 120:7c328cabac7e 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 120:7c328cabac7e 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 120:7c328cabac7e 314
Kojto 120:7c328cabac7e 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 120:7c328cabac7e 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 120:7c328cabac7e 317
Kojto 120:7c328cabac7e 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 120:7c328cabac7e 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 120:7c328cabac7e 320
Kojto 120:7c328cabac7e 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 120:7c328cabac7e 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 120:7c328cabac7e 323
Kojto 120:7c328cabac7e 324
Kojto 120:7c328cabac7e 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 120:7c328cabac7e 326 */
Kojto 120:7c328cabac7e 327 typedef union
Kojto 120:7c328cabac7e 328 {
Kojto 120:7c328cabac7e 329 struct
Kojto 120:7c328cabac7e 330 {
Kojto 120:7c328cabac7e 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 120:7c328cabac7e 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 120:7c328cabac7e 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 120:7c328cabac7e 334 } b; /*!< Structure used for bit access */
Kojto 120:7c328cabac7e 335 uint32_t w; /*!< Type used for word access */
Kojto 120:7c328cabac7e 336 } CONTROL_Type;
Kojto 120:7c328cabac7e 337
Kojto 120:7c328cabac7e 338 /* CONTROL Register Definitions */
Kojto 120:7c328cabac7e 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 120:7c328cabac7e 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 120:7c328cabac7e 341
Kojto 120:7c328cabac7e 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 120:7c328cabac7e 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 120:7c328cabac7e 344
Kojto 120:7c328cabac7e 345 /*@} end of group CMSIS_CORE */
Kojto 120:7c328cabac7e 346
Kojto 120:7c328cabac7e 347
Kojto 120:7c328cabac7e 348 /** \ingroup CMSIS_core_register
Kojto 120:7c328cabac7e 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 120:7c328cabac7e 350 \brief Type definitions for the NVIC Registers
Kojto 120:7c328cabac7e 351 @{
Kojto 120:7c328cabac7e 352 */
Kojto 120:7c328cabac7e 353
Kojto 120:7c328cabac7e 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 120:7c328cabac7e 355 */
Kojto 120:7c328cabac7e 356 typedef struct
Kojto 120:7c328cabac7e 357 {
Kojto 120:7c328cabac7e 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 120:7c328cabac7e 359 uint32_t RESERVED0[31];
Kojto 120:7c328cabac7e 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 120:7c328cabac7e 361 uint32_t RSERVED1[31];
Kojto 120:7c328cabac7e 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 120:7c328cabac7e 363 uint32_t RESERVED2[31];
Kojto 120:7c328cabac7e 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 120:7c328cabac7e 365 uint32_t RESERVED3[31];
Kojto 120:7c328cabac7e 366 uint32_t RESERVED4[64];
Kojto 120:7c328cabac7e 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 120:7c328cabac7e 368 } NVIC_Type;
Kojto 120:7c328cabac7e 369
Kojto 120:7c328cabac7e 370 /*@} end of group CMSIS_NVIC */
Kojto 120:7c328cabac7e 371
Kojto 120:7c328cabac7e 372
Kojto 120:7c328cabac7e 373 /** \ingroup CMSIS_core_register
Kojto 120:7c328cabac7e 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 120:7c328cabac7e 375 \brief Type definitions for the System Control Block Registers
Kojto 120:7c328cabac7e 376 @{
Kojto 120:7c328cabac7e 377 */
Kojto 120:7c328cabac7e 378
Kojto 120:7c328cabac7e 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 120:7c328cabac7e 380 */
Kojto 120:7c328cabac7e 381 typedef struct
Kojto 120:7c328cabac7e 382 {
Kojto 120:7c328cabac7e 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 120:7c328cabac7e 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 120:7c328cabac7e 385 #if (__VTOR_PRESENT == 1)
Kojto 120:7c328cabac7e 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 120:7c328cabac7e 387 #else
Kojto 120:7c328cabac7e 388 uint32_t RESERVED0;
Kojto 120:7c328cabac7e 389 #endif
Kojto 120:7c328cabac7e 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 120:7c328cabac7e 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 120:7c328cabac7e 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 120:7c328cabac7e 393 uint32_t RESERVED1;
Kojto 120:7c328cabac7e 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 120:7c328cabac7e 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 120:7c328cabac7e 396 } SCB_Type;
Kojto 120:7c328cabac7e 397
Kojto 120:7c328cabac7e 398 /* SCB CPUID Register Definitions */
Kojto 120:7c328cabac7e 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 120:7c328cabac7e 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 120:7c328cabac7e 401
Kojto 120:7c328cabac7e 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 120:7c328cabac7e 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 120:7c328cabac7e 404
Kojto 120:7c328cabac7e 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 120:7c328cabac7e 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 120:7c328cabac7e 407
Kojto 120:7c328cabac7e 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 120:7c328cabac7e 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 120:7c328cabac7e 410
Kojto 120:7c328cabac7e 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 120:7c328cabac7e 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 120:7c328cabac7e 413
Kojto 120:7c328cabac7e 414 /* SCB Interrupt Control State Register Definitions */
Kojto 120:7c328cabac7e 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 120:7c328cabac7e 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 120:7c328cabac7e 417
Kojto 120:7c328cabac7e 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 120:7c328cabac7e 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 120:7c328cabac7e 420
Kojto 120:7c328cabac7e 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 120:7c328cabac7e 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 120:7c328cabac7e 423
Kojto 120:7c328cabac7e 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 120:7c328cabac7e 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 120:7c328cabac7e 426
Kojto 120:7c328cabac7e 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 120:7c328cabac7e 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 120:7c328cabac7e 429
Kojto 120:7c328cabac7e 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 120:7c328cabac7e 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 120:7c328cabac7e 432
Kojto 120:7c328cabac7e 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 120:7c328cabac7e 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 120:7c328cabac7e 435
Kojto 120:7c328cabac7e 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 120:7c328cabac7e 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 120:7c328cabac7e 438
Kojto 120:7c328cabac7e 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 120:7c328cabac7e 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 120:7c328cabac7e 441
Kojto 120:7c328cabac7e 442 #if (__VTOR_PRESENT == 1)
Kojto 120:7c328cabac7e 443 /* SCB Interrupt Control State Register Definitions */
Kojto 120:7c328cabac7e 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 120:7c328cabac7e 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 120:7c328cabac7e 446 #endif
Kojto 120:7c328cabac7e 447
Kojto 120:7c328cabac7e 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 120:7c328cabac7e 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 120:7c328cabac7e 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 120:7c328cabac7e 451
Kojto 120:7c328cabac7e 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 120:7c328cabac7e 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 120:7c328cabac7e 454
Kojto 120:7c328cabac7e 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 120:7c328cabac7e 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 120:7c328cabac7e 457
Kojto 120:7c328cabac7e 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 120:7c328cabac7e 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 120:7c328cabac7e 460
Kojto 120:7c328cabac7e 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 120:7c328cabac7e 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 120:7c328cabac7e 463
Kojto 120:7c328cabac7e 464 /* SCB System Control Register Definitions */
Kojto 120:7c328cabac7e 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 120:7c328cabac7e 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 120:7c328cabac7e 467
Kojto 120:7c328cabac7e 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 120:7c328cabac7e 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 120:7c328cabac7e 470
Kojto 120:7c328cabac7e 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 120:7c328cabac7e 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 120:7c328cabac7e 473
Kojto 120:7c328cabac7e 474 /* SCB Configuration Control Register Definitions */
Kojto 120:7c328cabac7e 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 120:7c328cabac7e 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 120:7c328cabac7e 477
Kojto 120:7c328cabac7e 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 120:7c328cabac7e 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 120:7c328cabac7e 480
Kojto 120:7c328cabac7e 481 /* SCB System Handler Control and State Register Definitions */
Kojto 120:7c328cabac7e 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 120:7c328cabac7e 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 120:7c328cabac7e 484
Kojto 120:7c328cabac7e 485 /*@} end of group CMSIS_SCB */
Kojto 120:7c328cabac7e 486
Kojto 120:7c328cabac7e 487
Kojto 120:7c328cabac7e 488 /** \ingroup CMSIS_core_register
Kojto 120:7c328cabac7e 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 120:7c328cabac7e 490 \brief Type definitions for the System Timer Registers.
Kojto 120:7c328cabac7e 491 @{
Kojto 120:7c328cabac7e 492 */
Kojto 120:7c328cabac7e 493
Kojto 120:7c328cabac7e 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 120:7c328cabac7e 495 */
Kojto 120:7c328cabac7e 496 typedef struct
Kojto 120:7c328cabac7e 497 {
Kojto 120:7c328cabac7e 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 120:7c328cabac7e 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 120:7c328cabac7e 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 120:7c328cabac7e 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 120:7c328cabac7e 502 } SysTick_Type;
Kojto 120:7c328cabac7e 503
Kojto 120:7c328cabac7e 504 /* SysTick Control / Status Register Definitions */
Kojto 120:7c328cabac7e 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 120:7c328cabac7e 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 120:7c328cabac7e 507
Kojto 120:7c328cabac7e 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 120:7c328cabac7e 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 120:7c328cabac7e 510
Kojto 120:7c328cabac7e 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 120:7c328cabac7e 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 120:7c328cabac7e 513
Kojto 120:7c328cabac7e 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 120:7c328cabac7e 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 120:7c328cabac7e 516
Kojto 120:7c328cabac7e 517 /* SysTick Reload Register Definitions */
Kojto 120:7c328cabac7e 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 120:7c328cabac7e 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 120:7c328cabac7e 520
Kojto 120:7c328cabac7e 521 /* SysTick Current Register Definitions */
Kojto 120:7c328cabac7e 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 120:7c328cabac7e 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 120:7c328cabac7e 524
Kojto 120:7c328cabac7e 525 /* SysTick Calibration Register Definitions */
Kojto 120:7c328cabac7e 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 120:7c328cabac7e 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 120:7c328cabac7e 528
Kojto 120:7c328cabac7e 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 120:7c328cabac7e 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 120:7c328cabac7e 531
Kojto 120:7c328cabac7e 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 120:7c328cabac7e 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 120:7c328cabac7e 534
Kojto 120:7c328cabac7e 535 /*@} end of group CMSIS_SysTick */
Kojto 120:7c328cabac7e 536
Kojto 120:7c328cabac7e 537 #if (__MPU_PRESENT == 1)
Kojto 120:7c328cabac7e 538 /** \ingroup CMSIS_core_register
Kojto 120:7c328cabac7e 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 120:7c328cabac7e 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 120:7c328cabac7e 541 @{
Kojto 120:7c328cabac7e 542 */
Kojto 120:7c328cabac7e 543
Kojto 120:7c328cabac7e 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 120:7c328cabac7e 545 */
Kojto 120:7c328cabac7e 546 typedef struct
Kojto 120:7c328cabac7e 547 {
Kojto 120:7c328cabac7e 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 120:7c328cabac7e 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 120:7c328cabac7e 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 120:7c328cabac7e 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 120:7c328cabac7e 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 120:7c328cabac7e 553 } MPU_Type;
Kojto 120:7c328cabac7e 554
Kojto 120:7c328cabac7e 555 /* MPU Type Register */
Kojto 120:7c328cabac7e 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 120:7c328cabac7e 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 120:7c328cabac7e 558
Kojto 120:7c328cabac7e 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 120:7c328cabac7e 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 120:7c328cabac7e 561
Kojto 120:7c328cabac7e 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 120:7c328cabac7e 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 120:7c328cabac7e 564
Kojto 120:7c328cabac7e 565 /* MPU Control Register */
Kojto 120:7c328cabac7e 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 120:7c328cabac7e 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 120:7c328cabac7e 568
Kojto 120:7c328cabac7e 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 120:7c328cabac7e 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 120:7c328cabac7e 571
Kojto 120:7c328cabac7e 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 120:7c328cabac7e 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 120:7c328cabac7e 574
Kojto 120:7c328cabac7e 575 /* MPU Region Number Register */
Kojto 120:7c328cabac7e 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 120:7c328cabac7e 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 120:7c328cabac7e 578
Kojto 120:7c328cabac7e 579 /* MPU Region Base Address Register */
Kojto 120:7c328cabac7e 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 120:7c328cabac7e 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 120:7c328cabac7e 582
Kojto 120:7c328cabac7e 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 120:7c328cabac7e 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 120:7c328cabac7e 585
Kojto 120:7c328cabac7e 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 120:7c328cabac7e 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 120:7c328cabac7e 588
Kojto 120:7c328cabac7e 589 /* MPU Region Attribute and Size Register */
Kojto 120:7c328cabac7e 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 120:7c328cabac7e 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 120:7c328cabac7e 592
Kojto 120:7c328cabac7e 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 120:7c328cabac7e 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 120:7c328cabac7e 595
Kojto 120:7c328cabac7e 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 120:7c328cabac7e 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 120:7c328cabac7e 598
Kojto 120:7c328cabac7e 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 120:7c328cabac7e 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 120:7c328cabac7e 601
Kojto 120:7c328cabac7e 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 120:7c328cabac7e 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 120:7c328cabac7e 604
Kojto 120:7c328cabac7e 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 120:7c328cabac7e 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 120:7c328cabac7e 607
Kojto 120:7c328cabac7e 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 120:7c328cabac7e 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 120:7c328cabac7e 610
Kojto 120:7c328cabac7e 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 120:7c328cabac7e 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 120:7c328cabac7e 613
Kojto 120:7c328cabac7e 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 120:7c328cabac7e 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 120:7c328cabac7e 616
Kojto 120:7c328cabac7e 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 120:7c328cabac7e 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 120:7c328cabac7e 619
Kojto 120:7c328cabac7e 620 /*@} end of group CMSIS_MPU */
Kojto 120:7c328cabac7e 621 #endif
Kojto 120:7c328cabac7e 622
Kojto 120:7c328cabac7e 623
Kojto 120:7c328cabac7e 624 /** \ingroup CMSIS_core_register
Kojto 120:7c328cabac7e 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 120:7c328cabac7e 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 120:7c328cabac7e 627 are only accessible over DAP and not via processor. Therefore
Kojto 120:7c328cabac7e 628 they are not covered by the Cortex-M0 header file.
Kojto 120:7c328cabac7e 629 @{
Kojto 120:7c328cabac7e 630 */
Kojto 120:7c328cabac7e 631 /*@} end of group CMSIS_CoreDebug */
Kojto 120:7c328cabac7e 632
Kojto 120:7c328cabac7e 633
Kojto 120:7c328cabac7e 634 /** \ingroup CMSIS_core_register
Kojto 120:7c328cabac7e 635 \defgroup CMSIS_core_base Core Definitions
Kojto 120:7c328cabac7e 636 \brief Definitions for base addresses, unions, and structures.
Kojto 120:7c328cabac7e 637 @{
Kojto 120:7c328cabac7e 638 */
Kojto 120:7c328cabac7e 639
Kojto 120:7c328cabac7e 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 120:7c328cabac7e 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 120:7c328cabac7e 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 120:7c328cabac7e 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 120:7c328cabac7e 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 120:7c328cabac7e 645
Kojto 120:7c328cabac7e 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 120:7c328cabac7e 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 120:7c328cabac7e 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 120:7c328cabac7e 649
Kojto 120:7c328cabac7e 650 #if (__MPU_PRESENT == 1)
Kojto 120:7c328cabac7e 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 120:7c328cabac7e 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 120:7c328cabac7e 653 #endif
Kojto 120:7c328cabac7e 654
Kojto 120:7c328cabac7e 655 /*@} */
Kojto 120:7c328cabac7e 656
Kojto 120:7c328cabac7e 657
Kojto 120:7c328cabac7e 658
Kojto 120:7c328cabac7e 659 /*******************************************************************************
Kojto 120:7c328cabac7e 660 * Hardware Abstraction Layer
Kojto 120:7c328cabac7e 661 Core Function Interface contains:
Kojto 120:7c328cabac7e 662 - Core NVIC Functions
Kojto 120:7c328cabac7e 663 - Core SysTick Functions
Kojto 120:7c328cabac7e 664 - Core Register Access Functions
Kojto 120:7c328cabac7e 665 ******************************************************************************/
Kojto 120:7c328cabac7e 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 120:7c328cabac7e 667 */
Kojto 120:7c328cabac7e 668
Kojto 120:7c328cabac7e 669
Kojto 120:7c328cabac7e 670
Kojto 120:7c328cabac7e 671 /* ########################## NVIC functions #################################### */
Kojto 120:7c328cabac7e 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 120:7c328cabac7e 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 120:7c328cabac7e 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 120:7c328cabac7e 675 @{
Kojto 120:7c328cabac7e 676 */
Kojto 120:7c328cabac7e 677
Kojto 120:7c328cabac7e 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 120:7c328cabac7e 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 120:7c328cabac7e 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 120:7c328cabac7e 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 120:7c328cabac7e 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 120:7c328cabac7e 683
Kojto 120:7c328cabac7e 684
Kojto 120:7c328cabac7e 685 /** \brief Enable External Interrupt
Kojto 120:7c328cabac7e 686
Kojto 120:7c328cabac7e 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 120:7c328cabac7e 688
Kojto 120:7c328cabac7e 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 120:7c328cabac7e 690 */
Kojto 120:7c328cabac7e 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 120:7c328cabac7e 692 {
Kojto 120:7c328cabac7e 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 120:7c328cabac7e 694 }
Kojto 120:7c328cabac7e 695
Kojto 120:7c328cabac7e 696
Kojto 120:7c328cabac7e 697 /** \brief Disable External Interrupt
Kojto 120:7c328cabac7e 698
Kojto 120:7c328cabac7e 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 120:7c328cabac7e 700
Kojto 120:7c328cabac7e 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 120:7c328cabac7e 702 */
Kojto 120:7c328cabac7e 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 120:7c328cabac7e 704 {
Kojto 120:7c328cabac7e 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 120:7c328cabac7e 708 }
Kojto 120:7c328cabac7e 709
Kojto 120:7c328cabac7e 710
Kojto 120:7c328cabac7e 711 /** \brief Get Pending Interrupt
Kojto 120:7c328cabac7e 712
Kojto 120:7c328cabac7e 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 120:7c328cabac7e 714 for the specified interrupt.
Kojto 120:7c328cabac7e 715
Kojto 120:7c328cabac7e 716 \param [in] IRQn Interrupt number.
Kojto 120:7c328cabac7e 717
Kojto 120:7c328cabac7e 718 \return 0 Interrupt status is not pending.
Kojto 120:7c328cabac7e 719 \return 1 Interrupt status is pending.
Kojto 120:7c328cabac7e 720 */
Kojto 120:7c328cabac7e 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 120:7c328cabac7e 722 {
Kojto 120:7c328cabac7e 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 120:7c328cabac7e 724 }
Kojto 120:7c328cabac7e 725
Kojto 120:7c328cabac7e 726
Kojto 120:7c328cabac7e 727 /** \brief Set Pending Interrupt
Kojto 120:7c328cabac7e 728
Kojto 120:7c328cabac7e 729 The function sets the pending bit of an external interrupt.
Kojto 120:7c328cabac7e 730
Kojto 120:7c328cabac7e 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 120:7c328cabac7e 732 */
Kojto 120:7c328cabac7e 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 120:7c328cabac7e 734 {
Kojto 120:7c328cabac7e 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 120:7c328cabac7e 736 }
Kojto 120:7c328cabac7e 737
Kojto 120:7c328cabac7e 738
Kojto 120:7c328cabac7e 739 /** \brief Clear Pending Interrupt
Kojto 120:7c328cabac7e 740
Kojto 120:7c328cabac7e 741 The function clears the pending bit of an external interrupt.
Kojto 120:7c328cabac7e 742
Kojto 120:7c328cabac7e 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 120:7c328cabac7e 744 */
Kojto 120:7c328cabac7e 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 120:7c328cabac7e 746 {
Kojto 120:7c328cabac7e 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 120:7c328cabac7e 748 }
Kojto 120:7c328cabac7e 749
Kojto 120:7c328cabac7e 750
Kojto 120:7c328cabac7e 751 /** \brief Set Interrupt Priority
Kojto 120:7c328cabac7e 752
Kojto 120:7c328cabac7e 753 The function sets the priority of an interrupt.
Kojto 120:7c328cabac7e 754
Kojto 120:7c328cabac7e 755 \note The priority cannot be set for every core interrupt.
Kojto 120:7c328cabac7e 756
Kojto 120:7c328cabac7e 757 \param [in] IRQn Interrupt number.
Kojto 120:7c328cabac7e 758 \param [in] priority Priority to set.
Kojto 120:7c328cabac7e 759 */
Kojto 120:7c328cabac7e 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 120:7c328cabac7e 761 {
Kojto 120:7c328cabac7e 762 if((int32_t)(IRQn) < 0) {
Kojto 120:7c328cabac7e 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 120:7c328cabac7e 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 120:7c328cabac7e 765 }
Kojto 120:7c328cabac7e 766 else {
Kojto 120:7c328cabac7e 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 120:7c328cabac7e 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 120:7c328cabac7e 769 }
Kojto 120:7c328cabac7e 770 }
Kojto 120:7c328cabac7e 771
Kojto 120:7c328cabac7e 772
Kojto 120:7c328cabac7e 773 /** \brief Get Interrupt Priority
Kojto 120:7c328cabac7e 774
Kojto 120:7c328cabac7e 775 The function reads the priority of an interrupt. The interrupt
Kojto 120:7c328cabac7e 776 number can be positive to specify an external (device specific)
Kojto 120:7c328cabac7e 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 120:7c328cabac7e 778
Kojto 120:7c328cabac7e 779
Kojto 120:7c328cabac7e 780 \param [in] IRQn Interrupt number.
Kojto 120:7c328cabac7e 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 120:7c328cabac7e 782 priority bits of the microcontroller.
Kojto 120:7c328cabac7e 783 */
Kojto 120:7c328cabac7e 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 120:7c328cabac7e 785 {
Kojto 120:7c328cabac7e 786
Kojto 120:7c328cabac7e 787 if((int32_t)(IRQn) < 0) {
Kojto 120:7c328cabac7e 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 120:7c328cabac7e 789 }
Kojto 120:7c328cabac7e 790 else {
Kojto 120:7c328cabac7e 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 120:7c328cabac7e 792 }
Kojto 120:7c328cabac7e 793 }
Kojto 120:7c328cabac7e 794
Kojto 120:7c328cabac7e 795
Kojto 120:7c328cabac7e 796 /** \brief System Reset
Kojto 120:7c328cabac7e 797
Kojto 120:7c328cabac7e 798 The function initiates a system reset request to reset the MCU.
Kojto 120:7c328cabac7e 799 */
Kojto 120:7c328cabac7e 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 120:7c328cabac7e 801 {
Kojto 120:7c328cabac7e 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 120:7c328cabac7e 803 buffered write are completed before reset */
Kojto 120:7c328cabac7e 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 120:7c328cabac7e 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 120:7c328cabac7e 806 __DSB(); /* Ensure completion of memory access */
Kojto 120:7c328cabac7e 807 while(1) { __NOP(); } /* wait until reset */
Kojto 120:7c328cabac7e 808 }
Kojto 120:7c328cabac7e 809
Kojto 120:7c328cabac7e 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 120:7c328cabac7e 811
Kojto 120:7c328cabac7e 812
Kojto 120:7c328cabac7e 813
Kojto 120:7c328cabac7e 814 /* ################################## SysTick function ############################################ */
Kojto 120:7c328cabac7e 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 120:7c328cabac7e 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 120:7c328cabac7e 817 \brief Functions that configure the System.
Kojto 120:7c328cabac7e 818 @{
Kojto 120:7c328cabac7e 819 */
Kojto 120:7c328cabac7e 820
Kojto 120:7c328cabac7e 821 #if (__Vendor_SysTickConfig == 0)
Kojto 120:7c328cabac7e 822
Kojto 120:7c328cabac7e 823 /** \brief System Tick Configuration
Kojto 120:7c328cabac7e 824
Kojto 120:7c328cabac7e 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 120:7c328cabac7e 826 Counter is in free running mode to generate periodic interrupts.
Kojto 120:7c328cabac7e 827
Kojto 120:7c328cabac7e 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 120:7c328cabac7e 829
Kojto 120:7c328cabac7e 830 \return 0 Function succeeded.
Kojto 120:7c328cabac7e 831 \return 1 Function failed.
Kojto 120:7c328cabac7e 832
Kojto 120:7c328cabac7e 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 120:7c328cabac7e 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 120:7c328cabac7e 835 must contain a vendor-specific implementation of this function.
Kojto 120:7c328cabac7e 836
Kojto 120:7c328cabac7e 837 */
Kojto 120:7c328cabac7e 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 120:7c328cabac7e 839 {
Kojto 120:7c328cabac7e 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 120:7c328cabac7e 841
Kojto 120:7c328cabac7e 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 120:7c328cabac7e 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 120:7c328cabac7e 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 120:7c328cabac7e 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 120:7c328cabac7e 846 SysTick_CTRL_TICKINT_Msk |
Kojto 120:7c328cabac7e 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 120:7c328cabac7e 848 return (0UL); /* Function successful */
Kojto 120:7c328cabac7e 849 }
Kojto 120:7c328cabac7e 850
Kojto 120:7c328cabac7e 851 #endif
Kojto 120:7c328cabac7e 852
Kojto 120:7c328cabac7e 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 120:7c328cabac7e 854
Kojto 120:7c328cabac7e 855
Kojto 120:7c328cabac7e 856
Kojto 120:7c328cabac7e 857
Kojto 120:7c328cabac7e 858 #ifdef __cplusplus
Kojto 120:7c328cabac7e 859 }
Kojto 120:7c328cabac7e 860 #endif
Kojto 120:7c328cabac7e 861
Kojto 120:7c328cabac7e 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 120:7c328cabac7e 863
Kojto 120:7c328cabac7e 864 #endif /* __CMSIS_GENERIC */