mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K22F/core_cm0plus.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**************************************************************************//**
Kojto 90:cb3d968589d8 2 * @file core_cm0plus.h
Kojto 90:cb3d968589d8 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 90:cb3d968589d8 6 *
Kojto 90:cb3d968589d8 7 * @note
Kojto 90:cb3d968589d8 8 *
Kojto 90:cb3d968589d8 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 90:cb3d968589d8 11
Kojto 90:cb3d968589d8 12 All rights reserved.
Kojto 90:cb3d968589d8 13 Redistribution and use in source and binary forms, with or without
Kojto 90:cb3d968589d8 14 modification, are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 15 - Redistributions of source code must retain the above copyright
Kojto 90:cb3d968589d8 16 notice, this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 - Redistributions in binary form must reproduce the above copyright
Kojto 90:cb3d968589d8 18 notice, this list of conditions and the following disclaimer in the
Kojto 90:cb3d968589d8 19 documentation and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 90:cb3d968589d8 21 to endorse or promote products derived from this software without
Kojto 90:cb3d968589d8 22 specific prior written permission.
Kojto 90:cb3d968589d8 23 *
Kojto 90:cb3d968589d8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 90:cb3d968589d8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 90:cb3d968589d8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 90:cb3d968589d8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 90:cb3d968589d8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 90:cb3d968589d8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 90:cb3d968589d8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 90:cb3d968589d8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 90:cb3d968589d8 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 35 ---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 36
Kojto 90:cb3d968589d8 37
Kojto 90:cb3d968589d8 38 #if defined ( __ICCARM__ )
Kojto 90:cb3d968589d8 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 90:cb3d968589d8 40 #endif
Kojto 90:cb3d968589d8 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 90:cb3d968589d8 45 #ifdef __cplusplus
Kojto 90:cb3d968589d8 46 extern "C" {
Kojto 90:cb3d968589d8 47 #endif
Kojto 90:cb3d968589d8 48
Kojto 90:cb3d968589d8 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 90:cb3d968589d8 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 90:cb3d968589d8 51
Kojto 90:cb3d968589d8 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 90:cb3d968589d8 53 Function definitions in header files are used to allow 'inlining'.
Kojto 90:cb3d968589d8 54
Kojto 90:cb3d968589d8 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 90:cb3d968589d8 56 Unions are used for effective representation of core registers.
Kojto 90:cb3d968589d8 57
Kojto 90:cb3d968589d8 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 90:cb3d968589d8 59 Function-like macros are used to allow more efficient code.
Kojto 90:cb3d968589d8 60 */
Kojto 90:cb3d968589d8 61
Kojto 90:cb3d968589d8 62
Kojto 90:cb3d968589d8 63 /*******************************************************************************
Kojto 90:cb3d968589d8 64 * CMSIS definitions
Kojto 90:cb3d968589d8 65 ******************************************************************************/
Kojto 90:cb3d968589d8 66 /** \ingroup Cortex-M0+
Kojto 90:cb3d968589d8 67 @{
Kojto 90:cb3d968589d8 68 */
Kojto 90:cb3d968589d8 69
Kojto 90:cb3d968589d8 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 90:cb3d968589d8 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 90:cb3d968589d8 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 90:cb3d968589d8 75
Kojto 90:cb3d968589d8 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 90:cb3d968589d8 77
Kojto 90:cb3d968589d8 78
Kojto 90:cb3d968589d8 79 #if defined ( __CC_ARM )
Kojto 90:cb3d968589d8 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 90:cb3d968589d8 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 90:cb3d968589d8 82 #define __STATIC_INLINE static __inline
Kojto 90:cb3d968589d8 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 90:cb3d968589d8 89 #elif defined ( __ICCARM__ )
Kojto 90:cb3d968589d8 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 90:cb3d968589d8 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 90:cb3d968589d8 92 #define __STATIC_INLINE static inline
Kojto 90:cb3d968589d8 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 90:cb3d968589d8 96 #define __STATIC_INLINE static inline
Kojto 90:cb3d968589d8 97
Kojto 90:cb3d968589d8 98 #elif defined ( __TASKING__ )
Kojto 90:cb3d968589d8 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 90:cb3d968589d8 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 90:cb3d968589d8 101 #define __STATIC_INLINE static inline
Kojto 90:cb3d968589d8 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 90:cb3d968589d8 109 #endif
Kojto 90:cb3d968589d8 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 90:cb3d968589d8 113 */
Kojto 90:cb3d968589d8 114 #define __FPU_USED 0
Kojto 90:cb3d968589d8 115
Kojto 90:cb3d968589d8 116 #if defined ( __CC_ARM )
Kojto 90:cb3d968589d8 117 #if defined __TARGET_FPU_VFP
Kojto 90:cb3d968589d8 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 119 #endif
Kojto 90:cb3d968589d8 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 90:cb3d968589d8 126 #elif defined ( __ICCARM__ )
Kojto 90:cb3d968589d8 127 #if defined __ARMVFP__
Kojto 90:cb3d968589d8 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 129 #endif
Kojto 90:cb3d968589d8 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 90:cb3d968589d8 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 134 #endif
Kojto 90:cb3d968589d8 135
Kojto 90:cb3d968589d8 136 #elif defined ( __TASKING__ )
Kojto 90:cb3d968589d8 137 #if defined __FPU_VFP__
Kojto 90:cb3d968589d8 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 90:cb3d968589d8 145 #endif
Kojto 90:cb3d968589d8 146
Kojto 90:cb3d968589d8 147 #include <stdint.h> /* standard types definitions */
Kojto 90:cb3d968589d8 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 90:cb3d968589d8 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 90:cb3d968589d8 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 90:cb3d968589d8 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 90:cb3d968589d8 156
Kojto 90:cb3d968589d8 157 #ifndef __CMSIS_GENERIC
Kojto 90:cb3d968589d8 158
Kojto 90:cb3d968589d8 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 90:cb3d968589d8 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 90:cb3d968589d8 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 90:cb3d968589d8 166 /* check device defines and use defaults */
Kojto 90:cb3d968589d8 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 90:cb3d968589d8 168 #ifndef __CM0PLUS_REV
Kojto 90:cb3d968589d8 169 #define __CM0PLUS_REV 0x0000
Kojto 90:cb3d968589d8 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 90:cb3d968589d8 171 #endif
Kojto 90:cb3d968589d8 172
Kojto 90:cb3d968589d8 173 #ifndef __MPU_PRESENT
Kojto 90:cb3d968589d8 174 #define __MPU_PRESENT 0
Kojto 90:cb3d968589d8 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 90:cb3d968589d8 176 #endif
Kojto 90:cb3d968589d8 177
Kojto 90:cb3d968589d8 178 #ifndef __VTOR_PRESENT
Kojto 90:cb3d968589d8 179 #define __VTOR_PRESENT 0
Kojto 90:cb3d968589d8 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 90:cb3d968589d8 181 #endif
Kojto 90:cb3d968589d8 182
Kojto 90:cb3d968589d8 183 #ifndef __NVIC_PRIO_BITS
Kojto 90:cb3d968589d8 184 #define __NVIC_PRIO_BITS 2
Kojto 90:cb3d968589d8 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 90:cb3d968589d8 186 #endif
Kojto 90:cb3d968589d8 187
Kojto 90:cb3d968589d8 188 #ifndef __Vendor_SysTickConfig
Kojto 90:cb3d968589d8 189 #define __Vendor_SysTickConfig 0
Kojto 90:cb3d968589d8 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 90:cb3d968589d8 191 #endif
Kojto 90:cb3d968589d8 192 #endif
Kojto 90:cb3d968589d8 193
Kojto 90:cb3d968589d8 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 90:cb3d968589d8 195 /**
Kojto 90:cb3d968589d8 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 90:cb3d968589d8 197
Kojto 90:cb3d968589d8 198 <strong>IO Type Qualifiers</strong> are used
Kojto 90:cb3d968589d8 199 \li to specify the access to peripheral variables.
Kojto 90:cb3d968589d8 200 \li for automatic generation of peripheral register debug information.
Kojto 90:cb3d968589d8 201 */
Kojto 90:cb3d968589d8 202 #ifdef __cplusplus
Kojto 90:cb3d968589d8 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 90:cb3d968589d8 204 #else
Kojto 90:cb3d968589d8 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 90:cb3d968589d8 206 #endif
Kojto 90:cb3d968589d8 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 90:cb3d968589d8 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 90:cb3d968589d8 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 90:cb3d968589d8 218 /*@} end of group Cortex-M0+ */
Kojto 90:cb3d968589d8 219
Kojto 90:cb3d968589d8 220
Kojto 90:cb3d968589d8 221
Kojto 90:cb3d968589d8 222 /*******************************************************************************
Kojto 90:cb3d968589d8 223 * Register Abstraction
Kojto 90:cb3d968589d8 224 Core Register contain:
Kojto 90:cb3d968589d8 225 - Core Register
Kojto 90:cb3d968589d8 226 - Core NVIC Register
Kojto 90:cb3d968589d8 227 - Core SCB Register
Kojto 90:cb3d968589d8 228 - Core SysTick Register
Kojto 90:cb3d968589d8 229 - Core MPU Register
Kojto 90:cb3d968589d8 230 ******************************************************************************/
Kojto 90:cb3d968589d8 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 90:cb3d968589d8 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 90:cb3d968589d8 233 */
Kojto 90:cb3d968589d8 234
Kojto 90:cb3d968589d8 235 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 90:cb3d968589d8 237 \brief Core Register type definitions.
Kojto 90:cb3d968589d8 238 @{
Kojto 90:cb3d968589d8 239 */
Kojto 90:cb3d968589d8 240
Kojto 90:cb3d968589d8 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 90:cb3d968589d8 242 */
Kojto 90:cb3d968589d8 243 typedef union
Kojto 90:cb3d968589d8 244 {
Kojto 90:cb3d968589d8 245 struct
Kojto 90:cb3d968589d8 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 90:cb3d968589d8 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 90:cb3d968589d8 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 90:cb3d968589d8 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 90:cb3d968589d8 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 90:cb3d968589d8 252 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 253 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 254 } APSR_Type;
Kojto 90:cb3d968589d8 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
Kojto 90:cb3d968589d8 269
Kojto 90:cb3d968589d8 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 90:cb3d968589d8 271 */
Kojto 90:cb3d968589d8 272 typedef union
Kojto 90:cb3d968589d8 273 {
Kojto 90:cb3d968589d8 274 struct
Kojto 90:cb3d968589d8 275 {
Kojto 90:cb3d968589d8 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 90:cb3d968589d8 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 90:cb3d968589d8 278 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 279 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 280 } IPSR_Type;
Kojto 90:cb3d968589d8 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
Kojto 90:cb3d968589d8 286
Kojto 90:cb3d968589d8 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 90:cb3d968589d8 288 */
Kojto 90:cb3d968589d8 289 typedef union
Kojto 90:cb3d968589d8 290 {
Kojto 90:cb3d968589d8 291 struct
Kojto 90:cb3d968589d8 292 {
Kojto 90:cb3d968589d8 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 90:cb3d968589d8 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 90:cb3d968589d8 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 90:cb3d968589d8 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 90:cb3d968589d8 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 90:cb3d968589d8 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 90:cb3d968589d8 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 90:cb3d968589d8 301 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 302 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 303 } xPSR_Type;
Kojto 90:cb3d968589d8 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
Kojto 90:cb3d968589d8 324
Kojto 90:cb3d968589d8 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 90:cb3d968589d8 326 */
Kojto 90:cb3d968589d8 327 typedef union
Kojto 90:cb3d968589d8 328 {
Kojto 90:cb3d968589d8 329 struct
Kojto 90:cb3d968589d8 330 {
Kojto 90:cb3d968589d8 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 90:cb3d968589d8 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 90:cb3d968589d8 334 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 335 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 336 } CONTROL_Type;
Kojto 90:cb3d968589d8 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
Kojto 90:cb3d968589d8 345 /*@} end of group CMSIS_CORE */
Kojto 90:cb3d968589d8 346
Kojto 90:cb3d968589d8 347
Kojto 90:cb3d968589d8 348 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 90:cb3d968589d8 350 \brief Type definitions for the NVIC Registers
Kojto 90:cb3d968589d8 351 @{
Kojto 90:cb3d968589d8 352 */
Kojto 90:cb3d968589d8 353
Kojto 90:cb3d968589d8 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 90:cb3d968589d8 355 */
Kojto 90:cb3d968589d8 356 typedef struct
Kojto 90:cb3d968589d8 357 {
Kojto 90:cb3d968589d8 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 90:cb3d968589d8 359 uint32_t RESERVED0[31];
Kojto 90:cb3d968589d8 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 90:cb3d968589d8 361 uint32_t RSERVED1[31];
Kojto 90:cb3d968589d8 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 90:cb3d968589d8 363 uint32_t RESERVED2[31];
Kojto 90:cb3d968589d8 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 90:cb3d968589d8 365 uint32_t RESERVED3[31];
Kojto 90:cb3d968589d8 366 uint32_t RESERVED4[64];
Kojto 90:cb3d968589d8 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 90:cb3d968589d8 368 } NVIC_Type;
Kojto 90:cb3d968589d8 369
Kojto 90:cb3d968589d8 370 /*@} end of group CMSIS_NVIC */
Kojto 90:cb3d968589d8 371
Kojto 90:cb3d968589d8 372
Kojto 90:cb3d968589d8 373 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 90:cb3d968589d8 375 \brief Type definitions for the System Control Block Registers
Kojto 90:cb3d968589d8 376 @{
Kojto 90:cb3d968589d8 377 */
Kojto 90:cb3d968589d8 378
Kojto 90:cb3d968589d8 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 90:cb3d968589d8 380 */
Kojto 90:cb3d968589d8 381 typedef struct
Kojto 90:cb3d968589d8 382 {
Kojto 90:cb3d968589d8 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 90:cb3d968589d8 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 90:cb3d968589d8 385 #if (__VTOR_PRESENT == 1)
Kojto 90:cb3d968589d8 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 90:cb3d968589d8 387 #else
Kojto 90:cb3d968589d8 388 uint32_t RESERVED0;
Kojto 90:cb3d968589d8 389 #endif
Kojto 90:cb3d968589d8 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 90:cb3d968589d8 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 90:cb3d968589d8 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 90:cb3d968589d8 393 uint32_t RESERVED1;
Kojto 90:cb3d968589d8 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 90:cb3d968589d8 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 90:cb3d968589d8 396 } SCB_Type;
Kojto 90:cb3d968589d8 397
Kojto 90:cb3d968589d8 398 /* SCB CPUID Register Definitions */
Kojto 90:cb3d968589d8 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 90:cb3d968589d8 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 90:cb3d968589d8 401
Kojto 90:cb3d968589d8 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 90:cb3d968589d8 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 90:cb3d968589d8 404
Kojto 90:cb3d968589d8 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 90:cb3d968589d8 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 90:cb3d968589d8 407
Kojto 90:cb3d968589d8 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 90:cb3d968589d8 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 90:cb3d968589d8 410
Kojto 90:cb3d968589d8 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 90:cb3d968589d8 413
Kojto 90:cb3d968589d8 414 /* SCB Interrupt Control State Register Definitions */
Kojto 90:cb3d968589d8 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 90:cb3d968589d8 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 90:cb3d968589d8 417
Kojto 90:cb3d968589d8 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 90:cb3d968589d8 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 90:cb3d968589d8 420
Kojto 90:cb3d968589d8 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 90:cb3d968589d8 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 90:cb3d968589d8 423
Kojto 90:cb3d968589d8 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 90:cb3d968589d8 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 90:cb3d968589d8 426
Kojto 90:cb3d968589d8 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 90:cb3d968589d8 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 90:cb3d968589d8 429
Kojto 90:cb3d968589d8 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 90:cb3d968589d8 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 90:cb3d968589d8 432
Kojto 90:cb3d968589d8 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 90:cb3d968589d8 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 90:cb3d968589d8 435
Kojto 90:cb3d968589d8 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 90:cb3d968589d8 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 90:cb3d968589d8 438
Kojto 90:cb3d968589d8 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 90:cb3d968589d8 441
Kojto 90:cb3d968589d8 442 #if (__VTOR_PRESENT == 1)
Kojto 90:cb3d968589d8 443 /* SCB Interrupt Control State Register Definitions */
Kojto 90:cb3d968589d8 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 90:cb3d968589d8 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 90:cb3d968589d8 446 #endif
Kojto 90:cb3d968589d8 447
Kojto 90:cb3d968589d8 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 90:cb3d968589d8 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 90:cb3d968589d8 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 90:cb3d968589d8 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 90:cb3d968589d8 454
Kojto 90:cb3d968589d8 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 90:cb3d968589d8 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 90:cb3d968589d8 457
Kojto 90:cb3d968589d8 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 90:cb3d968589d8 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 90:cb3d968589d8 460
Kojto 90:cb3d968589d8 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 90:cb3d968589d8 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 90:cb3d968589d8 463
Kojto 90:cb3d968589d8 464 /* SCB System Control Register Definitions */
Kojto 90:cb3d968589d8 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 90:cb3d968589d8 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 90:cb3d968589d8 467
Kojto 90:cb3d968589d8 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 90:cb3d968589d8 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 90:cb3d968589d8 470
Kojto 90:cb3d968589d8 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 90:cb3d968589d8 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 90:cb3d968589d8 473
Kojto 90:cb3d968589d8 474 /* SCB Configuration Control Register Definitions */
Kojto 90:cb3d968589d8 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 90:cb3d968589d8 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 90:cb3d968589d8 477
Kojto 90:cb3d968589d8 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 90:cb3d968589d8 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 90:cb3d968589d8 480
Kojto 90:cb3d968589d8 481 /* SCB System Handler Control and State Register Definitions */
Kojto 90:cb3d968589d8 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 90:cb3d968589d8 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 90:cb3d968589d8 484
Kojto 90:cb3d968589d8 485 /*@} end of group CMSIS_SCB */
Kojto 90:cb3d968589d8 486
Kojto 90:cb3d968589d8 487
Kojto 90:cb3d968589d8 488 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 90:cb3d968589d8 490 \brief Type definitions for the System Timer Registers.
Kojto 90:cb3d968589d8 491 @{
Kojto 90:cb3d968589d8 492 */
Kojto 90:cb3d968589d8 493
Kojto 90:cb3d968589d8 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 90:cb3d968589d8 495 */
Kojto 90:cb3d968589d8 496 typedef struct
Kojto 90:cb3d968589d8 497 {
Kojto 90:cb3d968589d8 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 90:cb3d968589d8 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 90:cb3d968589d8 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 90:cb3d968589d8 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 90:cb3d968589d8 502 } SysTick_Type;
Kojto 90:cb3d968589d8 503
Kojto 90:cb3d968589d8 504 /* SysTick Control / Status Register Definitions */
Kojto 90:cb3d968589d8 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 90:cb3d968589d8 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 90:cb3d968589d8 507
Kojto 90:cb3d968589d8 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 90:cb3d968589d8 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 90:cb3d968589d8 510
Kojto 90:cb3d968589d8 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 90:cb3d968589d8 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 90:cb3d968589d8 513
Kojto 90:cb3d968589d8 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 90:cb3d968589d8 516
Kojto 90:cb3d968589d8 517 /* SysTick Reload Register Definitions */
Kojto 90:cb3d968589d8 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 90:cb3d968589d8 520
Kojto 90:cb3d968589d8 521 /* SysTick Current Register Definitions */
Kojto 90:cb3d968589d8 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 90:cb3d968589d8 524
Kojto 90:cb3d968589d8 525 /* SysTick Calibration Register Definitions */
Kojto 90:cb3d968589d8 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 90:cb3d968589d8 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 90:cb3d968589d8 528
Kojto 90:cb3d968589d8 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 90:cb3d968589d8 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 90:cb3d968589d8 531
Kojto 90:cb3d968589d8 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 90:cb3d968589d8 534
Kojto 90:cb3d968589d8 535 /*@} end of group CMSIS_SysTick */
Kojto 90:cb3d968589d8 536
Kojto 90:cb3d968589d8 537 #if (__MPU_PRESENT == 1)
Kojto 90:cb3d968589d8 538 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 90:cb3d968589d8 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 90:cb3d968589d8 541 @{
Kojto 90:cb3d968589d8 542 */
Kojto 90:cb3d968589d8 543
Kojto 90:cb3d968589d8 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 90:cb3d968589d8 545 */
Kojto 90:cb3d968589d8 546 typedef struct
Kojto 90:cb3d968589d8 547 {
Kojto 90:cb3d968589d8 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 90:cb3d968589d8 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 90:cb3d968589d8 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 90:cb3d968589d8 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 90:cb3d968589d8 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 90:cb3d968589d8 553 } MPU_Type;
Kojto 90:cb3d968589d8 554
Kojto 90:cb3d968589d8 555 /* MPU Type Register */
Kojto 90:cb3d968589d8 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 90:cb3d968589d8 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 90:cb3d968589d8 558
Kojto 90:cb3d968589d8 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 90:cb3d968589d8 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 90:cb3d968589d8 561
Kojto 90:cb3d968589d8 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 90:cb3d968589d8 564
Kojto 90:cb3d968589d8 565 /* MPU Control Register */
Kojto 90:cb3d968589d8 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 90:cb3d968589d8 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 90:cb3d968589d8 568
Kojto 90:cb3d968589d8 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 90:cb3d968589d8 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 90:cb3d968589d8 574
Kojto 90:cb3d968589d8 575 /* MPU Region Number Register */
Kojto 90:cb3d968589d8 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 90:cb3d968589d8 578
Kojto 90:cb3d968589d8 579 /* MPU Region Base Address Register */
Kojto 90:cb3d968589d8 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 90:cb3d968589d8 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 90:cb3d968589d8 582
Kojto 90:cb3d968589d8 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 90:cb3d968589d8 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 90:cb3d968589d8 585
Kojto 90:cb3d968589d8 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 90:cb3d968589d8 588
Kojto 90:cb3d968589d8 589 /* MPU Region Attribute and Size Register */
Kojto 90:cb3d968589d8 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 90:cb3d968589d8 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 90:cb3d968589d8 592
Kojto 90:cb3d968589d8 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 90:cb3d968589d8 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 90:cb3d968589d8 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 90:cb3d968589d8 598
Kojto 90:cb3d968589d8 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 90:cb3d968589d8 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 90:cb3d968589d8 601
Kojto 90:cb3d968589d8 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 90:cb3d968589d8 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 90:cb3d968589d8 604
Kojto 90:cb3d968589d8 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 90:cb3d968589d8 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 90:cb3d968589d8 607
Kojto 90:cb3d968589d8 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 90:cb3d968589d8 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 90:cb3d968589d8 610
Kojto 90:cb3d968589d8 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 90:cb3d968589d8 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 90:cb3d968589d8 613
Kojto 90:cb3d968589d8 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 90:cb3d968589d8 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 90:cb3d968589d8 616
Kojto 90:cb3d968589d8 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 90:cb3d968589d8 619
Kojto 90:cb3d968589d8 620 /*@} end of group CMSIS_MPU */
Kojto 90:cb3d968589d8 621 #endif
Kojto 90:cb3d968589d8 622
Kojto 90:cb3d968589d8 623
Kojto 90:cb3d968589d8 624 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 90:cb3d968589d8 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 90:cb3d968589d8 627 are only accessible over DAP and not via processor. Therefore
Kojto 90:cb3d968589d8 628 they are not covered by the Cortex-M0 header file.
Kojto 90:cb3d968589d8 629 @{
Kojto 90:cb3d968589d8 630 */
Kojto 90:cb3d968589d8 631 /*@} end of group CMSIS_CoreDebug */
Kojto 90:cb3d968589d8 632
Kojto 90:cb3d968589d8 633
Kojto 90:cb3d968589d8 634 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 635 \defgroup CMSIS_core_base Core Definitions
Kojto 90:cb3d968589d8 636 \brief Definitions for base addresses, unions, and structures.
Kojto 90:cb3d968589d8 637 @{
Kojto 90:cb3d968589d8 638 */
Kojto 90:cb3d968589d8 639
Kojto 90:cb3d968589d8 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 90:cb3d968589d8 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 90:cb3d968589d8 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 90:cb3d968589d8 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 90:cb3d968589d8 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 90:cb3d968589d8 645
Kojto 90:cb3d968589d8 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 90:cb3d968589d8 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 90:cb3d968589d8 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 90:cb3d968589d8 649
Kojto 90:cb3d968589d8 650 #if (__MPU_PRESENT == 1)
Kojto 90:cb3d968589d8 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 90:cb3d968589d8 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 90:cb3d968589d8 653 #endif
Kojto 90:cb3d968589d8 654
Kojto 90:cb3d968589d8 655 /*@} */
Kojto 90:cb3d968589d8 656
Kojto 90:cb3d968589d8 657
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659 /*******************************************************************************
Kojto 90:cb3d968589d8 660 * Hardware Abstraction Layer
Kojto 90:cb3d968589d8 661 Core Function Interface contains:
Kojto 90:cb3d968589d8 662 - Core NVIC Functions
Kojto 90:cb3d968589d8 663 - Core SysTick Functions
Kojto 90:cb3d968589d8 664 - Core Register Access Functions
Kojto 90:cb3d968589d8 665 ******************************************************************************/
Kojto 90:cb3d968589d8 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 90:cb3d968589d8 667 */
Kojto 90:cb3d968589d8 668
Kojto 90:cb3d968589d8 669
Kojto 90:cb3d968589d8 670
Kojto 90:cb3d968589d8 671 /* ########################## NVIC functions #################################### */
Kojto 90:cb3d968589d8 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 90:cb3d968589d8 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 90:cb3d968589d8 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 90:cb3d968589d8 675 @{
Kojto 90:cb3d968589d8 676 */
Kojto 90:cb3d968589d8 677
Kojto 90:cb3d968589d8 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 90:cb3d968589d8 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 90:cb3d968589d8 683
Kojto 90:cb3d968589d8 684
Kojto 90:cb3d968589d8 685 /** \brief Enable External Interrupt
Kojto 90:cb3d968589d8 686
Kojto 90:cb3d968589d8 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 90:cb3d968589d8 688
Kojto 90:cb3d968589d8 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 690 */
Kojto 90:cb3d968589d8 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 90:cb3d968589d8 694 }
Kojto 90:cb3d968589d8 695
Kojto 90:cb3d968589d8 696
Kojto 90:cb3d968589d8 697 /** \brief Disable External Interrupt
Kojto 90:cb3d968589d8 698
Kojto 90:cb3d968589d8 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 90:cb3d968589d8 700
Kojto 90:cb3d968589d8 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 702 */
Kojto 90:cb3d968589d8 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 90:cb3d968589d8 708 }
Kojto 90:cb3d968589d8 709
Kojto 90:cb3d968589d8 710
Kojto 90:cb3d968589d8 711 /** \brief Get Pending Interrupt
Kojto 90:cb3d968589d8 712
Kojto 90:cb3d968589d8 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 90:cb3d968589d8 714 for the specified interrupt.
Kojto 90:cb3d968589d8 715
Kojto 90:cb3d968589d8 716 \param [in] IRQn Interrupt number.
Kojto 90:cb3d968589d8 717
Kojto 90:cb3d968589d8 718 \return 0 Interrupt status is not pending.
Kojto 90:cb3d968589d8 719 \return 1 Interrupt status is pending.
Kojto 90:cb3d968589d8 720 */
Kojto 90:cb3d968589d8 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 90:cb3d968589d8 724 }
Kojto 90:cb3d968589d8 725
Kojto 90:cb3d968589d8 726
Kojto 90:cb3d968589d8 727 /** \brief Set Pending Interrupt
Kojto 90:cb3d968589d8 728
Kojto 90:cb3d968589d8 729 The function sets the pending bit of an external interrupt.
Kojto 90:cb3d968589d8 730
Kojto 90:cb3d968589d8 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 732 */
Kojto 90:cb3d968589d8 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 90:cb3d968589d8 736 }
Kojto 90:cb3d968589d8 737
Kojto 90:cb3d968589d8 738
Kojto 90:cb3d968589d8 739 /** \brief Clear Pending Interrupt
Kojto 90:cb3d968589d8 740
Kojto 90:cb3d968589d8 741 The function clears the pending bit of an external interrupt.
Kojto 90:cb3d968589d8 742
Kojto 90:cb3d968589d8 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 744 */
Kojto 90:cb3d968589d8 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 90:cb3d968589d8 748 }
Kojto 90:cb3d968589d8 749
Kojto 90:cb3d968589d8 750
Kojto 90:cb3d968589d8 751 /** \brief Set Interrupt Priority
Kojto 90:cb3d968589d8 752
Kojto 90:cb3d968589d8 753 The function sets the priority of an interrupt.
Kojto 90:cb3d968589d8 754
Kojto 90:cb3d968589d8 755 \note The priority cannot be set for every core interrupt.
Kojto 90:cb3d968589d8 756
Kojto 90:cb3d968589d8 757 \param [in] IRQn Interrupt number.
Kojto 90:cb3d968589d8 758 \param [in] priority Priority to set.
Kojto 90:cb3d968589d8 759 */
Kojto 90:cb3d968589d8 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 90:cb3d968589d8 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
Kojto 90:cb3d968589d8 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
Kojto 90:cb3d968589d8 770 }
Kojto 90:cb3d968589d8 771
Kojto 90:cb3d968589d8 772
Kojto 90:cb3d968589d8 773 /** \brief Get Interrupt Priority
Kojto 90:cb3d968589d8 774
Kojto 90:cb3d968589d8 775 The function reads the priority of an interrupt. The interrupt
Kojto 90:cb3d968589d8 776 number can be positive to specify an external (device specific)
Kojto 90:cb3d968589d8 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 90:cb3d968589d8 778
Kojto 90:cb3d968589d8 779
Kojto 90:cb3d968589d8 780 \param [in] IRQn Interrupt number.
Kojto 90:cb3d968589d8 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 90:cb3d968589d8 782 priority bits of the microcontroller.
Kojto 90:cb3d968589d8 783 */
Kojto 90:cb3d968589d8 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 785 {
Kojto 90:cb3d968589d8 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
Kojto 90:cb3d968589d8 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
Kojto 90:cb3d968589d8 793 }
Kojto 90:cb3d968589d8 794
Kojto 90:cb3d968589d8 795
Kojto 90:cb3d968589d8 796 /** \brief System Reset
Kojto 90:cb3d968589d8 797
Kojto 90:cb3d968589d8 798 The function initiates a system reset request to reset the MCU.
Kojto 90:cb3d968589d8 799 */
Kojto 90:cb3d968589d8 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 90:cb3d968589d8 801 {
Kojto 90:cb3d968589d8 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 90:cb3d968589d8 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 90:cb3d968589d8 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 90:cb3d968589d8 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
Kojto 90:cb3d968589d8 808 }
Kojto 90:cb3d968589d8 809
Kojto 90:cb3d968589d8 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 90:cb3d968589d8 811
Kojto 90:cb3d968589d8 812
Kojto 90:cb3d968589d8 813
Kojto 90:cb3d968589d8 814 /* ################################## SysTick function ############################################ */
Kojto 90:cb3d968589d8 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 90:cb3d968589d8 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 90:cb3d968589d8 817 \brief Functions that configure the System.
Kojto 90:cb3d968589d8 818 @{
Kojto 90:cb3d968589d8 819 */
Kojto 90:cb3d968589d8 820
Kojto 90:cb3d968589d8 821 #if (__Vendor_SysTickConfig == 0)
Kojto 90:cb3d968589d8 822
Kojto 90:cb3d968589d8 823 /** \brief System Tick Configuration
Kojto 90:cb3d968589d8 824
Kojto 90:cb3d968589d8 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 90:cb3d968589d8 826 Counter is in free running mode to generate periodic interrupts.
Kojto 90:cb3d968589d8 827
Kojto 90:cb3d968589d8 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 90:cb3d968589d8 829
Kojto 90:cb3d968589d8 830 \return 0 Function succeeded.
Kojto 90:cb3d968589d8 831 \return 1 Function failed.
Kojto 90:cb3d968589d8 832
Kojto 90:cb3d968589d8 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 90:cb3d968589d8 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 90:cb3d968589d8 835 must contain a vendor-specific implementation of this function.
Kojto 90:cb3d968589d8 836
Kojto 90:cb3d968589d8 837 */
Kojto 90:cb3d968589d8 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 90:cb3d968589d8 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 90:cb3d968589d8 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 90:cb3d968589d8 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 90:cb3d968589d8 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
Kojto 90:cb3d968589d8 849 }
Kojto 90:cb3d968589d8 850
Kojto 90:cb3d968589d8 851 #endif
Kojto 90:cb3d968589d8 852
Kojto 90:cb3d968589d8 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 90:cb3d968589d8 854
Kojto 90:cb3d968589d8 855
Kojto 90:cb3d968589d8 856
Kojto 90:cb3d968589d8 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
Kojto 90:cb3d968589d8 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 90:cb3d968589d8 863
Kojto 90:cb3d968589d8 864 #endif /* __CMSIS_GENERIC */