mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_B96B_F446VE/core_sc300.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 112:6f327212ef96 1 /**************************************************************************//**
Kojto 112:6f327212ef96 2 * @file core_sc300.h
Kojto 112:6f327212ef96 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
Kojto 112:6f327212ef96 4 * @version V4.10
Kojto 112:6f327212ef96 5 * @date 18. March 2015
Kojto 112:6f327212ef96 6 *
Kojto 112:6f327212ef96 7 * @note
Kojto 112:6f327212ef96 8 *
Kojto 112:6f327212ef96 9 ******************************************************************************/
Kojto 112:6f327212ef96 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 112:6f327212ef96 11
Kojto 112:6f327212ef96 12 All rights reserved.
Kojto 112:6f327212ef96 13 Redistribution and use in source and binary forms, with or without
Kojto 112:6f327212ef96 14 modification, are permitted provided that the following conditions are met:
Kojto 112:6f327212ef96 15 - Redistributions of source code must retain the above copyright
Kojto 112:6f327212ef96 16 notice, this list of conditions and the following disclaimer.
Kojto 112:6f327212ef96 17 - Redistributions in binary form must reproduce the above copyright
Kojto 112:6f327212ef96 18 notice, this list of conditions and the following disclaimer in the
Kojto 112:6f327212ef96 19 documentation and/or other materials provided with the distribution.
Kojto 112:6f327212ef96 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 112:6f327212ef96 21 to endorse or promote products derived from this software without
Kojto 112:6f327212ef96 22 specific prior written permission.
Kojto 112:6f327212ef96 23 *
Kojto 112:6f327212ef96 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 112:6f327212ef96 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 112:6f327212ef96 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 112:6f327212ef96 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 112:6f327212ef96 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 112:6f327212ef96 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 112:6f327212ef96 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 112:6f327212ef96 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 112:6f327212ef96 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 112:6f327212ef96 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 112:6f327212ef96 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 112:6f327212ef96 35 ---------------------------------------------------------------------------*/
Kojto 112:6f327212ef96 36
Kojto 112:6f327212ef96 37
Kojto 112:6f327212ef96 38 #if defined ( __ICCARM__ )
Kojto 112:6f327212ef96 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 112:6f327212ef96 40 #endif
Kojto 112:6f327212ef96 41
Kojto 112:6f327212ef96 42 #ifndef __CORE_SC300_H_GENERIC
Kojto 112:6f327212ef96 43 #define __CORE_SC300_H_GENERIC
Kojto 112:6f327212ef96 44
Kojto 112:6f327212ef96 45 #ifdef __cplusplus
Kojto 112:6f327212ef96 46 extern "C" {
Kojto 112:6f327212ef96 47 #endif
Kojto 112:6f327212ef96 48
Kojto 112:6f327212ef96 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 112:6f327212ef96 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 112:6f327212ef96 51
Kojto 112:6f327212ef96 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 112:6f327212ef96 53 Function definitions in header files are used to allow 'inlining'.
Kojto 112:6f327212ef96 54
Kojto 112:6f327212ef96 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 112:6f327212ef96 56 Unions are used for effective representation of core registers.
Kojto 112:6f327212ef96 57
Kojto 112:6f327212ef96 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 112:6f327212ef96 59 Function-like macros are used to allow more efficient code.
Kojto 112:6f327212ef96 60 */
Kojto 112:6f327212ef96 61
Kojto 112:6f327212ef96 62
Kojto 112:6f327212ef96 63 /*******************************************************************************
Kojto 112:6f327212ef96 64 * CMSIS definitions
Kojto 112:6f327212ef96 65 ******************************************************************************/
Kojto 112:6f327212ef96 66 /** \ingroup SC3000
Kojto 112:6f327212ef96 67 @{
Kojto 112:6f327212ef96 68 */
Kojto 112:6f327212ef96 69
Kojto 112:6f327212ef96 70 /* CMSIS SC300 definitions */
Kojto 112:6f327212ef96 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 112:6f327212ef96 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 112:6f327212ef96 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
Kojto 112:6f327212ef96 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 112:6f327212ef96 75
Kojto 112:6f327212ef96 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
Kojto 112:6f327212ef96 77
Kojto 112:6f327212ef96 78
Kojto 112:6f327212ef96 79 #if defined ( __CC_ARM )
Kojto 112:6f327212ef96 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 112:6f327212ef96 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 112:6f327212ef96 82 #define __STATIC_INLINE static __inline
Kojto 112:6f327212ef96 83
Kojto 112:6f327212ef96 84 #elif defined ( __GNUC__ )
Kojto 112:6f327212ef96 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 112:6f327212ef96 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 112:6f327212ef96 87 #define __STATIC_INLINE static inline
Kojto 112:6f327212ef96 88
Kojto 112:6f327212ef96 89 #elif defined ( __ICCARM__ )
Kojto 112:6f327212ef96 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 112:6f327212ef96 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 112:6f327212ef96 92 #define __STATIC_INLINE static inline
Kojto 112:6f327212ef96 93
Kojto 112:6f327212ef96 94 #elif defined ( __TMS470__ )
Kojto 112:6f327212ef96 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 112:6f327212ef96 96 #define __STATIC_INLINE static inline
Kojto 112:6f327212ef96 97
Kojto 112:6f327212ef96 98 #elif defined ( __TASKING__ )
Kojto 112:6f327212ef96 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 112:6f327212ef96 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 112:6f327212ef96 101 #define __STATIC_INLINE static inline
Kojto 112:6f327212ef96 102
Kojto 112:6f327212ef96 103 #elif defined ( __CSMC__ )
Kojto 112:6f327212ef96 104 #define __packed
Kojto 112:6f327212ef96 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 112:6f327212ef96 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 112:6f327212ef96 107 #define __STATIC_INLINE static inline
Kojto 112:6f327212ef96 108
Kojto 112:6f327212ef96 109 #endif
Kojto 112:6f327212ef96 110
Kojto 112:6f327212ef96 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 112:6f327212ef96 112 This core does not support an FPU at all
Kojto 112:6f327212ef96 113 */
Kojto 112:6f327212ef96 114 #define __FPU_USED 0
Kojto 112:6f327212ef96 115
Kojto 112:6f327212ef96 116 #if defined ( __CC_ARM )
Kojto 112:6f327212ef96 117 #if defined __TARGET_FPU_VFP
Kojto 112:6f327212ef96 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 112:6f327212ef96 119 #endif
Kojto 112:6f327212ef96 120
Kojto 112:6f327212ef96 121 #elif defined ( __GNUC__ )
Kojto 112:6f327212ef96 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 112:6f327212ef96 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 112:6f327212ef96 124 #endif
Kojto 112:6f327212ef96 125
Kojto 112:6f327212ef96 126 #elif defined ( __ICCARM__ )
Kojto 112:6f327212ef96 127 #if defined __ARMVFP__
Kojto 112:6f327212ef96 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 112:6f327212ef96 129 #endif
Kojto 112:6f327212ef96 130
Kojto 112:6f327212ef96 131 #elif defined ( __TMS470__ )
Kojto 112:6f327212ef96 132 #if defined __TI__VFP_SUPPORT____
Kojto 112:6f327212ef96 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 112:6f327212ef96 134 #endif
Kojto 112:6f327212ef96 135
Kojto 112:6f327212ef96 136 #elif defined ( __TASKING__ )
Kojto 112:6f327212ef96 137 #if defined __FPU_VFP__
Kojto 112:6f327212ef96 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 112:6f327212ef96 139 #endif
Kojto 112:6f327212ef96 140
Kojto 112:6f327212ef96 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 112:6f327212ef96 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 112:6f327212ef96 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 112:6f327212ef96 144 #endif
Kojto 112:6f327212ef96 145 #endif
Kojto 112:6f327212ef96 146
Kojto 112:6f327212ef96 147 #include <stdint.h> /* standard types definitions */
Kojto 112:6f327212ef96 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 112:6f327212ef96 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 112:6f327212ef96 150
Kojto 112:6f327212ef96 151 #ifdef __cplusplus
Kojto 112:6f327212ef96 152 }
Kojto 112:6f327212ef96 153 #endif
Kojto 112:6f327212ef96 154
Kojto 112:6f327212ef96 155 #endif /* __CORE_SC300_H_GENERIC */
Kojto 112:6f327212ef96 156
Kojto 112:6f327212ef96 157 #ifndef __CMSIS_GENERIC
Kojto 112:6f327212ef96 158
Kojto 112:6f327212ef96 159 #ifndef __CORE_SC300_H_DEPENDANT
Kojto 112:6f327212ef96 160 #define __CORE_SC300_H_DEPENDANT
Kojto 112:6f327212ef96 161
Kojto 112:6f327212ef96 162 #ifdef __cplusplus
Kojto 112:6f327212ef96 163 extern "C" {
Kojto 112:6f327212ef96 164 #endif
Kojto 112:6f327212ef96 165
Kojto 112:6f327212ef96 166 /* check device defines and use defaults */
Kojto 112:6f327212ef96 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 112:6f327212ef96 168 #ifndef __SC300_REV
Kojto 112:6f327212ef96 169 #define __SC300_REV 0x0000
Kojto 112:6f327212ef96 170 #warning "__SC300_REV not defined in device header file; using default!"
Kojto 112:6f327212ef96 171 #endif
Kojto 112:6f327212ef96 172
Kojto 112:6f327212ef96 173 #ifndef __MPU_PRESENT
Kojto 112:6f327212ef96 174 #define __MPU_PRESENT 0
Kojto 112:6f327212ef96 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 112:6f327212ef96 176 #endif
Kojto 112:6f327212ef96 177
Kojto 112:6f327212ef96 178 #ifndef __NVIC_PRIO_BITS
Kojto 112:6f327212ef96 179 #define __NVIC_PRIO_BITS 4
Kojto 112:6f327212ef96 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 112:6f327212ef96 181 #endif
Kojto 112:6f327212ef96 182
Kojto 112:6f327212ef96 183 #ifndef __Vendor_SysTickConfig
Kojto 112:6f327212ef96 184 #define __Vendor_SysTickConfig 0
Kojto 112:6f327212ef96 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 112:6f327212ef96 186 #endif
Kojto 112:6f327212ef96 187 #endif
Kojto 112:6f327212ef96 188
Kojto 112:6f327212ef96 189 /* IO definitions (access restrictions to peripheral registers) */
Kojto 112:6f327212ef96 190 /**
Kojto 112:6f327212ef96 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 112:6f327212ef96 192
Kojto 112:6f327212ef96 193 <strong>IO Type Qualifiers</strong> are used
Kojto 112:6f327212ef96 194 \li to specify the access to peripheral variables.
Kojto 112:6f327212ef96 195 \li for automatic generation of peripheral register debug information.
Kojto 112:6f327212ef96 196 */
Kojto 112:6f327212ef96 197 #ifdef __cplusplus
Kojto 112:6f327212ef96 198 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 112:6f327212ef96 199 #else
Kojto 112:6f327212ef96 200 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 112:6f327212ef96 201 #endif
Kojto 112:6f327212ef96 202 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 112:6f327212ef96 203 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 112:6f327212ef96 204
Kojto 112:6f327212ef96 205 /*@} end of group SC300 */
Kojto 112:6f327212ef96 206
Kojto 112:6f327212ef96 207
Kojto 112:6f327212ef96 208
Kojto 112:6f327212ef96 209 /*******************************************************************************
Kojto 112:6f327212ef96 210 * Register Abstraction
Kojto 112:6f327212ef96 211 Core Register contain:
Kojto 112:6f327212ef96 212 - Core Register
Kojto 112:6f327212ef96 213 - Core NVIC Register
Kojto 112:6f327212ef96 214 - Core SCB Register
Kojto 112:6f327212ef96 215 - Core SysTick Register
Kojto 112:6f327212ef96 216 - Core Debug Register
Kojto 112:6f327212ef96 217 - Core MPU Register
Kojto 112:6f327212ef96 218 ******************************************************************************/
Kojto 112:6f327212ef96 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 112:6f327212ef96 220 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 112:6f327212ef96 221 */
Kojto 112:6f327212ef96 222
Kojto 112:6f327212ef96 223 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 224 \defgroup CMSIS_CORE Status and Control Registers
Kojto 112:6f327212ef96 225 \brief Core Register type definitions.
Kojto 112:6f327212ef96 226 @{
Kojto 112:6f327212ef96 227 */
Kojto 112:6f327212ef96 228
Kojto 112:6f327212ef96 229 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 112:6f327212ef96 230 */
Kojto 112:6f327212ef96 231 typedef union
Kojto 112:6f327212ef96 232 {
Kojto 112:6f327212ef96 233 struct
Kojto 112:6f327212ef96 234 {
Kojto 112:6f327212ef96 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 112:6f327212ef96 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 112:6f327212ef96 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 112:6f327212ef96 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 112:6f327212ef96 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 112:6f327212ef96 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 112:6f327212ef96 241 } b; /*!< Structure used for bit access */
Kojto 112:6f327212ef96 242 uint32_t w; /*!< Type used for word access */
Kojto 112:6f327212ef96 243 } APSR_Type;
Kojto 112:6f327212ef96 244
Kojto 112:6f327212ef96 245 /* APSR Register Definitions */
Kojto 112:6f327212ef96 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 112:6f327212ef96 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 112:6f327212ef96 248
Kojto 112:6f327212ef96 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 112:6f327212ef96 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 112:6f327212ef96 251
Kojto 112:6f327212ef96 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 112:6f327212ef96 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 112:6f327212ef96 254
Kojto 112:6f327212ef96 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 112:6f327212ef96 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 112:6f327212ef96 257
Kojto 112:6f327212ef96 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 112:6f327212ef96 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 112:6f327212ef96 260
Kojto 112:6f327212ef96 261
Kojto 112:6f327212ef96 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 112:6f327212ef96 263 */
Kojto 112:6f327212ef96 264 typedef union
Kojto 112:6f327212ef96 265 {
Kojto 112:6f327212ef96 266 struct
Kojto 112:6f327212ef96 267 {
Kojto 112:6f327212ef96 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 112:6f327212ef96 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 112:6f327212ef96 270 } b; /*!< Structure used for bit access */
Kojto 112:6f327212ef96 271 uint32_t w; /*!< Type used for word access */
Kojto 112:6f327212ef96 272 } IPSR_Type;
Kojto 112:6f327212ef96 273
Kojto 112:6f327212ef96 274 /* IPSR Register Definitions */
Kojto 112:6f327212ef96 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 112:6f327212ef96 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 112:6f327212ef96 277
Kojto 112:6f327212ef96 278
Kojto 112:6f327212ef96 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 112:6f327212ef96 280 */
Kojto 112:6f327212ef96 281 typedef union
Kojto 112:6f327212ef96 282 {
Kojto 112:6f327212ef96 283 struct
Kojto 112:6f327212ef96 284 {
Kojto 112:6f327212ef96 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 112:6f327212ef96 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 112:6f327212ef96 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 112:6f327212ef96 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 112:6f327212ef96 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 112:6f327212ef96 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 112:6f327212ef96 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 112:6f327212ef96 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 112:6f327212ef96 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 112:6f327212ef96 294 } b; /*!< Structure used for bit access */
Kojto 112:6f327212ef96 295 uint32_t w; /*!< Type used for word access */
Kojto 112:6f327212ef96 296 } xPSR_Type;
Kojto 112:6f327212ef96 297
Kojto 112:6f327212ef96 298 /* xPSR Register Definitions */
Kojto 112:6f327212ef96 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 112:6f327212ef96 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 112:6f327212ef96 301
Kojto 112:6f327212ef96 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 112:6f327212ef96 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 112:6f327212ef96 304
Kojto 112:6f327212ef96 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 112:6f327212ef96 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 112:6f327212ef96 307
Kojto 112:6f327212ef96 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 112:6f327212ef96 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 112:6f327212ef96 310
Kojto 112:6f327212ef96 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 112:6f327212ef96 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 112:6f327212ef96 313
Kojto 112:6f327212ef96 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 112:6f327212ef96 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 112:6f327212ef96 316
Kojto 112:6f327212ef96 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 112:6f327212ef96 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 112:6f327212ef96 319
Kojto 112:6f327212ef96 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 112:6f327212ef96 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 112:6f327212ef96 322
Kojto 112:6f327212ef96 323
Kojto 112:6f327212ef96 324 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 112:6f327212ef96 325 */
Kojto 112:6f327212ef96 326 typedef union
Kojto 112:6f327212ef96 327 {
Kojto 112:6f327212ef96 328 struct
Kojto 112:6f327212ef96 329 {
Kojto 112:6f327212ef96 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 112:6f327212ef96 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 112:6f327212ef96 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 112:6f327212ef96 333 } b; /*!< Structure used for bit access */
Kojto 112:6f327212ef96 334 uint32_t w; /*!< Type used for word access */
Kojto 112:6f327212ef96 335 } CONTROL_Type;
Kojto 112:6f327212ef96 336
Kojto 112:6f327212ef96 337 /* CONTROL Register Definitions */
Kojto 112:6f327212ef96 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 112:6f327212ef96 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 112:6f327212ef96 340
Kojto 112:6f327212ef96 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 112:6f327212ef96 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 112:6f327212ef96 343
Kojto 112:6f327212ef96 344 /*@} end of group CMSIS_CORE */
Kojto 112:6f327212ef96 345
Kojto 112:6f327212ef96 346
Kojto 112:6f327212ef96 347 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 112:6f327212ef96 349 \brief Type definitions for the NVIC Registers
Kojto 112:6f327212ef96 350 @{
Kojto 112:6f327212ef96 351 */
Kojto 112:6f327212ef96 352
Kojto 112:6f327212ef96 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 112:6f327212ef96 354 */
Kojto 112:6f327212ef96 355 typedef struct
Kojto 112:6f327212ef96 356 {
Kojto 112:6f327212ef96 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 112:6f327212ef96 358 uint32_t RESERVED0[24];
Kojto 112:6f327212ef96 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 112:6f327212ef96 360 uint32_t RSERVED1[24];
Kojto 112:6f327212ef96 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 112:6f327212ef96 362 uint32_t RESERVED2[24];
Kojto 112:6f327212ef96 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 112:6f327212ef96 364 uint32_t RESERVED3[24];
Kojto 112:6f327212ef96 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 112:6f327212ef96 366 uint32_t RESERVED4[56];
Kojto 112:6f327212ef96 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 112:6f327212ef96 368 uint32_t RESERVED5[644];
Kojto 112:6f327212ef96 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 112:6f327212ef96 370 } NVIC_Type;
Kojto 112:6f327212ef96 371
Kojto 112:6f327212ef96 372 /* Software Triggered Interrupt Register Definitions */
Kojto 112:6f327212ef96 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 112:6f327212ef96 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 112:6f327212ef96 375
Kojto 112:6f327212ef96 376 /*@} end of group CMSIS_NVIC */
Kojto 112:6f327212ef96 377
Kojto 112:6f327212ef96 378
Kojto 112:6f327212ef96 379 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 380 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 112:6f327212ef96 381 \brief Type definitions for the System Control Block Registers
Kojto 112:6f327212ef96 382 @{
Kojto 112:6f327212ef96 383 */
Kojto 112:6f327212ef96 384
Kojto 112:6f327212ef96 385 /** \brief Structure type to access the System Control Block (SCB).
Kojto 112:6f327212ef96 386 */
Kojto 112:6f327212ef96 387 typedef struct
Kojto 112:6f327212ef96 388 {
Kojto 112:6f327212ef96 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 112:6f327212ef96 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 112:6f327212ef96 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 112:6f327212ef96 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 112:6f327212ef96 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 112:6f327212ef96 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 112:6f327212ef96 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 112:6f327212ef96 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 112:6f327212ef96 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 112:6f327212ef96 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 112:6f327212ef96 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 112:6f327212ef96 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 112:6f327212ef96 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 112:6f327212ef96 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 112:6f327212ef96 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 112:6f327212ef96 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 112:6f327212ef96 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 112:6f327212ef96 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 112:6f327212ef96 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 112:6f327212ef96 408 uint32_t RESERVED0[5];
Kojto 112:6f327212ef96 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 112:6f327212ef96 410 uint32_t RESERVED1[129];
Kojto 112:6f327212ef96 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Kojto 112:6f327212ef96 412 } SCB_Type;
Kojto 112:6f327212ef96 413
Kojto 112:6f327212ef96 414 /* SCB CPUID Register Definitions */
Kojto 112:6f327212ef96 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 112:6f327212ef96 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 112:6f327212ef96 417
Kojto 112:6f327212ef96 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 112:6f327212ef96 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 112:6f327212ef96 420
Kojto 112:6f327212ef96 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 112:6f327212ef96 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 112:6f327212ef96 423
Kojto 112:6f327212ef96 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 112:6f327212ef96 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 112:6f327212ef96 426
Kojto 112:6f327212ef96 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 112:6f327212ef96 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 112:6f327212ef96 429
Kojto 112:6f327212ef96 430 /* SCB Interrupt Control State Register Definitions */
Kojto 112:6f327212ef96 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 112:6f327212ef96 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 112:6f327212ef96 433
Kojto 112:6f327212ef96 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 112:6f327212ef96 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 112:6f327212ef96 436
Kojto 112:6f327212ef96 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 112:6f327212ef96 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 112:6f327212ef96 439
Kojto 112:6f327212ef96 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 112:6f327212ef96 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 112:6f327212ef96 442
Kojto 112:6f327212ef96 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 112:6f327212ef96 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 112:6f327212ef96 445
Kojto 112:6f327212ef96 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 112:6f327212ef96 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 112:6f327212ef96 448
Kojto 112:6f327212ef96 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 112:6f327212ef96 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 112:6f327212ef96 451
Kojto 112:6f327212ef96 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 112:6f327212ef96 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 112:6f327212ef96 454
Kojto 112:6f327212ef96 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 112:6f327212ef96 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 112:6f327212ef96 457
Kojto 112:6f327212ef96 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 112:6f327212ef96 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 112:6f327212ef96 460
Kojto 112:6f327212ef96 461 /* SCB Vector Table Offset Register Definitions */
Kojto 112:6f327212ef96 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Kojto 112:6f327212ef96 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kojto 112:6f327212ef96 464
Kojto 112:6f327212ef96 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 112:6f327212ef96 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 112:6f327212ef96 467
Kojto 112:6f327212ef96 468 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 112:6f327212ef96 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 112:6f327212ef96 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 112:6f327212ef96 471
Kojto 112:6f327212ef96 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 112:6f327212ef96 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 112:6f327212ef96 474
Kojto 112:6f327212ef96 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 112:6f327212ef96 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 112:6f327212ef96 477
Kojto 112:6f327212ef96 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 112:6f327212ef96 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 112:6f327212ef96 480
Kojto 112:6f327212ef96 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 112:6f327212ef96 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 112:6f327212ef96 483
Kojto 112:6f327212ef96 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 112:6f327212ef96 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 112:6f327212ef96 486
Kojto 112:6f327212ef96 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 112:6f327212ef96 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 112:6f327212ef96 489
Kojto 112:6f327212ef96 490 /* SCB System Control Register Definitions */
Kojto 112:6f327212ef96 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 112:6f327212ef96 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 112:6f327212ef96 493
Kojto 112:6f327212ef96 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 112:6f327212ef96 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 112:6f327212ef96 496
Kojto 112:6f327212ef96 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 112:6f327212ef96 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 112:6f327212ef96 499
Kojto 112:6f327212ef96 500 /* SCB Configuration Control Register Definitions */
Kojto 112:6f327212ef96 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 112:6f327212ef96 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 112:6f327212ef96 503
Kojto 112:6f327212ef96 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 112:6f327212ef96 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 112:6f327212ef96 506
Kojto 112:6f327212ef96 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 112:6f327212ef96 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 112:6f327212ef96 509
Kojto 112:6f327212ef96 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 112:6f327212ef96 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 112:6f327212ef96 512
Kojto 112:6f327212ef96 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 112:6f327212ef96 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 112:6f327212ef96 515
Kojto 112:6f327212ef96 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 112:6f327212ef96 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 112:6f327212ef96 518
Kojto 112:6f327212ef96 519 /* SCB System Handler Control and State Register Definitions */
Kojto 112:6f327212ef96 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 112:6f327212ef96 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 112:6f327212ef96 522
Kojto 112:6f327212ef96 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 112:6f327212ef96 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 112:6f327212ef96 525
Kojto 112:6f327212ef96 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 112:6f327212ef96 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 112:6f327212ef96 528
Kojto 112:6f327212ef96 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 112:6f327212ef96 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 112:6f327212ef96 531
Kojto 112:6f327212ef96 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 112:6f327212ef96 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 112:6f327212ef96 534
Kojto 112:6f327212ef96 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 112:6f327212ef96 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 112:6f327212ef96 537
Kojto 112:6f327212ef96 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 112:6f327212ef96 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 112:6f327212ef96 540
Kojto 112:6f327212ef96 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 112:6f327212ef96 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 112:6f327212ef96 543
Kojto 112:6f327212ef96 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 112:6f327212ef96 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 112:6f327212ef96 546
Kojto 112:6f327212ef96 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 112:6f327212ef96 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 112:6f327212ef96 549
Kojto 112:6f327212ef96 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 112:6f327212ef96 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 112:6f327212ef96 552
Kojto 112:6f327212ef96 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 112:6f327212ef96 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 112:6f327212ef96 555
Kojto 112:6f327212ef96 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 112:6f327212ef96 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 112:6f327212ef96 558
Kojto 112:6f327212ef96 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 112:6f327212ef96 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 112:6f327212ef96 561
Kojto 112:6f327212ef96 562 /* SCB Configurable Fault Status Registers Definitions */
Kojto 112:6f327212ef96 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 112:6f327212ef96 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 112:6f327212ef96 565
Kojto 112:6f327212ef96 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 112:6f327212ef96 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 112:6f327212ef96 568
Kojto 112:6f327212ef96 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 112:6f327212ef96 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 112:6f327212ef96 571
Kojto 112:6f327212ef96 572 /* SCB Hard Fault Status Registers Definitions */
Kojto 112:6f327212ef96 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 112:6f327212ef96 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 112:6f327212ef96 575
Kojto 112:6f327212ef96 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 112:6f327212ef96 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 112:6f327212ef96 578
Kojto 112:6f327212ef96 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 112:6f327212ef96 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 112:6f327212ef96 581
Kojto 112:6f327212ef96 582 /* SCB Debug Fault Status Register Definitions */
Kojto 112:6f327212ef96 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 112:6f327212ef96 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 112:6f327212ef96 585
Kojto 112:6f327212ef96 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 112:6f327212ef96 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 112:6f327212ef96 588
Kojto 112:6f327212ef96 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 112:6f327212ef96 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 112:6f327212ef96 591
Kojto 112:6f327212ef96 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 112:6f327212ef96 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 112:6f327212ef96 594
Kojto 112:6f327212ef96 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 112:6f327212ef96 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 112:6f327212ef96 597
Kojto 112:6f327212ef96 598 /*@} end of group CMSIS_SCB */
Kojto 112:6f327212ef96 599
Kojto 112:6f327212ef96 600
Kojto 112:6f327212ef96 601 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 112:6f327212ef96 603 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 112:6f327212ef96 604 @{
Kojto 112:6f327212ef96 605 */
Kojto 112:6f327212ef96 606
Kojto 112:6f327212ef96 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 112:6f327212ef96 608 */
Kojto 112:6f327212ef96 609 typedef struct
Kojto 112:6f327212ef96 610 {
Kojto 112:6f327212ef96 611 uint32_t RESERVED0[1];
Kojto 112:6f327212ef96 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 112:6f327212ef96 613 uint32_t RESERVED1[1];
Kojto 112:6f327212ef96 614 } SCnSCB_Type;
Kojto 112:6f327212ef96 615
Kojto 112:6f327212ef96 616 /* Interrupt Controller Type Register Definitions */
Kojto 112:6f327212ef96 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 112:6f327212ef96 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 112:6f327212ef96 619
Kojto 112:6f327212ef96 620 /*@} end of group CMSIS_SCnotSCB */
Kojto 112:6f327212ef96 621
Kojto 112:6f327212ef96 622
Kojto 112:6f327212ef96 623 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 112:6f327212ef96 625 \brief Type definitions for the System Timer Registers.
Kojto 112:6f327212ef96 626 @{
Kojto 112:6f327212ef96 627 */
Kojto 112:6f327212ef96 628
Kojto 112:6f327212ef96 629 /** \brief Structure type to access the System Timer (SysTick).
Kojto 112:6f327212ef96 630 */
Kojto 112:6f327212ef96 631 typedef struct
Kojto 112:6f327212ef96 632 {
Kojto 112:6f327212ef96 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 112:6f327212ef96 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 112:6f327212ef96 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 112:6f327212ef96 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 112:6f327212ef96 637 } SysTick_Type;
Kojto 112:6f327212ef96 638
Kojto 112:6f327212ef96 639 /* SysTick Control / Status Register Definitions */
Kojto 112:6f327212ef96 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 112:6f327212ef96 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 112:6f327212ef96 642
Kojto 112:6f327212ef96 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 112:6f327212ef96 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 112:6f327212ef96 645
Kojto 112:6f327212ef96 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 112:6f327212ef96 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 112:6f327212ef96 648
Kojto 112:6f327212ef96 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 112:6f327212ef96 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 112:6f327212ef96 651
Kojto 112:6f327212ef96 652 /* SysTick Reload Register Definitions */
Kojto 112:6f327212ef96 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 112:6f327212ef96 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 112:6f327212ef96 655
Kojto 112:6f327212ef96 656 /* SysTick Current Register Definitions */
Kojto 112:6f327212ef96 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 112:6f327212ef96 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 112:6f327212ef96 659
Kojto 112:6f327212ef96 660 /* SysTick Calibration Register Definitions */
Kojto 112:6f327212ef96 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 112:6f327212ef96 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 112:6f327212ef96 663
Kojto 112:6f327212ef96 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 112:6f327212ef96 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 112:6f327212ef96 666
Kojto 112:6f327212ef96 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 112:6f327212ef96 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 112:6f327212ef96 669
Kojto 112:6f327212ef96 670 /*@} end of group CMSIS_SysTick */
Kojto 112:6f327212ef96 671
Kojto 112:6f327212ef96 672
Kojto 112:6f327212ef96 673 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 112:6f327212ef96 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 112:6f327212ef96 676 @{
Kojto 112:6f327212ef96 677 */
Kojto 112:6f327212ef96 678
Kojto 112:6f327212ef96 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 112:6f327212ef96 680 */
Kojto 112:6f327212ef96 681 typedef struct
Kojto 112:6f327212ef96 682 {
Kojto 112:6f327212ef96 683 __O union
Kojto 112:6f327212ef96 684 {
Kojto 112:6f327212ef96 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 112:6f327212ef96 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 112:6f327212ef96 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 112:6f327212ef96 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 112:6f327212ef96 689 uint32_t RESERVED0[864];
Kojto 112:6f327212ef96 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 112:6f327212ef96 691 uint32_t RESERVED1[15];
Kojto 112:6f327212ef96 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 112:6f327212ef96 693 uint32_t RESERVED2[15];
Kojto 112:6f327212ef96 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 112:6f327212ef96 695 uint32_t RESERVED3[29];
Kojto 112:6f327212ef96 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 112:6f327212ef96 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 112:6f327212ef96 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 112:6f327212ef96 699 uint32_t RESERVED4[43];
Kojto 112:6f327212ef96 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 112:6f327212ef96 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 112:6f327212ef96 702 uint32_t RESERVED5[6];
Kojto 112:6f327212ef96 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 112:6f327212ef96 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 112:6f327212ef96 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 112:6f327212ef96 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 112:6f327212ef96 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 112:6f327212ef96 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 112:6f327212ef96 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 112:6f327212ef96 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 112:6f327212ef96 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 112:6f327212ef96 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 112:6f327212ef96 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 112:6f327212ef96 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 112:6f327212ef96 715 } ITM_Type;
Kojto 112:6f327212ef96 716
Kojto 112:6f327212ef96 717 /* ITM Trace Privilege Register Definitions */
Kojto 112:6f327212ef96 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 112:6f327212ef96 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 112:6f327212ef96 720
Kojto 112:6f327212ef96 721 /* ITM Trace Control Register Definitions */
Kojto 112:6f327212ef96 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 112:6f327212ef96 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 112:6f327212ef96 724
Kojto 112:6f327212ef96 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 112:6f327212ef96 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 112:6f327212ef96 727
Kojto 112:6f327212ef96 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 112:6f327212ef96 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 112:6f327212ef96 730
Kojto 112:6f327212ef96 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 112:6f327212ef96 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 112:6f327212ef96 733
Kojto 112:6f327212ef96 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 112:6f327212ef96 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 112:6f327212ef96 736
Kojto 112:6f327212ef96 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 112:6f327212ef96 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 112:6f327212ef96 739
Kojto 112:6f327212ef96 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 112:6f327212ef96 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 112:6f327212ef96 742
Kojto 112:6f327212ef96 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 112:6f327212ef96 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 112:6f327212ef96 745
Kojto 112:6f327212ef96 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 112:6f327212ef96 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 112:6f327212ef96 748
Kojto 112:6f327212ef96 749 /* ITM Integration Write Register Definitions */
Kojto 112:6f327212ef96 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 112:6f327212ef96 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 112:6f327212ef96 752
Kojto 112:6f327212ef96 753 /* ITM Integration Read Register Definitions */
Kojto 112:6f327212ef96 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 112:6f327212ef96 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 112:6f327212ef96 756
Kojto 112:6f327212ef96 757 /* ITM Integration Mode Control Register Definitions */
Kojto 112:6f327212ef96 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 112:6f327212ef96 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 112:6f327212ef96 760
Kojto 112:6f327212ef96 761 /* ITM Lock Status Register Definitions */
Kojto 112:6f327212ef96 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 112:6f327212ef96 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 112:6f327212ef96 764
Kojto 112:6f327212ef96 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 112:6f327212ef96 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 112:6f327212ef96 767
Kojto 112:6f327212ef96 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 112:6f327212ef96 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 112:6f327212ef96 770
Kojto 112:6f327212ef96 771 /*@}*/ /* end of group CMSIS_ITM */
Kojto 112:6f327212ef96 772
Kojto 112:6f327212ef96 773
Kojto 112:6f327212ef96 774 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 112:6f327212ef96 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 112:6f327212ef96 777 @{
Kojto 112:6f327212ef96 778 */
Kojto 112:6f327212ef96 779
Kojto 112:6f327212ef96 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 112:6f327212ef96 781 */
Kojto 112:6f327212ef96 782 typedef struct
Kojto 112:6f327212ef96 783 {
Kojto 112:6f327212ef96 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 112:6f327212ef96 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 112:6f327212ef96 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 112:6f327212ef96 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 112:6f327212ef96 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 112:6f327212ef96 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 112:6f327212ef96 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 112:6f327212ef96 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 112:6f327212ef96 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 112:6f327212ef96 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 112:6f327212ef96 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 112:6f327212ef96 795 uint32_t RESERVED0[1];
Kojto 112:6f327212ef96 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 112:6f327212ef96 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 112:6f327212ef96 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 112:6f327212ef96 799 uint32_t RESERVED1[1];
Kojto 112:6f327212ef96 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 112:6f327212ef96 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 112:6f327212ef96 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 112:6f327212ef96 803 uint32_t RESERVED2[1];
Kojto 112:6f327212ef96 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 112:6f327212ef96 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 112:6f327212ef96 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 112:6f327212ef96 807 } DWT_Type;
Kojto 112:6f327212ef96 808
Kojto 112:6f327212ef96 809 /* DWT Control Register Definitions */
Kojto 112:6f327212ef96 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 112:6f327212ef96 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 112:6f327212ef96 812
Kojto 112:6f327212ef96 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 112:6f327212ef96 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 112:6f327212ef96 815
Kojto 112:6f327212ef96 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 112:6f327212ef96 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 112:6f327212ef96 818
Kojto 112:6f327212ef96 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 112:6f327212ef96 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 112:6f327212ef96 821
Kojto 112:6f327212ef96 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 112:6f327212ef96 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 112:6f327212ef96 824
Kojto 112:6f327212ef96 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 112:6f327212ef96 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 112:6f327212ef96 827
Kojto 112:6f327212ef96 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 112:6f327212ef96 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 112:6f327212ef96 830
Kojto 112:6f327212ef96 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 112:6f327212ef96 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 112:6f327212ef96 833
Kojto 112:6f327212ef96 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 112:6f327212ef96 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 112:6f327212ef96 836
Kojto 112:6f327212ef96 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 112:6f327212ef96 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 112:6f327212ef96 839
Kojto 112:6f327212ef96 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 112:6f327212ef96 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 112:6f327212ef96 842
Kojto 112:6f327212ef96 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 112:6f327212ef96 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 112:6f327212ef96 845
Kojto 112:6f327212ef96 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 112:6f327212ef96 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 112:6f327212ef96 848
Kojto 112:6f327212ef96 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 112:6f327212ef96 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 112:6f327212ef96 851
Kojto 112:6f327212ef96 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 112:6f327212ef96 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 112:6f327212ef96 854
Kojto 112:6f327212ef96 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 112:6f327212ef96 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 112:6f327212ef96 857
Kojto 112:6f327212ef96 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 112:6f327212ef96 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 112:6f327212ef96 860
Kojto 112:6f327212ef96 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 112:6f327212ef96 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 112:6f327212ef96 863
Kojto 112:6f327212ef96 864 /* DWT CPI Count Register Definitions */
Kojto 112:6f327212ef96 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 112:6f327212ef96 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 112:6f327212ef96 867
Kojto 112:6f327212ef96 868 /* DWT Exception Overhead Count Register Definitions */
Kojto 112:6f327212ef96 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 112:6f327212ef96 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 112:6f327212ef96 871
Kojto 112:6f327212ef96 872 /* DWT Sleep Count Register Definitions */
Kojto 112:6f327212ef96 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 112:6f327212ef96 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 112:6f327212ef96 875
Kojto 112:6f327212ef96 876 /* DWT LSU Count Register Definitions */
Kojto 112:6f327212ef96 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 112:6f327212ef96 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 112:6f327212ef96 879
Kojto 112:6f327212ef96 880 /* DWT Folded-instruction Count Register Definitions */
Kojto 112:6f327212ef96 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 112:6f327212ef96 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 112:6f327212ef96 883
Kojto 112:6f327212ef96 884 /* DWT Comparator Mask Register Definitions */
Kojto 112:6f327212ef96 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 112:6f327212ef96 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 112:6f327212ef96 887
Kojto 112:6f327212ef96 888 /* DWT Comparator Function Register Definitions */
Kojto 112:6f327212ef96 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 112:6f327212ef96 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 112:6f327212ef96 891
Kojto 112:6f327212ef96 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 112:6f327212ef96 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 112:6f327212ef96 894
Kojto 112:6f327212ef96 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 112:6f327212ef96 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 112:6f327212ef96 897
Kojto 112:6f327212ef96 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 112:6f327212ef96 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 112:6f327212ef96 900
Kojto 112:6f327212ef96 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 112:6f327212ef96 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 112:6f327212ef96 903
Kojto 112:6f327212ef96 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 112:6f327212ef96 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 112:6f327212ef96 906
Kojto 112:6f327212ef96 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 112:6f327212ef96 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 112:6f327212ef96 909
Kojto 112:6f327212ef96 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 112:6f327212ef96 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 112:6f327212ef96 912
Kojto 112:6f327212ef96 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 112:6f327212ef96 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 112:6f327212ef96 915
Kojto 112:6f327212ef96 916 /*@}*/ /* end of group CMSIS_DWT */
Kojto 112:6f327212ef96 917
Kojto 112:6f327212ef96 918
Kojto 112:6f327212ef96 919 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 112:6f327212ef96 921 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 112:6f327212ef96 922 @{
Kojto 112:6f327212ef96 923 */
Kojto 112:6f327212ef96 924
Kojto 112:6f327212ef96 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 112:6f327212ef96 926 */
Kojto 112:6f327212ef96 927 typedef struct
Kojto 112:6f327212ef96 928 {
Kojto 112:6f327212ef96 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 112:6f327212ef96 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 112:6f327212ef96 931 uint32_t RESERVED0[2];
Kojto 112:6f327212ef96 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 112:6f327212ef96 933 uint32_t RESERVED1[55];
Kojto 112:6f327212ef96 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 112:6f327212ef96 935 uint32_t RESERVED2[131];
Kojto 112:6f327212ef96 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 112:6f327212ef96 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 112:6f327212ef96 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 112:6f327212ef96 939 uint32_t RESERVED3[759];
Kojto 112:6f327212ef96 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 112:6f327212ef96 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 112:6f327212ef96 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 112:6f327212ef96 943 uint32_t RESERVED4[1];
Kojto 112:6f327212ef96 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 112:6f327212ef96 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 112:6f327212ef96 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 112:6f327212ef96 947 uint32_t RESERVED5[39];
Kojto 112:6f327212ef96 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 112:6f327212ef96 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 112:6f327212ef96 950 uint32_t RESERVED7[8];
Kojto 112:6f327212ef96 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 112:6f327212ef96 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 112:6f327212ef96 953 } TPI_Type;
Kojto 112:6f327212ef96 954
Kojto 112:6f327212ef96 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 112:6f327212ef96 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 112:6f327212ef96 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 112:6f327212ef96 958
Kojto 112:6f327212ef96 959 /* TPI Selected Pin Protocol Register Definitions */
Kojto 112:6f327212ef96 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 112:6f327212ef96 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 112:6f327212ef96 962
Kojto 112:6f327212ef96 963 /* TPI Formatter and Flush Status Register Definitions */
Kojto 112:6f327212ef96 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 112:6f327212ef96 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 112:6f327212ef96 966
Kojto 112:6f327212ef96 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 112:6f327212ef96 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 112:6f327212ef96 969
Kojto 112:6f327212ef96 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 112:6f327212ef96 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 112:6f327212ef96 972
Kojto 112:6f327212ef96 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 112:6f327212ef96 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 112:6f327212ef96 975
Kojto 112:6f327212ef96 976 /* TPI Formatter and Flush Control Register Definitions */
Kojto 112:6f327212ef96 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 112:6f327212ef96 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 112:6f327212ef96 979
Kojto 112:6f327212ef96 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 112:6f327212ef96 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 112:6f327212ef96 982
Kojto 112:6f327212ef96 983 /* TPI TRIGGER Register Definitions */
Kojto 112:6f327212ef96 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 112:6f327212ef96 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 112:6f327212ef96 986
Kojto 112:6f327212ef96 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 112:6f327212ef96 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 112:6f327212ef96 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 112:6f327212ef96 990
Kojto 112:6f327212ef96 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 112:6f327212ef96 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 112:6f327212ef96 993
Kojto 112:6f327212ef96 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 112:6f327212ef96 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 112:6f327212ef96 996
Kojto 112:6f327212ef96 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 112:6f327212ef96 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 112:6f327212ef96 999
Kojto 112:6f327212ef96 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 112:6f327212ef96 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 112:6f327212ef96 1002
Kojto 112:6f327212ef96 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 112:6f327212ef96 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 112:6f327212ef96 1005
Kojto 112:6f327212ef96 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 112:6f327212ef96 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 112:6f327212ef96 1008
Kojto 112:6f327212ef96 1009 /* TPI ITATBCTR2 Register Definitions */
Kojto 112:6f327212ef96 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 112:6f327212ef96 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 112:6f327212ef96 1012
Kojto 112:6f327212ef96 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 112:6f327212ef96 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 112:6f327212ef96 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 112:6f327212ef96 1016
Kojto 112:6f327212ef96 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 112:6f327212ef96 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 112:6f327212ef96 1019
Kojto 112:6f327212ef96 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 112:6f327212ef96 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 112:6f327212ef96 1022
Kojto 112:6f327212ef96 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 112:6f327212ef96 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 112:6f327212ef96 1025
Kojto 112:6f327212ef96 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 112:6f327212ef96 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 112:6f327212ef96 1028
Kojto 112:6f327212ef96 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 112:6f327212ef96 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 112:6f327212ef96 1031
Kojto 112:6f327212ef96 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 112:6f327212ef96 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 112:6f327212ef96 1034
Kojto 112:6f327212ef96 1035 /* TPI ITATBCTR0 Register Definitions */
Kojto 112:6f327212ef96 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 112:6f327212ef96 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 112:6f327212ef96 1038
Kojto 112:6f327212ef96 1039 /* TPI Integration Mode Control Register Definitions */
Kojto 112:6f327212ef96 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 112:6f327212ef96 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 112:6f327212ef96 1042
Kojto 112:6f327212ef96 1043 /* TPI DEVID Register Definitions */
Kojto 112:6f327212ef96 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 112:6f327212ef96 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 112:6f327212ef96 1046
Kojto 112:6f327212ef96 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 112:6f327212ef96 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 112:6f327212ef96 1049
Kojto 112:6f327212ef96 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 112:6f327212ef96 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 112:6f327212ef96 1052
Kojto 112:6f327212ef96 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 112:6f327212ef96 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 112:6f327212ef96 1055
Kojto 112:6f327212ef96 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 112:6f327212ef96 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 112:6f327212ef96 1058
Kojto 112:6f327212ef96 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 112:6f327212ef96 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 112:6f327212ef96 1061
Kojto 112:6f327212ef96 1062 /* TPI DEVTYPE Register Definitions */
Kojto 112:6f327212ef96 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 112:6f327212ef96 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 112:6f327212ef96 1065
Kojto 112:6f327212ef96 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 112:6f327212ef96 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 112:6f327212ef96 1068
Kojto 112:6f327212ef96 1069 /*@}*/ /* end of group CMSIS_TPI */
Kojto 112:6f327212ef96 1070
Kojto 112:6f327212ef96 1071
Kojto 112:6f327212ef96 1072 #if (__MPU_PRESENT == 1)
Kojto 112:6f327212ef96 1073 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 112:6f327212ef96 1075 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 112:6f327212ef96 1076 @{
Kojto 112:6f327212ef96 1077 */
Kojto 112:6f327212ef96 1078
Kojto 112:6f327212ef96 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 112:6f327212ef96 1080 */
Kojto 112:6f327212ef96 1081 typedef struct
Kojto 112:6f327212ef96 1082 {
Kojto 112:6f327212ef96 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 112:6f327212ef96 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 112:6f327212ef96 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 112:6f327212ef96 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 112:6f327212ef96 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 112:6f327212ef96 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 112:6f327212ef96 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 112:6f327212ef96 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 112:6f327212ef96 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 112:6f327212ef96 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 112:6f327212ef96 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 112:6f327212ef96 1094 } MPU_Type;
Kojto 112:6f327212ef96 1095
Kojto 112:6f327212ef96 1096 /* MPU Type Register */
Kojto 112:6f327212ef96 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 112:6f327212ef96 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 112:6f327212ef96 1099
Kojto 112:6f327212ef96 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 112:6f327212ef96 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 112:6f327212ef96 1102
Kojto 112:6f327212ef96 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 112:6f327212ef96 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 112:6f327212ef96 1105
Kojto 112:6f327212ef96 1106 /* MPU Control Register */
Kojto 112:6f327212ef96 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 112:6f327212ef96 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 112:6f327212ef96 1109
Kojto 112:6f327212ef96 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 112:6f327212ef96 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 112:6f327212ef96 1112
Kojto 112:6f327212ef96 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 112:6f327212ef96 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 112:6f327212ef96 1115
Kojto 112:6f327212ef96 1116 /* MPU Region Number Register */
Kojto 112:6f327212ef96 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 112:6f327212ef96 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 112:6f327212ef96 1119
Kojto 112:6f327212ef96 1120 /* MPU Region Base Address Register */
Kojto 112:6f327212ef96 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 112:6f327212ef96 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 112:6f327212ef96 1123
Kojto 112:6f327212ef96 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 112:6f327212ef96 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 112:6f327212ef96 1126
Kojto 112:6f327212ef96 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 112:6f327212ef96 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 112:6f327212ef96 1129
Kojto 112:6f327212ef96 1130 /* MPU Region Attribute and Size Register */
Kojto 112:6f327212ef96 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 112:6f327212ef96 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 112:6f327212ef96 1133
Kojto 112:6f327212ef96 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 112:6f327212ef96 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 112:6f327212ef96 1136
Kojto 112:6f327212ef96 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 112:6f327212ef96 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 112:6f327212ef96 1139
Kojto 112:6f327212ef96 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 112:6f327212ef96 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 112:6f327212ef96 1142
Kojto 112:6f327212ef96 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 112:6f327212ef96 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 112:6f327212ef96 1145
Kojto 112:6f327212ef96 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 112:6f327212ef96 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 112:6f327212ef96 1148
Kojto 112:6f327212ef96 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 112:6f327212ef96 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 112:6f327212ef96 1151
Kojto 112:6f327212ef96 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 112:6f327212ef96 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 112:6f327212ef96 1154
Kojto 112:6f327212ef96 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 112:6f327212ef96 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 112:6f327212ef96 1157
Kojto 112:6f327212ef96 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 112:6f327212ef96 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 112:6f327212ef96 1160
Kojto 112:6f327212ef96 1161 /*@} end of group CMSIS_MPU */
Kojto 112:6f327212ef96 1162 #endif
Kojto 112:6f327212ef96 1163
Kojto 112:6f327212ef96 1164
Kojto 112:6f327212ef96 1165 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 112:6f327212ef96 1167 \brief Type definitions for the Core Debug Registers
Kojto 112:6f327212ef96 1168 @{
Kojto 112:6f327212ef96 1169 */
Kojto 112:6f327212ef96 1170
Kojto 112:6f327212ef96 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 112:6f327212ef96 1172 */
Kojto 112:6f327212ef96 1173 typedef struct
Kojto 112:6f327212ef96 1174 {
Kojto 112:6f327212ef96 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 112:6f327212ef96 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 112:6f327212ef96 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 112:6f327212ef96 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 112:6f327212ef96 1179 } CoreDebug_Type;
Kojto 112:6f327212ef96 1180
Kojto 112:6f327212ef96 1181 /* Debug Halting Control and Status Register */
Kojto 112:6f327212ef96 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 112:6f327212ef96 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 112:6f327212ef96 1184
Kojto 112:6f327212ef96 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 112:6f327212ef96 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 112:6f327212ef96 1187
Kojto 112:6f327212ef96 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 112:6f327212ef96 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 112:6f327212ef96 1190
Kojto 112:6f327212ef96 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 112:6f327212ef96 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 112:6f327212ef96 1193
Kojto 112:6f327212ef96 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 112:6f327212ef96 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 112:6f327212ef96 1196
Kojto 112:6f327212ef96 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 112:6f327212ef96 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 112:6f327212ef96 1199
Kojto 112:6f327212ef96 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 112:6f327212ef96 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 112:6f327212ef96 1202
Kojto 112:6f327212ef96 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 112:6f327212ef96 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 112:6f327212ef96 1205
Kojto 112:6f327212ef96 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 112:6f327212ef96 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 112:6f327212ef96 1208
Kojto 112:6f327212ef96 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 112:6f327212ef96 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 112:6f327212ef96 1211
Kojto 112:6f327212ef96 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 112:6f327212ef96 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 112:6f327212ef96 1214
Kojto 112:6f327212ef96 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 112:6f327212ef96 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 112:6f327212ef96 1217
Kojto 112:6f327212ef96 1218 /* Debug Core Register Selector Register */
Kojto 112:6f327212ef96 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 112:6f327212ef96 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 112:6f327212ef96 1221
Kojto 112:6f327212ef96 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 112:6f327212ef96 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 112:6f327212ef96 1224
Kojto 112:6f327212ef96 1225 /* Debug Exception and Monitor Control Register */
Kojto 112:6f327212ef96 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 112:6f327212ef96 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 112:6f327212ef96 1228
Kojto 112:6f327212ef96 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 112:6f327212ef96 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 112:6f327212ef96 1231
Kojto 112:6f327212ef96 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 112:6f327212ef96 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 112:6f327212ef96 1234
Kojto 112:6f327212ef96 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 112:6f327212ef96 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 112:6f327212ef96 1237
Kojto 112:6f327212ef96 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 112:6f327212ef96 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 112:6f327212ef96 1240
Kojto 112:6f327212ef96 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 112:6f327212ef96 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 112:6f327212ef96 1243
Kojto 112:6f327212ef96 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 112:6f327212ef96 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 112:6f327212ef96 1246
Kojto 112:6f327212ef96 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 112:6f327212ef96 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 112:6f327212ef96 1249
Kojto 112:6f327212ef96 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 112:6f327212ef96 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 112:6f327212ef96 1252
Kojto 112:6f327212ef96 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 112:6f327212ef96 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 112:6f327212ef96 1255
Kojto 112:6f327212ef96 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 112:6f327212ef96 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 112:6f327212ef96 1258
Kojto 112:6f327212ef96 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 112:6f327212ef96 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 112:6f327212ef96 1261
Kojto 112:6f327212ef96 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 112:6f327212ef96 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 112:6f327212ef96 1264
Kojto 112:6f327212ef96 1265 /*@} end of group CMSIS_CoreDebug */
Kojto 112:6f327212ef96 1266
Kojto 112:6f327212ef96 1267
Kojto 112:6f327212ef96 1268 /** \ingroup CMSIS_core_register
Kojto 112:6f327212ef96 1269 \defgroup CMSIS_core_base Core Definitions
Kojto 112:6f327212ef96 1270 \brief Definitions for base addresses, unions, and structures.
Kojto 112:6f327212ef96 1271 @{
Kojto 112:6f327212ef96 1272 */
Kojto 112:6f327212ef96 1273
Kojto 112:6f327212ef96 1274 /* Memory mapping of Cortex-M3 Hardware */
Kojto 112:6f327212ef96 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 112:6f327212ef96 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 112:6f327212ef96 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 112:6f327212ef96 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 112:6f327212ef96 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 112:6f327212ef96 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 112:6f327212ef96 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 112:6f327212ef96 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 112:6f327212ef96 1283
Kojto 112:6f327212ef96 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 112:6f327212ef96 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 112:6f327212ef96 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 112:6f327212ef96 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 112:6f327212ef96 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 112:6f327212ef96 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 112:6f327212ef96 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 112:6f327212ef96 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 112:6f327212ef96 1292
Kojto 112:6f327212ef96 1293 #if (__MPU_PRESENT == 1)
Kojto 112:6f327212ef96 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 112:6f327212ef96 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 112:6f327212ef96 1296 #endif
Kojto 112:6f327212ef96 1297
Kojto 112:6f327212ef96 1298 /*@} */
Kojto 112:6f327212ef96 1299
Kojto 112:6f327212ef96 1300
Kojto 112:6f327212ef96 1301
Kojto 112:6f327212ef96 1302 /*******************************************************************************
Kojto 112:6f327212ef96 1303 * Hardware Abstraction Layer
Kojto 112:6f327212ef96 1304 Core Function Interface contains:
Kojto 112:6f327212ef96 1305 - Core NVIC Functions
Kojto 112:6f327212ef96 1306 - Core SysTick Functions
Kojto 112:6f327212ef96 1307 - Core Debug Functions
Kojto 112:6f327212ef96 1308 - Core Register Access Functions
Kojto 112:6f327212ef96 1309 ******************************************************************************/
Kojto 112:6f327212ef96 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 112:6f327212ef96 1311 */
Kojto 112:6f327212ef96 1312
Kojto 112:6f327212ef96 1313
Kojto 112:6f327212ef96 1314
Kojto 112:6f327212ef96 1315 /* ########################## NVIC functions #################################### */
Kojto 112:6f327212ef96 1316 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 112:6f327212ef96 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 112:6f327212ef96 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 112:6f327212ef96 1319 @{
Kojto 112:6f327212ef96 1320 */
Kojto 112:6f327212ef96 1321
Kojto 112:6f327212ef96 1322 /** \brief Set Priority Grouping
Kojto 112:6f327212ef96 1323
Kojto 112:6f327212ef96 1324 The function sets the priority grouping field using the required unlock sequence.
Kojto 112:6f327212ef96 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 112:6f327212ef96 1326 Only values from 0..7 are used.
Kojto 112:6f327212ef96 1327 In case of a conflict between priority grouping and available
Kojto 112:6f327212ef96 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 112:6f327212ef96 1329
Kojto 112:6f327212ef96 1330 \param [in] PriorityGroup Priority grouping field.
Kojto 112:6f327212ef96 1331 */
Kojto 112:6f327212ef96 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 112:6f327212ef96 1333 {
Kojto 112:6f327212ef96 1334 uint32_t reg_value;
Kojto 112:6f327212ef96 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 112:6f327212ef96 1336
Kojto 112:6f327212ef96 1337 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 112:6f327212ef96 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 112:6f327212ef96 1339 reg_value = (reg_value |
Kojto 112:6f327212ef96 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 112:6f327212ef96 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto 112:6f327212ef96 1342 SCB->AIRCR = reg_value;
Kojto 112:6f327212ef96 1343 }
Kojto 112:6f327212ef96 1344
Kojto 112:6f327212ef96 1345
Kojto 112:6f327212ef96 1346 /** \brief Get Priority Grouping
Kojto 112:6f327212ef96 1347
Kojto 112:6f327212ef96 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 112:6f327212ef96 1349
Kojto 112:6f327212ef96 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 112:6f327212ef96 1351 */
Kojto 112:6f327212ef96 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto 112:6f327212ef96 1353 {
Kojto 112:6f327212ef96 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 112:6f327212ef96 1355 }
Kojto 112:6f327212ef96 1356
Kojto 112:6f327212ef96 1357
Kojto 112:6f327212ef96 1358 /** \brief Enable External Interrupt
Kojto 112:6f327212ef96 1359
Kojto 112:6f327212ef96 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 112:6f327212ef96 1361
Kojto 112:6f327212ef96 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 112:6f327212ef96 1363 */
Kojto 112:6f327212ef96 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 112:6f327212ef96 1365 {
Kojto 112:6f327212ef96 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 112:6f327212ef96 1367 }
Kojto 112:6f327212ef96 1368
Kojto 112:6f327212ef96 1369
Kojto 112:6f327212ef96 1370 /** \brief Disable External Interrupt
Kojto 112:6f327212ef96 1371
Kojto 112:6f327212ef96 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 112:6f327212ef96 1373
Kojto 112:6f327212ef96 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 112:6f327212ef96 1375 */
Kojto 112:6f327212ef96 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 112:6f327212ef96 1377 {
Kojto 112:6f327212ef96 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1379 __DSB();
<> 131:faff56e089b2 1380 __ISB();
Kojto 112:6f327212ef96 1381 }
Kojto 112:6f327212ef96 1382
Kojto 112:6f327212ef96 1383
Kojto 112:6f327212ef96 1384 /** \brief Get Pending Interrupt
Kojto 112:6f327212ef96 1385
Kojto 112:6f327212ef96 1386 The function reads the pending register in the NVIC and returns the pending bit
Kojto 112:6f327212ef96 1387 for the specified interrupt.
Kojto 112:6f327212ef96 1388
Kojto 112:6f327212ef96 1389 \param [in] IRQn Interrupt number.
Kojto 112:6f327212ef96 1390
Kojto 112:6f327212ef96 1391 \return 0 Interrupt status is not pending.
Kojto 112:6f327212ef96 1392 \return 1 Interrupt status is pending.
Kojto 112:6f327212ef96 1393 */
Kojto 112:6f327212ef96 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 112:6f327212ef96 1395 {
Kojto 112:6f327212ef96 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 112:6f327212ef96 1397 }
Kojto 112:6f327212ef96 1398
Kojto 112:6f327212ef96 1399
Kojto 112:6f327212ef96 1400 /** \brief Set Pending Interrupt
Kojto 112:6f327212ef96 1401
Kojto 112:6f327212ef96 1402 The function sets the pending bit of an external interrupt.
Kojto 112:6f327212ef96 1403
Kojto 112:6f327212ef96 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 112:6f327212ef96 1405 */
Kojto 112:6f327212ef96 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 112:6f327212ef96 1407 {
Kojto 112:6f327212ef96 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 112:6f327212ef96 1409 }
Kojto 112:6f327212ef96 1410
Kojto 112:6f327212ef96 1411
Kojto 112:6f327212ef96 1412 /** \brief Clear Pending Interrupt
Kojto 112:6f327212ef96 1413
Kojto 112:6f327212ef96 1414 The function clears the pending bit of an external interrupt.
Kojto 112:6f327212ef96 1415
Kojto 112:6f327212ef96 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 112:6f327212ef96 1417 */
Kojto 112:6f327212ef96 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 112:6f327212ef96 1419 {
Kojto 112:6f327212ef96 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 112:6f327212ef96 1421 }
Kojto 112:6f327212ef96 1422
Kojto 112:6f327212ef96 1423
Kojto 112:6f327212ef96 1424 /** \brief Get Active Interrupt
Kojto 112:6f327212ef96 1425
Kojto 112:6f327212ef96 1426 The function reads the active register in NVIC and returns the active bit.
Kojto 112:6f327212ef96 1427
Kojto 112:6f327212ef96 1428 \param [in] IRQn Interrupt number.
Kojto 112:6f327212ef96 1429
Kojto 112:6f327212ef96 1430 \return 0 Interrupt status is not active.
Kojto 112:6f327212ef96 1431 \return 1 Interrupt status is active.
Kojto 112:6f327212ef96 1432 */
Kojto 112:6f327212ef96 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto 112:6f327212ef96 1434 {
Kojto 112:6f327212ef96 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 112:6f327212ef96 1436 }
Kojto 112:6f327212ef96 1437
Kojto 112:6f327212ef96 1438
Kojto 112:6f327212ef96 1439 /** \brief Set Interrupt Priority
Kojto 112:6f327212ef96 1440
Kojto 112:6f327212ef96 1441 The function sets the priority of an interrupt.
Kojto 112:6f327212ef96 1442
Kojto 112:6f327212ef96 1443 \note The priority cannot be set for every core interrupt.
Kojto 112:6f327212ef96 1444
Kojto 112:6f327212ef96 1445 \param [in] IRQn Interrupt number.
Kojto 112:6f327212ef96 1446 \param [in] priority Priority to set.
Kojto 112:6f327212ef96 1447 */
Kojto 112:6f327212ef96 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 112:6f327212ef96 1449 {
Kojto 112:6f327212ef96 1450 if((int32_t)IRQn < 0) {
Kojto 112:6f327212ef96 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 112:6f327212ef96 1452 }
Kojto 112:6f327212ef96 1453 else {
Kojto 112:6f327212ef96 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 112:6f327212ef96 1455 }
Kojto 112:6f327212ef96 1456 }
Kojto 112:6f327212ef96 1457
Kojto 112:6f327212ef96 1458
Kojto 112:6f327212ef96 1459 /** \brief Get Interrupt Priority
Kojto 112:6f327212ef96 1460
Kojto 112:6f327212ef96 1461 The function reads the priority of an interrupt. The interrupt
Kojto 112:6f327212ef96 1462 number can be positive to specify an external (device specific)
Kojto 112:6f327212ef96 1463 interrupt, or negative to specify an internal (core) interrupt.
Kojto 112:6f327212ef96 1464
Kojto 112:6f327212ef96 1465
Kojto 112:6f327212ef96 1466 \param [in] IRQn Interrupt number.
Kojto 112:6f327212ef96 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 112:6f327212ef96 1468 priority bits of the microcontroller.
Kojto 112:6f327212ef96 1469 */
Kojto 112:6f327212ef96 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 112:6f327212ef96 1471 {
Kojto 112:6f327212ef96 1472
Kojto 112:6f327212ef96 1473 if((int32_t)IRQn < 0) {
Kojto 112:6f327212ef96 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 112:6f327212ef96 1475 }
Kojto 112:6f327212ef96 1476 else {
Kojto 112:6f327212ef96 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 112:6f327212ef96 1478 }
Kojto 112:6f327212ef96 1479 }
Kojto 112:6f327212ef96 1480
Kojto 112:6f327212ef96 1481
Kojto 112:6f327212ef96 1482 /** \brief Encode Priority
Kojto 112:6f327212ef96 1483
Kojto 112:6f327212ef96 1484 The function encodes the priority for an interrupt with the given priority group,
Kojto 112:6f327212ef96 1485 preemptive priority value, and subpriority value.
Kojto 112:6f327212ef96 1486 In case of a conflict between priority grouping and available
Kojto 112:6f327212ef96 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 112:6f327212ef96 1488
Kojto 112:6f327212ef96 1489 \param [in] PriorityGroup Used priority group.
Kojto 112:6f327212ef96 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 112:6f327212ef96 1491 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 112:6f327212ef96 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 112:6f327212ef96 1493 */
Kojto 112:6f327212ef96 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 112:6f327212ef96 1495 {
Kojto 112:6f327212ef96 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 112:6f327212ef96 1497 uint32_t PreemptPriorityBits;
Kojto 112:6f327212ef96 1498 uint32_t SubPriorityBits;
Kojto 112:6f327212ef96 1499
Kojto 112:6f327212ef96 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 112:6f327212ef96 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 112:6f327212ef96 1502
Kojto 112:6f327212ef96 1503 return (
Kojto 112:6f327212ef96 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 112:6f327212ef96 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 112:6f327212ef96 1506 );
Kojto 112:6f327212ef96 1507 }
Kojto 112:6f327212ef96 1508
Kojto 112:6f327212ef96 1509
Kojto 112:6f327212ef96 1510 /** \brief Decode Priority
Kojto 112:6f327212ef96 1511
Kojto 112:6f327212ef96 1512 The function decodes an interrupt priority value with a given priority group to
Kojto 112:6f327212ef96 1513 preemptive priority value and subpriority value.
Kojto 112:6f327212ef96 1514 In case of a conflict between priority grouping and available
Kojto 112:6f327212ef96 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 112:6f327212ef96 1516
Kojto 112:6f327212ef96 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 112:6f327212ef96 1518 \param [in] PriorityGroup Used priority group.
Kojto 112:6f327212ef96 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 112:6f327212ef96 1520 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 112:6f327212ef96 1521 */
Kojto 112:6f327212ef96 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 112:6f327212ef96 1523 {
Kojto 112:6f327212ef96 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 112:6f327212ef96 1525 uint32_t PreemptPriorityBits;
Kojto 112:6f327212ef96 1526 uint32_t SubPriorityBits;
Kojto 112:6f327212ef96 1527
Kojto 112:6f327212ef96 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 112:6f327212ef96 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 112:6f327212ef96 1530
Kojto 112:6f327212ef96 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 112:6f327212ef96 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 112:6f327212ef96 1533 }
Kojto 112:6f327212ef96 1534
Kojto 112:6f327212ef96 1535
Kojto 112:6f327212ef96 1536 /** \brief System Reset
Kojto 112:6f327212ef96 1537
Kojto 112:6f327212ef96 1538 The function initiates a system reset request to reset the MCU.
Kojto 112:6f327212ef96 1539 */
Kojto 112:6f327212ef96 1540 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 112:6f327212ef96 1541 {
Kojto 112:6f327212ef96 1542 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 112:6f327212ef96 1543 buffered write are completed before reset */
Kojto 112:6f327212ef96 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 112:6f327212ef96 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 112:6f327212ef96 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 112:6f327212ef96 1547 __DSB(); /* Ensure completion of memory access */
Kojto 112:6f327212ef96 1548 while(1) { __NOP(); } /* wait until reset */
Kojto 112:6f327212ef96 1549 }
Kojto 112:6f327212ef96 1550
Kojto 112:6f327212ef96 1551 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 112:6f327212ef96 1552
Kojto 112:6f327212ef96 1553
Kojto 112:6f327212ef96 1554
Kojto 112:6f327212ef96 1555 /* ################################## SysTick function ############################################ */
Kojto 112:6f327212ef96 1556 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 112:6f327212ef96 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 112:6f327212ef96 1558 \brief Functions that configure the System.
Kojto 112:6f327212ef96 1559 @{
Kojto 112:6f327212ef96 1560 */
Kojto 112:6f327212ef96 1561
Kojto 112:6f327212ef96 1562 #if (__Vendor_SysTickConfig == 0)
Kojto 112:6f327212ef96 1563
Kojto 112:6f327212ef96 1564 /** \brief System Tick Configuration
Kojto 112:6f327212ef96 1565
Kojto 112:6f327212ef96 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 112:6f327212ef96 1567 Counter is in free running mode to generate periodic interrupts.
Kojto 112:6f327212ef96 1568
Kojto 112:6f327212ef96 1569 \param [in] ticks Number of ticks between two interrupts.
Kojto 112:6f327212ef96 1570
Kojto 112:6f327212ef96 1571 \return 0 Function succeeded.
Kojto 112:6f327212ef96 1572 \return 1 Function failed.
Kojto 112:6f327212ef96 1573
Kojto 112:6f327212ef96 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 112:6f327212ef96 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 112:6f327212ef96 1576 must contain a vendor-specific implementation of this function.
Kojto 112:6f327212ef96 1577
Kojto 112:6f327212ef96 1578 */
Kojto 112:6f327212ef96 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 112:6f327212ef96 1580 {
Kojto 112:6f327212ef96 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 112:6f327212ef96 1582
Kojto 112:6f327212ef96 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 112:6f327212ef96 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 112:6f327212ef96 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 112:6f327212ef96 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 112:6f327212ef96 1587 SysTick_CTRL_TICKINT_Msk |
Kojto 112:6f327212ef96 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 112:6f327212ef96 1589 return (0UL); /* Function successful */
Kojto 112:6f327212ef96 1590 }
Kojto 112:6f327212ef96 1591
Kojto 112:6f327212ef96 1592 #endif
Kojto 112:6f327212ef96 1593
Kojto 112:6f327212ef96 1594 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 112:6f327212ef96 1595
Kojto 112:6f327212ef96 1596
Kojto 112:6f327212ef96 1597
Kojto 112:6f327212ef96 1598 /* ##################################### Debug In/Output function ########################################### */
Kojto 112:6f327212ef96 1599 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 112:6f327212ef96 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 112:6f327212ef96 1601 \brief Functions that access the ITM debug interface.
Kojto 112:6f327212ef96 1602 @{
Kojto 112:6f327212ef96 1603 */
Kojto 112:6f327212ef96 1604
Kojto 112:6f327212ef96 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 112:6f327212ef96 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 112:6f327212ef96 1607
Kojto 112:6f327212ef96 1608
Kojto 112:6f327212ef96 1609 /** \brief ITM Send Character
Kojto 112:6f327212ef96 1610
Kojto 112:6f327212ef96 1611 The function transmits a character via the ITM channel 0, and
Kojto 112:6f327212ef96 1612 \li Just returns when no debugger is connected that has booked the output.
Kojto 112:6f327212ef96 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 112:6f327212ef96 1614
Kojto 112:6f327212ef96 1615 \param [in] ch Character to transmit.
Kojto 112:6f327212ef96 1616
Kojto 112:6f327212ef96 1617 \returns Character to transmit.
Kojto 112:6f327212ef96 1618 */
Kojto 112:6f327212ef96 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 112:6f327212ef96 1620 {
Kojto 112:6f327212ef96 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 112:6f327212ef96 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 112:6f327212ef96 1623 {
Kojto 112:6f327212ef96 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 112:6f327212ef96 1625 ITM->PORT[0].u8 = (uint8_t)ch;
Kojto 112:6f327212ef96 1626 }
Kojto 112:6f327212ef96 1627 return (ch);
Kojto 112:6f327212ef96 1628 }
Kojto 112:6f327212ef96 1629
Kojto 112:6f327212ef96 1630
Kojto 112:6f327212ef96 1631 /** \brief ITM Receive Character
Kojto 112:6f327212ef96 1632
Kojto 112:6f327212ef96 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 112:6f327212ef96 1634
Kojto 112:6f327212ef96 1635 \return Received character.
Kojto 112:6f327212ef96 1636 \return -1 No character pending.
Kojto 112:6f327212ef96 1637 */
Kojto 112:6f327212ef96 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 112:6f327212ef96 1639 int32_t ch = -1; /* no character available */
Kojto 112:6f327212ef96 1640
Kojto 112:6f327212ef96 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 112:6f327212ef96 1642 ch = ITM_RxBuffer;
Kojto 112:6f327212ef96 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 112:6f327212ef96 1644 }
Kojto 112:6f327212ef96 1645
Kojto 112:6f327212ef96 1646 return (ch);
Kojto 112:6f327212ef96 1647 }
Kojto 112:6f327212ef96 1648
Kojto 112:6f327212ef96 1649
Kojto 112:6f327212ef96 1650 /** \brief ITM Check Character
Kojto 112:6f327212ef96 1651
Kojto 112:6f327212ef96 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 112:6f327212ef96 1653
Kojto 112:6f327212ef96 1654 \return 0 No character available.
Kojto 112:6f327212ef96 1655 \return 1 Character available.
Kojto 112:6f327212ef96 1656 */
Kojto 112:6f327212ef96 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 112:6f327212ef96 1658
Kojto 112:6f327212ef96 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 112:6f327212ef96 1660 return (0); /* no character available */
Kojto 112:6f327212ef96 1661 } else {
Kojto 112:6f327212ef96 1662 return (1); /* character available */
Kojto 112:6f327212ef96 1663 }
Kojto 112:6f327212ef96 1664 }
Kojto 112:6f327212ef96 1665
Kojto 112:6f327212ef96 1666 /*@} end of CMSIS_core_DebugFunctions */
Kojto 112:6f327212ef96 1667
Kojto 112:6f327212ef96 1668
Kojto 112:6f327212ef96 1669
Kojto 112:6f327212ef96 1670
Kojto 112:6f327212ef96 1671 #ifdef __cplusplus
Kojto 112:6f327212ef96 1672 }
Kojto 112:6f327212ef96 1673 #endif
Kojto 112:6f327212ef96 1674
Kojto 112:6f327212ef96 1675 #endif /* __CORE_SC300_H_DEPENDANT */
Kojto 112:6f327212ef96 1676
Kojto 112:6f327212ef96 1677 #endif /* __CMSIS_GENERIC */