mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_MPS2_M4/core_cm0.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**************************************************************************//**
Kojto 101:7cff1c4259d7 2 * @file core_cm0.h
Kojto 101:7cff1c4259d7 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 101:7cff1c4259d7 6 *
Kojto 101:7cff1c4259d7 7 * @note
Kojto 101:7cff1c4259d7 8 *
Kojto 101:7cff1c4259d7 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 101:7cff1c4259d7 11
Kojto 101:7cff1c4259d7 12 All rights reserved.
Kojto 101:7cff1c4259d7 13 Redistribution and use in source and binary forms, with or without
Kojto 101:7cff1c4259d7 14 modification, are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 15 - Redistributions of source code must retain the above copyright
Kojto 101:7cff1c4259d7 16 notice, this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 101:7cff1c4259d7 18 notice, this list of conditions and the following disclaimer in the
Kojto 101:7cff1c4259d7 19 documentation and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 101:7cff1c4259d7 21 to endorse or promote products derived from this software without
Kojto 101:7cff1c4259d7 22 specific prior written permission.
Kojto 101:7cff1c4259d7 23 *
Kojto 101:7cff1c4259d7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 101:7cff1c4259d7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 101:7cff1c4259d7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 101:7cff1c4259d7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 101:7cff1c4259d7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 101:7cff1c4259d7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 101:7cff1c4259d7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 101:7cff1c4259d7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 101:7cff1c4259d7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 35 ---------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 #if defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 101:7cff1c4259d7 40 #endif
Kojto 101:7cff1c4259d7 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 101:7cff1c4259d7 45 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 46 extern "C" {
Kojto 101:7cff1c4259d7 47 #endif
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 101:7cff1c4259d7 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 101:7cff1c4259d7 51
Kojto 101:7cff1c4259d7 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 101:7cff1c4259d7 53 Function definitions in header files are used to allow 'inlining'.
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 101:7cff1c4259d7 56 Unions are used for effective representation of core registers.
Kojto 101:7cff1c4259d7 57
Kojto 101:7cff1c4259d7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 101:7cff1c4259d7 59 Function-like macros are used to allow more efficient code.
Kojto 101:7cff1c4259d7 60 */
Kojto 101:7cff1c4259d7 61
Kojto 101:7cff1c4259d7 62
Kojto 101:7cff1c4259d7 63 /*******************************************************************************
Kojto 101:7cff1c4259d7 64 * CMSIS definitions
Kojto 101:7cff1c4259d7 65 ******************************************************************************/
Kojto 101:7cff1c4259d7 66 /** \ingroup Cortex_M0
Kojto 101:7cff1c4259d7 67 @{
Kojto 101:7cff1c4259d7 68 */
Kojto 101:7cff1c4259d7 69
Kojto 101:7cff1c4259d7 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 101:7cff1c4259d7 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 101:7cff1c4259d7 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 101:7cff1c4259d7 75
Kojto 101:7cff1c4259d7 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 101:7cff1c4259d7 77
Kojto 101:7cff1c4259d7 78
Kojto 101:7cff1c4259d7 79 #if defined ( __CC_ARM )
Kojto 101:7cff1c4259d7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 101:7cff1c4259d7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 101:7cff1c4259d7 82 #define __STATIC_INLINE static __inline
Kojto 101:7cff1c4259d7 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 101:7cff1c4259d7 89 #elif defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 101:7cff1c4259d7 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 101:7cff1c4259d7 92 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 101:7cff1c4259d7 96 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 97
Kojto 101:7cff1c4259d7 98 #elif defined ( __TASKING__ )
Kojto 101:7cff1c4259d7 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 101:7cff1c4259d7 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 101:7cff1c4259d7 101 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 101:7cff1c4259d7 109 #endif
Kojto 101:7cff1c4259d7 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 101:7cff1c4259d7 113 */
Kojto 101:7cff1c4259d7 114 #define __FPU_USED 0
Kojto 101:7cff1c4259d7 115
Kojto 101:7cff1c4259d7 116 #if defined ( __CC_ARM )
Kojto 101:7cff1c4259d7 117 #if defined __TARGET_FPU_VFP
Kojto 101:7cff1c4259d7 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 119 #endif
Kojto 101:7cff1c4259d7 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 101:7cff1c4259d7 126 #elif defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 127 #if defined __ARMVFP__
Kojto 101:7cff1c4259d7 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 129 #endif
Kojto 101:7cff1c4259d7 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 101:7cff1c4259d7 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 134 #endif
Kojto 101:7cff1c4259d7 135
Kojto 101:7cff1c4259d7 136 #elif defined ( __TASKING__ )
Kojto 101:7cff1c4259d7 137 #if defined __FPU_VFP__
Kojto 101:7cff1c4259d7 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 101:7cff1c4259d7 145 #endif
Kojto 101:7cff1c4259d7 146
Kojto 101:7cff1c4259d7 147 #include <stdint.h> /* standard types definitions */
Kojto 101:7cff1c4259d7 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 101:7cff1c4259d7 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 101:7cff1c4259d7 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 101:7cff1c4259d7 155 #endif /* __CORE_CM0_H_GENERIC */
Kojto 101:7cff1c4259d7 156
Kojto 101:7cff1c4259d7 157 #ifndef __CMSIS_GENERIC
Kojto 101:7cff1c4259d7 158
Kojto 101:7cff1c4259d7 159 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 101:7cff1c4259d7 160 #define __CORE_CM0_H_DEPENDANT
Kojto 101:7cff1c4259d7 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 101:7cff1c4259d7 166 /* check device defines and use defaults */
Kojto 101:7cff1c4259d7 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 101:7cff1c4259d7 168 #ifndef __CM0_REV
Kojto 101:7cff1c4259d7 169 #define __CM0_REV 0x0000
Kojto 101:7cff1c4259d7 170 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 171 #endif
Kojto 101:7cff1c4259d7 172
Kojto 101:7cff1c4259d7 173 #ifndef __NVIC_PRIO_BITS
Kojto 101:7cff1c4259d7 174 #define __NVIC_PRIO_BITS 2
Kojto 101:7cff1c4259d7 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 176 #endif
Kojto 101:7cff1c4259d7 177
Kojto 101:7cff1c4259d7 178 #ifndef __Vendor_SysTickConfig
Kojto 101:7cff1c4259d7 179 #define __Vendor_SysTickConfig 0
Kojto 101:7cff1c4259d7 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 181 #endif
Kojto 101:7cff1c4259d7 182 #endif
Kojto 101:7cff1c4259d7 183
Kojto 101:7cff1c4259d7 184 /* IO definitions (access restrictions to peripheral registers) */
Kojto 101:7cff1c4259d7 185 /**
Kojto 101:7cff1c4259d7 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 101:7cff1c4259d7 187
Kojto 101:7cff1c4259d7 188 <strong>IO Type Qualifiers</strong> are used
Kojto 101:7cff1c4259d7 189 \li to specify the access to peripheral variables.
Kojto 101:7cff1c4259d7 190 \li for automatic generation of peripheral register debug information.
Kojto 101:7cff1c4259d7 191 */
Kojto 101:7cff1c4259d7 192 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 193 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 101:7cff1c4259d7 194 #else
Kojto 101:7cff1c4259d7 195 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 101:7cff1c4259d7 196 #endif
Kojto 101:7cff1c4259d7 197 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 101:7cff1c4259d7 198 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 101:7cff1c4259d7 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
Kojto 101:7cff1c4259d7 208 /*@} end of group Cortex_M0 */
Kojto 101:7cff1c4259d7 209
Kojto 101:7cff1c4259d7 210
Kojto 101:7cff1c4259d7 211
Kojto 101:7cff1c4259d7 212 /*******************************************************************************
Kojto 101:7cff1c4259d7 213 * Register Abstraction
Kojto 101:7cff1c4259d7 214 Core Register contain:
Kojto 101:7cff1c4259d7 215 - Core Register
Kojto 101:7cff1c4259d7 216 - Core NVIC Register
Kojto 101:7cff1c4259d7 217 - Core SCB Register
Kojto 101:7cff1c4259d7 218 - Core SysTick Register
Kojto 101:7cff1c4259d7 219 ******************************************************************************/
Kojto 101:7cff1c4259d7 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 101:7cff1c4259d7 221 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 101:7cff1c4259d7 222 */
Kojto 101:7cff1c4259d7 223
Kojto 101:7cff1c4259d7 224 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 225 \defgroup CMSIS_CORE Status and Control Registers
Kojto 101:7cff1c4259d7 226 \brief Core Register type definitions.
Kojto 101:7cff1c4259d7 227 @{
Kojto 101:7cff1c4259d7 228 */
Kojto 101:7cff1c4259d7 229
Kojto 101:7cff1c4259d7 230 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 101:7cff1c4259d7 231 */
Kojto 101:7cff1c4259d7 232 typedef union
Kojto 101:7cff1c4259d7 233 {
Kojto 101:7cff1c4259d7 234 struct
Kojto 101:7cff1c4259d7 235 {
Kojto 110:165afa46840b 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 101:7cff1c4259d7 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 101:7cff1c4259d7 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 101:7cff1c4259d7 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 101:7cff1c4259d7 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 101:7cff1c4259d7 241 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 242 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 243 } APSR_Type;
Kojto 101:7cff1c4259d7 244
Kojto 110:165afa46840b 245 /* APSR Register Definitions */
Kojto 110:165afa46840b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 248
Kojto 110:165afa46840b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 257
Kojto 101:7cff1c4259d7 258
Kojto 101:7cff1c4259d7 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 101:7cff1c4259d7 260 */
Kojto 101:7cff1c4259d7 261 typedef union
Kojto 101:7cff1c4259d7 262 {
Kojto 101:7cff1c4259d7 263 struct
Kojto 101:7cff1c4259d7 264 {
Kojto 101:7cff1c4259d7 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 101:7cff1c4259d7 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 101:7cff1c4259d7 267 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 268 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 269 } IPSR_Type;
Kojto 101:7cff1c4259d7 270
Kojto 110:165afa46840b 271 /* IPSR Register Definitions */
Kojto 110:165afa46840b 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 274
Kojto 101:7cff1c4259d7 275
Kojto 101:7cff1c4259d7 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 101:7cff1c4259d7 277 */
Kojto 101:7cff1c4259d7 278 typedef union
Kojto 101:7cff1c4259d7 279 {
Kojto 101:7cff1c4259d7 280 struct
Kojto 101:7cff1c4259d7 281 {
Kojto 101:7cff1c4259d7 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 101:7cff1c4259d7 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 101:7cff1c4259d7 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 101:7cff1c4259d7 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 101:7cff1c4259d7 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 101:7cff1c4259d7 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 101:7cff1c4259d7 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 101:7cff1c4259d7 290 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 291 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 292 } xPSR_Type;
Kojto 101:7cff1c4259d7 293
Kojto 110:165afa46840b 294 /* xPSR Register Definitions */
Kojto 110:165afa46840b 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 297
Kojto 110:165afa46840b 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 312
Kojto 101:7cff1c4259d7 313
Kojto 101:7cff1c4259d7 314 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 101:7cff1c4259d7 315 */
Kojto 101:7cff1c4259d7 316 typedef union
Kojto 101:7cff1c4259d7 317 {
Kojto 101:7cff1c4259d7 318 struct
Kojto 101:7cff1c4259d7 319 {
Kojto 110:165afa46840b 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Kojto 101:7cff1c4259d7 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 101:7cff1c4259d7 323 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 324 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 325 } CONTROL_Type;
Kojto 101:7cff1c4259d7 326
Kojto 110:165afa46840b 327 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 330
Kojto 101:7cff1c4259d7 331 /*@} end of group CMSIS_CORE */
Kojto 101:7cff1c4259d7 332
Kojto 101:7cff1c4259d7 333
Kojto 101:7cff1c4259d7 334 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 101:7cff1c4259d7 336 \brief Type definitions for the NVIC Registers
Kojto 101:7cff1c4259d7 337 @{
Kojto 101:7cff1c4259d7 338 */
Kojto 101:7cff1c4259d7 339
Kojto 101:7cff1c4259d7 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 101:7cff1c4259d7 341 */
Kojto 101:7cff1c4259d7 342 typedef struct
Kojto 101:7cff1c4259d7 343 {
Kojto 101:7cff1c4259d7 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 101:7cff1c4259d7 345 uint32_t RESERVED0[31];
Kojto 101:7cff1c4259d7 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 101:7cff1c4259d7 347 uint32_t RSERVED1[31];
Kojto 101:7cff1c4259d7 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 101:7cff1c4259d7 349 uint32_t RESERVED2[31];
Kojto 101:7cff1c4259d7 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 101:7cff1c4259d7 351 uint32_t RESERVED3[31];
Kojto 101:7cff1c4259d7 352 uint32_t RESERVED4[64];
Kojto 101:7cff1c4259d7 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 101:7cff1c4259d7 354 } NVIC_Type;
Kojto 101:7cff1c4259d7 355
Kojto 101:7cff1c4259d7 356 /*@} end of group CMSIS_NVIC */
Kojto 101:7cff1c4259d7 357
Kojto 101:7cff1c4259d7 358
Kojto 101:7cff1c4259d7 359 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 360 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 101:7cff1c4259d7 361 \brief Type definitions for the System Control Block Registers
Kojto 101:7cff1c4259d7 362 @{
Kojto 101:7cff1c4259d7 363 */
Kojto 101:7cff1c4259d7 364
Kojto 101:7cff1c4259d7 365 /** \brief Structure type to access the System Control Block (SCB).
Kojto 101:7cff1c4259d7 366 */
Kojto 101:7cff1c4259d7 367 typedef struct
Kojto 101:7cff1c4259d7 368 {
Kojto 101:7cff1c4259d7 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 101:7cff1c4259d7 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 101:7cff1c4259d7 371 uint32_t RESERVED0;
Kojto 101:7cff1c4259d7 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 101:7cff1c4259d7 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 101:7cff1c4259d7 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 101:7cff1c4259d7 375 uint32_t RESERVED1;
Kojto 101:7cff1c4259d7 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 101:7cff1c4259d7 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 101:7cff1c4259d7 378 } SCB_Type;
Kojto 101:7cff1c4259d7 379
Kojto 101:7cff1c4259d7 380 /* SCB CPUID Register Definitions */
Kojto 101:7cff1c4259d7 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 101:7cff1c4259d7 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 101:7cff1c4259d7 383
Kojto 101:7cff1c4259d7 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 101:7cff1c4259d7 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 101:7cff1c4259d7 386
Kojto 101:7cff1c4259d7 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 101:7cff1c4259d7 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 101:7cff1c4259d7 389
Kojto 101:7cff1c4259d7 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 101:7cff1c4259d7 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 101:7cff1c4259d7 392
Kojto 101:7cff1c4259d7 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 101:7cff1c4259d7 395
Kojto 101:7cff1c4259d7 396 /* SCB Interrupt Control State Register Definitions */
Kojto 101:7cff1c4259d7 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 101:7cff1c4259d7 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 101:7cff1c4259d7 399
Kojto 101:7cff1c4259d7 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 101:7cff1c4259d7 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 101:7cff1c4259d7 402
Kojto 101:7cff1c4259d7 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 101:7cff1c4259d7 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 101:7cff1c4259d7 405
Kojto 101:7cff1c4259d7 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 101:7cff1c4259d7 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 101:7cff1c4259d7 408
Kojto 101:7cff1c4259d7 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 101:7cff1c4259d7 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 101:7cff1c4259d7 411
Kojto 101:7cff1c4259d7 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 101:7cff1c4259d7 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 101:7cff1c4259d7 414
Kojto 101:7cff1c4259d7 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 101:7cff1c4259d7 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 101:7cff1c4259d7 417
Kojto 101:7cff1c4259d7 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 101:7cff1c4259d7 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 101:7cff1c4259d7 420
Kojto 101:7cff1c4259d7 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 101:7cff1c4259d7 423
Kojto 101:7cff1c4259d7 424 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 101:7cff1c4259d7 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 101:7cff1c4259d7 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 101:7cff1c4259d7 427
Kojto 101:7cff1c4259d7 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 101:7cff1c4259d7 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 101:7cff1c4259d7 430
Kojto 101:7cff1c4259d7 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 101:7cff1c4259d7 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 101:7cff1c4259d7 433
Kojto 101:7cff1c4259d7 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 101:7cff1c4259d7 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 101:7cff1c4259d7 436
Kojto 101:7cff1c4259d7 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 101:7cff1c4259d7 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 101:7cff1c4259d7 439
Kojto 101:7cff1c4259d7 440 /* SCB System Control Register Definitions */
Kojto 101:7cff1c4259d7 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 101:7cff1c4259d7 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 101:7cff1c4259d7 443
Kojto 101:7cff1c4259d7 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 101:7cff1c4259d7 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 101:7cff1c4259d7 446
Kojto 101:7cff1c4259d7 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 101:7cff1c4259d7 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 101:7cff1c4259d7 449
Kojto 101:7cff1c4259d7 450 /* SCB Configuration Control Register Definitions */
Kojto 101:7cff1c4259d7 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 101:7cff1c4259d7 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 101:7cff1c4259d7 453
Kojto 101:7cff1c4259d7 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 101:7cff1c4259d7 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 101:7cff1c4259d7 456
Kojto 101:7cff1c4259d7 457 /* SCB System Handler Control and State Register Definitions */
Kojto 101:7cff1c4259d7 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 101:7cff1c4259d7 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 101:7cff1c4259d7 460
Kojto 101:7cff1c4259d7 461 /*@} end of group CMSIS_SCB */
Kojto 101:7cff1c4259d7 462
Kojto 101:7cff1c4259d7 463
Kojto 101:7cff1c4259d7 464 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 101:7cff1c4259d7 466 \brief Type definitions for the System Timer Registers.
Kojto 101:7cff1c4259d7 467 @{
Kojto 101:7cff1c4259d7 468 */
Kojto 101:7cff1c4259d7 469
Kojto 101:7cff1c4259d7 470 /** \brief Structure type to access the System Timer (SysTick).
Kojto 101:7cff1c4259d7 471 */
Kojto 101:7cff1c4259d7 472 typedef struct
Kojto 101:7cff1c4259d7 473 {
Kojto 101:7cff1c4259d7 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 101:7cff1c4259d7 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 101:7cff1c4259d7 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 101:7cff1c4259d7 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 101:7cff1c4259d7 478 } SysTick_Type;
Kojto 101:7cff1c4259d7 479
Kojto 101:7cff1c4259d7 480 /* SysTick Control / Status Register Definitions */
Kojto 101:7cff1c4259d7 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 101:7cff1c4259d7 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 101:7cff1c4259d7 483
Kojto 101:7cff1c4259d7 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 101:7cff1c4259d7 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 101:7cff1c4259d7 486
Kojto 101:7cff1c4259d7 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 101:7cff1c4259d7 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 101:7cff1c4259d7 489
Kojto 101:7cff1c4259d7 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 101:7cff1c4259d7 492
Kojto 101:7cff1c4259d7 493 /* SysTick Reload Register Definitions */
Kojto 101:7cff1c4259d7 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 101:7cff1c4259d7 496
Kojto 101:7cff1c4259d7 497 /* SysTick Current Register Definitions */
Kojto 101:7cff1c4259d7 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 101:7cff1c4259d7 500
Kojto 101:7cff1c4259d7 501 /* SysTick Calibration Register Definitions */
Kojto 101:7cff1c4259d7 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 101:7cff1c4259d7 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 101:7cff1c4259d7 504
Kojto 101:7cff1c4259d7 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 101:7cff1c4259d7 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 101:7cff1c4259d7 507
Kojto 101:7cff1c4259d7 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 101:7cff1c4259d7 510
Kojto 101:7cff1c4259d7 511 /*@} end of group CMSIS_SysTick */
Kojto 101:7cff1c4259d7 512
Kojto 101:7cff1c4259d7 513
Kojto 101:7cff1c4259d7 514 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 101:7cff1c4259d7 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 101:7cff1c4259d7 517 are only accessible over DAP and not via processor. Therefore
Kojto 101:7cff1c4259d7 518 they are not covered by the Cortex-M0 header file.
Kojto 101:7cff1c4259d7 519 @{
Kojto 101:7cff1c4259d7 520 */
Kojto 101:7cff1c4259d7 521 /*@} end of group CMSIS_CoreDebug */
Kojto 101:7cff1c4259d7 522
Kojto 101:7cff1c4259d7 523
Kojto 101:7cff1c4259d7 524 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 525 \defgroup CMSIS_core_base Core Definitions
Kojto 101:7cff1c4259d7 526 \brief Definitions for base addresses, unions, and structures.
Kojto 101:7cff1c4259d7 527 @{
Kojto 101:7cff1c4259d7 528 */
Kojto 101:7cff1c4259d7 529
Kojto 101:7cff1c4259d7 530 /* Memory mapping of Cortex-M0 Hardware */
Kojto 101:7cff1c4259d7 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 101:7cff1c4259d7 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 101:7cff1c4259d7 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 101:7cff1c4259d7 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 101:7cff1c4259d7 535
Kojto 101:7cff1c4259d7 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 101:7cff1c4259d7 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 101:7cff1c4259d7 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 101:7cff1c4259d7 539
Kojto 101:7cff1c4259d7 540
Kojto 101:7cff1c4259d7 541 /*@} */
Kojto 101:7cff1c4259d7 542
Kojto 101:7cff1c4259d7 543
Kojto 101:7cff1c4259d7 544
Kojto 101:7cff1c4259d7 545 /*******************************************************************************
Kojto 101:7cff1c4259d7 546 * Hardware Abstraction Layer
Kojto 101:7cff1c4259d7 547 Core Function Interface contains:
Kojto 101:7cff1c4259d7 548 - Core NVIC Functions
Kojto 101:7cff1c4259d7 549 - Core SysTick Functions
Kojto 101:7cff1c4259d7 550 - Core Register Access Functions
Kojto 101:7cff1c4259d7 551 ******************************************************************************/
Kojto 101:7cff1c4259d7 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 101:7cff1c4259d7 553 */
Kojto 101:7cff1c4259d7 554
Kojto 101:7cff1c4259d7 555
Kojto 101:7cff1c4259d7 556
Kojto 101:7cff1c4259d7 557 /* ########################## NVIC functions #################################### */
Kojto 101:7cff1c4259d7 558 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 101:7cff1c4259d7 560 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 101:7cff1c4259d7 561 @{
Kojto 101:7cff1c4259d7 562 */
Kojto 101:7cff1c4259d7 563
Kojto 101:7cff1c4259d7 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 101:7cff1c4259d7 565 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 101:7cff1c4259d7 569
Kojto 101:7cff1c4259d7 570
Kojto 101:7cff1c4259d7 571 /** \brief Enable External Interrupt
Kojto 101:7cff1c4259d7 572
Kojto 101:7cff1c4259d7 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 101:7cff1c4259d7 574
Kojto 101:7cff1c4259d7 575 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 576 */
Kojto 101:7cff1c4259d7 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 578 {
Kojto 110:165afa46840b 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 101:7cff1c4259d7 580 }
Kojto 101:7cff1c4259d7 581
Kojto 101:7cff1c4259d7 582
Kojto 101:7cff1c4259d7 583 /** \brief Disable External Interrupt
Kojto 101:7cff1c4259d7 584
Kojto 101:7cff1c4259d7 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 101:7cff1c4259d7 586
Kojto 101:7cff1c4259d7 587 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 588 */
Kojto 101:7cff1c4259d7 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 590 {
Kojto 110:165afa46840b 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
Kojto 101:7cff1c4259d7 594 }
Kojto 101:7cff1c4259d7 595
Kojto 101:7cff1c4259d7 596
Kojto 101:7cff1c4259d7 597 /** \brief Get Pending Interrupt
Kojto 101:7cff1c4259d7 598
Kojto 101:7cff1c4259d7 599 The function reads the pending register in the NVIC and returns the pending bit
Kojto 101:7cff1c4259d7 600 for the specified interrupt.
Kojto 101:7cff1c4259d7 601
Kojto 101:7cff1c4259d7 602 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 603
Kojto 101:7cff1c4259d7 604 \return 0 Interrupt status is not pending.
Kojto 101:7cff1c4259d7 605 \return 1 Interrupt status is pending.
Kojto 101:7cff1c4259d7 606 */
Kojto 101:7cff1c4259d7 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 608 {
Kojto 110:165afa46840b 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 101:7cff1c4259d7 610 }
Kojto 101:7cff1c4259d7 611
Kojto 101:7cff1c4259d7 612
Kojto 101:7cff1c4259d7 613 /** \brief Set Pending Interrupt
Kojto 101:7cff1c4259d7 614
Kojto 101:7cff1c4259d7 615 The function sets the pending bit of an external interrupt.
Kojto 101:7cff1c4259d7 616
Kojto 101:7cff1c4259d7 617 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 618 */
Kojto 101:7cff1c4259d7 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 620 {
Kojto 110:165afa46840b 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 101:7cff1c4259d7 622 }
Kojto 101:7cff1c4259d7 623
Kojto 101:7cff1c4259d7 624
Kojto 101:7cff1c4259d7 625 /** \brief Clear Pending Interrupt
Kojto 101:7cff1c4259d7 626
Kojto 101:7cff1c4259d7 627 The function clears the pending bit of an external interrupt.
Kojto 101:7cff1c4259d7 628
Kojto 101:7cff1c4259d7 629 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 630 */
Kojto 101:7cff1c4259d7 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 632 {
Kojto 110:165afa46840b 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 101:7cff1c4259d7 634 }
Kojto 101:7cff1c4259d7 635
Kojto 101:7cff1c4259d7 636
Kojto 101:7cff1c4259d7 637 /** \brief Set Interrupt Priority
Kojto 101:7cff1c4259d7 638
Kojto 101:7cff1c4259d7 639 The function sets the priority of an interrupt.
Kojto 101:7cff1c4259d7 640
Kojto 101:7cff1c4259d7 641 \note The priority cannot be set for every core interrupt.
Kojto 101:7cff1c4259d7 642
Kojto 101:7cff1c4259d7 643 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 644 \param [in] priority Priority to set.
Kojto 101:7cff1c4259d7 645 */
Kojto 101:7cff1c4259d7 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 101:7cff1c4259d7 647 {
Kojto 110:165afa46840b 648 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 651 }
Kojto 101:7cff1c4259d7 652 else {
Kojto 110:165afa46840b 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 655 }
Kojto 101:7cff1c4259d7 656 }
Kojto 101:7cff1c4259d7 657
Kojto 101:7cff1c4259d7 658
Kojto 101:7cff1c4259d7 659 /** \brief Get Interrupt Priority
Kojto 101:7cff1c4259d7 660
Kojto 101:7cff1c4259d7 661 The function reads the priority of an interrupt. The interrupt
Kojto 101:7cff1c4259d7 662 number can be positive to specify an external (device specific)
Kojto 101:7cff1c4259d7 663 interrupt, or negative to specify an internal (core) interrupt.
Kojto 101:7cff1c4259d7 664
Kojto 101:7cff1c4259d7 665
Kojto 101:7cff1c4259d7 666 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 667 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 101:7cff1c4259d7 668 priority bits of the microcontroller.
Kojto 101:7cff1c4259d7 669 */
Kojto 101:7cff1c4259d7 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 671 {
Kojto 101:7cff1c4259d7 672
Kojto 110:165afa46840b 673 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 675 }
Kojto 101:7cff1c4259d7 676 else {
Kojto 110:165afa46840b 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 678 }
Kojto 101:7cff1c4259d7 679 }
Kojto 101:7cff1c4259d7 680
Kojto 101:7cff1c4259d7 681
Kojto 101:7cff1c4259d7 682 /** \brief System Reset
Kojto 101:7cff1c4259d7 683
Kojto 101:7cff1c4259d7 684 The function initiates a system reset request to reset the MCU.
Kojto 101:7cff1c4259d7 685 */
Kojto 101:7cff1c4259d7 686 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 101:7cff1c4259d7 687 {
Kojto 101:7cff1c4259d7 688 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 101:7cff1c4259d7 689 buffered write are completed before reset */
Kojto 110:165afa46840b 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 101:7cff1c4259d7 691 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 101:7cff1c4259d7 692 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 693 while(1) { __NOP(); } /* wait until reset */
Kojto 101:7cff1c4259d7 694 }
Kojto 101:7cff1c4259d7 695
Kojto 101:7cff1c4259d7 696 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 101:7cff1c4259d7 697
Kojto 101:7cff1c4259d7 698
Kojto 101:7cff1c4259d7 699
Kojto 101:7cff1c4259d7 700 /* ################################## SysTick function ############################################ */
Kojto 101:7cff1c4259d7 701 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 101:7cff1c4259d7 703 \brief Functions that configure the System.
Kojto 101:7cff1c4259d7 704 @{
Kojto 101:7cff1c4259d7 705 */
Kojto 101:7cff1c4259d7 706
Kojto 101:7cff1c4259d7 707 #if (__Vendor_SysTickConfig == 0)
Kojto 101:7cff1c4259d7 708
Kojto 101:7cff1c4259d7 709 /** \brief System Tick Configuration
Kojto 101:7cff1c4259d7 710
Kojto 101:7cff1c4259d7 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 101:7cff1c4259d7 712 Counter is in free running mode to generate periodic interrupts.
Kojto 101:7cff1c4259d7 713
Kojto 101:7cff1c4259d7 714 \param [in] ticks Number of ticks between two interrupts.
Kojto 101:7cff1c4259d7 715
Kojto 101:7cff1c4259d7 716 \return 0 Function succeeded.
Kojto 101:7cff1c4259d7 717 \return 1 Function failed.
Kojto 101:7cff1c4259d7 718
Kojto 101:7cff1c4259d7 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 101:7cff1c4259d7 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 101:7cff1c4259d7 721 must contain a vendor-specific implementation of this function.
Kojto 101:7cff1c4259d7 722
Kojto 101:7cff1c4259d7 723 */
Kojto 101:7cff1c4259d7 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 101:7cff1c4259d7 725 {
Kojto 110:165afa46840b 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 101:7cff1c4259d7 727
Kojto 110:165afa46840b 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 101:7cff1c4259d7 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 101:7cff1c4259d7 732 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 734 return (0UL); /* Function successful */
Kojto 101:7cff1c4259d7 735 }
Kojto 101:7cff1c4259d7 736
Kojto 101:7cff1c4259d7 737 #endif
Kojto 101:7cff1c4259d7 738
Kojto 101:7cff1c4259d7 739 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 101:7cff1c4259d7 740
Kojto 101:7cff1c4259d7 741
Kojto 101:7cff1c4259d7 742
Kojto 101:7cff1c4259d7 743
Kojto 110:165afa46840b 744 #ifdef __cplusplus
Kojto 110:165afa46840b 745 }
Kojto 110:165afa46840b 746 #endif
Kojto 110:165afa46840b 747
Kojto 101:7cff1c4259d7 748 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 101:7cff1c4259d7 749
Kojto 101:7cff1c4259d7 750 #endif /* __CMSIS_GENERIC */