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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARCH_PRO/core_cm0plus.h@85:024bf7f99721, 2014-06-11 (annotated)

Committer:
bogdanm
Date:
Wed Jun 11 15:14:05 2014 +0100
Revision:
85:024bf7f99721
Child:
110:165afa46840b
Release 85 of the mbed library



Main changes:



- K64F Ethernet fixes

- Updated tests

- Fixes for various mbed targets

- Code cleanup: fixed warnings, more consistent code style

- GCC support for K64F



There is a known issue with the I2C interface on some ST targets. If you

find the I2C interface problematic on your ST board, please log a bug

against this on mbed.org.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**************************************************************************//**
bogdanm 85:024bf7f99721 2 * @file core_cm0plus.h
bogdanm 85:024bf7f99721 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
bogdanm 85:024bf7f99721 4 * @version V3.20
bogdanm 85:024bf7f99721 5 * @date 25. February 2013
bogdanm 85:024bf7f99721 6 *
bogdanm 85:024bf7f99721 7 * @note
bogdanm 85:024bf7f99721 8 *
bogdanm 85:024bf7f99721 9 ******************************************************************************/
bogdanm 85:024bf7f99721 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 85:024bf7f99721 11
bogdanm 85:024bf7f99721 12 All rights reserved.
bogdanm 85:024bf7f99721 13 Redistribution and use in source and binary forms, with or without
bogdanm 85:024bf7f99721 14 modification, are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 - Redistributions of source code must retain the above copyright
bogdanm 85:024bf7f99721 16 notice, this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 85:024bf7f99721 18 notice, this list of conditions and the following disclaimer in the
bogdanm 85:024bf7f99721 19 documentation and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 85:024bf7f99721 21 to endorse or promote products derived from this software without
bogdanm 85:024bf7f99721 22 specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 85:024bf7f99721 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 85:024bf7f99721 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 85:024bf7f99721 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 85:024bf7f99721 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 85:024bf7f99721 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 85:024bf7f99721 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 85:024bf7f99721 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 85:024bf7f99721 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 35 ---------------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 36
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 #if defined ( __ICCARM__ )
bogdanm 85:024bf7f99721 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 85:024bf7f99721 40 #endif
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 #ifndef __CORE_CM0PLUS_H_GENERIC
bogdanm 85:024bf7f99721 47 #define __CORE_CM0PLUS_H_GENERIC
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 85:024bf7f99721 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 85:024bf7f99721 51
bogdanm 85:024bf7f99721 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 85:024bf7f99721 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 85:024bf7f99721 54
bogdanm 85:024bf7f99721 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 85:024bf7f99721 56 Unions are used for effective representation of core registers.
bogdanm 85:024bf7f99721 57
bogdanm 85:024bf7f99721 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 85:024bf7f99721 59 Function-like macros are used to allow more efficient code.
bogdanm 85:024bf7f99721 60 */
bogdanm 85:024bf7f99721 61
bogdanm 85:024bf7f99721 62
bogdanm 85:024bf7f99721 63 /*******************************************************************************
bogdanm 85:024bf7f99721 64 * CMSIS definitions
bogdanm 85:024bf7f99721 65 ******************************************************************************/
bogdanm 85:024bf7f99721 66 /** \ingroup Cortex-M0+
bogdanm 85:024bf7f99721 67 @{
bogdanm 85:024bf7f99721 68 */
bogdanm 85:024bf7f99721 69
bogdanm 85:024bf7f99721 70 /* CMSIS CM0P definitions */
bogdanm 85:024bf7f99721 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 85:024bf7f99721 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 85:024bf7f99721 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 85:024bf7f99721 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 85:024bf7f99721 75
bogdanm 85:024bf7f99721 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 85:024bf7f99721 77
bogdanm 85:024bf7f99721 78
bogdanm 85:024bf7f99721 79 #if defined ( __CC_ARM )
bogdanm 85:024bf7f99721 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 85:024bf7f99721 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 85:024bf7f99721 82 #define __STATIC_INLINE static __inline
bogdanm 85:024bf7f99721 83
bogdanm 85:024bf7f99721 84 #elif defined ( __ICCARM__ )
bogdanm 85:024bf7f99721 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 85:024bf7f99721 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 85:024bf7f99721 87 #define __STATIC_INLINE static inline
bogdanm 85:024bf7f99721 88
bogdanm 85:024bf7f99721 89 #elif defined ( __GNUC__ )
bogdanm 85:024bf7f99721 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 85:024bf7f99721 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 85:024bf7f99721 92 #define __STATIC_INLINE static inline
bogdanm 85:024bf7f99721 93
bogdanm 85:024bf7f99721 94 #elif defined ( __TASKING__ )
bogdanm 85:024bf7f99721 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 85:024bf7f99721 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 85:024bf7f99721 97 #define __STATIC_INLINE static inline
bogdanm 85:024bf7f99721 98
bogdanm 85:024bf7f99721 99 #endif
bogdanm 85:024bf7f99721 100
bogdanm 85:024bf7f99721 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm 85:024bf7f99721 102 */
bogdanm 85:024bf7f99721 103 #define __FPU_USED 0
bogdanm 85:024bf7f99721 104
bogdanm 85:024bf7f99721 105 #if defined ( __CC_ARM )
bogdanm 85:024bf7f99721 106 #if defined __TARGET_FPU_VFP
bogdanm 85:024bf7f99721 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 85:024bf7f99721 108 #endif
bogdanm 85:024bf7f99721 109
bogdanm 85:024bf7f99721 110 #elif defined ( __ICCARM__ )
bogdanm 85:024bf7f99721 111 #if defined __ARMVFP__
bogdanm 85:024bf7f99721 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 85:024bf7f99721 113 #endif
bogdanm 85:024bf7f99721 114
bogdanm 85:024bf7f99721 115 #elif defined ( __GNUC__ )
bogdanm 85:024bf7f99721 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 85:024bf7f99721 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 85:024bf7f99721 118 #endif
bogdanm 85:024bf7f99721 119
bogdanm 85:024bf7f99721 120 #elif defined ( __TASKING__ )
bogdanm 85:024bf7f99721 121 #if defined __FPU_VFP__
bogdanm 85:024bf7f99721 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 85:024bf7f99721 123 #endif
bogdanm 85:024bf7f99721 124 #endif
bogdanm 85:024bf7f99721 125
bogdanm 85:024bf7f99721 126 #include <stdint.h> /* standard types definitions */
bogdanm 85:024bf7f99721 127 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 85:024bf7f99721 128 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 85:024bf7f99721 129
bogdanm 85:024bf7f99721 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 85:024bf7f99721 131
bogdanm 85:024bf7f99721 132 #ifndef __CMSIS_GENERIC
bogdanm 85:024bf7f99721 133
bogdanm 85:024bf7f99721 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 85:024bf7f99721 135 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 85:024bf7f99721 136
bogdanm 85:024bf7f99721 137 /* check device defines and use defaults */
bogdanm 85:024bf7f99721 138 #if defined __CHECK_DEVICE_DEFINES
bogdanm 85:024bf7f99721 139 #ifndef __CM0PLUS_REV
bogdanm 85:024bf7f99721 140 #define __CM0PLUS_REV 0x0000
bogdanm 85:024bf7f99721 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 85:024bf7f99721 142 #endif
bogdanm 85:024bf7f99721 143
bogdanm 85:024bf7f99721 144 #ifndef __MPU_PRESENT
bogdanm 85:024bf7f99721 145 #define __MPU_PRESENT 0
bogdanm 85:024bf7f99721 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 85:024bf7f99721 147 #endif
bogdanm 85:024bf7f99721 148
bogdanm 85:024bf7f99721 149 #ifndef __VTOR_PRESENT
bogdanm 85:024bf7f99721 150 #define __VTOR_PRESENT 0
bogdanm 85:024bf7f99721 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 85:024bf7f99721 152 #endif
bogdanm 85:024bf7f99721 153
bogdanm 85:024bf7f99721 154 #ifndef __NVIC_PRIO_BITS
bogdanm 85:024bf7f99721 155 #define __NVIC_PRIO_BITS 2
bogdanm 85:024bf7f99721 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 85:024bf7f99721 157 #endif
bogdanm 85:024bf7f99721 158
bogdanm 85:024bf7f99721 159 #ifndef __Vendor_SysTickConfig
bogdanm 85:024bf7f99721 160 #define __Vendor_SysTickConfig 0
bogdanm 85:024bf7f99721 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 85:024bf7f99721 162 #endif
bogdanm 85:024bf7f99721 163 #endif
bogdanm 85:024bf7f99721 164
bogdanm 85:024bf7f99721 165 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 85:024bf7f99721 166 /**
bogdanm 85:024bf7f99721 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 85:024bf7f99721 168
bogdanm 85:024bf7f99721 169 <strong>IO Type Qualifiers</strong> are used
bogdanm 85:024bf7f99721 170 \li to specify the access to peripheral variables.
bogdanm 85:024bf7f99721 171 \li for automatic generation of peripheral register debug information.
bogdanm 85:024bf7f99721 172 */
bogdanm 85:024bf7f99721 173 #ifdef __cplusplus
bogdanm 85:024bf7f99721 174 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 85:024bf7f99721 175 #else
bogdanm 85:024bf7f99721 176 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 85:024bf7f99721 177 #endif
bogdanm 85:024bf7f99721 178 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 85:024bf7f99721 179 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 85:024bf7f99721 180
bogdanm 85:024bf7f99721 181 /*@} end of group Cortex-M0+ */
bogdanm 85:024bf7f99721 182
bogdanm 85:024bf7f99721 183
bogdanm 85:024bf7f99721 184
bogdanm 85:024bf7f99721 185 /*******************************************************************************
bogdanm 85:024bf7f99721 186 * Register Abstraction
bogdanm 85:024bf7f99721 187 Core Register contain:
bogdanm 85:024bf7f99721 188 - Core Register
bogdanm 85:024bf7f99721 189 - Core NVIC Register
bogdanm 85:024bf7f99721 190 - Core SCB Register
bogdanm 85:024bf7f99721 191 - Core SysTick Register
bogdanm 85:024bf7f99721 192 - Core MPU Register
bogdanm 85:024bf7f99721 193 ******************************************************************************/
bogdanm 85:024bf7f99721 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 85:024bf7f99721 195 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 85:024bf7f99721 196 */
bogdanm 85:024bf7f99721 197
bogdanm 85:024bf7f99721 198 /** \ingroup CMSIS_core_register
bogdanm 85:024bf7f99721 199 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 85:024bf7f99721 200 \brief Core Register type definitions.
bogdanm 85:024bf7f99721 201 @{
bogdanm 85:024bf7f99721 202 */
bogdanm 85:024bf7f99721 203
bogdanm 85:024bf7f99721 204 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 85:024bf7f99721 205 */
bogdanm 85:024bf7f99721 206 typedef union
bogdanm 85:024bf7f99721 207 {
bogdanm 85:024bf7f99721 208 struct
bogdanm 85:024bf7f99721 209 {
bogdanm 85:024bf7f99721 210 #if (__CORTEX_M != 0x04)
bogdanm 85:024bf7f99721 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 85:024bf7f99721 212 #else
bogdanm 85:024bf7f99721 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 85:024bf7f99721 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 85:024bf7f99721 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 85:024bf7f99721 216 #endif
bogdanm 85:024bf7f99721 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 85:024bf7f99721 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 85:024bf7f99721 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 85:024bf7f99721 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 85:024bf7f99721 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 85:024bf7f99721 222 } b; /*!< Structure used for bit access */
bogdanm 85:024bf7f99721 223 uint32_t w; /*!< Type used for word access */
bogdanm 85:024bf7f99721 224 } APSR_Type;
bogdanm 85:024bf7f99721 225
bogdanm 85:024bf7f99721 226
bogdanm 85:024bf7f99721 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 85:024bf7f99721 228 */
bogdanm 85:024bf7f99721 229 typedef union
bogdanm 85:024bf7f99721 230 {
bogdanm 85:024bf7f99721 231 struct
bogdanm 85:024bf7f99721 232 {
bogdanm 85:024bf7f99721 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 85:024bf7f99721 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 85:024bf7f99721 235 } b; /*!< Structure used for bit access */
bogdanm 85:024bf7f99721 236 uint32_t w; /*!< Type used for word access */
bogdanm 85:024bf7f99721 237 } IPSR_Type;
bogdanm 85:024bf7f99721 238
bogdanm 85:024bf7f99721 239
bogdanm 85:024bf7f99721 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 85:024bf7f99721 241 */
bogdanm 85:024bf7f99721 242 typedef union
bogdanm 85:024bf7f99721 243 {
bogdanm 85:024bf7f99721 244 struct
bogdanm 85:024bf7f99721 245 {
bogdanm 85:024bf7f99721 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 85:024bf7f99721 247 #if (__CORTEX_M != 0x04)
bogdanm 85:024bf7f99721 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 85:024bf7f99721 249 #else
bogdanm 85:024bf7f99721 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 85:024bf7f99721 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 85:024bf7f99721 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 85:024bf7f99721 253 #endif
bogdanm 85:024bf7f99721 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 85:024bf7f99721 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 85:024bf7f99721 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 85:024bf7f99721 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 85:024bf7f99721 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 85:024bf7f99721 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 85:024bf7f99721 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 85:024bf7f99721 261 } b; /*!< Structure used for bit access */
bogdanm 85:024bf7f99721 262 uint32_t w; /*!< Type used for word access */
bogdanm 85:024bf7f99721 263 } xPSR_Type;
bogdanm 85:024bf7f99721 264
bogdanm 85:024bf7f99721 265
bogdanm 85:024bf7f99721 266 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 85:024bf7f99721 267 */
bogdanm 85:024bf7f99721 268 typedef union
bogdanm 85:024bf7f99721 269 {
bogdanm 85:024bf7f99721 270 struct
bogdanm 85:024bf7f99721 271 {
bogdanm 85:024bf7f99721 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 85:024bf7f99721 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 85:024bf7f99721 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 85:024bf7f99721 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 85:024bf7f99721 276 } b; /*!< Structure used for bit access */
bogdanm 85:024bf7f99721 277 uint32_t w; /*!< Type used for word access */
bogdanm 85:024bf7f99721 278 } CONTROL_Type;
bogdanm 85:024bf7f99721 279
bogdanm 85:024bf7f99721 280 /*@} end of group CMSIS_CORE */
bogdanm 85:024bf7f99721 281
bogdanm 85:024bf7f99721 282
bogdanm 85:024bf7f99721 283 /** \ingroup CMSIS_core_register
bogdanm 85:024bf7f99721 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 85:024bf7f99721 285 \brief Type definitions for the NVIC Registers
bogdanm 85:024bf7f99721 286 @{
bogdanm 85:024bf7f99721 287 */
bogdanm 85:024bf7f99721 288
bogdanm 85:024bf7f99721 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 85:024bf7f99721 290 */
bogdanm 85:024bf7f99721 291 typedef struct
bogdanm 85:024bf7f99721 292 {
bogdanm 85:024bf7f99721 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 85:024bf7f99721 294 uint32_t RESERVED0[31];
bogdanm 85:024bf7f99721 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 85:024bf7f99721 296 uint32_t RSERVED1[31];
bogdanm 85:024bf7f99721 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 85:024bf7f99721 298 uint32_t RESERVED2[31];
bogdanm 85:024bf7f99721 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 85:024bf7f99721 300 uint32_t RESERVED3[31];
bogdanm 85:024bf7f99721 301 uint32_t RESERVED4[64];
bogdanm 85:024bf7f99721 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 85:024bf7f99721 303 } NVIC_Type;
bogdanm 85:024bf7f99721 304
bogdanm 85:024bf7f99721 305 /*@} end of group CMSIS_NVIC */
bogdanm 85:024bf7f99721 306
bogdanm 85:024bf7f99721 307
bogdanm 85:024bf7f99721 308 /** \ingroup CMSIS_core_register
bogdanm 85:024bf7f99721 309 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 85:024bf7f99721 310 \brief Type definitions for the System Control Block Registers
bogdanm 85:024bf7f99721 311 @{
bogdanm 85:024bf7f99721 312 */
bogdanm 85:024bf7f99721 313
bogdanm 85:024bf7f99721 314 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 85:024bf7f99721 315 */
bogdanm 85:024bf7f99721 316 typedef struct
bogdanm 85:024bf7f99721 317 {
bogdanm 85:024bf7f99721 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 85:024bf7f99721 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 85:024bf7f99721 320 #if (__VTOR_PRESENT == 1)
bogdanm 85:024bf7f99721 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 85:024bf7f99721 322 #else
bogdanm 85:024bf7f99721 323 uint32_t RESERVED0;
bogdanm 85:024bf7f99721 324 #endif
bogdanm 85:024bf7f99721 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 85:024bf7f99721 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 85:024bf7f99721 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 85:024bf7f99721 328 uint32_t RESERVED1;
bogdanm 85:024bf7f99721 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 85:024bf7f99721 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 85:024bf7f99721 331 } SCB_Type;
bogdanm 85:024bf7f99721 332
bogdanm 85:024bf7f99721 333 /* SCB CPUID Register Definitions */
bogdanm 85:024bf7f99721 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 85:024bf7f99721 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 85:024bf7f99721 336
bogdanm 85:024bf7f99721 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 85:024bf7f99721 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 85:024bf7f99721 339
bogdanm 85:024bf7f99721 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 85:024bf7f99721 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 85:024bf7f99721 342
bogdanm 85:024bf7f99721 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 85:024bf7f99721 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 85:024bf7f99721 345
bogdanm 85:024bf7f99721 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 85:024bf7f99721 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 85:024bf7f99721 348
bogdanm 85:024bf7f99721 349 /* SCB Interrupt Control State Register Definitions */
bogdanm 85:024bf7f99721 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 85:024bf7f99721 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 85:024bf7f99721 352
bogdanm 85:024bf7f99721 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 85:024bf7f99721 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 85:024bf7f99721 355
bogdanm 85:024bf7f99721 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 85:024bf7f99721 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 85:024bf7f99721 358
bogdanm 85:024bf7f99721 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 85:024bf7f99721 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 85:024bf7f99721 361
bogdanm 85:024bf7f99721 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 85:024bf7f99721 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 85:024bf7f99721 364
bogdanm 85:024bf7f99721 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 85:024bf7f99721 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 85:024bf7f99721 367
bogdanm 85:024bf7f99721 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 85:024bf7f99721 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 85:024bf7f99721 370
bogdanm 85:024bf7f99721 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 85:024bf7f99721 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 85:024bf7f99721 373
bogdanm 85:024bf7f99721 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 85:024bf7f99721 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 85:024bf7f99721 376
bogdanm 85:024bf7f99721 377 #if (__VTOR_PRESENT == 1)
bogdanm 85:024bf7f99721 378 /* SCB Interrupt Control State Register Definitions */
bogdanm 85:024bf7f99721 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 85:024bf7f99721 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 85:024bf7f99721 381 #endif
bogdanm 85:024bf7f99721 382
bogdanm 85:024bf7f99721 383 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 85:024bf7f99721 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 85:024bf7f99721 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 85:024bf7f99721 386
bogdanm 85:024bf7f99721 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 85:024bf7f99721 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 85:024bf7f99721 389
bogdanm 85:024bf7f99721 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 85:024bf7f99721 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 85:024bf7f99721 392
bogdanm 85:024bf7f99721 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 85:024bf7f99721 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 85:024bf7f99721 395
bogdanm 85:024bf7f99721 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 85:024bf7f99721 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 85:024bf7f99721 398
bogdanm 85:024bf7f99721 399 /* SCB System Control Register Definitions */
bogdanm 85:024bf7f99721 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 85:024bf7f99721 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 85:024bf7f99721 402
bogdanm 85:024bf7f99721 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 85:024bf7f99721 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 85:024bf7f99721 405
bogdanm 85:024bf7f99721 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 85:024bf7f99721 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 85:024bf7f99721 408
bogdanm 85:024bf7f99721 409 /* SCB Configuration Control Register Definitions */
bogdanm 85:024bf7f99721 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 85:024bf7f99721 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 85:024bf7f99721 412
bogdanm 85:024bf7f99721 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 85:024bf7f99721 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 85:024bf7f99721 415
bogdanm 85:024bf7f99721 416 /* SCB System Handler Control and State Register Definitions */
bogdanm 85:024bf7f99721 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 85:024bf7f99721 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 85:024bf7f99721 419
bogdanm 85:024bf7f99721 420 /*@} end of group CMSIS_SCB */
bogdanm 85:024bf7f99721 421
bogdanm 85:024bf7f99721 422
bogdanm 85:024bf7f99721 423 /** \ingroup CMSIS_core_register
bogdanm 85:024bf7f99721 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 85:024bf7f99721 425 \brief Type definitions for the System Timer Registers.
bogdanm 85:024bf7f99721 426 @{
bogdanm 85:024bf7f99721 427 */
bogdanm 85:024bf7f99721 428
bogdanm 85:024bf7f99721 429 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 85:024bf7f99721 430 */
bogdanm 85:024bf7f99721 431 typedef struct
bogdanm 85:024bf7f99721 432 {
bogdanm 85:024bf7f99721 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 85:024bf7f99721 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 85:024bf7f99721 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 85:024bf7f99721 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 85:024bf7f99721 437 } SysTick_Type;
bogdanm 85:024bf7f99721 438
bogdanm 85:024bf7f99721 439 /* SysTick Control / Status Register Definitions */
bogdanm 85:024bf7f99721 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 85:024bf7f99721 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 85:024bf7f99721 442
bogdanm 85:024bf7f99721 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 85:024bf7f99721 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 85:024bf7f99721 445
bogdanm 85:024bf7f99721 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 85:024bf7f99721 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 85:024bf7f99721 448
bogdanm 85:024bf7f99721 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 85:024bf7f99721 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 85:024bf7f99721 451
bogdanm 85:024bf7f99721 452 /* SysTick Reload Register Definitions */
bogdanm 85:024bf7f99721 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 85:024bf7f99721 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 85:024bf7f99721 455
bogdanm 85:024bf7f99721 456 /* SysTick Current Register Definitions */
bogdanm 85:024bf7f99721 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 85:024bf7f99721 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 85:024bf7f99721 459
bogdanm 85:024bf7f99721 460 /* SysTick Calibration Register Definitions */
bogdanm 85:024bf7f99721 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 85:024bf7f99721 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 85:024bf7f99721 463
bogdanm 85:024bf7f99721 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 85:024bf7f99721 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 85:024bf7f99721 466
bogdanm 85:024bf7f99721 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 85:024bf7f99721 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 85:024bf7f99721 469
bogdanm 85:024bf7f99721 470 /*@} end of group CMSIS_SysTick */
bogdanm 85:024bf7f99721 471
bogdanm 85:024bf7f99721 472 #if (__MPU_PRESENT == 1)
bogdanm 85:024bf7f99721 473 /** \ingroup CMSIS_core_register
bogdanm 85:024bf7f99721 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 85:024bf7f99721 475 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 85:024bf7f99721 476 @{
bogdanm 85:024bf7f99721 477 */
bogdanm 85:024bf7f99721 478
bogdanm 85:024bf7f99721 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 85:024bf7f99721 480 */
bogdanm 85:024bf7f99721 481 typedef struct
bogdanm 85:024bf7f99721 482 {
bogdanm 85:024bf7f99721 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 85:024bf7f99721 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 85:024bf7f99721 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 85:024bf7f99721 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 85:024bf7f99721 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 85:024bf7f99721 488 } MPU_Type;
bogdanm 85:024bf7f99721 489
bogdanm 85:024bf7f99721 490 /* MPU Type Register */
bogdanm 85:024bf7f99721 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 85:024bf7f99721 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 85:024bf7f99721 493
bogdanm 85:024bf7f99721 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 85:024bf7f99721 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 85:024bf7f99721 496
bogdanm 85:024bf7f99721 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 85:024bf7f99721 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 85:024bf7f99721 499
bogdanm 85:024bf7f99721 500 /* MPU Control Register */
bogdanm 85:024bf7f99721 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 85:024bf7f99721 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 85:024bf7f99721 503
bogdanm 85:024bf7f99721 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 85:024bf7f99721 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 85:024bf7f99721 506
bogdanm 85:024bf7f99721 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 85:024bf7f99721 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 85:024bf7f99721 509
bogdanm 85:024bf7f99721 510 /* MPU Region Number Register */
bogdanm 85:024bf7f99721 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 85:024bf7f99721 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 85:024bf7f99721 513
bogdanm 85:024bf7f99721 514 /* MPU Region Base Address Register */
bogdanm 85:024bf7f99721 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 85:024bf7f99721 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 85:024bf7f99721 517
bogdanm 85:024bf7f99721 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 85:024bf7f99721 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 85:024bf7f99721 520
bogdanm 85:024bf7f99721 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 85:024bf7f99721 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 85:024bf7f99721 523
bogdanm 85:024bf7f99721 524 /* MPU Region Attribute and Size Register */
bogdanm 85:024bf7f99721 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 85:024bf7f99721 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 85:024bf7f99721 527
bogdanm 85:024bf7f99721 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 85:024bf7f99721 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 85:024bf7f99721 530
bogdanm 85:024bf7f99721 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 85:024bf7f99721 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 85:024bf7f99721 533
bogdanm 85:024bf7f99721 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 85:024bf7f99721 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 85:024bf7f99721 536
bogdanm 85:024bf7f99721 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 85:024bf7f99721 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 85:024bf7f99721 539
bogdanm 85:024bf7f99721 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 85:024bf7f99721 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 85:024bf7f99721 542
bogdanm 85:024bf7f99721 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 85:024bf7f99721 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 85:024bf7f99721 545
bogdanm 85:024bf7f99721 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 85:024bf7f99721 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 85:024bf7f99721 548
bogdanm 85:024bf7f99721 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 85:024bf7f99721 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 85:024bf7f99721 551
bogdanm 85:024bf7f99721 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 85:024bf7f99721 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 85:024bf7f99721 554
bogdanm 85:024bf7f99721 555 /*@} end of group CMSIS_MPU */
bogdanm 85:024bf7f99721 556 #endif
bogdanm 85:024bf7f99721 557
bogdanm 85:024bf7f99721 558
bogdanm 85:024bf7f99721 559 /** \ingroup CMSIS_core_register
bogdanm 85:024bf7f99721 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 85:024bf7f99721 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 85:024bf7f99721 562 are only accessible over DAP and not via processor. Therefore
bogdanm 85:024bf7f99721 563 they are not covered by the Cortex-M0 header file.
bogdanm 85:024bf7f99721 564 @{
bogdanm 85:024bf7f99721 565 */
bogdanm 85:024bf7f99721 566 /*@} end of group CMSIS_CoreDebug */
bogdanm 85:024bf7f99721 567
bogdanm 85:024bf7f99721 568
bogdanm 85:024bf7f99721 569 /** \ingroup CMSIS_core_register
bogdanm 85:024bf7f99721 570 \defgroup CMSIS_core_base Core Definitions
bogdanm 85:024bf7f99721 571 \brief Definitions for base addresses, unions, and structures.
bogdanm 85:024bf7f99721 572 @{
bogdanm 85:024bf7f99721 573 */
bogdanm 85:024bf7f99721 574
bogdanm 85:024bf7f99721 575 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 85:024bf7f99721 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 85:024bf7f99721 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 85:024bf7f99721 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 85:024bf7f99721 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 85:024bf7f99721 580
bogdanm 85:024bf7f99721 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 85:024bf7f99721 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 85:024bf7f99721 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 85:024bf7f99721 584
bogdanm 85:024bf7f99721 585 #if (__MPU_PRESENT == 1)
bogdanm 85:024bf7f99721 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 85:024bf7f99721 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 85:024bf7f99721 588 #endif
bogdanm 85:024bf7f99721 589
bogdanm 85:024bf7f99721 590 /*@} */
bogdanm 85:024bf7f99721 591
bogdanm 85:024bf7f99721 592
bogdanm 85:024bf7f99721 593
bogdanm 85:024bf7f99721 594 /*******************************************************************************
bogdanm 85:024bf7f99721 595 * Hardware Abstraction Layer
bogdanm 85:024bf7f99721 596 Core Function Interface contains:
bogdanm 85:024bf7f99721 597 - Core NVIC Functions
bogdanm 85:024bf7f99721 598 - Core SysTick Functions
bogdanm 85:024bf7f99721 599 - Core Register Access Functions
bogdanm 85:024bf7f99721 600 ******************************************************************************/
bogdanm 85:024bf7f99721 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 85:024bf7f99721 602 */
bogdanm 85:024bf7f99721 603
bogdanm 85:024bf7f99721 604
bogdanm 85:024bf7f99721 605
bogdanm 85:024bf7f99721 606 /* ########################## NVIC functions #################################### */
bogdanm 85:024bf7f99721 607 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 85:024bf7f99721 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 85:024bf7f99721 609 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 85:024bf7f99721 610 @{
bogdanm 85:024bf7f99721 611 */
bogdanm 85:024bf7f99721 612
bogdanm 85:024bf7f99721 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 85:024bf7f99721 614 /* The following MACROS handle generation of the register offset and byte masks */
bogdanm 85:024bf7f99721 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
bogdanm 85:024bf7f99721 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
bogdanm 85:024bf7f99721 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
bogdanm 85:024bf7f99721 618
bogdanm 85:024bf7f99721 619
bogdanm 85:024bf7f99721 620 /** \brief Enable External Interrupt
bogdanm 85:024bf7f99721 621
bogdanm 85:024bf7f99721 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 85:024bf7f99721 623
bogdanm 85:024bf7f99721 624 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 85:024bf7f99721 625 */
bogdanm 85:024bf7f99721 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 85:024bf7f99721 627 {
bogdanm 85:024bf7f99721 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 85:024bf7f99721 629 }
bogdanm 85:024bf7f99721 630
bogdanm 85:024bf7f99721 631
bogdanm 85:024bf7f99721 632 /** \brief Disable External Interrupt
bogdanm 85:024bf7f99721 633
bogdanm 85:024bf7f99721 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 85:024bf7f99721 635
bogdanm 85:024bf7f99721 636 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 85:024bf7f99721 637 */
bogdanm 85:024bf7f99721 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 85:024bf7f99721 639 {
bogdanm 85:024bf7f99721 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 85:024bf7f99721 641 }
bogdanm 85:024bf7f99721 642
bogdanm 85:024bf7f99721 643
bogdanm 85:024bf7f99721 644 /** \brief Get Pending Interrupt
bogdanm 85:024bf7f99721 645
bogdanm 85:024bf7f99721 646 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 85:024bf7f99721 647 for the specified interrupt.
bogdanm 85:024bf7f99721 648
bogdanm 85:024bf7f99721 649 \param [in] IRQn Interrupt number.
bogdanm 85:024bf7f99721 650
bogdanm 85:024bf7f99721 651 \return 0 Interrupt status is not pending.
bogdanm 85:024bf7f99721 652 \return 1 Interrupt status is pending.
bogdanm 85:024bf7f99721 653 */
bogdanm 85:024bf7f99721 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 85:024bf7f99721 655 {
bogdanm 85:024bf7f99721 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
bogdanm 85:024bf7f99721 657 }
bogdanm 85:024bf7f99721 658
bogdanm 85:024bf7f99721 659
bogdanm 85:024bf7f99721 660 /** \brief Set Pending Interrupt
bogdanm 85:024bf7f99721 661
bogdanm 85:024bf7f99721 662 The function sets the pending bit of an external interrupt.
bogdanm 85:024bf7f99721 663
bogdanm 85:024bf7f99721 664 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 85:024bf7f99721 665 */
bogdanm 85:024bf7f99721 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 85:024bf7f99721 667 {
bogdanm 85:024bf7f99721 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 85:024bf7f99721 669 }
bogdanm 85:024bf7f99721 670
bogdanm 85:024bf7f99721 671
bogdanm 85:024bf7f99721 672 /** \brief Clear Pending Interrupt
bogdanm 85:024bf7f99721 673
bogdanm 85:024bf7f99721 674 The function clears the pending bit of an external interrupt.
bogdanm 85:024bf7f99721 675
bogdanm 85:024bf7f99721 676 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 85:024bf7f99721 677 */
bogdanm 85:024bf7f99721 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 85:024bf7f99721 679 {
bogdanm 85:024bf7f99721 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 85:024bf7f99721 681 }
bogdanm 85:024bf7f99721 682
bogdanm 85:024bf7f99721 683
bogdanm 85:024bf7f99721 684 /** \brief Set Interrupt Priority
bogdanm 85:024bf7f99721 685
bogdanm 85:024bf7f99721 686 The function sets the priority of an interrupt.
bogdanm 85:024bf7f99721 687
bogdanm 85:024bf7f99721 688 \note The priority cannot be set for every core interrupt.
bogdanm 85:024bf7f99721 689
bogdanm 85:024bf7f99721 690 \param [in] IRQn Interrupt number.
bogdanm 85:024bf7f99721 691 \param [in] priority Priority to set.
bogdanm 85:024bf7f99721 692 */
bogdanm 85:024bf7f99721 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 85:024bf7f99721 694 {
bogdanm 85:024bf7f99721 695 if(IRQn < 0) {
bogdanm 85:024bf7f99721 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 85:024bf7f99721 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 85:024bf7f99721 698 else {
bogdanm 85:024bf7f99721 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 85:024bf7f99721 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 85:024bf7f99721 701 }
bogdanm 85:024bf7f99721 702
bogdanm 85:024bf7f99721 703
bogdanm 85:024bf7f99721 704 /** \brief Get Interrupt Priority
bogdanm 85:024bf7f99721 705
bogdanm 85:024bf7f99721 706 The function reads the priority of an interrupt. The interrupt
bogdanm 85:024bf7f99721 707 number can be positive to specify an external (device specific)
bogdanm 85:024bf7f99721 708 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 85:024bf7f99721 709
bogdanm 85:024bf7f99721 710
bogdanm 85:024bf7f99721 711 \param [in] IRQn Interrupt number.
bogdanm 85:024bf7f99721 712 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 85:024bf7f99721 713 priority bits of the microcontroller.
bogdanm 85:024bf7f99721 714 */
bogdanm 85:024bf7f99721 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 85:024bf7f99721 716 {
bogdanm 85:024bf7f99721 717
bogdanm 85:024bf7f99721 718 if(IRQn < 0) {
bogdanm 85:024bf7f99721 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
bogdanm 85:024bf7f99721 720 else {
bogdanm 85:024bf7f99721 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 85:024bf7f99721 722 }
bogdanm 85:024bf7f99721 723
bogdanm 85:024bf7f99721 724
bogdanm 85:024bf7f99721 725 /** \brief System Reset
bogdanm 85:024bf7f99721 726
bogdanm 85:024bf7f99721 727 The function initiates a system reset request to reset the MCU.
bogdanm 85:024bf7f99721 728 */
bogdanm 85:024bf7f99721 729 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 85:024bf7f99721 730 {
bogdanm 85:024bf7f99721 731 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 85:024bf7f99721 732 buffered write are completed before reset */
bogdanm 85:024bf7f99721 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 85:024bf7f99721 734 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 85:024bf7f99721 735 __DSB(); /* Ensure completion of memory access */
bogdanm 85:024bf7f99721 736 while(1); /* wait until reset */
bogdanm 85:024bf7f99721 737 }
bogdanm 85:024bf7f99721 738
bogdanm 85:024bf7f99721 739 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 85:024bf7f99721 740
bogdanm 85:024bf7f99721 741
bogdanm 85:024bf7f99721 742
bogdanm 85:024bf7f99721 743 /* ################################## SysTick function ############################################ */
bogdanm 85:024bf7f99721 744 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 85:024bf7f99721 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 85:024bf7f99721 746 \brief Functions that configure the System.
bogdanm 85:024bf7f99721 747 @{
bogdanm 85:024bf7f99721 748 */
bogdanm 85:024bf7f99721 749
bogdanm 85:024bf7f99721 750 #if (__Vendor_SysTickConfig == 0)
bogdanm 85:024bf7f99721 751
bogdanm 85:024bf7f99721 752 /** \brief System Tick Configuration
bogdanm 85:024bf7f99721 753
bogdanm 85:024bf7f99721 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 85:024bf7f99721 755 Counter is in free running mode to generate periodic interrupts.
bogdanm 85:024bf7f99721 756
bogdanm 85:024bf7f99721 757 \param [in] ticks Number of ticks between two interrupts.
bogdanm 85:024bf7f99721 758
bogdanm 85:024bf7f99721 759 \return 0 Function succeeded.
bogdanm 85:024bf7f99721 760 \return 1 Function failed.
bogdanm 85:024bf7f99721 761
bogdanm 85:024bf7f99721 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 85:024bf7f99721 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 85:024bf7f99721 764 must contain a vendor-specific implementation of this function.
bogdanm 85:024bf7f99721 765
bogdanm 85:024bf7f99721 766 */
bogdanm 85:024bf7f99721 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 85:024bf7f99721 768 {
bogdanm 85:024bf7f99721 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 85:024bf7f99721 770
bogdanm 85:024bf7f99721 771 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 85:024bf7f99721 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 85:024bf7f99721 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 85:024bf7f99721 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 85:024bf7f99721 775 SysTick_CTRL_TICKINT_Msk |
bogdanm 85:024bf7f99721 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 85:024bf7f99721 777 return (0); /* Function successful */
bogdanm 85:024bf7f99721 778 }
bogdanm 85:024bf7f99721 779
bogdanm 85:024bf7f99721 780 #endif
bogdanm 85:024bf7f99721 781
bogdanm 85:024bf7f99721 782 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 85:024bf7f99721 783
bogdanm 85:024bf7f99721 784
bogdanm 85:024bf7f99721 785
bogdanm 85:024bf7f99721 786
bogdanm 85:024bf7f99721 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 85:024bf7f99721 788
bogdanm 85:024bf7f99721 789 #endif /* __CMSIS_GENERIC */
bogdanm 85:024bf7f99721 790
bogdanm 85:024bf7f99721 791 #ifdef __cplusplus
bogdanm 85:024bf7f99721 792 }
bogdanm 85:024bf7f99721 793 #endif