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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c@250:a49055e7a707, 2014-07-08 (annotated)

Committer:
mbed_official
Date:
Tue Jul 08 11:15:08 2014 +0100
Revision:
250:a49055e7a707
Parent:
227:7bd0639b8911
Child:
251:de9a1e4ffd79
Synchronized with git revision 3197042b65f8d28e856e1a7812d45e2fbe80e3f1



Full URL: https://github.com/mbedmicro/mbed/commit/3197042b65f8d28e856e1a7812d45e2fbe80e3f1/



error.h -> mbed_error.h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
emilmont 10:3bc89ef62ce7 17 #include <math.h>
emilmont 10:3bc89ef62ce7 18 #include "spi_api.h"
emilmont 10:3bc89ef62ce7 19 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 20 #include "pinmap.h"
mbed_official 250:a49055e7a707 21 #include "mbed_error.h"
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 static const PinMap PinMap_SPI_SCLK[] = {
emilmont 10:3bc89ef62ce7 24 {P0_6 , SPI_0, 0x02},
emilmont 10:3bc89ef62ce7 25 {P0_10, SPI_0, 0x02},
emilmont 10:3bc89ef62ce7 26 {P1_29, SPI_0, 0x01},
emilmont 10:3bc89ef62ce7 27 {P1_15, SPI_1, 0x03},
emilmont 10:3bc89ef62ce7 28 {P1_20, SPI_1, 0x02},
emilmont 10:3bc89ef62ce7 29 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 30 };
emilmont 10:3bc89ef62ce7 31
emilmont 10:3bc89ef62ce7 32 static const PinMap PinMap_SPI_MOSI[] = {
emilmont 10:3bc89ef62ce7 33 {P0_9 , SPI_0, 0x01},
emilmont 10:3bc89ef62ce7 34 {P0_21, SPI_1, 0x02},
emilmont 10:3bc89ef62ce7 35 {P1_22, SPI_1, 0x02},
emilmont 10:3bc89ef62ce7 36 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 37 };
emilmont 10:3bc89ef62ce7 38
emilmont 10:3bc89ef62ce7 39 static const PinMap PinMap_SPI_MISO[] = {
emilmont 10:3bc89ef62ce7 40 {P0_8 , SPI_0, 0x01},
emilmont 10:3bc89ef62ce7 41 {P0_22, SPI_1, 0x03},
emilmont 10:3bc89ef62ce7 42 {P1_21, SPI_1, 0x02},
emilmont 10:3bc89ef62ce7 43 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 44 };
emilmont 10:3bc89ef62ce7 45
emilmont 10:3bc89ef62ce7 46 static const PinMap PinMap_SPI_SSEL[] = {
emilmont 10:3bc89ef62ce7 47 {P0_2 , SPI_0, 0x01},
emilmont 10:3bc89ef62ce7 48 {P1_19, SPI_1, 0x02},
emilmont 10:3bc89ef62ce7 49 {P1_23, SPI_1, 0x02},
emilmont 10:3bc89ef62ce7 50 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 51 };
emilmont 10:3bc89ef62ce7 52
emilmont 10:3bc89ef62ce7 53 static inline int ssp_disable(spi_t *obj);
emilmont 10:3bc89ef62ce7 54 static inline int ssp_enable(spi_t *obj);
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
emilmont 10:3bc89ef62ce7 57 // determine the SPI to use
emilmont 10:3bc89ef62ce7 58 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 59 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 60 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 61 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 62 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
emilmont 10:3bc89ef62ce7 63 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
emilmont 10:3bc89ef62ce7 64
emilmont 10:3bc89ef62ce7 65 obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
mbed_official 227:7bd0639b8911 66 MBED_ASSERT((int)obj->spi != NC);
emilmont 10:3bc89ef62ce7 67
emilmont 10:3bc89ef62ce7 68 // enable power and clocking
emilmont 10:3bc89ef62ce7 69 switch ((int)obj->spi) {
emilmont 10:3bc89ef62ce7 70 case SPI_0:
emilmont 10:3bc89ef62ce7 71 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
emilmont 10:3bc89ef62ce7 72 LPC_SYSCON->SSP0CLKDIV = 0x01;
emilmont 10:3bc89ef62ce7 73 LPC_SYSCON->PRESETCTRL |= 1 << 0;
emilmont 10:3bc89ef62ce7 74 break;
emilmont 10:3bc89ef62ce7 75 case SPI_1:
emilmont 10:3bc89ef62ce7 76 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
emilmont 10:3bc89ef62ce7 77 LPC_SYSCON->SSP1CLKDIV = 0x01;
emilmont 10:3bc89ef62ce7 78 LPC_SYSCON->PRESETCTRL |= 1 << 2;
emilmont 10:3bc89ef62ce7 79 break;
emilmont 10:3bc89ef62ce7 80 }
emilmont 10:3bc89ef62ce7 81
emilmont 10:3bc89ef62ce7 82 // set default format and frequency
emilmont 10:3bc89ef62ce7 83 if (ssel == NC) {
emilmont 10:3bc89ef62ce7 84 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
emilmont 10:3bc89ef62ce7 85 } else {
emilmont 10:3bc89ef62ce7 86 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
emilmont 10:3bc89ef62ce7 87 }
emilmont 10:3bc89ef62ce7 88 spi_frequency(obj, 1000000);
emilmont 10:3bc89ef62ce7 89
emilmont 10:3bc89ef62ce7 90 // enable the ssp channel
emilmont 10:3bc89ef62ce7 91 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 92
emilmont 10:3bc89ef62ce7 93 // pin out the spi pins
emilmont 10:3bc89ef62ce7 94 pinmap_pinout(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 95 pinmap_pinout(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 96 pinmap_pinout(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 97 if (ssel != NC) {
emilmont 10:3bc89ef62ce7 98 pinmap_pinout(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 99 }
emilmont 10:3bc89ef62ce7 100 }
emilmont 10:3bc89ef62ce7 101
emilmont 10:3bc89ef62ce7 102 void spi_free(spi_t *obj) {}
emilmont 10:3bc89ef62ce7 103
emilmont 10:3bc89ef62ce7 104 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 227:7bd0639b8911 105 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
mbed_official 227:7bd0639b8911 106
emilmont 10:3bc89ef62ce7 107 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 108
emilmont 10:3bc89ef62ce7 109 int polarity = (mode & 0x2) ? 1 : 0;
emilmont 10:3bc89ef62ce7 110 int phase = (mode & 0x1) ? 1 : 0;
emilmont 10:3bc89ef62ce7 111
emilmont 10:3bc89ef62ce7 112 // set it up
emilmont 10:3bc89ef62ce7 113 int DSS = bits - 1; // DSS (data select size)
emilmont 10:3bc89ef62ce7 114 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
emilmont 10:3bc89ef62ce7 115 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
emilmont 10:3bc89ef62ce7 116
emilmont 10:3bc89ef62ce7 117 int FRF = 0; // FRF (frame format) = SPI
emilmont 10:3bc89ef62ce7 118 uint32_t tmp = obj->spi->CR0;
emilmont 10:3bc89ef62ce7 119 tmp &= ~(0xFFFF);
emilmont 10:3bc89ef62ce7 120 tmp |= DSS << 0
emilmont 10:3bc89ef62ce7 121 | FRF << 4
emilmont 10:3bc89ef62ce7 122 | SPO << 6
emilmont 10:3bc89ef62ce7 123 | SPH << 7;
emilmont 10:3bc89ef62ce7 124 obj->spi->CR0 = tmp;
emilmont 10:3bc89ef62ce7 125
emilmont 10:3bc89ef62ce7 126 tmp = obj->spi->CR1;
emilmont 10:3bc89ef62ce7 127 tmp &= ~(0xD);
emilmont 10:3bc89ef62ce7 128 tmp |= 0 << 0 // LBM - loop back mode - off
emilmont 10:3bc89ef62ce7 129 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
emilmont 10:3bc89ef62ce7 130 | 0 << 3; // SOD - slave output disable - na
emilmont 10:3bc89ef62ce7 131 obj->spi->CR1 = tmp;
emilmont 10:3bc89ef62ce7 132
emilmont 10:3bc89ef62ce7 133 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 134 }
emilmont 10:3bc89ef62ce7 135
emilmont 10:3bc89ef62ce7 136 void spi_frequency(spi_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 137 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 138
emilmont 10:3bc89ef62ce7 139 uint32_t PCLK = SystemCoreClock;
emilmont 10:3bc89ef62ce7 140
emilmont 10:3bc89ef62ce7 141 int prescaler;
emilmont 10:3bc89ef62ce7 142
emilmont 10:3bc89ef62ce7 143 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
emilmont 10:3bc89ef62ce7 144 int prescale_hz = PCLK / prescaler;
emilmont 10:3bc89ef62ce7 145
emilmont 10:3bc89ef62ce7 146 // calculate the divider
emilmont 10:3bc89ef62ce7 147 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
emilmont 10:3bc89ef62ce7 148
emilmont 10:3bc89ef62ce7 149 // check we can support the divider
emilmont 10:3bc89ef62ce7 150 if (divider < 256) {
emilmont 10:3bc89ef62ce7 151 // prescaler
emilmont 10:3bc89ef62ce7 152 obj->spi->CPSR = prescaler;
emilmont 10:3bc89ef62ce7 153
emilmont 10:3bc89ef62ce7 154 // divider
emilmont 10:3bc89ef62ce7 155 obj->spi->CR0 &= ~(0xFFFF << 8);
emilmont 10:3bc89ef62ce7 156 obj->spi->CR0 |= (divider - 1) << 8;
emilmont 10:3bc89ef62ce7 157 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 158 return;
emilmont 10:3bc89ef62ce7 159 }
emilmont 10:3bc89ef62ce7 160 }
emilmont 10:3bc89ef62ce7 161 error("Couldn't setup requested SPI frequency");
emilmont 10:3bc89ef62ce7 162 }
emilmont 10:3bc89ef62ce7 163
emilmont 10:3bc89ef62ce7 164 static inline int ssp_disable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 165 return obj->spi->CR1 &= ~(1 << 1);
emilmont 10:3bc89ef62ce7 166 }
emilmont 10:3bc89ef62ce7 167
emilmont 10:3bc89ef62ce7 168 static inline int ssp_enable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 169 return obj->spi->CR1 |= (1 << 1);
emilmont 10:3bc89ef62ce7 170 }
emilmont 10:3bc89ef62ce7 171
emilmont 10:3bc89ef62ce7 172 static inline int ssp_readable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 173 return obj->spi->SR & (1 << 2);
emilmont 10:3bc89ef62ce7 174 }
emilmont 10:3bc89ef62ce7 175
emilmont 10:3bc89ef62ce7 176 static inline int ssp_writeable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 177 return obj->spi->SR & (1 << 1);
emilmont 10:3bc89ef62ce7 178 }
emilmont 10:3bc89ef62ce7 179
emilmont 10:3bc89ef62ce7 180 static inline void ssp_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 181 while (!ssp_writeable(obj));
emilmont 10:3bc89ef62ce7 182 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 183 }
emilmont 10:3bc89ef62ce7 184
emilmont 10:3bc89ef62ce7 185 static inline int ssp_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 186 while (!ssp_readable(obj));
emilmont 10:3bc89ef62ce7 187 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 188 }
emilmont 10:3bc89ef62ce7 189
emilmont 10:3bc89ef62ce7 190 static inline int ssp_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 191 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
emilmont 10:3bc89ef62ce7 192 }
emilmont 10:3bc89ef62ce7 193
emilmont 10:3bc89ef62ce7 194 int spi_master_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 195 ssp_write(obj, value);
emilmont 10:3bc89ef62ce7 196 return ssp_read(obj);
emilmont 10:3bc89ef62ce7 197 }
emilmont 10:3bc89ef62ce7 198
emilmont 10:3bc89ef62ce7 199 int spi_slave_receive(spi_t *obj) {
emilmont 10:3bc89ef62ce7 200 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
mbed_official 81:a9456fdf72fa 201 }
emilmont 10:3bc89ef62ce7 202
emilmont 10:3bc89ef62ce7 203 int spi_slave_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 204 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 205 }
emilmont 10:3bc89ef62ce7 206
emilmont 10:3bc89ef62ce7 207 void spi_slave_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 208 while (ssp_writeable(obj) == 0) ;
emilmont 10:3bc89ef62ce7 209 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 210 }
emilmont 10:3bc89ef62ce7 211
emilmont 10:3bc89ef62ce7 212 int spi_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 213 return ssp_busy(obj);
emilmont 10:3bc89ef62ce7 214 }