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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c@635:a11c0372f0ba, 2015-09-30 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Sep 30 17:00:09 2015 +0100
- Revision:
- 635:a11c0372f0ba
- Parent:
- 520:7182721120da
Synchronized with git revision d29c98dae61be0946ddf3a3c641c7726056f9452
Full URL: https://github.com/mbedmicro/mbed/commit/d29c98dae61be0946ddf3a3c641c7726056f9452/
Added support for SAMW25
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 489:119543c9f674 | 1 | /** |
| mbed_official | 489:119543c9f674 | 2 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 3 | * @file system_stm32f1xx.c |
| mbed_official | 489:119543c9f674 | 4 | * @author MCD Application Team |
| mbed_official | 489:119543c9f674 | 5 | * @version V4.0.0 |
| mbed_official | 489:119543c9f674 | 6 | * @date 16-December-2014 |
| mbed_official | 489:119543c9f674 | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
| mbed_official | 489:119543c9f674 | 8 | * |
| mbed_official | 489:119543c9f674 | 9 | * 1. This file provides two functions and one global variable to be called from |
| mbed_official | 489:119543c9f674 | 10 | * user application: |
| mbed_official | 489:119543c9f674 | 11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
| mbed_official | 489:119543c9f674 | 12 | * factors, AHB/APBx prescalers and Flash settings). |
| mbed_official | 489:119543c9f674 | 13 | * This function is called at startup just after reset and |
| mbed_official | 489:119543c9f674 | 14 | * before branch to main program. This call is made inside |
| mbed_official | 489:119543c9f674 | 15 | * the "startup_stm32f1xx_xx.s" file. |
| mbed_official | 489:119543c9f674 | 16 | * |
| mbed_official | 489:119543c9f674 | 17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| mbed_official | 489:119543c9f674 | 18 | * by the user application to setup the SysTick |
| mbed_official | 489:119543c9f674 | 19 | * timer or configure other parameters. |
| mbed_official | 489:119543c9f674 | 20 | * |
| mbed_official | 489:119543c9f674 | 21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| mbed_official | 489:119543c9f674 | 22 | * be called whenever the core clock is changed |
| mbed_official | 489:119543c9f674 | 23 | * during program execution. |
| mbed_official | 489:119543c9f674 | 24 | * |
| mbed_official | 489:119543c9f674 | 25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
| mbed_official | 489:119543c9f674 | 26 | * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to |
| mbed_official | 489:119543c9f674 | 27 | * configure the system clock before to branch to main program. |
| mbed_official | 489:119543c9f674 | 28 | * |
| mbed_official | 489:119543c9f674 | 29 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on |
| mbed_official | 489:119543c9f674 | 30 | * the product used), refer to "HSE_VALUE". |
| mbed_official | 489:119543c9f674 | 31 | * When HSE is used as system clock source, directly or through PLL, and you |
| mbed_official | 489:119543c9f674 | 32 | * are using different crystal you have to adapt the HSE value to your own |
| mbed_official | 489:119543c9f674 | 33 | * configuration. |
| mbed_official | 489:119543c9f674 | 34 | * |
| mbed_official | 489:119543c9f674 | 35 | * This file configures the system clock as follows: |
| mbed_official | 489:119543c9f674 | 36 | *----------------------------------------------------------------------------- |
| mbed_official | 489:119543c9f674 | 37 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
| mbed_official | 489:119543c9f674 | 38 | * | (external 8 MHz clock) | (internal 8 MHz) |
| mbed_official | 489:119543c9f674 | 39 | * | 2- PLL_HSE_XTAL | |
| mbed_official | 489:119543c9f674 | 40 | * | (external 8 MHz xtal) | |
| mbed_official | 489:119543c9f674 | 41 | *----------------------------------------------------------------------------- |
| mbed_official | 489:119543c9f674 | 42 | * SYSCLK(MHz) | 72 | 64 |
| mbed_official | 489:119543c9f674 | 43 | *----------------------------------------------------------------------------- |
| mbed_official | 489:119543c9f674 | 44 | * AHBCLK (MHz) | 72 | 64 |
| mbed_official | 489:119543c9f674 | 45 | *----------------------------------------------------------------------------- |
| mbed_official | 489:119543c9f674 | 46 | * APB1CLK (MHz) | 36 | 32 |
| mbed_official | 489:119543c9f674 | 47 | *----------------------------------------------------------------------------- |
| mbed_official | 489:119543c9f674 | 48 | * APB2CLK (MHz) | 72 | 64 |
| mbed_official | 489:119543c9f674 | 49 | *----------------------------------------------------------------------------- |
| mbed_official | 489:119543c9f674 | 50 | * USB capable (48 MHz precise clock) | NO | NO |
| mbed_official | 489:119543c9f674 | 51 | *----------------------------------------------------------------------------- |
| mbed_official | 489:119543c9f674 | 52 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 53 | * @attention |
| mbed_official | 489:119543c9f674 | 54 | * |
| mbed_official | 489:119543c9f674 | 55 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 489:119543c9f674 | 56 | * |
| mbed_official | 489:119543c9f674 | 57 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 489:119543c9f674 | 58 | * are permitted provided that the following conditions are met: |
| mbed_official | 489:119543c9f674 | 59 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 489:119543c9f674 | 60 | * this list of conditions and the following disclaimer. |
| mbed_official | 489:119543c9f674 | 61 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 489:119543c9f674 | 62 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 489:119543c9f674 | 63 | * and/or other materials provided with the distribution. |
| mbed_official | 489:119543c9f674 | 64 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 489:119543c9f674 | 65 | * may be used to endorse or promote products derived from this software |
| mbed_official | 489:119543c9f674 | 66 | * without specific prior written permission. |
| mbed_official | 489:119543c9f674 | 67 | * |
| mbed_official | 489:119543c9f674 | 68 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 489:119543c9f674 | 69 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 489:119543c9f674 | 70 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 489:119543c9f674 | 71 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 489:119543c9f674 | 72 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 489:119543c9f674 | 73 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 489:119543c9f674 | 74 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 489:119543c9f674 | 75 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 489:119543c9f674 | 76 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 489:119543c9f674 | 77 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 489:119543c9f674 | 78 | * |
| mbed_official | 489:119543c9f674 | 79 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 80 | */ |
| mbed_official | 489:119543c9f674 | 81 | |
| mbed_official | 489:119543c9f674 | 82 | /** @addtogroup CMSIS |
| mbed_official | 489:119543c9f674 | 83 | * @{ |
| mbed_official | 489:119543c9f674 | 84 | */ |
| mbed_official | 489:119543c9f674 | 85 | |
| mbed_official | 489:119543c9f674 | 86 | /** @addtogroup stm32f1xx_system |
| mbed_official | 489:119543c9f674 | 87 | * @{ |
| mbed_official | 489:119543c9f674 | 88 | */ |
| mbed_official | 489:119543c9f674 | 89 | |
| mbed_official | 489:119543c9f674 | 90 | /** @addtogroup STM32F1xx_System_Private_Includes |
| mbed_official | 489:119543c9f674 | 91 | * @{ |
| mbed_official | 489:119543c9f674 | 92 | */ |
| mbed_official | 489:119543c9f674 | 93 | |
| mbed_official | 489:119543c9f674 | 94 | #include "stm32f1xx.h" |
| mbed_official | 489:119543c9f674 | 95 | #include "hal_tick.h" |
| mbed_official | 489:119543c9f674 | 96 | |
| mbed_official | 489:119543c9f674 | 97 | /** |
| mbed_official | 489:119543c9f674 | 98 | * @} |
| mbed_official | 489:119543c9f674 | 99 | */ |
| mbed_official | 489:119543c9f674 | 100 | |
| mbed_official | 489:119543c9f674 | 101 | /** @addtogroup STM32F1xx_System_Private_TypesDefinitions |
| mbed_official | 489:119543c9f674 | 102 | * @{ |
| mbed_official | 489:119543c9f674 | 103 | */ |
| mbed_official | 489:119543c9f674 | 104 | |
| mbed_official | 489:119543c9f674 | 105 | /** |
| mbed_official | 489:119543c9f674 | 106 | * @} |
| mbed_official | 489:119543c9f674 | 107 | */ |
| mbed_official | 489:119543c9f674 | 108 | |
| mbed_official | 489:119543c9f674 | 109 | /** @addtogroup STM32F1xx_System_Private_Defines |
| mbed_official | 489:119543c9f674 | 110 | * @{ |
| mbed_official | 489:119543c9f674 | 111 | */ |
| mbed_official | 489:119543c9f674 | 112 | |
| mbed_official | 489:119543c9f674 | 113 | #if !defined (HSE_VALUE) |
| mbed_official | 489:119543c9f674 | 114 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
| mbed_official | 489:119543c9f674 | 115 | This value can be provided and adapted by the user application. */ |
| mbed_official | 489:119543c9f674 | 116 | #endif /* HSE_VALUE */ |
| mbed_official | 489:119543c9f674 | 117 | |
| mbed_official | 489:119543c9f674 | 118 | #if !defined (HSI_VALUE) |
| mbed_official | 489:119543c9f674 | 119 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. |
| mbed_official | 489:119543c9f674 | 120 | This value can be provided and adapted by the user application. */ |
| mbed_official | 489:119543c9f674 | 121 | #endif /* HSI_VALUE */ |
| mbed_official | 489:119543c9f674 | 122 | |
| mbed_official | 489:119543c9f674 | 123 | /*!< Uncomment the following line if you need to use external SRAM */ |
| mbed_official | 489:119543c9f674 | 124 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 489:119543c9f674 | 125 | /* #define DATA_IN_ExtSRAM */ |
| mbed_official | 489:119543c9f674 | 126 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
| mbed_official | 489:119543c9f674 | 127 | |
| mbed_official | 489:119543c9f674 | 128 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| mbed_official | 489:119543c9f674 | 129 | Internal SRAM. */ |
| mbed_official | 489:119543c9f674 | 130 | /* #define VECT_TAB_SRAM */ |
| mbed_official | 489:119543c9f674 | 131 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
| mbed_official | 489:119543c9f674 | 132 | This value must be a multiple of 0x200. */ |
| mbed_official | 489:119543c9f674 | 133 | |
| mbed_official | 489:119543c9f674 | 134 | |
| mbed_official | 489:119543c9f674 | 135 | /** |
| mbed_official | 489:119543c9f674 | 136 | * @} |
| mbed_official | 489:119543c9f674 | 137 | */ |
| mbed_official | 489:119543c9f674 | 138 | |
| mbed_official | 489:119543c9f674 | 139 | /** @addtogroup STM32F1xx_System_Private_Macros |
| mbed_official | 489:119543c9f674 | 140 | * @{ |
| mbed_official | 489:119543c9f674 | 141 | */ |
| mbed_official | 489:119543c9f674 | 142 | |
| mbed_official | 489:119543c9f674 | 143 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| mbed_official | 489:119543c9f674 | 144 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
| mbed_official | 489:119543c9f674 | 145 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| mbed_official | 489:119543c9f674 | 146 | |
| mbed_official | 489:119543c9f674 | 147 | /** |
| mbed_official | 489:119543c9f674 | 148 | * @} |
| mbed_official | 489:119543c9f674 | 149 | */ |
| mbed_official | 489:119543c9f674 | 150 | |
| mbed_official | 489:119543c9f674 | 151 | /** @addtogroup STM32F1xx_System_Private_Variables |
| mbed_official | 489:119543c9f674 | 152 | * @{ |
| mbed_official | 489:119543c9f674 | 153 | */ |
| mbed_official | 489:119543c9f674 | 154 | |
| mbed_official | 489:119543c9f674 | 155 | /******************************************************************************* |
| mbed_official | 489:119543c9f674 | 156 | * Clock Definitions |
| mbed_official | 489:119543c9f674 | 157 | *******************************************************************************/ |
| mbed_official | 489:119543c9f674 | 158 | #if defined(STM32F100xB) ||defined(STM32F100xE) |
| mbed_official | 489:119543c9f674 | 159 | uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */ |
| mbed_official | 489:119543c9f674 | 160 | #else /*!< HSI Selected as System Clock source */ |
| mbed_official | 489:119543c9f674 | 161 | uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ |
| mbed_official | 489:119543c9f674 | 162 | #endif |
| mbed_official | 489:119543c9f674 | 163 | |
| mbed_official | 520:7182721120da | 164 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| mbed_official | 489:119543c9f674 | 165 | /** |
| mbed_official | 489:119543c9f674 | 166 | * @} |
| mbed_official | 489:119543c9f674 | 167 | */ |
| mbed_official | 489:119543c9f674 | 168 | |
| mbed_official | 489:119543c9f674 | 169 | /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes |
| mbed_official | 489:119543c9f674 | 170 | * @{ |
| mbed_official | 489:119543c9f674 | 171 | */ |
| mbed_official | 489:119543c9f674 | 172 | |
| mbed_official | 489:119543c9f674 | 173 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 489:119543c9f674 | 174 | #ifdef DATA_IN_ExtSRAM |
| mbed_official | 489:119543c9f674 | 175 | static void SystemInit_ExtMemCtl(void); |
| mbed_official | 489:119543c9f674 | 176 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 489:119543c9f674 | 177 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
| mbed_official | 489:119543c9f674 | 178 | |
| mbed_official | 489:119543c9f674 | 179 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 489:119543c9f674 | 180 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| mbed_official | 489:119543c9f674 | 181 | #endif |
| mbed_official | 489:119543c9f674 | 182 | |
| mbed_official | 489:119543c9f674 | 183 | uint8_t SetSysClock_PLL_HSI(void); |
| mbed_official | 489:119543c9f674 | 184 | |
| mbed_official | 489:119543c9f674 | 185 | /** |
| mbed_official | 489:119543c9f674 | 186 | * @} |
| mbed_official | 489:119543c9f674 | 187 | */ |
| mbed_official | 489:119543c9f674 | 188 | |
| mbed_official | 489:119543c9f674 | 189 | /** @addtogroup STM32F1xx_System_Private_Functions |
| mbed_official | 489:119543c9f674 | 190 | * @{ |
| mbed_official | 489:119543c9f674 | 191 | */ |
| mbed_official | 489:119543c9f674 | 192 | |
| mbed_official | 489:119543c9f674 | 193 | /** |
| mbed_official | 489:119543c9f674 | 194 | * @brief Setup the microcontroller system |
| mbed_official | 489:119543c9f674 | 195 | * Initialize the Embedded Flash Interface, the PLL and update the |
| mbed_official | 489:119543c9f674 | 196 | * SystemCoreClock variable. |
| mbed_official | 489:119543c9f674 | 197 | * @note This function should be used only after reset. |
| mbed_official | 489:119543c9f674 | 198 | * @param None |
| mbed_official | 489:119543c9f674 | 199 | * @retval None |
| mbed_official | 489:119543c9f674 | 200 | */ |
| mbed_official | 489:119543c9f674 | 201 | void SystemInit (void) |
| mbed_official | 489:119543c9f674 | 202 | { |
| mbed_official | 489:119543c9f674 | 203 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ |
| mbed_official | 489:119543c9f674 | 204 | /* Set HSION bit */ |
| mbed_official | 489:119543c9f674 | 205 | RCC->CR |= (uint32_t)0x00000001; |
| mbed_official | 489:119543c9f674 | 206 | |
| mbed_official | 489:119543c9f674 | 207 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ |
| mbed_official | 489:119543c9f674 | 208 | #if !defined(STM32F105xC) && !defined(STM32F107xC) |
| mbed_official | 489:119543c9f674 | 209 | RCC->CFGR &= (uint32_t)0xF8FF0000; |
| mbed_official | 489:119543c9f674 | 210 | #else |
| mbed_official | 489:119543c9f674 | 211 | RCC->CFGR &= (uint32_t)0xF0FF0000; |
| mbed_official | 489:119543c9f674 | 212 | #endif /* STM32F105xC */ |
| mbed_official | 489:119543c9f674 | 213 | |
| mbed_official | 489:119543c9f674 | 214 | /* Reset HSEON, CSSON and PLLON bits */ |
| mbed_official | 489:119543c9f674 | 215 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| mbed_official | 489:119543c9f674 | 216 | |
| mbed_official | 489:119543c9f674 | 217 | /* Reset HSEBYP bit */ |
| mbed_official | 489:119543c9f674 | 218 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| mbed_official | 489:119543c9f674 | 219 | |
| mbed_official | 489:119543c9f674 | 220 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ |
| mbed_official | 489:119543c9f674 | 221 | RCC->CFGR &= (uint32_t)0xFF80FFFF; |
| mbed_official | 489:119543c9f674 | 222 | |
| mbed_official | 489:119543c9f674 | 223 | #if defined(STM32F105xC) || defined(STM32F107xC) |
| mbed_official | 489:119543c9f674 | 224 | /* Reset PLL2ON and PLL3ON bits */ |
| mbed_official | 489:119543c9f674 | 225 | RCC->CR &= (uint32_t)0xEBFFFFFF; |
| mbed_official | 489:119543c9f674 | 226 | |
| mbed_official | 489:119543c9f674 | 227 | /* Disable all interrupts and clear pending bits */ |
| mbed_official | 489:119543c9f674 | 228 | RCC->CIR = 0x00FF0000; |
| mbed_official | 489:119543c9f674 | 229 | |
| mbed_official | 489:119543c9f674 | 230 | /* Reset CFGR2 register */ |
| mbed_official | 489:119543c9f674 | 231 | RCC->CFGR2 = 0x00000000; |
| mbed_official | 489:119543c9f674 | 232 | #elif defined(STM32F100xB) || defined(STM32F100xE) |
| mbed_official | 489:119543c9f674 | 233 | /* Disable all interrupts and clear pending bits */ |
| mbed_official | 489:119543c9f674 | 234 | RCC->CIR = 0x009F0000; |
| mbed_official | 489:119543c9f674 | 235 | |
| mbed_official | 489:119543c9f674 | 236 | /* Reset CFGR2 register */ |
| mbed_official | 489:119543c9f674 | 237 | RCC->CFGR2 = 0x00000000; |
| mbed_official | 489:119543c9f674 | 238 | #else |
| mbed_official | 489:119543c9f674 | 239 | /* Disable all interrupts and clear pending bits */ |
| mbed_official | 489:119543c9f674 | 240 | RCC->CIR = 0x009F0000; |
| mbed_official | 489:119543c9f674 | 241 | #endif /* STM32F105xC */ |
| mbed_official | 489:119543c9f674 | 242 | |
| mbed_official | 489:119543c9f674 | 243 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 489:119543c9f674 | 244 | #ifdef DATA_IN_ExtSRAM |
| mbed_official | 489:119543c9f674 | 245 | SystemInit_ExtMemCtl(); |
| mbed_official | 489:119543c9f674 | 246 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 489:119543c9f674 | 247 | #endif |
| mbed_official | 489:119543c9f674 | 248 | |
| mbed_official | 489:119543c9f674 | 249 | #ifdef VECT_TAB_SRAM |
| mbed_official | 489:119543c9f674 | 250 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
| mbed_official | 489:119543c9f674 | 251 | #else |
| mbed_official | 489:119543c9f674 | 252 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
| mbed_official | 489:119543c9f674 | 253 | #endif |
| mbed_official | 489:119543c9f674 | 254 | |
| mbed_official | 489:119543c9f674 | 255 | /* Configure the Cube driver */ |
| mbed_official | 489:119543c9f674 | 256 | SystemCoreClock = 8000000; // At this stage the HSI is used as system clock |
| mbed_official | 489:119543c9f674 | 257 | HAL_Init(); |
| mbed_official | 489:119543c9f674 | 258 | |
| mbed_official | 489:119543c9f674 | 259 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 489:119543c9f674 | 260 | AHB/APBx prescalers and Flash settings */ |
| mbed_official | 489:119543c9f674 | 261 | SetSysClock(); |
| mbed_official | 489:119543c9f674 | 262 | |
| mbed_official | 489:119543c9f674 | 263 | /* Reset the timer to avoid issues after the RAM initialization */ |
| mbed_official | 489:119543c9f674 | 264 | TIM_MST_RESET_ON; |
| mbed_official | 489:119543c9f674 | 265 | TIM_MST_RESET_OFF; |
| mbed_official | 489:119543c9f674 | 266 | } |
| mbed_official | 489:119543c9f674 | 267 | |
| mbed_official | 489:119543c9f674 | 268 | /** |
| mbed_official | 489:119543c9f674 | 269 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| mbed_official | 489:119543c9f674 | 270 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| mbed_official | 489:119543c9f674 | 271 | * be used by the user application to setup the SysTick timer or configure |
| mbed_official | 489:119543c9f674 | 272 | * other parameters. |
| mbed_official | 489:119543c9f674 | 273 | * |
| mbed_official | 489:119543c9f674 | 274 | * @note Each time the core clock (HCLK) changes, this function must be called |
| mbed_official | 489:119543c9f674 | 275 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| mbed_official | 489:119543c9f674 | 276 | * based on this variable will be incorrect. |
| mbed_official | 489:119543c9f674 | 277 | * |
| mbed_official | 489:119543c9f674 | 278 | * @note - The system frequency computed by this function is not the real |
| mbed_official | 489:119543c9f674 | 279 | * frequency in the chip. It is calculated based on the predefined |
| mbed_official | 489:119543c9f674 | 280 | * constant and the selected clock source: |
| mbed_official | 489:119543c9f674 | 281 | * |
| mbed_official | 489:119543c9f674 | 282 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| mbed_official | 489:119543c9f674 | 283 | * |
| mbed_official | 489:119543c9f674 | 284 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 489:119543c9f674 | 285 | * |
| mbed_official | 489:119543c9f674 | 286 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 489:119543c9f674 | 287 | * or HSI_VALUE(*) multiplied by the PLL factors. |
| mbed_official | 489:119543c9f674 | 288 | * |
| mbed_official | 489:119543c9f674 | 289 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value |
| mbed_official | 489:119543c9f674 | 290 | * 8 MHz) but the real value may vary depending on the variations |
| mbed_official | 489:119543c9f674 | 291 | * in voltage and temperature. |
| mbed_official | 489:119543c9f674 | 292 | * |
| mbed_official | 489:119543c9f674 | 293 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value |
| mbed_official | 489:119543c9f674 | 294 | * 8 MHz or 25 MHz, depending on the product used), user has to ensure |
| mbed_official | 489:119543c9f674 | 295 | * that HSE_VALUE is same as the real frequency of the crystal used. |
| mbed_official | 489:119543c9f674 | 296 | * Otherwise, this function may have wrong result. |
| mbed_official | 489:119543c9f674 | 297 | * |
| mbed_official | 489:119543c9f674 | 298 | * - The result of this function could be not correct when using fractional |
| mbed_official | 489:119543c9f674 | 299 | * value for HSE crystal. |
| mbed_official | 489:119543c9f674 | 300 | * @param None |
| mbed_official | 489:119543c9f674 | 301 | * @retval None |
| mbed_official | 489:119543c9f674 | 302 | */ |
| mbed_official | 489:119543c9f674 | 303 | void SystemCoreClockUpdate (void) |
| mbed_official | 489:119543c9f674 | 304 | { |
| mbed_official | 489:119543c9f674 | 305 | uint32_t tmp = 0, pllmull = 0, pllsource = 0; |
| mbed_official | 489:119543c9f674 | 306 | |
| mbed_official | 489:119543c9f674 | 307 | #if defined(STM32F105xC) || defined(STM32F107xC) |
| mbed_official | 489:119543c9f674 | 308 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; |
| mbed_official | 489:119543c9f674 | 309 | #endif /* STM32F105xC */ |
| mbed_official | 489:119543c9f674 | 310 | |
| mbed_official | 489:119543c9f674 | 311 | #if defined(STM32F100xB) || defined(STM32F100xE) |
| mbed_official | 489:119543c9f674 | 312 | uint32_t prediv1factor = 0; |
| mbed_official | 489:119543c9f674 | 313 | #endif /* STM32F100xB or STM32F100xE */ |
| mbed_official | 489:119543c9f674 | 314 | |
| mbed_official | 489:119543c9f674 | 315 | /* Get SYSCLK source -------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 316 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| mbed_official | 489:119543c9f674 | 317 | |
| mbed_official | 489:119543c9f674 | 318 | switch (tmp) |
| mbed_official | 489:119543c9f674 | 319 | { |
| mbed_official | 489:119543c9f674 | 320 | case 0x00: /* HSI used as system clock */ |
| mbed_official | 489:119543c9f674 | 321 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 489:119543c9f674 | 322 | break; |
| mbed_official | 489:119543c9f674 | 323 | case 0x04: /* HSE used as system clock */ |
| mbed_official | 489:119543c9f674 | 324 | SystemCoreClock = HSE_VALUE; |
| mbed_official | 489:119543c9f674 | 325 | break; |
| mbed_official | 489:119543c9f674 | 326 | case 0x08: /* PLL used as system clock */ |
| mbed_official | 489:119543c9f674 | 327 | |
| mbed_official | 489:119543c9f674 | 328 | /* Get PLL clock source and multiplication factor ----------------------*/ |
| mbed_official | 489:119543c9f674 | 329 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
| mbed_official | 489:119543c9f674 | 330 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
| mbed_official | 489:119543c9f674 | 331 | |
| mbed_official | 489:119543c9f674 | 332 | #if !defined(STM32F105xC) && !defined(STM32F107xC) |
| mbed_official | 489:119543c9f674 | 333 | pllmull = ( pllmull >> 18) + 2; |
| mbed_official | 489:119543c9f674 | 334 | |
| mbed_official | 489:119543c9f674 | 335 | if (pllsource == 0x00) |
| mbed_official | 489:119543c9f674 | 336 | { |
| mbed_official | 489:119543c9f674 | 337 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
| mbed_official | 489:119543c9f674 | 338 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
| mbed_official | 489:119543c9f674 | 339 | } |
| mbed_official | 489:119543c9f674 | 340 | else |
| mbed_official | 489:119543c9f674 | 341 | { |
| mbed_official | 489:119543c9f674 | 342 | #if defined(STM32F100xB) || defined(STM32F100xE) |
| mbed_official | 489:119543c9f674 | 343 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
| mbed_official | 489:119543c9f674 | 344 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
| mbed_official | 489:119543c9f674 | 345 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
| mbed_official | 489:119543c9f674 | 346 | #else |
| mbed_official | 489:119543c9f674 | 347 | /* HSE selected as PLL clock entry */ |
| mbed_official | 489:119543c9f674 | 348 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) |
| mbed_official | 489:119543c9f674 | 349 | {/* HSE oscillator clock divided by 2 */ |
| mbed_official | 489:119543c9f674 | 350 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull; |
| mbed_official | 489:119543c9f674 | 351 | } |
| mbed_official | 489:119543c9f674 | 352 | else |
| mbed_official | 489:119543c9f674 | 353 | { |
| mbed_official | 489:119543c9f674 | 354 | SystemCoreClock = HSE_VALUE * pllmull; |
| mbed_official | 489:119543c9f674 | 355 | } |
| mbed_official | 489:119543c9f674 | 356 | #endif |
| mbed_official | 489:119543c9f674 | 357 | } |
| mbed_official | 489:119543c9f674 | 358 | #else |
| mbed_official | 489:119543c9f674 | 359 | pllmull = pllmull >> 18; |
| mbed_official | 489:119543c9f674 | 360 | |
| mbed_official | 489:119543c9f674 | 361 | if (pllmull != 0x0D) |
| mbed_official | 489:119543c9f674 | 362 | { |
| mbed_official | 489:119543c9f674 | 363 | pllmull += 2; |
| mbed_official | 489:119543c9f674 | 364 | } |
| mbed_official | 489:119543c9f674 | 365 | else |
| mbed_official | 489:119543c9f674 | 366 | { /* PLL multiplication factor = PLL input clock * 6.5 */ |
| mbed_official | 489:119543c9f674 | 367 | pllmull = 13 / 2; |
| mbed_official | 489:119543c9f674 | 368 | } |
| mbed_official | 489:119543c9f674 | 369 | |
| mbed_official | 489:119543c9f674 | 370 | if (pllsource == 0x00) |
| mbed_official | 489:119543c9f674 | 371 | { |
| mbed_official | 489:119543c9f674 | 372 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
| mbed_official | 489:119543c9f674 | 373 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
| mbed_official | 489:119543c9f674 | 374 | } |
| mbed_official | 489:119543c9f674 | 375 | else |
| mbed_official | 489:119543c9f674 | 376 | {/* PREDIV1 selected as PLL clock entry */ |
| mbed_official | 489:119543c9f674 | 377 | |
| mbed_official | 489:119543c9f674 | 378 | /* Get PREDIV1 clock source and division factor */ |
| mbed_official | 489:119543c9f674 | 379 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; |
| mbed_official | 489:119543c9f674 | 380 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
| mbed_official | 489:119543c9f674 | 381 | |
| mbed_official | 489:119543c9f674 | 382 | if (prediv1source == 0) |
| mbed_official | 489:119543c9f674 | 383 | { |
| mbed_official | 489:119543c9f674 | 384 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
| mbed_official | 489:119543c9f674 | 385 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
| mbed_official | 489:119543c9f674 | 386 | } |
| mbed_official | 489:119543c9f674 | 387 | else |
| mbed_official | 489:119543c9f674 | 388 | {/* PLL2 clock selected as PREDIV1 clock entry */ |
| mbed_official | 489:119543c9f674 | 389 | |
| mbed_official | 489:119543c9f674 | 390 | /* Get PREDIV2 division factor and PLL2 multiplication factor */ |
| mbed_official | 489:119543c9f674 | 391 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; |
| mbed_official | 489:119543c9f674 | 392 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; |
| mbed_official | 489:119543c9f674 | 393 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; |
| mbed_official | 489:119543c9f674 | 394 | } |
| mbed_official | 489:119543c9f674 | 395 | } |
| mbed_official | 489:119543c9f674 | 396 | #endif /* STM32F105xC */ |
| mbed_official | 489:119543c9f674 | 397 | break; |
| mbed_official | 489:119543c9f674 | 398 | |
| mbed_official | 489:119543c9f674 | 399 | default: |
| mbed_official | 489:119543c9f674 | 400 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 489:119543c9f674 | 401 | break; |
| mbed_official | 489:119543c9f674 | 402 | } |
| mbed_official | 489:119543c9f674 | 403 | |
| mbed_official | 489:119543c9f674 | 404 | /* Compute HCLK clock frequency ----------------*/ |
| mbed_official | 489:119543c9f674 | 405 | /* Get HCLK prescaler */ |
| mbed_official | 489:119543c9f674 | 406 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| mbed_official | 489:119543c9f674 | 407 | /* HCLK clock frequency */ |
| mbed_official | 489:119543c9f674 | 408 | SystemCoreClock >>= tmp; |
| mbed_official | 489:119543c9f674 | 409 | } |
| mbed_official | 489:119543c9f674 | 410 | |
| mbed_official | 489:119543c9f674 | 411 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| mbed_official | 489:119543c9f674 | 412 | /** |
| mbed_official | 489:119543c9f674 | 413 | * @brief Setup the external memory controller. Called in startup_stm32f1xx.s |
| mbed_official | 489:119543c9f674 | 414 | * before jump to __main |
| mbed_official | 489:119543c9f674 | 415 | * @param None |
| mbed_official | 489:119543c9f674 | 416 | * @retval None |
| mbed_official | 489:119543c9f674 | 417 | */ |
| mbed_official | 489:119543c9f674 | 418 | #ifdef DATA_IN_ExtSRAM |
| mbed_official | 489:119543c9f674 | 419 | /** |
| mbed_official | 489:119543c9f674 | 420 | * @brief Setup the external memory controller. |
| mbed_official | 489:119543c9f674 | 421 | * Called in startup_stm32f1xx_xx.s/.c before jump to main. |
| mbed_official | 489:119543c9f674 | 422 | * This function configures the external SRAM mounted on STM3210E-EVAL |
| mbed_official | 489:119543c9f674 | 423 | * board (STM32 High density devices). This SRAM will be used as program |
| mbed_official | 489:119543c9f674 | 424 | * data memory (including heap and stack). |
| mbed_official | 489:119543c9f674 | 425 | * @param None |
| mbed_official | 489:119543c9f674 | 426 | * @retval None |
| mbed_official | 489:119543c9f674 | 427 | */ |
| mbed_official | 489:119543c9f674 | 428 | void SystemInit_ExtMemCtl(void) |
| mbed_official | 489:119543c9f674 | 429 | { |
| mbed_official | 489:119543c9f674 | 430 | __IO uint32_t tmpreg; |
| mbed_official | 489:119543c9f674 | 431 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is |
| mbed_official | 489:119543c9f674 | 432 | required, then adjust the Register Addresses */ |
| mbed_official | 489:119543c9f674 | 433 | |
| mbed_official | 489:119543c9f674 | 434 | /* Enable FSMC clock */ |
| mbed_official | 489:119543c9f674 | 435 | RCC->AHBENR = 0x00000114; |
| mbed_official | 489:119543c9f674 | 436 | |
| mbed_official | 489:119543c9f674 | 437 | /* Delay after an RCC peripheral clock enabling */ |
| mbed_official | 489:119543c9f674 | 438 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); |
| mbed_official | 489:119543c9f674 | 439 | |
| mbed_official | 489:119543c9f674 | 440 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ |
| mbed_official | 489:119543c9f674 | 441 | RCC->APB2ENR = 0x000001E0; |
| mbed_official | 489:119543c9f674 | 442 | |
| mbed_official | 489:119543c9f674 | 443 | /* Delay after an RCC peripheral clock enabling */ |
| mbed_official | 489:119543c9f674 | 444 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); |
| mbed_official | 489:119543c9f674 | 445 | |
| mbed_official | 489:119543c9f674 | 446 | (void)(tmpreg); |
| mbed_official | 489:119543c9f674 | 447 | |
| mbed_official | 489:119543c9f674 | 448 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ |
| mbed_official | 489:119543c9f674 | 449 | /*---------------- SRAM Address lines configuration -------------------------*/ |
| mbed_official | 489:119543c9f674 | 450 | /*---------------- NOE and NWE configuration --------------------------------*/ |
| mbed_official | 489:119543c9f674 | 451 | /*---------------- NE3 configuration ----------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 452 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/ |
| mbed_official | 489:119543c9f674 | 453 | |
| mbed_official | 489:119543c9f674 | 454 | GPIOD->CRL = 0x44BB44BB; |
| mbed_official | 489:119543c9f674 | 455 | GPIOD->CRH = 0xBBBBBBBB; |
| mbed_official | 489:119543c9f674 | 456 | |
| mbed_official | 489:119543c9f674 | 457 | GPIOE->CRL = 0xB44444BB; |
| mbed_official | 489:119543c9f674 | 458 | GPIOE->CRH = 0xBBBBBBBB; |
| mbed_official | 489:119543c9f674 | 459 | |
| mbed_official | 489:119543c9f674 | 460 | GPIOF->CRL = 0x44BBBBBB; |
| mbed_official | 489:119543c9f674 | 461 | GPIOF->CRH = 0xBBBB4444; |
| mbed_official | 489:119543c9f674 | 462 | |
| mbed_official | 489:119543c9f674 | 463 | GPIOG->CRL = 0x44BBBBBB; |
| mbed_official | 489:119543c9f674 | 464 | GPIOG->CRH = 0x444B4B44; |
| mbed_official | 489:119543c9f674 | 465 | |
| mbed_official | 489:119543c9f674 | 466 | /*---------------- FSMC Configuration ---------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 467 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ |
| mbed_official | 489:119543c9f674 | 468 | |
| mbed_official | 489:119543c9f674 | 469 | FSMC_Bank1->BTCR[4] = 0x00001091; |
| mbed_official | 489:119543c9f674 | 470 | FSMC_Bank1->BTCR[5] = 0x00110212; |
| mbed_official | 489:119543c9f674 | 471 | } |
| mbed_official | 489:119543c9f674 | 472 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 489:119543c9f674 | 473 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
| mbed_official | 489:119543c9f674 | 474 | |
| mbed_official | 489:119543c9f674 | 475 | /** |
| mbed_official | 489:119543c9f674 | 476 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 489:119543c9f674 | 477 | * AHB/APBx prescalers and Flash settings |
| mbed_official | 489:119543c9f674 | 478 | * @note This function should be called only once the RCC clock configuration |
| mbed_official | 489:119543c9f674 | 479 | * is reset to the default reset state (done in SystemInit() function). |
| mbed_official | 489:119543c9f674 | 480 | * @param None |
| mbed_official | 489:119543c9f674 | 481 | * @retval None |
| mbed_official | 489:119543c9f674 | 482 | */ |
| mbed_official | 489:119543c9f674 | 483 | void SetSysClock(void) |
| mbed_official | 489:119543c9f674 | 484 | { |
| mbed_official | 489:119543c9f674 | 485 | /* 1- Try to start with HSE and external clock */ |
| mbed_official | 489:119543c9f674 | 486 | #if USE_PLL_HSE_EXTC != 0 |
| mbed_official | 489:119543c9f674 | 487 | if (SetSysClock_PLL_HSE(1) == 0) |
| mbed_official | 489:119543c9f674 | 488 | #endif |
| mbed_official | 489:119543c9f674 | 489 | { |
| mbed_official | 489:119543c9f674 | 490 | /* 2- If fail try to start with HSE and external xtal */ |
| mbed_official | 489:119543c9f674 | 491 | #if USE_PLL_HSE_XTAL != 0 |
| mbed_official | 489:119543c9f674 | 492 | if (SetSysClock_PLL_HSE(0) == 0) |
| mbed_official | 489:119543c9f674 | 493 | #endif |
| mbed_official | 489:119543c9f674 | 494 | { |
| mbed_official | 489:119543c9f674 | 495 | /* 3- If fail start with HSI clock */ |
| mbed_official | 489:119543c9f674 | 496 | if (SetSysClock_PLL_HSI() == 0) |
| mbed_official | 489:119543c9f674 | 497 | { |
| mbed_official | 489:119543c9f674 | 498 | while(1) |
| mbed_official | 489:119543c9f674 | 499 | { |
| mbed_official | 489:119543c9f674 | 500 | // [TODO] Put something here to tell the user that a problem occured... |
| mbed_official | 489:119543c9f674 | 501 | } |
| mbed_official | 489:119543c9f674 | 502 | } |
| mbed_official | 489:119543c9f674 | 503 | } |
| mbed_official | 489:119543c9f674 | 504 | } |
| mbed_official | 489:119543c9f674 | 505 | |
| mbed_official | 489:119543c9f674 | 506 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 489:119543c9f674 | 507 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz |
| mbed_official | 489:119543c9f674 | 508 | } |
| mbed_official | 489:119543c9f674 | 509 | |
| mbed_official | 489:119543c9f674 | 510 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 489:119543c9f674 | 511 | /******************************************************************************/ |
| mbed_official | 489:119543c9f674 | 512 | /* PLL (clocked by HSE) used as System clock source */ |
| mbed_official | 489:119543c9f674 | 513 | /******************************************************************************/ |
| mbed_official | 489:119543c9f674 | 514 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| mbed_official | 489:119543c9f674 | 515 | { |
| mbed_official | 489:119543c9f674 | 516 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 489:119543c9f674 | 517 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 489:119543c9f674 | 518 | |
| mbed_official | 489:119543c9f674 | 519 | /* Enable HSE oscillator and activate PLL with HSE as source */ |
| mbed_official | 489:119543c9f674 | 520 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 489:119543c9f674 | 521 | if (bypass == 0) |
| mbed_official | 489:119543c9f674 | 522 | { |
| mbed_official | 489:119543c9f674 | 523 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
| mbed_official | 489:119543c9f674 | 524 | } |
| mbed_official | 489:119543c9f674 | 525 | else |
| mbed_official | 489:119543c9f674 | 526 | { |
| mbed_official | 489:119543c9f674 | 527 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
| mbed_official | 489:119543c9f674 | 528 | } |
| mbed_official | 489:119543c9f674 | 529 | RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; |
| mbed_official | 489:119543c9f674 | 530 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 489:119543c9f674 | 531 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 489:119543c9f674 | 532 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) |
| mbed_official | 489:119543c9f674 | 533 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 489:119543c9f674 | 534 | { |
| mbed_official | 489:119543c9f674 | 535 | return 0; // FAIL |
| mbed_official | 489:119543c9f674 | 536 | } |
| mbed_official | 489:119543c9f674 | 537 | |
| mbed_official | 489:119543c9f674 | 538 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 489:119543c9f674 | 539 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 489:119543c9f674 | 540 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz |
| mbed_official | 489:119543c9f674 | 541 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz |
| mbed_official | 489:119543c9f674 | 542 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz |
| mbed_official | 489:119543c9f674 | 543 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz |
| mbed_official | 489:119543c9f674 | 544 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) |
| mbed_official | 489:119543c9f674 | 545 | { |
| mbed_official | 489:119543c9f674 | 546 | return 0; // FAIL |
| mbed_official | 489:119543c9f674 | 547 | } |
| mbed_official | 489:119543c9f674 | 548 | |
| mbed_official | 489:119543c9f674 | 549 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 489:119543c9f674 | 550 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
| mbed_official | 489:119543c9f674 | 551 | |
| mbed_official | 489:119543c9f674 | 552 | return 1; // OK |
| mbed_official | 489:119543c9f674 | 553 | } |
| mbed_official | 489:119543c9f674 | 554 | #endif |
| mbed_official | 489:119543c9f674 | 555 | |
| mbed_official | 489:119543c9f674 | 556 | /******************************************************************************/ |
| mbed_official | 489:119543c9f674 | 557 | /* PLL (clocked by HSI) used as System clock source */ |
| mbed_official | 489:119543c9f674 | 558 | /******************************************************************************/ |
| mbed_official | 489:119543c9f674 | 559 | uint8_t SetSysClock_PLL_HSI(void) |
| mbed_official | 489:119543c9f674 | 560 | { |
| mbed_official | 489:119543c9f674 | 561 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 489:119543c9f674 | 562 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 489:119543c9f674 | 563 | |
| mbed_official | 489:119543c9f674 | 564 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
| mbed_official | 489:119543c9f674 | 565 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 489:119543c9f674 | 566 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| mbed_official | 489:119543c9f674 | 567 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| mbed_official | 489:119543c9f674 | 568 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
| mbed_official | 489:119543c9f674 | 569 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 489:119543c9f674 | 570 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; |
| mbed_official | 489:119543c9f674 | 571 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) |
| mbed_official | 489:119543c9f674 | 572 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 489:119543c9f674 | 573 | { |
| mbed_official | 489:119543c9f674 | 574 | return 0; // FAIL |
| mbed_official | 489:119543c9f674 | 575 | } |
| mbed_official | 489:119543c9f674 | 576 | |
| mbed_official | 489:119543c9f674 | 577 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 489:119543c9f674 | 578 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 489:119543c9f674 | 579 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz |
| mbed_official | 489:119543c9f674 | 580 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz |
| mbed_official | 489:119543c9f674 | 581 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz |
| mbed_official | 489:119543c9f674 | 582 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz |
| mbed_official | 489:119543c9f674 | 583 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) |
| mbed_official | 489:119543c9f674 | 584 | { |
| mbed_official | 489:119543c9f674 | 585 | return 0; // FAIL |
| mbed_official | 489:119543c9f674 | 586 | } |
| mbed_official | 489:119543c9f674 | 587 | |
| mbed_official | 489:119543c9f674 | 588 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 489:119543c9f674 | 589 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz |
| mbed_official | 489:119543c9f674 | 590 | |
| mbed_official | 489:119543c9f674 | 591 | return 1; // OK |
| mbed_official | 489:119543c9f674 | 592 | } |
| mbed_official | 489:119543c9f674 | 593 | |
| mbed_official | 489:119543c9f674 | 594 | /** |
| mbed_official | 489:119543c9f674 | 595 | * @} |
| mbed_official | 489:119543c9f674 | 596 | */ |
| mbed_official | 489:119543c9f674 | 597 | |
| mbed_official | 489:119543c9f674 | 598 | /** |
| mbed_official | 489:119543c9f674 | 599 | * @} |
| mbed_official | 489:119543c9f674 | 600 | */ |
| mbed_official | 489:119543c9f674 | 601 | |
| mbed_official | 489:119543c9f674 | 602 | /** |
| mbed_official | 489:119543c9f674 | 603 | * @} |
| mbed_official | 489:119543c9f674 | 604 | */ |
| mbed_official | 489:119543c9f674 | 605 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
