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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c@463:5c73c3744533, 2015-02-03 (annotated)

Committer:
mbed_official
Date:
Tue Feb 03 17:00:07 2015 +0000
Revision:
463:5c73c3744533
Parent:
285:31249416b6f9 
Synchronized with git revision 134a67aab259d410373367cb96b73420b390d385



Full URL: https://github.com/mbedmicro/mbed/commit/134a67aab259d410373367cb96b73420b390d385/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /* mbed Microcontroller Library
bogdanm 20:4263a77256ae 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 20:4263a77256ae 3 *
bogdanm 20:4263a77256ae 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 20:4263a77256ae 5 * you may not use this file except in compliance with the License.
bogdanm 20:4263a77256ae 6 * You may obtain a copy of the License at
bogdanm 20:4263a77256ae 7 *
bogdanm 20:4263a77256ae 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 20:4263a77256ae 9 *
bogdanm 20:4263a77256ae 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 20:4263a77256ae 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 20:4263a77256ae 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 20:4263a77256ae 13 * See the License for the specific language governing permissions and
bogdanm 20:4263a77256ae 14 * limitations under the License.
bogdanm 20:4263a77256ae 15 *
bogdanm 20:4263a77256ae 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
bogdanm 20:4263a77256ae 17 */
bogdanm 20:4263a77256ae 18 #include <stddef.h>
bogdanm 20:4263a77256ae 19 #include "gpio_irq_api.h"
mbed_official 285:31249416b6f9 20 #include "mbed_error.h"
bogdanm 20:4263a77256ae 21 #include "cmsis.h"
bogdanm 20:4263a77256ae 22
bogdanm 20:4263a77256ae 23 /* The LPC43xx implements GPIO pin and group interrupts. Any pin in the
bogdanm 20:4263a77256ae 24 * 8 32-bit GPIO ports can interrupt. On group interrupts a pin can
bogdanm 20:4263a77256ae 25 * only interrupt on the rising or falling edge, not both as required
bogdanm 20:4263a77256ae 26 * by mbed. Also, group interrupts can't be cleared individually.
bogdanm 20:4263a77256ae 27 * This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
bogdanm 20:4263a77256ae 28 * A future implementation may provide group interrupt support.
bogdanm 20:4263a77256ae 29 */
bogdanm 20:4263a77256ae 30 #if !defined(CORE_M0)
mbed_official 256:76fd9a263045 31 #define CHANNEL_MAX 8
bogdanm 20:4263a77256ae 32 #else
mbed_official 256:76fd9a263045 33 #define CHANNEL_MAX 1
bogdanm 20:4263a77256ae 34 #endif
bogdanm 20:4263a77256ae 35
mbed_official 256:76fd9a263045 36 static uint32_t channel_ids[CHANNEL_MAX] = {0};
mbed_official 256:76fd9a263045 37 static uint8_t channel = 0;
bogdanm 20:4263a77256ae 38 static gpio_irq_handler irq_handler;
bogdanm 20:4263a77256ae 39
bogdanm 20:4263a77256ae 40 static void handle_interrupt_in(void) {
bogdanm 20:4263a77256ae 41 uint32_t rise = LPC_GPIO_PIN_INT->RISE;
bogdanm 20:4263a77256ae 42 uint32_t fall = LPC_GPIO_PIN_INT->FALL;
bogdanm 20:4263a77256ae 43 uint32_t pmask;
bogdanm 20:4263a77256ae 44 int i;
bogdanm 20:4263a77256ae 45
mbed_official 256:76fd9a263045 46 for (i = 0; i < CHANNEL_MAX; i++) {
bogdanm 20:4263a77256ae 47 pmask = (1 << i);
bogdanm 20:4263a77256ae 48 if (rise & pmask) {
bogdanm 20:4263a77256ae 49 /* Rising edge interrupts */
mbed_official 256:76fd9a263045 50 if (channel_ids[i] != 0) {
bogdanm 20:4263a77256ae 51 irq_handler(channel_ids[i], IRQ_RISE);
mbed_official 256:76fd9a263045 52 }
bogdanm 20:4263a77256ae 53 /* Clear rising edge detected */
bogdanm 20:4263a77256ae 54 LPC_GPIO_PIN_INT->RISE = pmask;
bogdanm 20:4263a77256ae 55 }
bogdanm 20:4263a77256ae 56 if (fall & pmask) {
bogdanm 20:4263a77256ae 57 /* Falling edge interrupts */
mbed_official 256:76fd9a263045 58 if (channel_ids[i] != 0) {
bogdanm 20:4263a77256ae 59 irq_handler(channel_ids[i], IRQ_FALL);
mbed_official 256:76fd9a263045 60 }
bogdanm 20:4263a77256ae 61 /* Clear falling edge detected */
bogdanm 20:4263a77256ae 62 LPC_GPIO_PIN_INT->FALL = pmask;
bogdanm 20:4263a77256ae 63 }
bogdanm 20:4263a77256ae 64 }
bogdanm 20:4263a77256ae 65 }
bogdanm 20:4263a77256ae 66
bogdanm 20:4263a77256ae 67 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 20:4263a77256ae 68 uint32_t portnum, pinnum; //, pmask;
bogdanm 20:4263a77256ae 69
bogdanm 20:4263a77256ae 70 if (pin == NC) return -1;
bogdanm 20:4263a77256ae 71
bogdanm 20:4263a77256ae 72 irq_handler = handler;
bogdanm 20:4263a77256ae 73
bogdanm 20:4263a77256ae 74 /* Set port and pin numbers */
bogdanm 20:4263a77256ae 75 obj->port = portnum = MBED_GPIO_PORT(pin);
bogdanm 20:4263a77256ae 76 obj->pin = pinnum = MBED_GPIO_PIN(pin);
bogdanm 20:4263a77256ae 77
bogdanm 20:4263a77256ae 78 /* Add to channel table */
bogdanm 20:4263a77256ae 79 channel_ids[channel] = id;
bogdanm 20:4263a77256ae 80 obj->ch = channel;
bogdanm 20:4263a77256ae 81
bogdanm 20:4263a77256ae 82 /* Clear rising and falling edge detection */
bogdanm 20:4263a77256ae 83 //pmask = (1 << channel);
bogdanm 20:4263a77256ae 84 //LPC_GPIO_PIN_INT->IST = pmask;
bogdanm 20:4263a77256ae 85
bogdanm 20:4263a77256ae 86 /* Set SCU */
bogdanm 20:4263a77256ae 87 if (channel < 4) {
bogdanm 20:4263a77256ae 88 LPC_SCU->PINTSEL0 &= ~(0xFF << (portnum << 3));
bogdanm 20:4263a77256ae 89 LPC_SCU->PINTSEL0 |= (((portnum << 5) | pinnum) << (channel << 3));
bogdanm 20:4263a77256ae 90 } else {
bogdanm 20:4263a77256ae 91 LPC_SCU->PINTSEL1 &= ~(0xFF << ((portnum - 4) << 3));
bogdanm 20:4263a77256ae 92 LPC_SCU->PINTSEL1 |= (((portnum << 5) | pinnum) << ((channel - 4) << 3));
bogdanm 20:4263a77256ae 93 }
bogdanm 20:4263a77256ae 94
bogdanm 20:4263a77256ae 95 #if !defined(CORE_M0)
bogdanm 20:4263a77256ae 96 NVIC_SetVector((IRQn_Type)(PIN_INT0_IRQn + channel), (uint32_t)handle_interrupt_in);
bogdanm 20:4263a77256ae 97 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + channel));
bogdanm 20:4263a77256ae 98 #else
bogdanm 20:4263a77256ae 99 NVIC_SetVector((IRQn_Type)PIN_INT4_IRQn, (uint32_t)handle_interrupt_in);
bogdanm 20:4263a77256ae 100 NVIC_EnableIRQ((IRQn_Type)PIN_INT4_IRQn);
bogdanm 20:4263a77256ae 101 #endif
bogdanm 20:4263a77256ae 102
bogdanm 20:4263a77256ae 103 // Increment channel number
bogdanm 20:4263a77256ae 104 channel++;
mbed_official 256:76fd9a263045 105 channel %= CHANNEL_MAX;
bogdanm 20:4263a77256ae 106
bogdanm 20:4263a77256ae 107 return 0;
bogdanm 20:4263a77256ae 108 }
bogdanm 20:4263a77256ae 109
bogdanm 20:4263a77256ae 110 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 20:4263a77256ae 111 channel_ids[obj->ch] = 0;
bogdanm 20:4263a77256ae 112 }
bogdanm 20:4263a77256ae 113
bogdanm 20:4263a77256ae 114 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 20:4263a77256ae 115 uint32_t pmask;
bogdanm 20:4263a77256ae 116
bogdanm 20:4263a77256ae 117 /* Clear pending interrupts */
bogdanm 20:4263a77256ae 118 pmask = (1 << obj->ch);
bogdanm 20:4263a77256ae 119 LPC_GPIO_PIN_INT->IST = pmask;
bogdanm 20:4263a77256ae 120
bogdanm 20:4263a77256ae 121 /* Configure pin interrupt */
bogdanm 20:4263a77256ae 122 LPC_GPIO_PIN_INT->ISEL &= ~pmask;
bogdanm 20:4263a77256ae 123 if (event == IRQ_RISE) {
bogdanm 20:4263a77256ae 124 /* Rising edge interrupts */
bogdanm 20:4263a77256ae 125 if (enable) {
bogdanm 20:4263a77256ae 126 LPC_GPIO_PIN_INT->SIENR |= pmask;
bogdanm 20:4263a77256ae 127 } else {
bogdanm 20:4263a77256ae 128 LPC_GPIO_PIN_INT->CIENR |= pmask;
bogdanm 20:4263a77256ae 129 }
bogdanm 20:4263a77256ae 130 } else {
bogdanm 20:4263a77256ae 131 /* Falling edge interrupts */
bogdanm 20:4263a77256ae 132 if (enable) {
bogdanm 20:4263a77256ae 133 LPC_GPIO_PIN_INT->SIENF |= pmask;
bogdanm 20:4263a77256ae 134 } else {
bogdanm 20:4263a77256ae 135 LPC_GPIO_PIN_INT->CIENF |= pmask;
bogdanm 20:4263a77256ae 136 }
bogdanm 20:4263a77256ae 137 }
bogdanm 20:4263a77256ae 138 }
mbed_official 35:371630885ad6 139
mbed_official 35:371630885ad6 140 void gpio_irq_enable(gpio_irq_t *obj) {
mbed_official 35:371630885ad6 141 #if !defined(CORE_M0)
mbed_official 35:371630885ad6 142 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
mbed_official 35:371630885ad6 143 #else
mbed_official 35:371630885ad6 144 NVIC_EnableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
mbed_official 35:371630885ad6 145 #endif
mbed_official 35:371630885ad6 146 }
mbed_official 35:371630885ad6 147
mbed_official 35:371630885ad6 148 void gpio_irq_disable(gpio_irq_t *obj) {
mbed_official 35:371630885ad6 149 #if !defined(CORE_M0)
mbed_official 35:371630885ad6 150 NVIC_DisableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
mbed_official 35:371630885ad6 151 #else
mbed_official 35:371630885ad6 152 NVIC_DisableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
mbed_official 35:371630885ad6 153 #endif
mbed_official 35:371630885ad6 154 }