mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c@463:5c73c3744533, 2015-02-03 (annotated)

Committer:
mbed_official
Date:
Tue Feb 03 17:00:07 2015 +0000
Revision:
463:5c73c3744533
Parent:
285:31249416b6f9
Child:
552:a1b9575155a3
Synchronized with git revision 134a67aab259d410373367cb96b73420b390d385



Full URL: https://github.com/mbedmicro/mbed/commit/134a67aab259d410373367cb96b73420b390d385/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
emilmont 10:3bc89ef62ce7 17 #include <math.h>
emilmont 10:3bc89ef62ce7 18 #include "spi_api.h"
emilmont 10:3bc89ef62ce7 19 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 20 #include "pinmap.h"
mbed_official 285:31249416b6f9 21 #include "mbed_error.h"
mbed_official 274:6937b19af361 22 #include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 static inline int ssp_disable(spi_t *obj);
emilmont 10:3bc89ef62ce7 25 static inline int ssp_enable(spi_t *obj);
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
emilmont 10:3bc89ef62ce7 28 // determine the SPI to use
emilmont 10:3bc89ef62ce7 29 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 30 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 31 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 32 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 33 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
emilmont 10:3bc89ef62ce7 34 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
emilmont 10:3bc89ef62ce7 35
emilmont 10:3bc89ef62ce7 36 obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
mbed_official 227:7bd0639b8911 37 MBED_ASSERT((int)obj->spi != NC);
emilmont 10:3bc89ef62ce7 38
emilmont 10:3bc89ef62ce7 39 // enable power and clocking
emilmont 10:3bc89ef62ce7 40 switch ((int)obj->spi) {
emilmont 10:3bc89ef62ce7 41 case SPI_0:
emilmont 10:3bc89ef62ce7 42 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
emilmont 10:3bc89ef62ce7 43 LPC_SYSCON->SSP0CLKDIV = 0x01;
emilmont 10:3bc89ef62ce7 44 LPC_SYSCON->PRESETCTRL |= 1 << 0;
emilmont 10:3bc89ef62ce7 45 break;
emilmont 10:3bc89ef62ce7 46 case SPI_1:
emilmont 10:3bc89ef62ce7 47 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
emilmont 10:3bc89ef62ce7 48 LPC_SYSCON->SSP1CLKDIV = 0x01;
emilmont 10:3bc89ef62ce7 49 LPC_SYSCON->PRESETCTRL |= 1 << 2;
emilmont 10:3bc89ef62ce7 50 break;
emilmont 10:3bc89ef62ce7 51 }
emilmont 10:3bc89ef62ce7 52
emilmont 10:3bc89ef62ce7 53 // set default format and frequency
emilmont 10:3bc89ef62ce7 54 if (ssel == NC) {
emilmont 10:3bc89ef62ce7 55 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
emilmont 10:3bc89ef62ce7 56 } else {
emilmont 10:3bc89ef62ce7 57 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
emilmont 10:3bc89ef62ce7 58 }
emilmont 10:3bc89ef62ce7 59 spi_frequency(obj, 1000000);
emilmont 10:3bc89ef62ce7 60
emilmont 10:3bc89ef62ce7 61 // enable the ssp channel
emilmont 10:3bc89ef62ce7 62 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 63
emilmont 10:3bc89ef62ce7 64 // pin out the spi pins
emilmont 10:3bc89ef62ce7 65 pinmap_pinout(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 66 pinmap_pinout(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 67 pinmap_pinout(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 68 if (ssel != NC) {
emilmont 10:3bc89ef62ce7 69 pinmap_pinout(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 70 }
emilmont 10:3bc89ef62ce7 71 }
emilmont 10:3bc89ef62ce7 72
emilmont 10:3bc89ef62ce7 73 void spi_free(spi_t *obj) {}
emilmont 10:3bc89ef62ce7 74
emilmont 10:3bc89ef62ce7 75 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 227:7bd0639b8911 76 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
mbed_official 227:7bd0639b8911 77
emilmont 10:3bc89ef62ce7 78 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 int polarity = (mode & 0x2) ? 1 : 0;
emilmont 10:3bc89ef62ce7 81 int phase = (mode & 0x1) ? 1 : 0;
emilmont 10:3bc89ef62ce7 82
emilmont 10:3bc89ef62ce7 83 // set it up
emilmont 10:3bc89ef62ce7 84 int DSS = bits - 1; // DSS (data select size)
emilmont 10:3bc89ef62ce7 85 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
emilmont 10:3bc89ef62ce7 86 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
emilmont 10:3bc89ef62ce7 87
emilmont 10:3bc89ef62ce7 88 int FRF = 0; // FRF (frame format) = SPI
emilmont 10:3bc89ef62ce7 89 uint32_t tmp = obj->spi->CR0;
emilmont 10:3bc89ef62ce7 90 tmp &= ~(0xFFFF);
emilmont 10:3bc89ef62ce7 91 tmp |= DSS << 0
emilmont 10:3bc89ef62ce7 92 | FRF << 4
emilmont 10:3bc89ef62ce7 93 | SPO << 6
emilmont 10:3bc89ef62ce7 94 | SPH << 7;
emilmont 10:3bc89ef62ce7 95 obj->spi->CR0 = tmp;
emilmont 10:3bc89ef62ce7 96
emilmont 10:3bc89ef62ce7 97 tmp = obj->spi->CR1;
emilmont 10:3bc89ef62ce7 98 tmp &= ~(0xD);
emilmont 10:3bc89ef62ce7 99 tmp |= 0 << 0 // LBM - loop back mode - off
emilmont 10:3bc89ef62ce7 100 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
emilmont 10:3bc89ef62ce7 101 | 0 << 3; // SOD - slave output disable - na
emilmont 10:3bc89ef62ce7 102 obj->spi->CR1 = tmp;
emilmont 10:3bc89ef62ce7 103
emilmont 10:3bc89ef62ce7 104 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 105 }
emilmont 10:3bc89ef62ce7 106
emilmont 10:3bc89ef62ce7 107 void spi_frequency(spi_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 108 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 109
emilmont 10:3bc89ef62ce7 110 uint32_t PCLK = SystemCoreClock;
emilmont 10:3bc89ef62ce7 111
emilmont 10:3bc89ef62ce7 112 int prescaler;
emilmont 10:3bc89ef62ce7 113
emilmont 10:3bc89ef62ce7 114 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
emilmont 10:3bc89ef62ce7 115 int prescale_hz = PCLK / prescaler;
emilmont 10:3bc89ef62ce7 116
emilmont 10:3bc89ef62ce7 117 // calculate the divider
emilmont 10:3bc89ef62ce7 118 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
emilmont 10:3bc89ef62ce7 119
emilmont 10:3bc89ef62ce7 120 // check we can support the divider
emilmont 10:3bc89ef62ce7 121 if (divider < 256) {
emilmont 10:3bc89ef62ce7 122 // prescaler
emilmont 10:3bc89ef62ce7 123 obj->spi->CPSR = prescaler;
emilmont 10:3bc89ef62ce7 124
emilmont 10:3bc89ef62ce7 125 // divider
emilmont 10:3bc89ef62ce7 126 obj->spi->CR0 &= ~(0xFFFF << 8);
emilmont 10:3bc89ef62ce7 127 obj->spi->CR0 |= (divider - 1) << 8;
emilmont 10:3bc89ef62ce7 128 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 129 return;
emilmont 10:3bc89ef62ce7 130 }
emilmont 10:3bc89ef62ce7 131 }
emilmont 10:3bc89ef62ce7 132 error("Couldn't setup requested SPI frequency");
emilmont 10:3bc89ef62ce7 133 }
emilmont 10:3bc89ef62ce7 134
emilmont 10:3bc89ef62ce7 135 static inline int ssp_disable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 136 return obj->spi->CR1 &= ~(1 << 1);
emilmont 10:3bc89ef62ce7 137 }
emilmont 10:3bc89ef62ce7 138
emilmont 10:3bc89ef62ce7 139 static inline int ssp_enable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 140 return obj->spi->CR1 |= (1 << 1);
emilmont 10:3bc89ef62ce7 141 }
emilmont 10:3bc89ef62ce7 142
emilmont 10:3bc89ef62ce7 143 static inline int ssp_readable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 144 return obj->spi->SR & (1 << 2);
emilmont 10:3bc89ef62ce7 145 }
emilmont 10:3bc89ef62ce7 146
emilmont 10:3bc89ef62ce7 147 static inline int ssp_writeable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 148 return obj->spi->SR & (1 << 1);
emilmont 10:3bc89ef62ce7 149 }
emilmont 10:3bc89ef62ce7 150
emilmont 10:3bc89ef62ce7 151 static inline void ssp_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 152 while (!ssp_writeable(obj));
emilmont 10:3bc89ef62ce7 153 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 154 }
emilmont 10:3bc89ef62ce7 155
emilmont 10:3bc89ef62ce7 156 static inline int ssp_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 157 while (!ssp_readable(obj));
emilmont 10:3bc89ef62ce7 158 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 159 }
emilmont 10:3bc89ef62ce7 160
emilmont 10:3bc89ef62ce7 161 static inline int ssp_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 162 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
emilmont 10:3bc89ef62ce7 163 }
emilmont 10:3bc89ef62ce7 164
emilmont 10:3bc89ef62ce7 165 int spi_master_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 166 ssp_write(obj, value);
emilmont 10:3bc89ef62ce7 167 return ssp_read(obj);
emilmont 10:3bc89ef62ce7 168 }
emilmont 10:3bc89ef62ce7 169
emilmont 10:3bc89ef62ce7 170 int spi_slave_receive(spi_t *obj) {
emilmont 10:3bc89ef62ce7 171 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
mbed_official 81:a9456fdf72fa 172 }
emilmont 10:3bc89ef62ce7 173
emilmont 10:3bc89ef62ce7 174 int spi_slave_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 175 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 176 }
emilmont 10:3bc89ef62ce7 177
emilmont 10:3bc89ef62ce7 178 void spi_slave_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 179 while (ssp_writeable(obj) == 0) ;
emilmont 10:3bc89ef62ce7 180 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 181 }
emilmont 10:3bc89ef62ce7 182
emilmont 10:3bc89ef62ce7 183 int spi_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 184 return ssp_busy(obj);
emilmont 10:3bc89ef62ce7 185 }