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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c@463:5c73c3744533, 2015-02-03 (annotated)

Committer:
mbed_official
Date:
Tue Feb 03 17:00:07 2015 +0000
Revision:
463:5c73c3744533
Parent:
285:31249416b6f9 
Synchronized with git revision 134a67aab259d410373367cb96b73420b390d385



Full URL: https://github.com/mbedmicro/mbed/commit/134a67aab259d410373367cb96b73420b390d385/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include <stddef.h>
emilmont 10:3bc89ef62ce7 17 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 18 #include "gpio_irq_api.h"
mbed_official 285:31249416b6f9 19 #include "mbed_error.h"
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 #define CHANNEL_NUM 8
emilmont 10:3bc89ef62ce7 22 #define LPC_GPIO_X LPC_GPIO_PIN_INT
emilmont 10:3bc89ef62ce7 23 #define PININT_IRQ 0
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
emilmont 10:3bc89ef62ce7 26 static gpio_irq_handler irq_handler;
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 static inline void handle_interrupt_in(uint32_t channel) {
emilmont 10:3bc89ef62ce7 29 uint32_t ch_bit = (1 << channel);
emilmont 10:3bc89ef62ce7 30 // Return immediately if:
emilmont 10:3bc89ef62ce7 31 // * The interrupt was already served
emilmont 10:3bc89ef62ce7 32 // * There is no user handler
emilmont 10:3bc89ef62ce7 33 // * It is a level interrupt, not an edge interrupt
emilmont 10:3bc89ef62ce7 34 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
emilmont 10:3bc89ef62ce7 35 (channel_ids[channel] == 0 ) ||
emilmont 10:3bc89ef62ce7 36 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
emilmont 10:3bc89ef62ce7 39 irq_handler(channel_ids[channel], IRQ_RISE);
emilmont 10:3bc89ef62ce7 40 LPC_GPIO_X->RISE = ch_bit;
emilmont 10:3bc89ef62ce7 41 }
emilmont 10:3bc89ef62ce7 42 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
emilmont 10:3bc89ef62ce7 43 irq_handler(channel_ids[channel], IRQ_FALL);
emilmont 10:3bc89ef62ce7 44 }
emilmont 10:3bc89ef62ce7 45 LPC_GPIO_X->IST = ch_bit;
emilmont 10:3bc89ef62ce7 46 }
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48 void gpio_irq0(void) {handle_interrupt_in(0);}
emilmont 10:3bc89ef62ce7 49 void gpio_irq1(void) {handle_interrupt_in(1);}
emilmont 10:3bc89ef62ce7 50 void gpio_irq2(void) {handle_interrupt_in(2);}
emilmont 10:3bc89ef62ce7 51 void gpio_irq3(void) {handle_interrupt_in(3);}
emilmont 10:3bc89ef62ce7 52 void gpio_irq4(void) {handle_interrupt_in(4);}
emilmont 10:3bc89ef62ce7 53 void gpio_irq5(void) {handle_interrupt_in(5);}
emilmont 10:3bc89ef62ce7 54 void gpio_irq6(void) {handle_interrupt_in(6);}
emilmont 10:3bc89ef62ce7 55 void gpio_irq7(void) {handle_interrupt_in(7);}
emilmont 10:3bc89ef62ce7 56
emilmont 10:3bc89ef62ce7 57 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
emilmont 10:3bc89ef62ce7 58 if (pin == NC) return -1;
emilmont 10:3bc89ef62ce7 59
emilmont 10:3bc89ef62ce7 60 irq_handler = handler;
emilmont 10:3bc89ef62ce7 61
emilmont 10:3bc89ef62ce7 62 int found_free_channel = 0;
emilmont 10:3bc89ef62ce7 63 int i = 0;
emilmont 10:3bc89ef62ce7 64 for (i=0; i<CHANNEL_NUM; i++) {
emilmont 10:3bc89ef62ce7 65 if (channel_ids[i] == 0) {
emilmont 10:3bc89ef62ce7 66 channel_ids[i] = id;
emilmont 10:3bc89ef62ce7 67 obj->ch = i;
emilmont 10:3bc89ef62ce7 68 found_free_channel = 1;
emilmont 10:3bc89ef62ce7 69 break;
emilmont 10:3bc89ef62ce7 70 }
emilmont 10:3bc89ef62ce7 71 }
emilmont 10:3bc89ef62ce7 72 if (!found_free_channel) return -1;
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 /* Enable AHB clock to the GPIO domain. */
emilmont 10:3bc89ef62ce7 75 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
emilmont 10:3bc89ef62ce7 76
emilmont 10:3bc89ef62ce7 77 /* Enable AHB clock to the FlexInt, GroupedInt domain. */
emilmont 10:3bc89ef62ce7 78 LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 /* To select a pin for any of the eight pin interrupts, write the pin number
emilmont 10:3bc89ef62ce7 81 * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
emilmont 10:3bc89ef62ce7 82 * @see: mbed_capi/PinNames.h
emilmont 10:3bc89ef62ce7 83 */
emilmont 10:3bc89ef62ce7 84 LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 // Interrupt Wake-Up Enable
emilmont 10:3bc89ef62ce7 87 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
emilmont 10:3bc89ef62ce7 88
emilmont 10:3bc89ef62ce7 89 void (*channels_irq)(void) = NULL;
emilmont 10:3bc89ef62ce7 90 switch (obj->ch) {
emilmont 10:3bc89ef62ce7 91 case 0: channels_irq = &gpio_irq0; break;
emilmont 10:3bc89ef62ce7 92 case 1: channels_irq = &gpio_irq1; break;
emilmont 10:3bc89ef62ce7 93 case 2: channels_irq = &gpio_irq2; break;
emilmont 10:3bc89ef62ce7 94 case 3: channels_irq = &gpio_irq3; break;
emilmont 10:3bc89ef62ce7 95 case 4: channels_irq = &gpio_irq4; break;
emilmont 10:3bc89ef62ce7 96 case 5: channels_irq = &gpio_irq5; break;
emilmont 10:3bc89ef62ce7 97 case 6: channels_irq = &gpio_irq6; break;
emilmont 10:3bc89ef62ce7 98 case 7: channels_irq = &gpio_irq7; break;
emilmont 10:3bc89ef62ce7 99 }
emilmont 10:3bc89ef62ce7 100 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
emilmont 10:3bc89ef62ce7 101 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
emilmont 10:3bc89ef62ce7 102
emilmont 10:3bc89ef62ce7 103 return 0;
emilmont 10:3bc89ef62ce7 104 }
emilmont 10:3bc89ef62ce7 105
emilmont 10:3bc89ef62ce7 106 void gpio_irq_free(gpio_irq_t *obj) {
emilmont 10:3bc89ef62ce7 107 channel_ids[obj->ch] = 0;
emilmont 10:3bc89ef62ce7 108 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
emilmont 10:3bc89ef62ce7 109 }
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
emilmont 10:3bc89ef62ce7 112 unsigned int ch_bit = (1 << obj->ch);
emilmont 10:3bc89ef62ce7 113
emilmont 10:3bc89ef62ce7 114 // Clear interrupt
emilmont 10:3bc89ef62ce7 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
emilmont 10:3bc89ef62ce7 116 LPC_GPIO_X->IST = ch_bit;
emilmont 10:3bc89ef62ce7 117
emilmont 10:3bc89ef62ce7 118 // Edge trigger
emilmont 10:3bc89ef62ce7 119 LPC_GPIO_X->ISEL &= ~ch_bit;
emilmont 10:3bc89ef62ce7 120 if (event == IRQ_RISE) {
emilmont 10:3bc89ef62ce7 121 if (enable) {
emilmont 10:3bc89ef62ce7 122 LPC_GPIO_X->IENR |= ch_bit;
emilmont 10:3bc89ef62ce7 123 } else {
emilmont 10:3bc89ef62ce7 124 LPC_GPIO_X->IENR &= ~ch_bit;
emilmont 10:3bc89ef62ce7 125 }
emilmont 10:3bc89ef62ce7 126 } else {
emilmont 10:3bc89ef62ce7 127 if (enable) {
emilmont 10:3bc89ef62ce7 128 LPC_GPIO_X->IENF |= ch_bit;
emilmont 10:3bc89ef62ce7 129 } else {
emilmont 10:3bc89ef62ce7 130 LPC_GPIO_X->IENF &= ~ch_bit;
emilmont 10:3bc89ef62ce7 131 }
emilmont 10:3bc89ef62ce7 132 }
emilmont 10:3bc89ef62ce7 133 }
mbed_official 35:371630885ad6 134
mbed_official 35:371630885ad6 135 void gpio_irq_enable(gpio_irq_t *obj) {
mbed_official 35:371630885ad6 136 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 35:371630885ad6 137 }
mbed_official 35:371630885ad6 138
mbed_official 35:371630885ad6 139 void gpio_irq_disable(gpio_irq_t *obj) {
mbed_official 35:371630885ad6 140 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 35:371630885ad6 141 }