mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
Parent:
149:156823d33999
Child:
161:2cc1468da177
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.1.2
<> 157:ff67d9f36b67 6 * @date 23-September-2016
<> 144:ef7eb2e8f9f7 7 * @brief SPI HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The SPI HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SPI_HandleTypeDef hspi;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
<> 144:ef7eb2e8f9f7 26 (##) Enable the SPIx interface clock
<> 144:ef7eb2e8f9f7 27 (##) SPI pins configuration
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the SPI GPIOs
<> 144:ef7eb2e8f9f7 29 (+++) Configure these SPI pins as alternate function push-pull
<> 144:ef7eb2e8f9f7 30 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 31 (+++) Configure the SPIx interrupt priority
<> 144:ef7eb2e8f9f7 32 (+++) Enable the NVIC SPI IRQ handle
<> 144:ef7eb2e8f9f7 33 (##) DMA Configuration if you need to use DMA process
<> 157:ff67d9f36b67 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
<> 144:ef7eb2e8f9f7 35 (+++) Enable the DMAx clock
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA handle parameters
<> 157:ff67d9f36b67 37 (+++) Configure the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
<> 157:ff67d9f36b67 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
<> 144:ef7eb2e8f9f7 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<> 144:ef7eb2e8f9f7 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 46 by calling the customized HAL_SPI_MspInit() API.
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 Circular mode restriction:
<> 144:ef7eb2e8f9f7 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<> 144:ef7eb2e8f9f7 50 (##) Master 2Lines RxOnly
<> 144:ef7eb2e8f9f7 51 (##) Master 1Line Rx
<> 144:ef7eb2e8f9f7 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
<> 144:ef7eb2e8f9f7 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<> 144:ef7eb2e8f9f7 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<> 157:ff67d9f36b67 55 [..]
<> 157:ff67d9f36b67 56 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
<> 157:ff67d9f36b67 57 the following table resume the max SPI frequency reached with data size 8bits/16bits,
<> 157:ff67d9f36b67 58 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
<> 157:ff67d9f36b67 59
<> 157:ff67d9f36b67 60 DataSize = SPI_DATASIZE_8BIT:
<> 157:ff67d9f36b67 61 +----------------------------------------------------------------------------------------------+
<> 157:ff67d9f36b67 62 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 157:ff67d9f36b67 63 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 157:ff67d9f36b67 64 | | | Master | Slave | Master | Slave | Master | Slave |
<> 157:ff67d9f36b67 65 |==============================================================================================|
<> 157:ff67d9f36b67 66 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 157:ff67d9f36b67 67 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 68 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
<> 157:ff67d9f36b67 69 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 70 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
<> 157:ff67d9f36b67 71 |=========|================|==========|==========|===========|==========|===========|==========|
<> 157:ff67d9f36b67 72 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 157:ff67d9f36b67 73 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 74 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
<> 157:ff67d9f36b67 75 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 76 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
<> 157:ff67d9f36b67 77 |=========|================|==========|==========|===========|==========|===========|==========|
<> 157:ff67d9f36b67 78 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 157:ff67d9f36b67 79 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 80 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
<> 157:ff67d9f36b67 81 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 82 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 157:ff67d9f36b67 83 +----------------------------------------------------------------------------------------------+
<> 157:ff67d9f36b67 84
<> 157:ff67d9f36b67 85 DataSize = SPI_DATASIZE_16BIT:
<> 157:ff67d9f36b67 86 +----------------------------------------------------------------------------------------------+
<> 157:ff67d9f36b67 87 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 157:ff67d9f36b67 88 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 157:ff67d9f36b67 89 | | | Master | Slave | Master | Slave | Master | Slave |
<> 157:ff67d9f36b67 90 |==============================================================================================|
<> 157:ff67d9f36b67 91 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 157:ff67d9f36b67 92 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 93 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
<> 157:ff67d9f36b67 94 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 95 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
<> 157:ff67d9f36b67 96 |=========|================|==========|==========|===========|==========|===========|==========|
<> 157:ff67d9f36b67 97 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 157:ff67d9f36b67 98 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 99 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
<> 157:ff67d9f36b67 100 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 101 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
<> 157:ff67d9f36b67 102 |=========|================|==========|==========|===========|==========|===========|==========|
<> 157:ff67d9f36b67 103 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 157:ff67d9f36b67 104 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 105 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
<> 157:ff67d9f36b67 106 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 157:ff67d9f36b67 107 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 157:ff67d9f36b67 108 +----------------------------------------------------------------------------------------------+
<> 157:ff67d9f36b67 109 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
<> 157:ff67d9f36b67 110 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
<> 157:ff67d9f36b67 111 @note
<> 157:ff67d9f36b67 112 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
<> 157:ff67d9f36b67 113 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
<> 157:ff67d9f36b67 114 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 @endverbatim
<> 144:ef7eb2e8f9f7 117 ******************************************************************************
<> 144:ef7eb2e8f9f7 118 * @attention
<> 144:ef7eb2e8f9f7 119 *
<> 144:ef7eb2e8f9f7 120 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 121 *
<> 144:ef7eb2e8f9f7 122 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 123 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 124 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 125 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 126 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 127 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 128 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 129 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 130 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 131 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 134 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 135 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 136 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 137 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 138 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 139 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 140 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 141 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 142 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 143 *
<> 144:ef7eb2e8f9f7 144 ******************************************************************************
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 148 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /** @defgroup SPI SPI
<> 144:ef7eb2e8f9f7 155 * @brief SPI HAL module driver
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 161 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 162 /** @defgroup SPI_Private_Constants SPI Private Constants
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 157:ff67d9f36b67 165 #define SPI_DEFAULT_TIMEOUT 100U
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 171 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 172 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 /** @defgroup SPI_Private_Functions SPI Private Functions
<> 144:ef7eb2e8f9f7 174 * @{
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 177 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 178 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 179 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 180 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 181 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 182 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 183 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 157:ff67d9f36b67 184 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<> 157:ff67d9f36b67 185 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<> 157:ff67d9f36b67 186 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
<> 157:ff67d9f36b67 187 uint32_t Timeout, uint32_t Tickstart);
<> 157:ff67d9f36b67 188 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
<> 157:ff67d9f36b67 189 uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 190 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 191 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 192 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 193 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 194 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 195 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 196 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 197 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 198 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 199 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 200 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 201 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 202 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 203 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 204 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 205 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 206 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 207 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 208 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
<> 157:ff67d9f36b67 209 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 157:ff67d9f36b67 210 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @}
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 157:ff67d9f36b67 215 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 216 /** @defgroup SPI_Exported_Functions SPI Exported Functions
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 221 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 222 *
<> 144:ef7eb2e8f9f7 223 @verbatim
<> 144:ef7eb2e8f9f7 224 ===============================================================================
<> 144:ef7eb2e8f9f7 225 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 226 ===============================================================================
<> 144:ef7eb2e8f9f7 227 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 228 de-initialize the SPIx peripheral:
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 (+) User must implement HAL_SPI_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 231 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 (+) Call the function HAL_SPI_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 234 the selected configuration:
<> 144:ef7eb2e8f9f7 235 (++) Mode
<> 144:ef7eb2e8f9f7 236 (++) Direction
<> 144:ef7eb2e8f9f7 237 (++) Data Size
<> 144:ef7eb2e8f9f7 238 (++) Clock Polarity and Phase
<> 144:ef7eb2e8f9f7 239 (++) NSS Management
<> 144:ef7eb2e8f9f7 240 (++) BaudRate Prescaler
<> 144:ef7eb2e8f9f7 241 (++) FirstBit
<> 144:ef7eb2e8f9f7 242 (++) TIMode
<> 144:ef7eb2e8f9f7 243 (++) CRC Calculation
<> 144:ef7eb2e8f9f7 244 (++) CRC Polynomial if CRC enabled
<> 144:ef7eb2e8f9f7 245 (++) CRC Length, used only with Data8 and Data16
<> 144:ef7eb2e8f9f7 246 (++) FIFO reception threshold
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 249 of the selected SPIx peripheral.
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 @endverbatim
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief Initialize the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 257 * in the SPI_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 258 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 259 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 260 * @retval HAL status
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 uint32_t frxth;
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Check the SPI handle allocation */
<> 157:ff67d9f36b67 267 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Check the parameters */
<> 144:ef7eb2e8f9f7 273 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 274 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 275 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 276 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 277 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 278 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
<> 144:ef7eb2e8f9f7 279 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 280 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 281 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 157:ff67d9f36b67 282 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
<> 157:ff67d9f36b67 283 {
<> 157:ff67d9f36b67 284 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 157:ff67d9f36b67 285 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 157:ff67d9f36b67 286 }
<> 144:ef7eb2e8f9f7 287 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 288 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 157:ff67d9f36b67 289 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 144:ef7eb2e8f9f7 292 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
<> 144:ef7eb2e8f9f7 293 }
<> 157:ff67d9f36b67 294 #else
<> 157:ff67d9f36b67 295 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 157:ff67d9f36b67 296 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 297
<> 157:ff67d9f36b67 298 if (hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 301 hspi->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 304 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Disable the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 310 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Align by default the rs fifo threshold on the data size */
<> 157:ff67d9f36b67 313 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 frxth = SPI_RXFIFO_THRESHOLD_HF;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317 else
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 frxth = SPI_RXFIFO_THRESHOLD_QF;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* CRC calculation is valid only for 16Bit and 8 Bit */
<> 157:ff67d9f36b67 323 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 /* CRC must be disabled */
<> 144:ef7eb2e8f9f7 326 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 157:ff67d9f36b67 329 /* Align the CRC Length on the data size */
<> 157:ff67d9f36b67 330 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
<> 157:ff67d9f36b67 331 {
<> 157:ff67d9f36b67 332 /* CRC Length aligned on the data size : value set by default */
<> 157:ff67d9f36b67 333 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 157:ff67d9f36b67 334 {
<> 157:ff67d9f36b67 335 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
<> 157:ff67d9f36b67 336 }
<> 157:ff67d9f36b67 337 else
<> 157:ff67d9f36b67 338 {
<> 157:ff67d9f36b67 339 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
<> 157:ff67d9f36b67 340 }
<> 157:ff67d9f36b67 341 }
<> 157:ff67d9f36b67 342
<> 157:ff67d9f36b67 343 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 344 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
<> 157:ff67d9f36b67 345 Communication speed, First bit, CRC calculation state */
<> 157:ff67d9f36b67 346 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
<> 157:ff67d9f36b67 347 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 157:ff67d9f36b67 348 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
<> 157:ff67d9f36b67 349 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 350 /* Configure : CRC Length */
<> 157:ff67d9f36b67 351 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 352 {
<> 157:ff67d9f36b67 353 hspi->Instance->CR1 |= SPI_CR1_CRCL;
<> 144:ef7eb2e8f9f7 354 }
<> 157:ff67d9f36b67 355 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 356
<> 157:ff67d9f36b67 357 /* Configure : NSS management, TI Mode and Rx Fifo Threshold */
<> 157:ff67d9f36b67 358 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode |
<> 157:ff67d9f36b67 359 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 362 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 363 /* Configure : CRC Polynomial */
<> 157:ff67d9f36b67 364 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 157:ff67d9f36b67 365 {
<> 157:ff67d9f36b67 366 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<> 157:ff67d9f36b67 367 }
<> 157:ff67d9f36b67 368 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 369
<> 157:ff67d9f36b67 370 #if defined(SPI_I2SCFGR_I2SMOD)
<> 157:ff67d9f36b67 371 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 157:ff67d9f36b67 372 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 157:ff67d9f36b67 373 #endif /* SPI_I2SCFGR_I2SMOD */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 376 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 return HAL_OK;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 157:ff67d9f36b67 382 * @brief De-Initialize the SPI peripheral.
<> 144:ef7eb2e8f9f7 383 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 384 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 385 * @retval HAL status
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Check the SPI handle allocation */
<> 157:ff67d9f36b67 390 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 157:ff67d9f36b67 395 /* Check SPI Instance parameter */
<> 144:ef7eb2e8f9f7 396 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Disable the SPI Peripheral Clock */
<> 144:ef7eb2e8f9f7 401 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 404 HAL_SPI_MspDeInit(hspi);
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 407 hspi->State = HAL_SPI_STATE_RESET;
<> 144:ef7eb2e8f9f7 408
<> 157:ff67d9f36b67 409 /* Release Lock */
<> 144:ef7eb2e8f9f7 410 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 return HAL_OK;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 157:ff67d9f36b67 416 * @brief Initialize the SPI MSP.
<> 144:ef7eb2e8f9f7 417 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 418 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 419 * @retval None
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 422 {
<> 144:ef7eb2e8f9f7 423 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 424 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 427 the HAL_SPI_MspInit should be implemented in the user file
<> 157:ff67d9f36b67 428 */
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 157:ff67d9f36b67 432 * @brief De-Initialize the SPI MSP.
<> 144:ef7eb2e8f9f7 433 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 434 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 435 * @retval None
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 438 {
<> 144:ef7eb2e8f9f7 439 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 440 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 443 the HAL_SPI_MspDeInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 452 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 453 *
<> 144:ef7eb2e8f9f7 454 @verbatim
<> 144:ef7eb2e8f9f7 455 ==============================================================================
<> 144:ef7eb2e8f9f7 456 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 457 ===============================================================================
<> 144:ef7eb2e8f9f7 458 [..]
<> 144:ef7eb2e8f9f7 459 This subsection provides a set of functions allowing to manage the SPI
<> 144:ef7eb2e8f9f7 460 data transfers.
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 [..] The SPI supports master and slave mode :
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 465 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 466 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 467 after finishing transfer.
<> 144:ef7eb2e8f9f7 468 (++) No-Blocking mode: The communication is performed using Interrupts
<> 157:ff67d9f36b67 469 or DMA, These APIs return the HAL status.
<> 157:ff67d9f36b67 470 The end of the data processing will be indicated through the
<> 157:ff67d9f36b67 471 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<> 157:ff67d9f36b67 472 using DMA mode.
<> 157:ff67d9f36b67 473 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<> 157:ff67d9f36b67 474 will be executed respectively at the end of the transmit or Receive process
<> 157:ff67d9f36b67 475 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<> 144:ef7eb2e8f9f7 478 exist for 1Line (simplex) and 2Lines (full duplex) modes.
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 @endverbatim
<> 144:ef7eb2e8f9f7 481 * @{
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @brief Transmit an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 486 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 487 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 488 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 489 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 490 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 491 * @retval HAL status
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 494 {
<> 157:ff67d9f36b67 495 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 497
<> 157:ff67d9f36b67 498 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 499 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Process Locked */
<> 144:ef7eb2e8f9f7 502 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 503
<> 157:ff67d9f36b67 504 /* Init tickstart for timeout management*/
<> 157:ff67d9f36b67 505 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 506
<> 157:ff67d9f36b67 507 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 510 goto error;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 157:ff67d9f36b67 513 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 516 goto error;
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 520 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 521 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 522 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 523 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 524 hspi->TxXferCount = Size;
<> 157:ff67d9f36b67 525
<> 157:ff67d9f36b67 526 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 527 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 157:ff67d9f36b67 528 hspi->RxXferSize = 0U;
<> 157:ff67d9f36b67 529 hspi->RxXferCount = 0U;
<> 157:ff67d9f36b67 530 hspi->TxISR = NULL;
<> 157:ff67d9f36b67 531 hspi->RxISR = NULL;
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Configure communication direction : 1Line */
<> 157:ff67d9f36b67 534 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 540 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 541 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 544 }
<> 157:ff67d9f36b67 545 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 548 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 551 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 552 }
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Transmit data in 16 Bit mode */
<> 157:ff67d9f36b67 555 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Transmit data in 16 Bit mode */
<> 157:ff67d9f36b67 558 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Wait until TXE flag is set to send data */
<> 157:ff67d9f36b67 561 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 562 {
<> 157:ff67d9f36b67 563 hspi->Instance->DR = *((uint16_t *)pData);
<> 157:ff67d9f36b67 564 pData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 565 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567 else
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 /* Timeout management */
<> 157:ff67d9f36b67 570 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 573 goto error;
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 579 else
<> 144:ef7eb2e8f9f7 580 {
<> 157:ff67d9f36b67 581 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 /* Wait until TXE flag is set to send data */
<> 157:ff67d9f36b67 584 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 585 {
<> 157:ff67d9f36b67 586 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 /* write on the data register in packing mode */
<> 157:ff67d9f36b67 589 hspi->Instance->DR = *((uint16_t *)pData);
<> 157:ff67d9f36b67 590 pData += sizeof(uint16_t);
<> 157:ff67d9f36b67 591 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593 else
<> 144:ef7eb2e8f9f7 594 {
<> 157:ff67d9f36b67 595 *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
<> 144:ef7eb2e8f9f7 596 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599 else
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Timeout management */
<> 157:ff67d9f36b67 602 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 605 goto error;
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 611 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 612 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 613 {
<> 157:ff67d9f36b67 614 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 615 }
<> 157:ff67d9f36b67 616 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Check the end of the transaction */
<> 157:ff67d9f36b67 619 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 157:ff67d9f36b67 625 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629
<> 157:ff67d9f36b67 630 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 error:
<> 144:ef7eb2e8f9f7 636 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 637 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 638 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 639 return errorcode;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /**
<> 144:ef7eb2e8f9f7 643 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 644 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 645 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 646 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 647 * @param Size: amount of data to be received
<> 144:ef7eb2e8f9f7 648 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 649 * @retval HAL status
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 654 __IO uint16_t tmpreg = 0U;
<> 157:ff67d9f36b67 655 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 656 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 657 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 658
<> 157:ff67d9f36b67 659 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 660 {
<> 157:ff67d9f36b67 661 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 157:ff67d9f36b67 662 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 157:ff67d9f36b67 663 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* Process Locked */
<> 144:ef7eb2e8f9f7 667 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 668
<> 157:ff67d9f36b67 669 /* Init tickstart for timeout management*/
<> 157:ff67d9f36b67 670 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 671
<> 157:ff67d9f36b67 672 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 675 goto error;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 157:ff67d9f36b67 678 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 681 goto error;
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683
<> 157:ff67d9f36b67 684 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 685 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 686 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 687 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 688 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 689 hspi->RxXferCount = Size;
<> 157:ff67d9f36b67 690
<> 157:ff67d9f36b67 691 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 692 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 157:ff67d9f36b67 693 hspi->TxXferSize = 0U;
<> 157:ff67d9f36b67 694 hspi->TxXferCount = 0U;
<> 157:ff67d9f36b67 695 hspi->RxISR = NULL;
<> 157:ff67d9f36b67 696 hspi->TxISR = NULL;
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 699 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 700 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 703 /* this is done to handle the CRCNEXT before the latest data */
<> 144:ef7eb2e8f9f7 704 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 705 }
<> 157:ff67d9f36b67 706 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 707
<> 157:ff67d9f36b67 708 /* Set the Rx Fifo threshold */
<> 157:ff67d9f36b67 709 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 712 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714 else
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 717 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 157:ff67d9f36b67 720 /* Configure communication direction: 1Line */
<> 157:ff67d9f36b67 721 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 727 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 730 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Receive data in 8 Bit mode */
<> 157:ff67d9f36b67 734 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 /* Transfer loop */
<> 157:ff67d9f36b67 737 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 /* Check the RXNE flag */
<> 157:ff67d9f36b67 740 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 741 {
<> 144:ef7eb2e8f9f7 742 /* read the received data */
<> 157:ff67d9f36b67 743 (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 744 pData += sizeof(uint8_t);
<> 144:ef7eb2e8f9f7 745 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747 else
<> 144:ef7eb2e8f9f7 748 {
<> 144:ef7eb2e8f9f7 749 /* Timeout management */
<> 157:ff67d9f36b67 750 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 753 goto error;
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755 }
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 else
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 /* Transfer loop */
<> 157:ff67d9f36b67 761 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 /* Check the RXNE flag */
<> 157:ff67d9f36b67 764 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 765 {
<> 157:ff67d9f36b67 766 *((uint16_t *)pData) = hspi->Instance->DR;
<> 157:ff67d9f36b67 767 pData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 768 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770 else
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 /* Timeout management */
<> 157:ff67d9f36b67 773 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 776 goto error;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 783 /* Handle the CRC Transmission */
<> 157:ff67d9f36b67 784 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 /* freeze the CRC before the latest data */
<> 157:ff67d9f36b67 787 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Read the latest data */
<> 157:ff67d9f36b67 790 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 /* the latest data has not been received */
<> 144:ef7eb2e8f9f7 793 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 794 goto error;
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Receive last data in 16 Bit mode */
<> 157:ff67d9f36b67 798 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 799 {
<> 157:ff67d9f36b67 800 *((uint16_t *)pData) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802 /* Receive last data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 803 else
<> 144:ef7eb2e8f9f7 804 {
<> 157:ff67d9f36b67 805 (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807
<> 157:ff67d9f36b67 808 /* Wait the CRC data */
<> 157:ff67d9f36b67 809 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 810 {
<> 157:ff67d9f36b67 811 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 812 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 813 goto error;
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815
<> 157:ff67d9f36b67 816 /* Read CRC to Flush DR and RXNE flag */
<> 157:ff67d9f36b67 817 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 tmpreg = hspi->Instance->DR;
<> 157:ff67d9f36b67 820 /* To avoid GCC warning */
<> 157:ff67d9f36b67 821 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823 else
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 826 /* To avoid GCC warning */
<> 157:ff67d9f36b67 827 UNUSED(tmpreg);
<> 157:ff67d9f36b67 828
<> 157:ff67d9f36b67 829 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 830 {
<> 157:ff67d9f36b67 831 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 /* Error on the CRC reception */
<> 157:ff67d9f36b67 834 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 835 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 836 goto error;
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 839 /* To avoid GCC warning */
<> 157:ff67d9f36b67 840 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843 }
<> 157:ff67d9f36b67 844 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Check the end of the transaction */
<> 157:ff67d9f36b67 847 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 853 /* Check if CRC error occurred */
<> 157:ff67d9f36b67 854 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 855 {
<> 157:ff67d9f36b67 856 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 857 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 858 }
<> 157:ff67d9f36b67 859 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 860
<> 157:ff67d9f36b67 861 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 error :
<> 144:ef7eb2e8f9f7 867 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 868 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 869 return errorcode;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /**
<> 144:ef7eb2e8f9f7 873 * @brief Transmit and Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 874 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 875 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 876 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 877 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 878 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 879 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 880 * @retval HAL status
<> 144:ef7eb2e8f9f7 881 */
<> 157:ff67d9f36b67 882 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
<> 157:ff67d9f36b67 883 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 884 {
<> 157:ff67d9f36b67 885 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 886 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 887 __IO uint16_t tmpreg = 0U;
<> 157:ff67d9f36b67 888 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 889 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 890 /* Variable used to alternate Rx and Tx during transfer */
<> 144:ef7eb2e8f9f7 891 uint32_t txallowed = 1U;
<> 144:ef7eb2e8f9f7 892 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 893
<> 157:ff67d9f36b67 894 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 895 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Process Locked */
<> 144:ef7eb2e8f9f7 898 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 899
<> 157:ff67d9f36b67 900 /* Init tickstart for timeout management*/
<> 157:ff67d9f36b67 901 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 902
<> 157:ff67d9f36b67 903 tmp = hspi->State;
<> 157:ff67d9f36b67 904 tmp1 = hspi->Init.Mode;
<> 157:ff67d9f36b67 905
<> 157:ff67d9f36b67 906 if (!((tmp == HAL_SPI_STATE_READY) || \
<> 157:ff67d9f36b67 907 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 910 goto error;
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912
<> 157:ff67d9f36b67 913 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 916 goto error;
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918
<> 157:ff67d9f36b67 919 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 157:ff67d9f36b67 920 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 157:ff67d9f36b67 921 {
<> 157:ff67d9f36b67 922 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 157:ff67d9f36b67 923 }
<> 157:ff67d9f36b67 924
<> 157:ff67d9f36b67 925 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 926 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 927 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 928 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 929 hspi->RxXferSize = Size;
<> 157:ff67d9f36b67 930 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 931 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 932 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 933
<> 157:ff67d9f36b67 934 /*Init field not used in handle to zero */
<> 157:ff67d9f36b67 935 hspi->RxISR = NULL;
<> 157:ff67d9f36b67 936 hspi->TxISR = NULL;
<> 157:ff67d9f36b67 937
<> 144:ef7eb2e8f9f7 938 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 939 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 940 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 943 }
<> 157:ff67d9f36b67 944 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Set the Rx Fifo threshold */
<> 157:ff67d9f36b67 947 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
<> 144:ef7eb2e8f9f7 948 {
<> 144:ef7eb2e8f9f7 949 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 950 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952 else
<> 144:ef7eb2e8f9f7 953 {
<> 144:ef7eb2e8f9f7 954 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 955 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 956 }
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 959 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 962 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /* Transmit and Receive data in 16 Bit mode */
<> 157:ff67d9f36b67 966 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 967 {
<> 157:ff67d9f36b67 968 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
<> 157:ff67d9f36b67 969 {
<> 157:ff67d9f36b67 970 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 157:ff67d9f36b67 971 pTxData += sizeof(uint16_t);
<> 157:ff67d9f36b67 972 hspi->TxXferCount--;
<> 157:ff67d9f36b67 973 }
<> 157:ff67d9f36b67 974 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 /* Check TXE flag */
<> 157:ff67d9f36b67 977 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 978 {
<> 157:ff67d9f36b67 979 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 157:ff67d9f36b67 980 pTxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 981 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 982 /* Next Data is a reception (Rx). Tx not allowed */
<> 144:ef7eb2e8f9f7 983 txallowed = 0U;
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 986 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 987 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 157:ff67d9f36b67 990 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 995 }
<> 157:ff67d9f36b67 996 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 997 }
<> 157:ff67d9f36b67 998
<> 144:ef7eb2e8f9f7 999 /* Check RXNE flag */
<> 157:ff67d9f36b67 1000 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1001 {
<> 157:ff67d9f36b67 1002 *((uint16_t *)pRxData) = hspi->Instance->DR;
<> 157:ff67d9f36b67 1003 pRxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 1004 hspi->RxXferCount--;
<> 157:ff67d9f36b67 1005 /* Next Data is a Transmission (Tx). Tx is allowed */
<> 144:ef7eb2e8f9f7 1006 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1007 }
<> 157:ff67d9f36b67 1008 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1009 {
<> 144:ef7eb2e8f9f7 1010 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1011 goto error;
<> 144:ef7eb2e8f9f7 1012 }
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015 /* Transmit and Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 1016 else
<> 144:ef7eb2e8f9f7 1017 {
<> 157:ff67d9f36b67 1018 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
<> 157:ff67d9f36b67 1019 {
<> 157:ff67d9f36b67 1020 *((__IO uint8_t *)&hspi->Instance->DR) = (*pTxData);
<> 157:ff67d9f36b67 1021 pTxData += sizeof(uint8_t);
<> 157:ff67d9f36b67 1022 hspi->TxXferCount--;
<> 157:ff67d9f36b67 1023 }
<> 157:ff67d9f36b67 1024 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 /* check TXE flag */
<> 157:ff67d9f36b67 1027 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 1028 {
<> 157:ff67d9f36b67 1029 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1030 {
<> 157:ff67d9f36b67 1031 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 157:ff67d9f36b67 1032 pTxData += sizeof(uint16_t);
<> 157:ff67d9f36b67 1033 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 1034 }
<> 144:ef7eb2e8f9f7 1035 else
<> 144:ef7eb2e8f9f7 1036 {
<> 157:ff67d9f36b67 1037 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
<> 144:ef7eb2e8f9f7 1038 hspi->TxXferCount--;
<> 157:ff67d9f36b67 1039 }
<> 157:ff67d9f36b67 1040 /* Next Data is a reception (Rx). Tx not allowed */
<> 144:ef7eb2e8f9f7 1041 txallowed = 0U;
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1044 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 1045 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 1046 {
<> 144:ef7eb2e8f9f7 1047 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 157:ff67d9f36b67 1048 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 1051 }
<> 144:ef7eb2e8f9f7 1052 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1053 }
<> 157:ff67d9f36b67 1054 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1055 }
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* Wait until RXNE flag is reset */
<> 157:ff67d9f36b67 1058 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1059 {
<> 157:ff67d9f36b67 1060 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1061 {
<> 157:ff67d9f36b67 1062 *((uint16_t *)pRxData) = hspi->Instance->DR;
<> 157:ff67d9f36b67 1063 pRxData += sizeof(uint16_t);
<> 157:ff67d9f36b67 1064 hspi->RxXferCount -= 2U;
<> 157:ff67d9f36b67 1065 if (hspi->RxXferCount <= 1U)
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 /* set fiforxthreshold before to switch on 8 bit data size */
<> 144:ef7eb2e8f9f7 1068 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 }
<> 144:ef7eb2e8f9f7 1071 else
<> 144:ef7eb2e8f9f7 1072 {
<> 157:ff67d9f36b67 1073 (*pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1074 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 1075 }
<> 157:ff67d9f36b67 1076 /* Next Data is a Transmission (Tx). Tx is allowed */
<> 157:ff67d9f36b67 1077 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1078 }
<> 157:ff67d9f36b67 1079 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1082 goto error;
<> 144:ef7eb2e8f9f7 1083 }
<> 144:ef7eb2e8f9f7 1084 }
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1088 /* Read CRC from DR to close CRC calculation process */
<> 157:ff67d9f36b67 1089 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1090 {
<> 144:ef7eb2e8f9f7 1091 /* Wait until TXE flag */
<> 157:ff67d9f36b67 1092 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* Error on the CRC reception */
<> 157:ff67d9f36b67 1095 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1096 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1097 goto error;
<> 144:ef7eb2e8f9f7 1098 }
<> 157:ff67d9f36b67 1099 /* Read CRC */
<> 157:ff67d9f36b67 1100 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 1101 {
<> 144:ef7eb2e8f9f7 1102 tmpreg = hspi->Instance->DR;
<> 157:ff67d9f36b67 1103 /* To avoid GCC warning */
<> 157:ff67d9f36b67 1104 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106 else
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 1109 /* To avoid GCC warning */
<> 157:ff67d9f36b67 1110 UNUSED(tmpreg);
<> 157:ff67d9f36b67 1111
<> 157:ff67d9f36b67 1112 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 1113 {
<> 157:ff67d9f36b67 1114 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1115 {
<> 144:ef7eb2e8f9f7 1116 /* Error on the CRC reception */
<> 157:ff67d9f36b67 1117 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1118 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1119 goto error;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 1122 /* To avoid GCC warning */
<> 157:ff67d9f36b67 1123 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1124 }
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Check if CRC error occurred */
<> 157:ff67d9f36b67 1129 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 1130 {
<> 157:ff67d9f36b67 1131 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1132 /* Clear CRC Flag */
<> 144:ef7eb2e8f9f7 1133 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1136 }
<> 157:ff67d9f36b67 1137 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Check the end of the transaction */
<> 157:ff67d9f36b67 1140 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144
<> 157:ff67d9f36b67 1145 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 error :
<> 144:ef7eb2e8f9f7 1151 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1152 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1153 return errorcode;
<> 144:ef7eb2e8f9f7 1154 }
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /**
<> 144:ef7eb2e8f9f7 1157 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1158 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1159 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1160 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1161 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1162 * @retval HAL status
<> 144:ef7eb2e8f9f7 1163 */
<> 144:ef7eb2e8f9f7 1164 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1165 {
<> 144:ef7eb2e8f9f7 1166 HAL_StatusTypeDef errorcode = HAL_OK;
<> 157:ff67d9f36b67 1167
<> 157:ff67d9f36b67 1168 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1169 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Process Locked */
<> 144:ef7eb2e8f9f7 1172 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1173
<> 157:ff67d9f36b67 1174 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1175 {
<> 144:ef7eb2e8f9f7 1176 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1177 goto error;
<> 144:ef7eb2e8f9f7 1178 }
<> 144:ef7eb2e8f9f7 1179
<> 157:ff67d9f36b67 1180 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1181 {
<> 144:ef7eb2e8f9f7 1182 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1183 goto error;
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185
<> 157:ff67d9f36b67 1186 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1187 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1188 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 1189 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1190 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1191 hspi->TxXferCount = Size;
<> 157:ff67d9f36b67 1192
<> 157:ff67d9f36b67 1193 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1194 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 157:ff67d9f36b67 1195 hspi->RxXferSize = 0U;
<> 157:ff67d9f36b67 1196 hspi->RxXferCount = 0U;
<> 157:ff67d9f36b67 1197 hspi->RxISR = NULL;
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* Set the function for IT treatment */
<> 157:ff67d9f36b67 1200 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1201 {
<> 144:ef7eb2e8f9f7 1202 hspi->TxISR = SPI_TxISR_16BIT;
<> 144:ef7eb2e8f9f7 1203 }
<> 144:ef7eb2e8f9f7 1204 else
<> 144:ef7eb2e8f9f7 1205 {
<> 144:ef7eb2e8f9f7 1206 hspi->TxISR = SPI_TxISR_8BIT;
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Configure communication direction : 1Line */
<> 157:ff67d9f36b67 1210 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1211 {
<> 144:ef7eb2e8f9f7 1212 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1216 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 1217 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1218 {
<> 144:ef7eb2e8f9f7 1219 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1220 }
<> 157:ff67d9f36b67 1221 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /* Enable TXE and ERR interrupt */
<> 157:ff67d9f36b67 1224 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 157:ff67d9f36b67 1225
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 1228 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1231 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 error :
<> 144:ef7eb2e8f9f7 1235 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1236 return errorcode;
<> 144:ef7eb2e8f9f7 1237 }
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /**
<> 144:ef7eb2e8f9f7 1240 * @brief Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1241 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1242 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1243 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1244 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1245 * @retval HAL status
<> 144:ef7eb2e8f9f7 1246 */
<> 144:ef7eb2e8f9f7 1247 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1250
<> 157:ff67d9f36b67 1251 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 157:ff67d9f36b67 1252 {
<> 157:ff67d9f36b67 1253 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 157:ff67d9f36b67 1254 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 157:ff67d9f36b67 1255 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<> 157:ff67d9f36b67 1256 }
<> 157:ff67d9f36b67 1257
<> 144:ef7eb2e8f9f7 1258 /* Process Locked */
<> 144:ef7eb2e8f9f7 1259 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1260
<> 157:ff67d9f36b67 1261 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1262 {
<> 144:ef7eb2e8f9f7 1263 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1264 goto error;
<> 144:ef7eb2e8f9f7 1265 }
<> 157:ff67d9f36b67 1266
<> 157:ff67d9f36b67 1267 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1268 {
<> 144:ef7eb2e8f9f7 1269 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1270 goto error;
<> 144:ef7eb2e8f9f7 1271 }
<> 144:ef7eb2e8f9f7 1272
<> 157:ff67d9f36b67 1273 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1274 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1275 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 1276 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1277 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1278 hspi->RxXferCount = Size;
<> 157:ff67d9f36b67 1279
<> 157:ff67d9f36b67 1280 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1281 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 157:ff67d9f36b67 1282 hspi->TxXferSize = 0U;
<> 157:ff67d9f36b67 1283 hspi->TxXferCount = 0U;
<> 157:ff67d9f36b67 1284 hspi->TxISR = NULL;
<> 157:ff67d9f36b67 1285
<> 157:ff67d9f36b67 1286 /* check the data size to adapt Rx threshold and the set the function for IT treatment */
<> 157:ff67d9f36b67 1287 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1288 {
<> 157:ff67d9f36b67 1289 /* set fiforxthreshold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1290 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1291 hspi->RxISR = SPI_RxISR_16BIT;
<> 144:ef7eb2e8f9f7 1292 }
<> 144:ef7eb2e8f9f7 1293 else
<> 144:ef7eb2e8f9f7 1294 {
<> 157:ff67d9f36b67 1295 /* set fiforxthreshold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1296 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1297 hspi->RxISR = SPI_RxISR_8BIT;
<> 144:ef7eb2e8f9f7 1298 }
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 /* Configure communication direction : 1Line */
<> 157:ff67d9f36b67 1301 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1302 {
<> 144:ef7eb2e8f9f7 1303 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1304 }
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1307 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 1308 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1309 {
<> 157:ff67d9f36b67 1310 hspi->CRCSize = 1U;
<> 157:ff67d9f36b67 1311 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 157:ff67d9f36b67 1312 {
<> 157:ff67d9f36b67 1313 hspi->CRCSize = 2U;
<> 157:ff67d9f36b67 1314 }
<> 144:ef7eb2e8f9f7 1315 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1316 }
<> 157:ff67d9f36b67 1317 else
<> 157:ff67d9f36b67 1318 {
<> 157:ff67d9f36b67 1319 hspi->CRCSize = 0U;
<> 157:ff67d9f36b67 1320 }
<> 157:ff67d9f36b67 1321 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1324 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1325
<> 157:ff67d9f36b67 1326 /* Note : The SPI must be enabled after unlocking current process
<> 157:ff67d9f36b67 1327 to avoid the risk of SPI interrupt handle execution before current
<> 157:ff67d9f36b67 1328 process unlock */
<> 157:ff67d9f36b67 1329
<> 144:ef7eb2e8f9f7 1330 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 1331 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1332 {
<> 144:ef7eb2e8f9f7 1333 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1334 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1335 }
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 error :
<> 144:ef7eb2e8f9f7 1338 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1339 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1340 return errorcode;
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /**
<> 144:ef7eb2e8f9f7 1344 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1345 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1346 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1347 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1348 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1349 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 1350 * @retval HAL status
<> 144:ef7eb2e8f9f7 1351 */
<> 144:ef7eb2e8f9f7 1352 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1353 {
<> 157:ff67d9f36b67 1354 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1355 HAL_StatusTypeDef errorcode = HAL_OK;
<> 157:ff67d9f36b67 1356
<> 157:ff67d9f36b67 1357 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1358 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 /* Process locked */
<> 144:ef7eb2e8f9f7 1361 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1362
<> 157:ff67d9f36b67 1363 tmp = hspi->State;
<> 157:ff67d9f36b67 1364 tmp1 = hspi->Init.Mode;
<> 157:ff67d9f36b67 1365
<> 157:ff67d9f36b67 1366 if (!((tmp == HAL_SPI_STATE_READY) || \
<> 157:ff67d9f36b67 1367 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1368 {
<> 144:ef7eb2e8f9f7 1369 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1370 goto error;
<> 144:ef7eb2e8f9f7 1371 }
<> 144:ef7eb2e8f9f7 1372
<> 157:ff67d9f36b67 1373 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1374 {
<> 144:ef7eb2e8f9f7 1375 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1376 goto error;
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378
<> 157:ff67d9f36b67 1379 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 157:ff67d9f36b67 1380 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1381 {
<> 144:ef7eb2e8f9f7 1382 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1383 }
<> 144:ef7eb2e8f9f7 1384
<> 157:ff67d9f36b67 1385 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1386 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 1387 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1388 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1389 hspi->TxXferCount = Size;
<> 157:ff67d9f36b67 1390 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1391 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1392 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* Set the function for IT treatment */
<> 157:ff67d9f36b67 1395 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1396 {
<> 157:ff67d9f36b67 1397 hspi->RxISR = SPI_2linesRxISR_16BIT;
<> 157:ff67d9f36b67 1398 hspi->TxISR = SPI_2linesTxISR_16BIT;
<> 144:ef7eb2e8f9f7 1399 }
<> 144:ef7eb2e8f9f7 1400 else
<> 144:ef7eb2e8f9f7 1401 {
<> 157:ff67d9f36b67 1402 hspi->RxISR = SPI_2linesRxISR_8BIT;
<> 157:ff67d9f36b67 1403 hspi->TxISR = SPI_2linesTxISR_8BIT;
<> 144:ef7eb2e8f9f7 1404 }
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1407 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 1408 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1409 {
<> 157:ff67d9f36b67 1410 hspi->CRCSize = 1U;
<> 157:ff67d9f36b67 1411 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 157:ff67d9f36b67 1412 {
<> 157:ff67d9f36b67 1413 hspi->CRCSize = 2U;
<> 157:ff67d9f36b67 1414 }
<> 144:ef7eb2e8f9f7 1415 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1416 }
<> 157:ff67d9f36b67 1417 else
<> 157:ff67d9f36b67 1418 {
<> 157:ff67d9f36b67 1419 hspi->CRCSize = 0U;
<> 157:ff67d9f36b67 1420 }
<> 157:ff67d9f36b67 1421 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 /* check if packing mode is enabled and if there is more than 2 data to receive */
<> 157:ff67d9f36b67 1424 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
<> 144:ef7eb2e8f9f7 1425 {
<> 157:ff67d9f36b67 1426 /* set fiforxthreshold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1427 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1428 }
<> 144:ef7eb2e8f9f7 1429 else
<> 144:ef7eb2e8f9f7 1430 {
<> 157:ff67d9f36b67 1431 /* set fiforxthreshold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1432 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1433 }
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /* Enable TXE, RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1436 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 1439 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1440 {
<> 144:ef7eb2e8f9f7 1441 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1442 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1443 }
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 error :
<> 144:ef7eb2e8f9f7 1446 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1447 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1448 return errorcode;
<> 144:ef7eb2e8f9f7 1449 }
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /**
<> 144:ef7eb2e8f9f7 1452 * @brief Transmit an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1453 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1454 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1455 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1456 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1457 * @retval HAL status
<> 144:ef7eb2e8f9f7 1458 */
<> 144:ef7eb2e8f9f7 1459 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1460 {
<> 144:ef7eb2e8f9f7 1461 HAL_StatusTypeDef errorcode = HAL_OK;
<> 157:ff67d9f36b67 1462
<> 157:ff67d9f36b67 1463 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1464 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 /* Process Locked */
<> 144:ef7eb2e8f9f7 1467 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1468
<> 157:ff67d9f36b67 1469 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1470 {
<> 144:ef7eb2e8f9f7 1471 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1472 goto error;
<> 144:ef7eb2e8f9f7 1473 }
<> 144:ef7eb2e8f9f7 1474
<> 157:ff67d9f36b67 1475 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1476 {
<> 144:ef7eb2e8f9f7 1477 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1478 goto error;
<> 144:ef7eb2e8f9f7 1479 }
<> 144:ef7eb2e8f9f7 1480
<> 157:ff67d9f36b67 1481 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1482 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1483 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 1484 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1485 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1486 hspi->TxXferCount = Size;
<> 157:ff67d9f36b67 1487
<> 157:ff67d9f36b67 1488 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1489 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 157:ff67d9f36b67 1490 hspi->TxISR = NULL;
<> 157:ff67d9f36b67 1491 hspi->RxISR = NULL;
<> 157:ff67d9f36b67 1492 hspi->RxXferSize = 0U;
<> 157:ff67d9f36b67 1493 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* Configure communication direction : 1Line */
<> 157:ff67d9f36b67 1496 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1497 {
<> 144:ef7eb2e8f9f7 1498 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1499 }
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1502 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 1503 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1504 {
<> 144:ef7eb2e8f9f7 1505 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1506 }
<> 157:ff67d9f36b67 1507 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1508
<> 144:ef7eb2e8f9f7 1509 /* Set the SPI TxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1510 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 /* Set the SPI TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1513 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1516 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1517
<> 157:ff67d9f36b67 1518 /* Set the DMA AbortCpltCallback */
<> 157:ff67d9f36b67 1519 hspi->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1520
<> 144:ef7eb2e8f9f7 1521 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 144:ef7eb2e8f9f7 1522 /* packing mode is enabled only if the DMA setting is HALWORD */
<> 157:ff67d9f36b67 1523 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1524 {
<> 144:ef7eb2e8f9f7 1525 /* Check the even/odd of the data size + crc if enabled */
<> 157:ff67d9f36b67 1526 if ((hspi->TxXferCount & 0x1U) == 0U)
<> 144:ef7eb2e8f9f7 1527 {
<> 144:ef7eb2e8f9f7 1528 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 157:ff67d9f36b67 1529 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
<> 144:ef7eb2e8f9f7 1530 }
<> 144:ef7eb2e8f9f7 1531 else
<> 144:ef7eb2e8f9f7 1532 {
<> 144:ef7eb2e8f9f7 1533 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 157:ff67d9f36b67 1534 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1535 }
<> 144:ef7eb2e8f9f7 1536 }
<> 144:ef7eb2e8f9f7 1537
<> 157:ff67d9f36b67 1538 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1539 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 1542 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1543 {
<> 144:ef7eb2e8f9f7 1544 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1545 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1546 }
<> 144:ef7eb2e8f9f7 1547
<> 157:ff67d9f36b67 1548 /* Enable the SPI Error Interrupt Bit */
<> 157:ff67d9f36b67 1549 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 157:ff67d9f36b67 1550
<> 144:ef7eb2e8f9f7 1551 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1552 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 error :
<> 144:ef7eb2e8f9f7 1555 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1556 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1557 return errorcode;
<> 144:ef7eb2e8f9f7 1558 }
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /**
<> 144:ef7eb2e8f9f7 1561 * @brief Receive an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1562 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1563 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1564 * @param pData: pointer to data buffer
<> 157:ff67d9f36b67 1565 * @note When the CRC feature is enabled the pData Length must be Size + 1.
<> 144:ef7eb2e8f9f7 1566 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1567 * @retval HAL status
<> 144:ef7eb2e8f9f7 1568 */
<> 144:ef7eb2e8f9f7 1569 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1570 {
<> 144:ef7eb2e8f9f7 1571 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1572
<> 157:ff67d9f36b67 1573 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 157:ff67d9f36b67 1574 {
<> 157:ff67d9f36b67 1575 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 157:ff67d9f36b67 1576 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 157:ff67d9f36b67 1577 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<> 157:ff67d9f36b67 1578 }
<> 157:ff67d9f36b67 1579
<> 144:ef7eb2e8f9f7 1580 /* Process Locked */
<> 144:ef7eb2e8f9f7 1581 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1582
<> 157:ff67d9f36b67 1583 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1584 {
<> 144:ef7eb2e8f9f7 1585 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1586 goto error;
<> 144:ef7eb2e8f9f7 1587 }
<> 144:ef7eb2e8f9f7 1588
<> 157:ff67d9f36b67 1589 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1590 {
<> 144:ef7eb2e8f9f7 1591 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1592 goto error;
<> 144:ef7eb2e8f9f7 1593 }
<> 144:ef7eb2e8f9f7 1594
<> 157:ff67d9f36b67 1595 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1596 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1597 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 1598 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1599 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1600 hspi->RxXferCount = Size;
<> 157:ff67d9f36b67 1601
<> 157:ff67d9f36b67 1602 /*Init field not used in handle to zero */
<> 157:ff67d9f36b67 1603 hspi->RxISR = NULL;
<> 157:ff67d9f36b67 1604 hspi->TxISR = NULL;
<> 157:ff67d9f36b67 1605 hspi->TxXferSize = 0U;
<> 157:ff67d9f36b67 1606 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 /* Configure communication direction : 1Line */
<> 157:ff67d9f36b67 1609 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1610 {
<> 144:ef7eb2e8f9f7 1611 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1612 }
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1615 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 1616 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1617 {
<> 144:ef7eb2e8f9f7 1618 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1619 }
<> 157:ff67d9f36b67 1620 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 /* packing mode management is enabled by the DMA settings */
<> 157:ff67d9f36b67 1623 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1624 {
<> 144:ef7eb2e8f9f7 1625 /* Restriction the DMA data received is not allowed in this mode */
<> 144:ef7eb2e8f9f7 1626 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1627 goto error;
<> 144:ef7eb2e8f9f7 1628 }
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 157:ff67d9f36b67 1631 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1632 {
<> 144:ef7eb2e8f9f7 1633 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1634 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1635 }
<> 144:ef7eb2e8f9f7 1636 else
<> 144:ef7eb2e8f9f7 1637 {
<> 144:ef7eb2e8f9f7 1638 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1639 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1640 }
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /* Set the SPI RxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1643 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 /* Set the SPI Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1646 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1649 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1650
<> 157:ff67d9f36b67 1651 /* Set the DMA AbortCpltCallback */
<> 157:ff67d9f36b67 1652 hspi->hdmarx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 1653
<> 157:ff67d9f36b67 1654 /* Enable the Rx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1655 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 1658 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1659 {
<> 144:ef7eb2e8f9f7 1660 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1661 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1662 }
<> 144:ef7eb2e8f9f7 1663
<> 157:ff67d9f36b67 1664 /* Enable the SPI Error Interrupt Bit */
<> 157:ff67d9f36b67 1665 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 157:ff67d9f36b67 1666
<> 157:ff67d9f36b67 1667 /* Enable Rx DMA Request */
<> 157:ff67d9f36b67 1668 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 157:ff67d9f36b67 1669
<> 144:ef7eb2e8f9f7 1670 error:
<> 144:ef7eb2e8f9f7 1671 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1672 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1673 return errorcode;
<> 144:ef7eb2e8f9f7 1674 }
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 /**
<> 144:ef7eb2e8f9f7 1677 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1678 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1679 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1680 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1681 * @param pRxData: pointer to reception data buffer
<> 157:ff67d9f36b67 1682 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
<> 144:ef7eb2e8f9f7 1683 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1684 * @retval HAL status
<> 144:ef7eb2e8f9f7 1685 */
<> 157:ff67d9f36b67 1686 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 157:ff67d9f36b67 1687 uint16_t Size)
<> 144:ef7eb2e8f9f7 1688 {
<> 157:ff67d9f36b67 1689 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1690 HAL_StatusTypeDef errorcode = HAL_OK;
<> 157:ff67d9f36b67 1691
<> 157:ff67d9f36b67 1692 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1693 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 /* Process locked */
<> 144:ef7eb2e8f9f7 1696 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1697
<> 157:ff67d9f36b67 1698 tmp = hspi->State;
<> 157:ff67d9f36b67 1699 tmp1 = hspi->Init.Mode;
<> 157:ff67d9f36b67 1700 if (!((tmp == HAL_SPI_STATE_READY) ||
<> 157:ff67d9f36b67 1701 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1702 {
<> 144:ef7eb2e8f9f7 1703 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1704 goto error;
<> 144:ef7eb2e8f9f7 1705 }
<> 144:ef7eb2e8f9f7 1706
<> 157:ff67d9f36b67 1707 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1708 {
<> 144:ef7eb2e8f9f7 1709 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1710 goto error;
<> 144:ef7eb2e8f9f7 1711 }
<> 144:ef7eb2e8f9f7 1712
<> 157:ff67d9f36b67 1713 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 157:ff67d9f36b67 1714 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1715 {
<> 144:ef7eb2e8f9f7 1716 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1717 }
<> 144:ef7eb2e8f9f7 1718
<> 157:ff67d9f36b67 1719 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1720 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1721 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1722 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1723 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1724 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1725 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1726 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1727
<> 157:ff67d9f36b67 1728 /* Init field not used in handle to zero */
<> 157:ff67d9f36b67 1729 hspi->RxISR = NULL;
<> 157:ff67d9f36b67 1730 hspi->TxISR = NULL;
<> 157:ff67d9f36b67 1731
<> 144:ef7eb2e8f9f7 1732 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 1733 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 1734 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1735 {
<> 144:ef7eb2e8f9f7 1736 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1737 }
<> 157:ff67d9f36b67 1738 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 /* Reset the threshold bit */
<> 144:ef7eb2e8f9f7 1741 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /* the packing mode management is enabled by the DMA settings according the spi data size */
<> 157:ff67d9f36b67 1744 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1745 {
<> 144:ef7eb2e8f9f7 1746 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1747 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1748 }
<> 144:ef7eb2e8f9f7 1749 else
<> 144:ef7eb2e8f9f7 1750 {
<> 157:ff67d9f36b67 1751 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1752 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1753
<> 157:ff67d9f36b67 1754 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1755 {
<> 157:ff67d9f36b67 1756 if ((hspi->TxXferSize & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1757 {
<> 144:ef7eb2e8f9f7 1758 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 157:ff67d9f36b67 1759 hspi->TxXferCount = hspi->TxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1760 }
<> 144:ef7eb2e8f9f7 1761 else
<> 144:ef7eb2e8f9f7 1762 {
<> 144:ef7eb2e8f9f7 1763 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 157:ff67d9f36b67 1764 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1765 }
<> 144:ef7eb2e8f9f7 1766 }
<> 144:ef7eb2e8f9f7 1767
<> 157:ff67d9f36b67 1768 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1769 {
<> 157:ff67d9f36b67 1770 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1771 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1772
<> 157:ff67d9f36b67 1773 if ((hspi->RxXferCount & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1774 {
<> 144:ef7eb2e8f9f7 1775 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 157:ff67d9f36b67 1776 hspi->RxXferCount = hspi->RxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1777 }
<> 144:ef7eb2e8f9f7 1778 else
<> 144:ef7eb2e8f9f7 1779 {
<> 144:ef7eb2e8f9f7 1780 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 157:ff67d9f36b67 1781 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1782 }
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784 }
<> 144:ef7eb2e8f9f7 1785
<> 157:ff67d9f36b67 1786 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<> 157:ff67d9f36b67 1787 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1788 {
<> 144:ef7eb2e8f9f7 1789 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1790 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 157:ff67d9f36b67 1791 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1792 }
<> 144:ef7eb2e8f9f7 1793 else
<> 144:ef7eb2e8f9f7 1794 {
<> 157:ff67d9f36b67 1795 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1796 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<> 157:ff67d9f36b67 1797 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1798 }
<> 144:ef7eb2e8f9f7 1799
<> 144:ef7eb2e8f9f7 1800 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1801 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1802
<> 157:ff67d9f36b67 1803 /* Set the DMA AbortCpltCallback */
<> 157:ff67d9f36b67 1804 hspi->hdmarx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 1805
<> 157:ff67d9f36b67 1806 /* Enable the Rx DMA Stream/Channel */
<> 157:ff67d9f36b67 1807 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1808
<> 144:ef7eb2e8f9f7 1809 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1810 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<> 144:ef7eb2e8f9f7 1813 is performed in DMA reception complete callback */
<> 144:ef7eb2e8f9f7 1814 hspi->hdmatx->XferHalfCpltCallback = NULL;
<> 157:ff67d9f36b67 1815 hspi->hdmatx->XferCpltCallback = NULL;
<> 157:ff67d9f36b67 1816 hspi->hdmatx->XferErrorCallback = NULL;
<> 157:ff67d9f36b67 1817 hspi->hdmatx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 1818
<> 157:ff67d9f36b67 1819 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1820 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 /* Check if the SPI is already enabled */
<> 157:ff67d9f36b67 1823 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1824 {
<> 144:ef7eb2e8f9f7 1825 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1826 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1827 }
<> 157:ff67d9f36b67 1828 /* Enable the SPI Error Interrupt Bit */
<> 157:ff67d9f36b67 1829 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1832 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 error :
<> 144:ef7eb2e8f9f7 1835 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1836 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1837 return errorcode;
<> 144:ef7eb2e8f9f7 1838 }
<> 144:ef7eb2e8f9f7 1839
<> 144:ef7eb2e8f9f7 1840 /**
<> 157:ff67d9f36b67 1841 * @brief Abort ongoing transfer (blocking mode).
<> 157:ff67d9f36b67 1842 * @param hspi SPI handle.
<> 157:ff67d9f36b67 1843 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
<> 157:ff67d9f36b67 1844 * started in Interrupt or DMA mode.
<> 157:ff67d9f36b67 1845 * This procedure performs following operations :
<> 157:ff67d9f36b67 1846 * - Disable SPI Interrupts (depending of transfer direction)
<> 157:ff67d9f36b67 1847 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 157:ff67d9f36b67 1848 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 157:ff67d9f36b67 1849 * - Set handle State to READY
<> 157:ff67d9f36b67 1850 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 157:ff67d9f36b67 1851 * @retval HAL status
<> 157:ff67d9f36b67 1852 */
<> 157:ff67d9f36b67 1853 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
<> 157:ff67d9f36b67 1854 {
<> 157:ff67d9f36b67 1855 HAL_StatusTypeDef errorcode;
<> 157:ff67d9f36b67 1856
<> 157:ff67d9f36b67 1857 /* Initialized local variable */
<> 157:ff67d9f36b67 1858 errorcode = HAL_OK;
<> 157:ff67d9f36b67 1859
<> 157:ff67d9f36b67 1860 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 157:ff67d9f36b67 1861 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
<> 157:ff67d9f36b67 1862 {
<> 157:ff67d9f36b67 1863 hspi->TxISR = SPI_AbortTx_ISR;
<> 157:ff67d9f36b67 1864 while (hspi->State != HAL_SPI_STATE_ABORT);
<> 157:ff67d9f36b67 1865 }
<> 157:ff67d9f36b67 1866
<> 157:ff67d9f36b67 1867 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
<> 157:ff67d9f36b67 1868 {
<> 157:ff67d9f36b67 1869 hspi->RxISR = SPI_AbortRx_ISR;
<> 157:ff67d9f36b67 1870 while (hspi->State != HAL_SPI_STATE_ABORT);
<> 157:ff67d9f36b67 1871 }
<> 157:ff67d9f36b67 1872
<> 157:ff67d9f36b67 1873 /* Clear ERRIE interrupts in case of DMA Mode */
<> 157:ff67d9f36b67 1874 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
<> 157:ff67d9f36b67 1875
<> 157:ff67d9f36b67 1876 /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
<> 157:ff67d9f36b67 1877 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
<> 157:ff67d9f36b67 1878 {
<> 157:ff67d9f36b67 1879 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
<> 157:ff67d9f36b67 1880 if (hspi->hdmatx != NULL)
<> 157:ff67d9f36b67 1881 {
<> 157:ff67d9f36b67 1882 /* Set the SPI DMA Abort callback :
<> 157:ff67d9f36b67 1883 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
<> 157:ff67d9f36b67 1884 hspi->hdmatx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 1885
<> 157:ff67d9f36b67 1886 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 157:ff67d9f36b67 1887 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
<> 157:ff67d9f36b67 1888 {
<> 157:ff67d9f36b67 1889 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 1890 }
<> 157:ff67d9f36b67 1891
<> 157:ff67d9f36b67 1892 /* Disable Tx DMA Request */
<> 157:ff67d9f36b67 1893 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
<> 157:ff67d9f36b67 1894
<> 157:ff67d9f36b67 1895 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 1896 {
<> 157:ff67d9f36b67 1897 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 1898 }
<> 157:ff67d9f36b67 1899
<> 157:ff67d9f36b67 1900 /* Disable SPI Peripheral */
<> 157:ff67d9f36b67 1901 __HAL_SPI_DISABLE(hspi);
<> 157:ff67d9f36b67 1902
<> 157:ff67d9f36b67 1903 /* Empty the FRLVL fifo */
<> 157:ff67d9f36b67 1904 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 1905 {
<> 157:ff67d9f36b67 1906 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 1907 }
<> 157:ff67d9f36b67 1908 }
<> 157:ff67d9f36b67 1909 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
<> 157:ff67d9f36b67 1910 if (hspi->hdmarx != NULL)
<> 157:ff67d9f36b67 1911 {
<> 157:ff67d9f36b67 1912 /* Set the SPI DMA Abort callback :
<> 157:ff67d9f36b67 1913 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
<> 157:ff67d9f36b67 1914 hspi->hdmarx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 1915
<> 157:ff67d9f36b67 1916 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 157:ff67d9f36b67 1917 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
<> 157:ff67d9f36b67 1918 {
<> 157:ff67d9f36b67 1919 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 1920 }
<> 157:ff67d9f36b67 1921
<> 157:ff67d9f36b67 1922 /* Disable peripheral */
<> 157:ff67d9f36b67 1923 __HAL_SPI_DISABLE(hspi);
<> 157:ff67d9f36b67 1924
<> 157:ff67d9f36b67 1925 /* Control the BSY flag */
<> 157:ff67d9f36b67 1926 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 1927 {
<> 157:ff67d9f36b67 1928 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 1929 }
<> 157:ff67d9f36b67 1930
<> 157:ff67d9f36b67 1931 /* Empty the FRLVL fifo */
<> 157:ff67d9f36b67 1932 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 1933 {
<> 157:ff67d9f36b67 1934 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 1935 }
<> 157:ff67d9f36b67 1936
<> 157:ff67d9f36b67 1937 /* Disable Rx DMA Request */
<> 157:ff67d9f36b67 1938 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
<> 157:ff67d9f36b67 1939 }
<> 157:ff67d9f36b67 1940 }
<> 157:ff67d9f36b67 1941 /* Reset Tx and Rx transfer counters */
<> 157:ff67d9f36b67 1942 hspi->RxXferCount = 0U;
<> 157:ff67d9f36b67 1943 hspi->TxXferCount = 0U;
<> 157:ff67d9f36b67 1944
<> 157:ff67d9f36b67 1945 /* Check error during Abort procedure */
<> 157:ff67d9f36b67 1946 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
<> 157:ff67d9f36b67 1947 {
<> 157:ff67d9f36b67 1948 /* return HAL_Error in case of error during Abort procedure */
<> 157:ff67d9f36b67 1949 errorcode = HAL_ERROR;
<> 157:ff67d9f36b67 1950 }
<> 157:ff67d9f36b67 1951 else
<> 157:ff67d9f36b67 1952 {
<> 157:ff67d9f36b67 1953 /* Reset errorCode */
<> 157:ff67d9f36b67 1954 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 1955 }
<> 157:ff67d9f36b67 1956
<> 157:ff67d9f36b67 1957 /* Clear the Error flags in the SR register */
<> 157:ff67d9f36b67 1958 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 157:ff67d9f36b67 1959 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 157:ff67d9f36b67 1960
<> 157:ff67d9f36b67 1961 /* Restore hspi->state to ready */
<> 157:ff67d9f36b67 1962 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 1963
<> 157:ff67d9f36b67 1964 return errorcode;
<> 157:ff67d9f36b67 1965 }
<> 157:ff67d9f36b67 1966
<> 157:ff67d9f36b67 1967 /**
<> 157:ff67d9f36b67 1968 * @brief Abort ongoing transfer (Interrupt mode).
<> 157:ff67d9f36b67 1969 * @param hspi SPI handle.
<> 157:ff67d9f36b67 1970 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
<> 157:ff67d9f36b67 1971 * started in Interrupt or DMA mode.
<> 157:ff67d9f36b67 1972 * This procedure performs following operations :
<> 157:ff67d9f36b67 1973 * - Disable SPI Interrupts (depending of transfer direction)
<> 157:ff67d9f36b67 1974 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 157:ff67d9f36b67 1975 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 157:ff67d9f36b67 1976 * - Set handle State to READY
<> 157:ff67d9f36b67 1977 * - At abort completion, call user abort complete callback
<> 157:ff67d9f36b67 1978 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 157:ff67d9f36b67 1979 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 157:ff67d9f36b67 1980 * @retval HAL status
<> 157:ff67d9f36b67 1981 */
<> 157:ff67d9f36b67 1982 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
<> 157:ff67d9f36b67 1983 {
<> 157:ff67d9f36b67 1984 HAL_StatusTypeDef errorcode;
<> 157:ff67d9f36b67 1985 uint32_t abortcplt ;
<> 157:ff67d9f36b67 1986
<> 157:ff67d9f36b67 1987 /* Initialized local variable */
<> 157:ff67d9f36b67 1988 errorcode = HAL_OK;
<> 157:ff67d9f36b67 1989 abortcplt = 1U;
<> 157:ff67d9f36b67 1990
<> 157:ff67d9f36b67 1991 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
<> 157:ff67d9f36b67 1992 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
<> 157:ff67d9f36b67 1993 {
<> 157:ff67d9f36b67 1994 hspi->TxISR = SPI_AbortTx_ISR;
<> 157:ff67d9f36b67 1995 while (hspi->State != HAL_SPI_STATE_ABORT);
<> 157:ff67d9f36b67 1996 }
<> 157:ff67d9f36b67 1997
<> 157:ff67d9f36b67 1998 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
<> 157:ff67d9f36b67 1999 {
<> 157:ff67d9f36b67 2000 hspi->RxISR = SPI_AbortRx_ISR;
<> 157:ff67d9f36b67 2001 while (hspi->State != HAL_SPI_STATE_ABORT);
<> 157:ff67d9f36b67 2002 }
<> 157:ff67d9f36b67 2003
<> 157:ff67d9f36b67 2004 /* Clear ERRIE interrupts in case of DMA Mode */
<> 157:ff67d9f36b67 2005 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
<> 157:ff67d9f36b67 2006
<> 157:ff67d9f36b67 2007 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
<> 157:ff67d9f36b67 2008 before any call to DMA Abort functions */
<> 157:ff67d9f36b67 2009 /* DMA Tx Handle is valid */
<> 157:ff67d9f36b67 2010 if (hspi->hdmatx != NULL)
<> 157:ff67d9f36b67 2011 {
<> 157:ff67d9f36b67 2012 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
<> 157:ff67d9f36b67 2013 Otherwise, set it to NULL */
<> 157:ff67d9f36b67 2014 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
<> 157:ff67d9f36b67 2015 {
<> 157:ff67d9f36b67 2016 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
<> 157:ff67d9f36b67 2017 }
<> 157:ff67d9f36b67 2018 else
<> 157:ff67d9f36b67 2019 {
<> 157:ff67d9f36b67 2020 hspi->hdmatx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2021 }
<> 157:ff67d9f36b67 2022 }
<> 157:ff67d9f36b67 2023 /* DMA Rx Handle is valid */
<> 157:ff67d9f36b67 2024 if (hspi->hdmarx != NULL)
<> 157:ff67d9f36b67 2025 {
<> 157:ff67d9f36b67 2026 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
<> 157:ff67d9f36b67 2027 Otherwise, set it to NULL */
<> 157:ff67d9f36b67 2028 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
<> 157:ff67d9f36b67 2029 {
<> 157:ff67d9f36b67 2030 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
<> 157:ff67d9f36b67 2031 }
<> 157:ff67d9f36b67 2032 else
<> 157:ff67d9f36b67 2033 {
<> 157:ff67d9f36b67 2034 hspi->hdmarx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2035 }
<> 157:ff67d9f36b67 2036 }
<> 157:ff67d9f36b67 2037
<> 157:ff67d9f36b67 2038 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 157:ff67d9f36b67 2039 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
<> 157:ff67d9f36b67 2040 {
<> 157:ff67d9f36b67 2041 /* Abort the SPI DMA Tx Stream/Channel */
<> 157:ff67d9f36b67 2042 if (hspi->hdmatx != NULL)
<> 157:ff67d9f36b67 2043 {
<> 157:ff67d9f36b67 2044 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 157:ff67d9f36b67 2045 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
<> 157:ff67d9f36b67 2046 {
<> 157:ff67d9f36b67 2047 hspi->hdmatx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2048 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2049 }
<> 157:ff67d9f36b67 2050 else
<> 157:ff67d9f36b67 2051 {
<> 157:ff67d9f36b67 2052 abortcplt = 0U;
<> 157:ff67d9f36b67 2053 }
<> 157:ff67d9f36b67 2054 }
<> 157:ff67d9f36b67 2055 /* Abort the SPI DMA Rx Stream/Channel */
<> 157:ff67d9f36b67 2056 if (hspi->hdmarx != NULL)
<> 157:ff67d9f36b67 2057 {
<> 157:ff67d9f36b67 2058 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 157:ff67d9f36b67 2059 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
<> 157:ff67d9f36b67 2060 {
<> 157:ff67d9f36b67 2061 hspi->hdmarx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2062 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2063 abortcplt = 1U;
<> 157:ff67d9f36b67 2064 }
<> 157:ff67d9f36b67 2065 else
<> 157:ff67d9f36b67 2066 {
<> 157:ff67d9f36b67 2067 abortcplt = 0U;
<> 157:ff67d9f36b67 2068 }
<> 157:ff67d9f36b67 2069 }
<> 157:ff67d9f36b67 2070 }
<> 157:ff67d9f36b67 2071
<> 157:ff67d9f36b67 2072 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 157:ff67d9f36b67 2073 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
<> 157:ff67d9f36b67 2074 {
<> 157:ff67d9f36b67 2075 /* Abort the SPI DMA Tx Stream/Channel */
<> 157:ff67d9f36b67 2076 if (hspi->hdmatx != NULL)
<> 157:ff67d9f36b67 2077 {
<> 157:ff67d9f36b67 2078 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 157:ff67d9f36b67 2079 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
<> 157:ff67d9f36b67 2080 {
<> 157:ff67d9f36b67 2081 hspi->hdmatx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2082 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2083 }
<> 157:ff67d9f36b67 2084 else
<> 157:ff67d9f36b67 2085 {
<> 157:ff67d9f36b67 2086 abortcplt = 0U;
<> 157:ff67d9f36b67 2087 }
<> 157:ff67d9f36b67 2088 }
<> 157:ff67d9f36b67 2089 }
<> 157:ff67d9f36b67 2090 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 157:ff67d9f36b67 2091 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
<> 157:ff67d9f36b67 2092 {
<> 157:ff67d9f36b67 2093 /* Abort the SPI DMA Rx Stream/Channel */
<> 157:ff67d9f36b67 2094 if (hspi->hdmarx != NULL)
<> 157:ff67d9f36b67 2095 {
<> 157:ff67d9f36b67 2096 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 157:ff67d9f36b67 2097 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
<> 157:ff67d9f36b67 2098 {
<> 157:ff67d9f36b67 2099 hspi->hdmarx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2100 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2101 }
<> 157:ff67d9f36b67 2102 else
<> 157:ff67d9f36b67 2103 {
<> 157:ff67d9f36b67 2104 abortcplt = 0U;
<> 157:ff67d9f36b67 2105 }
<> 157:ff67d9f36b67 2106 }
<> 157:ff67d9f36b67 2107 }
<> 157:ff67d9f36b67 2108
<> 157:ff67d9f36b67 2109 if (abortcplt == 1U)
<> 157:ff67d9f36b67 2110 {
<> 157:ff67d9f36b67 2111 /* Reset Tx and Rx transfer counters */
<> 157:ff67d9f36b67 2112 hspi->RxXferCount = 0U;
<> 157:ff67d9f36b67 2113 hspi->TxXferCount = 0U;
<> 157:ff67d9f36b67 2114
<> 157:ff67d9f36b67 2115 /* Check error during Abort procedure */
<> 157:ff67d9f36b67 2116 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
<> 157:ff67d9f36b67 2117 {
<> 157:ff67d9f36b67 2118 /* return HAL_Error in case of error during Abort procedure */
<> 157:ff67d9f36b67 2119 errorcode = HAL_ERROR;
<> 157:ff67d9f36b67 2120 }
<> 157:ff67d9f36b67 2121 else
<> 157:ff67d9f36b67 2122 {
<> 157:ff67d9f36b67 2123 /* Reset errorCode */
<> 157:ff67d9f36b67 2124 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 2125 }
<> 157:ff67d9f36b67 2126
<> 157:ff67d9f36b67 2127 /* Clear the Error flags in the SR register */
<> 157:ff67d9f36b67 2128 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 157:ff67d9f36b67 2129 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 157:ff67d9f36b67 2130
<> 157:ff67d9f36b67 2131 /* Restore hspi->State to Ready */
<> 157:ff67d9f36b67 2132 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 2133
<> 157:ff67d9f36b67 2134 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 157:ff67d9f36b67 2135 HAL_SPI_AbortCpltCallback(hspi);
<> 157:ff67d9f36b67 2136 }
<> 157:ff67d9f36b67 2137
<> 157:ff67d9f36b67 2138 return errorcode;
<> 157:ff67d9f36b67 2139 }
<> 157:ff67d9f36b67 2140
<> 157:ff67d9f36b67 2141 /**
<> 157:ff67d9f36b67 2142 * @brief Pause the DMA Transfer.
<> 144:ef7eb2e8f9f7 2143 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2144 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2145 * @retval HAL status
<> 144:ef7eb2e8f9f7 2146 */
<> 144:ef7eb2e8f9f7 2147 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2148 {
<> 144:ef7eb2e8f9f7 2149 /* Process Locked */
<> 144:ef7eb2e8f9f7 2150 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2151
<> 144:ef7eb2e8f9f7 2152 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2153 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2154
<> 144:ef7eb2e8f9f7 2155 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2156 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2157
<> 144:ef7eb2e8f9f7 2158 return HAL_OK;
<> 144:ef7eb2e8f9f7 2159 }
<> 144:ef7eb2e8f9f7 2160
<> 144:ef7eb2e8f9f7 2161 /**
<> 157:ff67d9f36b67 2162 * @brief Resume the DMA Transfer.
<> 144:ef7eb2e8f9f7 2163 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2164 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2165 * @retval HAL status
<> 144:ef7eb2e8f9f7 2166 */
<> 144:ef7eb2e8f9f7 2167 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2168 {
<> 144:ef7eb2e8f9f7 2169 /* Process Locked */
<> 144:ef7eb2e8f9f7 2170 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2171
<> 144:ef7eb2e8f9f7 2172 /* Enable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2173 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2174
<> 144:ef7eb2e8f9f7 2175 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2176 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2177
<> 144:ef7eb2e8f9f7 2178 return HAL_OK;
<> 144:ef7eb2e8f9f7 2179 }
<> 144:ef7eb2e8f9f7 2180
<> 144:ef7eb2e8f9f7 2181 /**
<> 157:ff67d9f36b67 2182 * @brief Stop the DMA Transfer.
<> 144:ef7eb2e8f9f7 2183 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2184 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2185 * @retval HAL status
<> 144:ef7eb2e8f9f7 2186 */
<> 144:ef7eb2e8f9f7 2187 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2188 {
<> 144:ef7eb2e8f9f7 2189 /* The Lock is not implemented on this API to allow the user application
<> 157:ff67d9f36b67 2190 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<> 157:ff67d9f36b67 2191 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 157:ff67d9f36b67 2192 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<> 157:ff67d9f36b67 2193 */
<> 157:ff67d9f36b67 2194
<> 157:ff67d9f36b67 2195 /* Abort the SPI DMA tx Stream/Channel */
<> 157:ff67d9f36b67 2196 if (hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 2197 {
<> 144:ef7eb2e8f9f7 2198 HAL_DMA_Abort(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 2199 }
<> 157:ff67d9f36b67 2200 /* Abort the SPI DMA rx Stream/Channel */
<> 157:ff67d9f36b67 2201 if (hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 2202 {
<> 144:ef7eb2e8f9f7 2203 HAL_DMA_Abort(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 2204 }
<> 144:ef7eb2e8f9f7 2205
<> 144:ef7eb2e8f9f7 2206 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2207 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2208 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2209 return HAL_OK;
<> 144:ef7eb2e8f9f7 2210 }
<> 144:ef7eb2e8f9f7 2211
<> 144:ef7eb2e8f9f7 2212 /**
<> 157:ff67d9f36b67 2213 * @brief Handle SPI interrupt request.
<> 144:ef7eb2e8f9f7 2214 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2215 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2216 * @retval None
<> 144:ef7eb2e8f9f7 2217 */
<> 144:ef7eb2e8f9f7 2218 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2219 {
<> 144:ef7eb2e8f9f7 2220 uint32_t itsource = hspi->Instance->CR2;
<> 144:ef7eb2e8f9f7 2221 uint32_t itflag = hspi->Instance->SR;
<> 144:ef7eb2e8f9f7 2222
<> 144:ef7eb2e8f9f7 2223 /* SPI in mode Receiver ----------------------------------------------------*/
<> 157:ff67d9f36b67 2224 if (((itflag & SPI_FLAG_OVR) == RESET) &&
<> 157:ff67d9f36b67 2225 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 2226 {
<> 144:ef7eb2e8f9f7 2227 hspi->RxISR(hspi);
<> 144:ef7eb2e8f9f7 2228 return;
<> 144:ef7eb2e8f9f7 2229 }
<> 144:ef7eb2e8f9f7 2230
<> 157:ff67d9f36b67 2231 /* SPI in mode Transmitter -------------------------------------------------*/
<> 157:ff67d9f36b67 2232 if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 2233 {
<> 144:ef7eb2e8f9f7 2234 hspi->TxISR(hspi);
<> 144:ef7eb2e8f9f7 2235 return;
<> 144:ef7eb2e8f9f7 2236 }
<> 144:ef7eb2e8f9f7 2237
<> 157:ff67d9f36b67 2238 /* SPI in Error Treatment --------------------------------------------------*/
<> 157:ff67d9f36b67 2239 if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 2240 {
<> 157:ff67d9f36b67 2241 /* SPI Overrun error interrupt occurred ----------------------------------*/
<> 157:ff67d9f36b67 2242 if ((itflag & SPI_FLAG_OVR) != RESET)
<> 144:ef7eb2e8f9f7 2243 {
<> 157:ff67d9f36b67 2244 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2245 {
<> 157:ff67d9f36b67 2246 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<> 144:ef7eb2e8f9f7 2247 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2248 }
<> 144:ef7eb2e8f9f7 2249 else
<> 144:ef7eb2e8f9f7 2250 {
<> 157:ff67d9f36b67 2251 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2252 return;
<> 144:ef7eb2e8f9f7 2253 }
<> 144:ef7eb2e8f9f7 2254 }
<> 144:ef7eb2e8f9f7 2255
<> 157:ff67d9f36b67 2256 /* SPI Mode Fault error interrupt occurred -------------------------------*/
<> 157:ff67d9f36b67 2257 if ((itflag & SPI_FLAG_MODF) != RESET)
<> 144:ef7eb2e8f9f7 2258 {
<> 157:ff67d9f36b67 2259 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<> 144:ef7eb2e8f9f7 2260 __HAL_SPI_CLEAR_MODFFLAG(hspi);
<> 144:ef7eb2e8f9f7 2261 }
<> 144:ef7eb2e8f9f7 2262
<> 157:ff67d9f36b67 2263 /* SPI Frame error interrupt occurred ------------------------------------*/
<> 157:ff67d9f36b67 2264 if ((itflag & SPI_FLAG_FRE) != RESET)
<> 144:ef7eb2e8f9f7 2265 {
<> 157:ff67d9f36b67 2266 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<> 144:ef7eb2e8f9f7 2267 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 144:ef7eb2e8f9f7 2268 }
<> 144:ef7eb2e8f9f7 2269
<> 157:ff67d9f36b67 2270 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2271 {
<> 157:ff67d9f36b67 2272 /* Disable all interrupts */
<> 157:ff67d9f36b67 2273 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
<> 157:ff67d9f36b67 2274
<> 144:ef7eb2e8f9f7 2275 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2276 /* Disable the SPI DMA requests if enabled */
<> 157:ff67d9f36b67 2277 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
<> 144:ef7eb2e8f9f7 2278 {
<> 144:ef7eb2e8f9f7 2279 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
<> 144:ef7eb2e8f9f7 2280
<> 144:ef7eb2e8f9f7 2281 /* Abort the SPI DMA Rx channel */
<> 157:ff67d9f36b67 2282 if (hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 2283 {
<> 144:ef7eb2e8f9f7 2284 /* Set the SPI DMA Abort callback :
<> 144:ef7eb2e8f9f7 2285 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
<> 144:ef7eb2e8f9f7 2286 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
<> 157:ff67d9f36b67 2287 HAL_DMA_Abort_IT(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 2288 }
<> 144:ef7eb2e8f9f7 2289 /* Abort the SPI DMA Tx channel */
<> 157:ff67d9f36b67 2290 if (hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 2291 {
<> 144:ef7eb2e8f9f7 2292 /* Set the SPI DMA Abort callback :
<> 144:ef7eb2e8f9f7 2293 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
<> 144:ef7eb2e8f9f7 2294 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
<> 157:ff67d9f36b67 2295 HAL_DMA_Abort_IT(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 2296 }
<> 144:ef7eb2e8f9f7 2297 }
<> 144:ef7eb2e8f9f7 2298 else
<> 144:ef7eb2e8f9f7 2299 {
<> 144:ef7eb2e8f9f7 2300 /* Call user error callback */
<> 144:ef7eb2e8f9f7 2301 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2302 }
<> 144:ef7eb2e8f9f7 2303 }
<> 157:ff67d9f36b67 2304 return;
<> 144:ef7eb2e8f9f7 2305 }
<> 144:ef7eb2e8f9f7 2306 }
<> 144:ef7eb2e8f9f7 2307
<> 144:ef7eb2e8f9f7 2308 /**
<> 144:ef7eb2e8f9f7 2309 * @brief Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2310 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2311 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2312 * @retval None
<> 144:ef7eb2e8f9f7 2313 */
<> 144:ef7eb2e8f9f7 2314 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2315 {
<> 144:ef7eb2e8f9f7 2316 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2317 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2318
<> 144:ef7eb2e8f9f7 2319 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2320 the HAL_SPI_TxCpltCallback should be implemented in the user file
<> 157:ff67d9f36b67 2321 */
<> 144:ef7eb2e8f9f7 2322 }
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 /**
<> 144:ef7eb2e8f9f7 2325 * @brief Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2326 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2327 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2328 * @retval None
<> 144:ef7eb2e8f9f7 2329 */
<> 144:ef7eb2e8f9f7 2330 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2331 {
<> 144:ef7eb2e8f9f7 2332 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2333 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2334
<> 144:ef7eb2e8f9f7 2335 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2336 the HAL_SPI_RxCpltCallback should be implemented in the user file
<> 157:ff67d9f36b67 2337 */
<> 144:ef7eb2e8f9f7 2338 }
<> 144:ef7eb2e8f9f7 2339
<> 144:ef7eb2e8f9f7 2340 /**
<> 144:ef7eb2e8f9f7 2341 * @brief Tx and Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2342 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2343 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2344 * @retval None
<> 144:ef7eb2e8f9f7 2345 */
<> 144:ef7eb2e8f9f7 2346 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2347 {
<> 144:ef7eb2e8f9f7 2348 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2349 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2350
<> 144:ef7eb2e8f9f7 2351 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2352 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
<> 157:ff67d9f36b67 2353 */
<> 144:ef7eb2e8f9f7 2354 }
<> 144:ef7eb2e8f9f7 2355
<> 144:ef7eb2e8f9f7 2356 /**
<> 144:ef7eb2e8f9f7 2357 * @brief Tx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 2358 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2359 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2360 * @retval None
<> 144:ef7eb2e8f9f7 2361 */
<> 144:ef7eb2e8f9f7 2362 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2363 {
<> 144:ef7eb2e8f9f7 2364 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2365 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2366
<> 144:ef7eb2e8f9f7 2367 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2368 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
<> 157:ff67d9f36b67 2369 */
<> 144:ef7eb2e8f9f7 2370 }
<> 144:ef7eb2e8f9f7 2371
<> 144:ef7eb2e8f9f7 2372 /**
<> 144:ef7eb2e8f9f7 2373 * @brief Rx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 2374 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2375 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2376 * @retval None
<> 144:ef7eb2e8f9f7 2377 */
<> 144:ef7eb2e8f9f7 2378 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2379 {
<> 144:ef7eb2e8f9f7 2380 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2381 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2384 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
<> 157:ff67d9f36b67 2385 */
<> 144:ef7eb2e8f9f7 2386 }
<> 144:ef7eb2e8f9f7 2387
<> 144:ef7eb2e8f9f7 2388 /**
<> 144:ef7eb2e8f9f7 2389 * @brief Tx and Rx Half Transfer callback.
<> 144:ef7eb2e8f9f7 2390 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2391 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2392 * @retval None
<> 144:ef7eb2e8f9f7 2393 */
<> 144:ef7eb2e8f9f7 2394 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2395 {
<> 144:ef7eb2e8f9f7 2396 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2397 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2398
<> 144:ef7eb2e8f9f7 2399 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2400 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
<> 157:ff67d9f36b67 2401 */
<> 144:ef7eb2e8f9f7 2402 }
<> 144:ef7eb2e8f9f7 2403
<> 144:ef7eb2e8f9f7 2404 /**
<> 144:ef7eb2e8f9f7 2405 * @brief SPI error callback.
<> 144:ef7eb2e8f9f7 2406 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2407 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2408 * @retval None
<> 144:ef7eb2e8f9f7 2409 */
<> 144:ef7eb2e8f9f7 2410 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2411 {
<> 144:ef7eb2e8f9f7 2412 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2413 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2414
<> 144:ef7eb2e8f9f7 2415 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2416 the HAL_SPI_ErrorCallback should be implemented in the user file
<> 157:ff67d9f36b67 2417 */
<> 144:ef7eb2e8f9f7 2418 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
<> 157:ff67d9f36b67 2419 and user can use HAL_SPI_GetError() API to check the latest error occurred
<> 157:ff67d9f36b67 2420 */
<> 157:ff67d9f36b67 2421 }
<> 157:ff67d9f36b67 2422
<> 157:ff67d9f36b67 2423 /**
<> 157:ff67d9f36b67 2424 * @brief SPI Abort Complete callback.
<> 157:ff67d9f36b67 2425 * @param hspi SPI handle.
<> 157:ff67d9f36b67 2426 * @retval None
<> 144:ef7eb2e8f9f7 2427 */
<> 157:ff67d9f36b67 2428 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
<> 157:ff67d9f36b67 2429 {
<> 157:ff67d9f36b67 2430 /* Prevent unused argument(s) compilation warning */
<> 157:ff67d9f36b67 2431 UNUSED(hspi);
<> 157:ff67d9f36b67 2432
<> 157:ff67d9f36b67 2433 /* NOTE : This function should not be modified, when the callback is needed,
<> 157:ff67d9f36b67 2434 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
<> 157:ff67d9f36b67 2435 */
<> 144:ef7eb2e8f9f7 2436 }
<> 144:ef7eb2e8f9f7 2437
<> 144:ef7eb2e8f9f7 2438 /**
<> 144:ef7eb2e8f9f7 2439 * @}
<> 144:ef7eb2e8f9f7 2440 */
<> 144:ef7eb2e8f9f7 2441
<> 144:ef7eb2e8f9f7 2442 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<> 157:ff67d9f36b67 2443 * @brief SPI control functions
<> 144:ef7eb2e8f9f7 2444 *
<> 144:ef7eb2e8f9f7 2445 @verbatim
<> 144:ef7eb2e8f9f7 2446 ===============================================================================
<> 144:ef7eb2e8f9f7 2447 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 2448 ===============================================================================
<> 144:ef7eb2e8f9f7 2449 [..]
<> 144:ef7eb2e8f9f7 2450 This subsection provides a set of functions allowing to control the SPI.
<> 144:ef7eb2e8f9f7 2451 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<> 144:ef7eb2e8f9f7 2452 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<> 144:ef7eb2e8f9f7 2453 @endverbatim
<> 144:ef7eb2e8f9f7 2454 * @{
<> 144:ef7eb2e8f9f7 2455 */
<> 144:ef7eb2e8f9f7 2456
<> 144:ef7eb2e8f9f7 2457 /**
<> 144:ef7eb2e8f9f7 2458 * @brief Return the SPI handle state.
<> 144:ef7eb2e8f9f7 2459 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2460 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2461 * @retval SPI state
<> 144:ef7eb2e8f9f7 2462 */
<> 144:ef7eb2e8f9f7 2463 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2464 {
<> 144:ef7eb2e8f9f7 2465 /* Return SPI handle state */
<> 144:ef7eb2e8f9f7 2466 return hspi->State;
<> 144:ef7eb2e8f9f7 2467 }
<> 144:ef7eb2e8f9f7 2468
<> 144:ef7eb2e8f9f7 2469 /**
<> 144:ef7eb2e8f9f7 2470 * @brief Return the SPI error code.
<> 144:ef7eb2e8f9f7 2471 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2472 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2473 * @retval SPI error code in bitmap format
<> 144:ef7eb2e8f9f7 2474 */
<> 144:ef7eb2e8f9f7 2475 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2476 {
<> 157:ff67d9f36b67 2477 /* Return SPI ErrorCode */
<> 144:ef7eb2e8f9f7 2478 return hspi->ErrorCode;
<> 144:ef7eb2e8f9f7 2479 }
<> 144:ef7eb2e8f9f7 2480
<> 144:ef7eb2e8f9f7 2481 /**
<> 144:ef7eb2e8f9f7 2482 * @}
<> 144:ef7eb2e8f9f7 2483 */
<> 144:ef7eb2e8f9f7 2484
<> 144:ef7eb2e8f9f7 2485 /**
<> 144:ef7eb2e8f9f7 2486 * @}
<> 144:ef7eb2e8f9f7 2487 */
<> 144:ef7eb2e8f9f7 2488
<> 144:ef7eb2e8f9f7 2489 /** @addtogroup SPI_Private_Functions
<> 157:ff67d9f36b67 2490 * @brief Private functions
<> 144:ef7eb2e8f9f7 2491 * @{
<> 144:ef7eb2e8f9f7 2492 */
<> 144:ef7eb2e8f9f7 2493
<> 144:ef7eb2e8f9f7 2494 /**
<> 144:ef7eb2e8f9f7 2495 * @brief DMA SPI transmit process complete callback.
<> 144:ef7eb2e8f9f7 2496 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2497 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2498 * @retval None
<> 144:ef7eb2e8f9f7 2499 */
<> 144:ef7eb2e8f9f7 2500 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2501 {
<> 157:ff67d9f36b67 2502 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2503 uint32_t tickstart = 0U;
<> 157:ff67d9f36b67 2504
<> 157:ff67d9f36b67 2505 /* Init tickstart for timeout managment*/
<> 157:ff67d9f36b67 2506 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2507
<> 144:ef7eb2e8f9f7 2508 /* DMA Normal Mode */
<> 157:ff67d9f36b67 2509 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
<> 144:ef7eb2e8f9f7 2510 {
<> 157:ff67d9f36b67 2511 /* Disable ERR interrupt */
<> 157:ff67d9f36b67 2512 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 157:ff67d9f36b67 2513
<> 144:ef7eb2e8f9f7 2514 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 2515 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2516
<> 144:ef7eb2e8f9f7 2517 /* Check the end of the transaction */
<> 157:ff67d9f36b67 2518 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2519 {
<> 157:ff67d9f36b67 2520 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2521 }
<> 144:ef7eb2e8f9f7 2522
<> 144:ef7eb2e8f9f7 2523 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
<> 157:ff67d9f36b67 2524 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 2525 {
<> 144:ef7eb2e8f9f7 2526 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2527 }
<> 144:ef7eb2e8f9f7 2528
<> 157:ff67d9f36b67 2529 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2530 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2531
<> 157:ff67d9f36b67 2532 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2533 {
<> 144:ef7eb2e8f9f7 2534 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2535 return;
<> 144:ef7eb2e8f9f7 2536 }
<> 144:ef7eb2e8f9f7 2537 }
<> 144:ef7eb2e8f9f7 2538 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2539 }
<> 144:ef7eb2e8f9f7 2540
<> 144:ef7eb2e8f9f7 2541 /**
<> 144:ef7eb2e8f9f7 2542 * @brief DMA SPI receive process complete callback.
<> 144:ef7eb2e8f9f7 2543 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2544 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2545 * @retval None
<> 144:ef7eb2e8f9f7 2546 */
<> 144:ef7eb2e8f9f7 2547 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2548 {
<> 157:ff67d9f36b67 2549 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2550 uint32_t tickstart = 0U;
<> 157:ff67d9f36b67 2551 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 2552 __IO uint16_t tmpreg = 0U;
<> 157:ff67d9f36b67 2553 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 2554
<> 157:ff67d9f36b67 2555 /* Init tickstart for timeout management*/
<> 157:ff67d9f36b67 2556 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 2557
<> 157:ff67d9f36b67 2558 /* DMA Normal Mode */
<> 157:ff67d9f36b67 2559 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
<> 144:ef7eb2e8f9f7 2560 {
<> 157:ff67d9f36b67 2561 /* Disable ERR interrupt */
<> 157:ff67d9f36b67 2562 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 2563
<> 144:ef7eb2e8f9f7 2564 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2565 /* CRC handling */
<> 157:ff67d9f36b67 2566 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2567 {
<> 157:ff67d9f36b67 2568 /* Wait until RXNE flag */
<> 157:ff67d9f36b67 2569 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2570 {
<> 144:ef7eb2e8f9f7 2571 /* Error on the CRC reception */
<> 157:ff67d9f36b67 2572 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2573 }
<> 157:ff67d9f36b67 2574 /* Read CRC */
<> 157:ff67d9f36b67 2575 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 2576 {
<> 144:ef7eb2e8f9f7 2577 tmpreg = hspi->Instance->DR;
<> 157:ff67d9f36b67 2578 /* To avoid GCC warning */
<> 157:ff67d9f36b67 2579 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2580 }
<> 144:ef7eb2e8f9f7 2581 else
<> 144:ef7eb2e8f9f7 2582 {
<> 144:ef7eb2e8f9f7 2583 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 2584 /* To avoid GCC warning */
<> 157:ff67d9f36b67 2585 UNUSED(tmpreg);
<> 157:ff67d9f36b67 2586
<> 157:ff67d9f36b67 2587 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 2588 {
<> 157:ff67d9f36b67 2589 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2590 {
<> 144:ef7eb2e8f9f7 2591 /* Error on the CRC reception */
<> 157:ff67d9f36b67 2592 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2593 }
<> 144:ef7eb2e8f9f7 2594 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 2595 /* To avoid GCC warning */
<> 157:ff67d9f36b67 2596 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2597 }
<> 144:ef7eb2e8f9f7 2598 }
<> 144:ef7eb2e8f9f7 2599 }
<> 157:ff67d9f36b67 2600 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2601
<> 144:ef7eb2e8f9f7 2602 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
<> 144:ef7eb2e8f9f7 2603 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2604
<> 144:ef7eb2e8f9f7 2605 /* Check the end of the transaction */
<> 157:ff67d9f36b67 2606 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2607 {
<> 157:ff67d9f36b67 2608 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2609 }
<> 144:ef7eb2e8f9f7 2610
<> 157:ff67d9f36b67 2611 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2612 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2613
<> 144:ef7eb2e8f9f7 2614 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2615 /* Check if CRC error occurred */
<> 157:ff67d9f36b67 2616 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 2617 {
<> 157:ff67d9f36b67 2618 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2619 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2620 }
<> 157:ff67d9f36b67 2621 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 2622
<> 157:ff67d9f36b67 2623 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2624 {
<> 144:ef7eb2e8f9f7 2625 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2626 return;
<> 144:ef7eb2e8f9f7 2627 }
<> 144:ef7eb2e8f9f7 2628 }
<> 144:ef7eb2e8f9f7 2629 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2630 }
<> 144:ef7eb2e8f9f7 2631
<> 144:ef7eb2e8f9f7 2632 /**
<> 157:ff67d9f36b67 2633 * @brief DMA SPI transmit receive process complete callback.
<> 157:ff67d9f36b67 2634 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2635 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2636 * @retval None
<> 144:ef7eb2e8f9f7 2637 */
<> 144:ef7eb2e8f9f7 2638 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2639 {
<> 157:ff67d9f36b67 2640 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2641 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 2642 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 2643 __IO int16_t tmpreg = 0U;
<> 157:ff67d9f36b67 2644 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 2645 /* Init tickstart for timeout management*/
<> 157:ff67d9f36b67 2646 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 2647
<> 157:ff67d9f36b67 2648 /* DMA Normal Mode */
<> 157:ff67d9f36b67 2649 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
<> 144:ef7eb2e8f9f7 2650 {
<> 157:ff67d9f36b67 2651 /* Disable ERR interrupt */
<> 157:ff67d9f36b67 2652 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 2653
<> 144:ef7eb2e8f9f7 2654 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 2655 /* CRC handling */
<> 157:ff67d9f36b67 2656 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 157:ff67d9f36b67 2657 {
<> 157:ff67d9f36b67 2658 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
<> 157:ff67d9f36b67 2659 {
<> 157:ff67d9f36b67 2660 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
<> 157:ff67d9f36b67 2661 tickstart) != HAL_OK)
<> 157:ff67d9f36b67 2662 {
<> 157:ff67d9f36b67 2663 /* Error on the CRC reception */
<> 157:ff67d9f36b67 2664 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 157:ff67d9f36b67 2665 }
<> 157:ff67d9f36b67 2666 /* Read CRC to Flush DR and RXNE flag */
<> 157:ff67d9f36b67 2667 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 157:ff67d9f36b67 2668 /* To avoid GCC warning */
<> 157:ff67d9f36b67 2669 UNUSED(tmpreg);
<> 157:ff67d9f36b67 2670 }
<> 157:ff67d9f36b67 2671 else
<> 157:ff67d9f36b67 2672 {
<> 157:ff67d9f36b67 2673 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 157:ff67d9f36b67 2674 {
<> 157:ff67d9f36b67 2675 /* Error on the CRC reception */
<> 157:ff67d9f36b67 2676 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 157:ff67d9f36b67 2677 }
<> 157:ff67d9f36b67 2678 /* Read CRC to Flush DR and RXNE flag */
<> 157:ff67d9f36b67 2679 tmpreg = hspi->Instance->DR;
<> 157:ff67d9f36b67 2680 /* To avoid GCC warning */
<> 157:ff67d9f36b67 2681 UNUSED(tmpreg);
<> 157:ff67d9f36b67 2682 }
<> 157:ff67d9f36b67 2683 }
<> 157:ff67d9f36b67 2684 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 2685
<> 157:ff67d9f36b67 2686 /* Check the end of the transaction */
<> 157:ff67d9f36b67 2687 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 157:ff67d9f36b67 2688 {
<> 157:ff67d9f36b67 2689 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 157:ff67d9f36b67 2690 }
<> 157:ff67d9f36b67 2691
<> 157:ff67d9f36b67 2692 /* Disable Rx/Tx DMA Request */
<> 157:ff67d9f36b67 2693 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 157:ff67d9f36b67 2694
<> 157:ff67d9f36b67 2695 hspi->TxXferCount = 0U;
<> 157:ff67d9f36b67 2696 hspi->RxXferCount = 0U;
<> 157:ff67d9f36b67 2697 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 2698
<> 157:ff67d9f36b67 2699 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 2700 /* Check if CRC error occurred */
<> 157:ff67d9f36b67 2701 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 157:ff67d9f36b67 2702 {
<> 157:ff67d9f36b67 2703 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 157:ff67d9f36b67 2704 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 157:ff67d9f36b67 2705 }
<> 157:ff67d9f36b67 2706 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 2707
<> 157:ff67d9f36b67 2708 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 157:ff67d9f36b67 2709 {
<> 157:ff67d9f36b67 2710 HAL_SPI_ErrorCallback(hspi);
<> 157:ff67d9f36b67 2711 return;
<> 157:ff67d9f36b67 2712 }
<> 144:ef7eb2e8f9f7 2713 }
<> 144:ef7eb2e8f9f7 2714 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2715 }
<> 144:ef7eb2e8f9f7 2716
<> 144:ef7eb2e8f9f7 2717 /**
<> 157:ff67d9f36b67 2718 * @brief DMA SPI half transmit process complete callback.
<> 157:ff67d9f36b67 2719 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2720 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2721 * @retval None
<> 144:ef7eb2e8f9f7 2722 */
<> 144:ef7eb2e8f9f7 2723 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2724 {
<> 157:ff67d9f36b67 2725 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2726
<> 144:ef7eb2e8f9f7 2727 HAL_SPI_TxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2728 }
<> 144:ef7eb2e8f9f7 2729
<> 144:ef7eb2e8f9f7 2730 /**
<> 157:ff67d9f36b67 2731 * @brief DMA SPI half receive process complete callback
<> 144:ef7eb2e8f9f7 2732 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2733 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2734 * @retval None
<> 144:ef7eb2e8f9f7 2735 */
<> 144:ef7eb2e8f9f7 2736 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2737 {
<> 157:ff67d9f36b67 2738 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2739
<> 144:ef7eb2e8f9f7 2740 HAL_SPI_RxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2741 }
<> 144:ef7eb2e8f9f7 2742
<> 144:ef7eb2e8f9f7 2743 /**
<> 157:ff67d9f36b67 2744 * @brief DMA SPI half transmit receive process complete callback.
<> 157:ff67d9f36b67 2745 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2746 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2747 * @retval None
<> 144:ef7eb2e8f9f7 2748 */
<> 144:ef7eb2e8f9f7 2749 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2750 {
<> 157:ff67d9f36b67 2751 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2752
<> 144:ef7eb2e8f9f7 2753 HAL_SPI_TxRxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2754 }
<> 144:ef7eb2e8f9f7 2755
<> 144:ef7eb2e8f9f7 2756 /**
<> 157:ff67d9f36b67 2757 * @brief DMA SPI communication error callback.
<> 157:ff67d9f36b67 2758 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2759 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2760 * @retval None
<> 144:ef7eb2e8f9f7 2761 */
<> 144:ef7eb2e8f9f7 2762 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2763 {
<> 157:ff67d9f36b67 2764 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2765
<> 144:ef7eb2e8f9f7 2766 /* Stop the disable DMA transfer on SPI side */
<> 144:ef7eb2e8f9f7 2767 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2768
<> 157:ff67d9f36b67 2769 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2770 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2771 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2772 }
<> 144:ef7eb2e8f9f7 2773
<> 144:ef7eb2e8f9f7 2774 /**
<> 157:ff67d9f36b67 2775 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
<> 157:ff67d9f36b67 2776 * (To be called at end of DMA Abort procedure following error occurrence).
<> 157:ff67d9f36b67 2777 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2778 * @retval None
<> 144:ef7eb2e8f9f7 2779 */
<> 144:ef7eb2e8f9f7 2780 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2781 {
<> 157:ff67d9f36b67 2782 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2783 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2784 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2785
<> 144:ef7eb2e8f9f7 2786 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2787 }
<> 144:ef7eb2e8f9f7 2788
<> 144:ef7eb2e8f9f7 2789 /**
<> 157:ff67d9f36b67 2790 * @brief DMA SPI Tx communication abort callback, when initiated by user
<> 157:ff67d9f36b67 2791 * (To be called at end of DMA Tx Abort procedure following user abort request).
<> 157:ff67d9f36b67 2792 * @note When this callback is executed, User Abort complete call back is called only if no
<> 157:ff67d9f36b67 2793 * Abort still ongoing for Rx DMA Handle.
<> 157:ff67d9f36b67 2794 * @param hdma DMA handle.
<> 157:ff67d9f36b67 2795 * @retval None
<> 157:ff67d9f36b67 2796 */
<> 157:ff67d9f36b67 2797 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<> 157:ff67d9f36b67 2798 {
<> 157:ff67d9f36b67 2799 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2800
<> 157:ff67d9f36b67 2801 hspi->hdmatx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2802
<> 157:ff67d9f36b67 2803 /* Disable Tx DMA Request */
<> 157:ff67d9f36b67 2804 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 157:ff67d9f36b67 2805
<> 157:ff67d9f36b67 2806 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 2807 {
<> 157:ff67d9f36b67 2808 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2809 }
<> 157:ff67d9f36b67 2810
<> 157:ff67d9f36b67 2811 /* Disable SPI Peripheral */
<> 157:ff67d9f36b67 2812 __HAL_SPI_DISABLE(hspi);
<> 157:ff67d9f36b67 2813
<> 157:ff67d9f36b67 2814 /* Empty the FRLVL fifo */
<> 157:ff67d9f36b67 2815 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 2816 {
<> 157:ff67d9f36b67 2817 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2818 }
<> 157:ff67d9f36b67 2819
<> 157:ff67d9f36b67 2820 /* Check if an Abort process is still ongoing */
<> 157:ff67d9f36b67 2821 if (hspi->hdmarx != NULL)
<> 157:ff67d9f36b67 2822 {
<> 157:ff67d9f36b67 2823 if (hspi->hdmarx->XferAbortCallback != NULL)
<> 157:ff67d9f36b67 2824 {
<> 157:ff67d9f36b67 2825 return;
<> 157:ff67d9f36b67 2826 }
<> 157:ff67d9f36b67 2827 }
<> 157:ff67d9f36b67 2828
<> 157:ff67d9f36b67 2829 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
<> 157:ff67d9f36b67 2830 hspi->RxXferCount = 0U;
<> 157:ff67d9f36b67 2831 hspi->TxXferCount = 0U;
<> 157:ff67d9f36b67 2832
<> 157:ff67d9f36b67 2833 /* Check no error during Abort procedure */
<> 157:ff67d9f36b67 2834 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
<> 157:ff67d9f36b67 2835 {
<> 157:ff67d9f36b67 2836 /* Reset errorCode */
<> 157:ff67d9f36b67 2837 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 2838 }
<> 157:ff67d9f36b67 2839
<> 157:ff67d9f36b67 2840 /* Clear the Error flags in the SR register */
<> 157:ff67d9f36b67 2841 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 157:ff67d9f36b67 2842 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 157:ff67d9f36b67 2843
<> 157:ff67d9f36b67 2844 /* Restore hspi->State to Ready */
<> 157:ff67d9f36b67 2845 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 2846
<> 157:ff67d9f36b67 2847 /* Call user Abort complete callback */
<> 157:ff67d9f36b67 2848 HAL_SPI_AbortCpltCallback(hspi);
<> 157:ff67d9f36b67 2849 }
<> 157:ff67d9f36b67 2850
<> 157:ff67d9f36b67 2851 /**
<> 157:ff67d9f36b67 2852 * @brief DMA SPI Rx communication abort callback, when initiated by user
<> 157:ff67d9f36b67 2853 * (To be called at end of DMA Rx Abort procedure following user abort request).
<> 157:ff67d9f36b67 2854 * @note When this callback is executed, User Abort complete call back is called only if no
<> 157:ff67d9f36b67 2855 * Abort still ongoing for Tx DMA Handle.
<> 157:ff67d9f36b67 2856 * @param hdma DMA handle.
<> 157:ff67d9f36b67 2857 * @retval None
<> 157:ff67d9f36b67 2858 */
<> 157:ff67d9f36b67 2859 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<> 157:ff67d9f36b67 2860 {
<> 157:ff67d9f36b67 2861 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 157:ff67d9f36b67 2862
<> 157:ff67d9f36b67 2863 /* Disable SPI Peripheral */
<> 157:ff67d9f36b67 2864 __HAL_SPI_DISABLE(hspi);
<> 157:ff67d9f36b67 2865
<> 157:ff67d9f36b67 2866 hspi->hdmarx->XferAbortCallback = NULL;
<> 157:ff67d9f36b67 2867
<> 157:ff67d9f36b67 2868 /* Disable Rx DMA Request */
<> 157:ff67d9f36b67 2869 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 157:ff67d9f36b67 2870
<> 157:ff67d9f36b67 2871 /* Control the BSY flag */
<> 157:ff67d9f36b67 2872 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 2873 {
<> 157:ff67d9f36b67 2874 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2875 }
<> 157:ff67d9f36b67 2876
<> 157:ff67d9f36b67 2877 /* Empty the FRLVL fifo */
<> 157:ff67d9f36b67 2878 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 2879 {
<> 157:ff67d9f36b67 2880 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 2881 }
<> 157:ff67d9f36b67 2882
<> 157:ff67d9f36b67 2883 /* Check if an Abort process is still ongoing */
<> 157:ff67d9f36b67 2884 if (hspi->hdmatx != NULL)
<> 157:ff67d9f36b67 2885 {
<> 157:ff67d9f36b67 2886 if (hspi->hdmatx->XferAbortCallback != NULL)
<> 157:ff67d9f36b67 2887 {
<> 157:ff67d9f36b67 2888 return;
<> 157:ff67d9f36b67 2889 }
<> 157:ff67d9f36b67 2890 }
<> 157:ff67d9f36b67 2891
<> 157:ff67d9f36b67 2892 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
<> 157:ff67d9f36b67 2893 hspi->RxXferCount = 0U;
<> 157:ff67d9f36b67 2894 hspi->TxXferCount = 0U;
<> 157:ff67d9f36b67 2895
<> 157:ff67d9f36b67 2896 /* Check no error during Abort procedure */
<> 157:ff67d9f36b67 2897 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
<> 157:ff67d9f36b67 2898 {
<> 157:ff67d9f36b67 2899 /* Reset errorCode */
<> 157:ff67d9f36b67 2900 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 157:ff67d9f36b67 2901 }
<> 157:ff67d9f36b67 2902
<> 157:ff67d9f36b67 2903 /* Clear the Error flags in the SR register */
<> 157:ff67d9f36b67 2904 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 157:ff67d9f36b67 2905 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 157:ff67d9f36b67 2906
<> 157:ff67d9f36b67 2907 /* Restore hspi->State to Ready */
<> 157:ff67d9f36b67 2908 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 2909
<> 157:ff67d9f36b67 2910 /* Call user Abort complete callback */
<> 157:ff67d9f36b67 2911 HAL_SPI_AbortCpltCallback(hspi);
<> 157:ff67d9f36b67 2912 }
<> 157:ff67d9f36b67 2913
<> 157:ff67d9f36b67 2914 /**
<> 144:ef7eb2e8f9f7 2915 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2916 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2917 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2918 * @retval None
<> 144:ef7eb2e8f9f7 2919 */
<> 144:ef7eb2e8f9f7 2920 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2921 {
<> 144:ef7eb2e8f9f7 2922 /* Receive data in packing mode */
<> 157:ff67d9f36b67 2923 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 2924 {
<> 157:ff67d9f36b67 2925 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2926 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 157:ff67d9f36b67 2927 hspi->RxXferCount -= 2U;
<> 157:ff67d9f36b67 2928 if (hspi->RxXferCount == 1U)
<> 144:ef7eb2e8f9f7 2929 {
<> 144:ef7eb2e8f9f7 2930 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 2931 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 2932 }
<> 144:ef7eb2e8f9f7 2933 }
<> 144:ef7eb2e8f9f7 2934 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 2935 else
<> 144:ef7eb2e8f9f7 2936 {
<> 144:ef7eb2e8f9f7 2937 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 2938 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 2939 }
<> 144:ef7eb2e8f9f7 2940
<> 144:ef7eb2e8f9f7 2941 /* check end of the reception */
<> 157:ff67d9f36b67 2942 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2943 {
<> 144:ef7eb2e8f9f7 2944 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 2945 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2946 {
<> 144:ef7eb2e8f9f7 2947 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 2948 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 2949 return;
<> 144:ef7eb2e8f9f7 2950 }
<> 157:ff67d9f36b67 2951 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 2952
<> 157:ff67d9f36b67 2953 /* Disable RXNE and ERR interrupt */
<> 157:ff67d9f36b67 2954 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 157:ff67d9f36b67 2955
<> 157:ff67d9f36b67 2956 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2957 {
<> 144:ef7eb2e8f9f7 2958 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2959 }
<> 144:ef7eb2e8f9f7 2960 }
<> 144:ef7eb2e8f9f7 2961 }
<> 144:ef7eb2e8f9f7 2962
<> 144:ef7eb2e8f9f7 2963 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2964 /**
<> 144:ef7eb2e8f9f7 2965 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2966 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2967 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2968 * @retval None
<> 144:ef7eb2e8f9f7 2969 */
<> 144:ef7eb2e8f9f7 2970 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2971 {
<> 157:ff67d9f36b67 2972 __IO uint8_t tmpreg = 0U;
<> 157:ff67d9f36b67 2973
<> 157:ff67d9f36b67 2974 /* Read data register to flush CRC */
<> 157:ff67d9f36b67 2975 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 157:ff67d9f36b67 2976
<> 157:ff67d9f36b67 2977 /* To avoid GCC warning */
<> 157:ff67d9f36b67 2978 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2979
<> 144:ef7eb2e8f9f7 2980 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 2981
<> 144:ef7eb2e8f9f7 2982 /* check end of the reception */
<> 157:ff67d9f36b67 2983 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 2984 {
<> 157:ff67d9f36b67 2985 /* Disable RXNE and ERR interrupt */
<> 157:ff67d9f36b67 2986 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 157:ff67d9f36b67 2987
<> 157:ff67d9f36b67 2988 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2989 {
<> 144:ef7eb2e8f9f7 2990 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2991 }
<> 144:ef7eb2e8f9f7 2992 }
<> 144:ef7eb2e8f9f7 2993 }
<> 157:ff67d9f36b67 2994 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2995
<> 144:ef7eb2e8f9f7 2996 /**
<> 144:ef7eb2e8f9f7 2997 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2998 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2999 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3000 * @retval None
<> 144:ef7eb2e8f9f7 3001 */
<> 144:ef7eb2e8f9f7 3002 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3003 {
<> 144:ef7eb2e8f9f7 3004 /* Transmit data in packing Bit mode */
<> 157:ff67d9f36b67 3005 if (hspi->TxXferCount >= 2U)
<> 144:ef7eb2e8f9f7 3006 {
<> 144:ef7eb2e8f9f7 3007 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3008 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 157:ff67d9f36b67 3009 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 3010 }
<> 144:ef7eb2e8f9f7 3011 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 3012 else
<> 144:ef7eb2e8f9f7 3013 {
<> 144:ef7eb2e8f9f7 3014 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3015 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3016 }
<> 144:ef7eb2e8f9f7 3017
<> 144:ef7eb2e8f9f7 3018 /* check the end of the transmission */
<> 157:ff67d9f36b67 3019 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3020 {
<> 144:ef7eb2e8f9f7 3021 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 3022 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3023 {
<> 157:ff67d9f36b67 3024 /* Set CRC Next Bit to send CRC */
<> 157:ff67d9f36b67 3025 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 157:ff67d9f36b67 3026 /* Disable TXE interrupt */
<> 157:ff67d9f36b67 3027 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 157:ff67d9f36b67 3028 return;
<> 144:ef7eb2e8f9f7 3029 }
<> 157:ff67d9f36b67 3030 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3031
<> 144:ef7eb2e8f9f7 3032 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3033 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3034
<> 157:ff67d9f36b67 3035 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3036 {
<> 144:ef7eb2e8f9f7 3037 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3038 }
<> 144:ef7eb2e8f9f7 3039 }
<> 144:ef7eb2e8f9f7 3040 }
<> 144:ef7eb2e8f9f7 3041
<> 144:ef7eb2e8f9f7 3042 /**
<> 144:ef7eb2e8f9f7 3043 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3044 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3045 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3046 * @retval None
<> 144:ef7eb2e8f9f7 3047 */
<> 144:ef7eb2e8f9f7 3048 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3049 {
<> 144:ef7eb2e8f9f7 3050 /* Receive data in 16 Bit mode */
<> 157:ff67d9f36b67 3051 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3052 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3053 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3054
<> 157:ff67d9f36b67 3055 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3056 {
<> 144:ef7eb2e8f9f7 3057 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 3058 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3059 {
<> 144:ef7eb2e8f9f7 3060 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3061 return;
<> 144:ef7eb2e8f9f7 3062 }
<> 157:ff67d9f36b67 3063 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3064
<> 144:ef7eb2e8f9f7 3065 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3066 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3067
<> 157:ff67d9f36b67 3068 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3069 {
<> 144:ef7eb2e8f9f7 3070 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3071 }
<> 144:ef7eb2e8f9f7 3072 }
<> 144:ef7eb2e8f9f7 3073 }
<> 144:ef7eb2e8f9f7 3074
<> 144:ef7eb2e8f9f7 3075 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3076 /**
<> 144:ef7eb2e8f9f7 3077 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3078 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3079 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3080 * @retval None
<> 144:ef7eb2e8f9f7 3081 */
<> 144:ef7eb2e8f9f7 3082 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3083 {
<> 144:ef7eb2e8f9f7 3084 /* Receive data in 16 Bit mode */
<> 157:ff67d9f36b67 3085 __IO uint16_t tmpreg = 0U;
<> 157:ff67d9f36b67 3086
<> 157:ff67d9f36b67 3087 /* Read data register to flush CRC */
<> 157:ff67d9f36b67 3088 tmpreg = hspi->Instance->DR;
<> 157:ff67d9f36b67 3089
<> 157:ff67d9f36b67 3090 /* To avoid GCC warning */
<> 157:ff67d9f36b67 3091 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3092
<> 144:ef7eb2e8f9f7 3093 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3094 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3095
<> 144:ef7eb2e8f9f7 3096 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3097 }
<> 157:ff67d9f36b67 3098 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3099
<> 144:ef7eb2e8f9f7 3100 /**
<> 144:ef7eb2e8f9f7 3101 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3102 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3103 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3104 * @retval None
<> 144:ef7eb2e8f9f7 3105 */
<> 144:ef7eb2e8f9f7 3106 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3107 {
<> 144:ef7eb2e8f9f7 3108 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3109 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3110 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3111 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3112
<> 144:ef7eb2e8f9f7 3113 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 3114 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3115 {
<> 144:ef7eb2e8f9f7 3116 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 3117 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3118 {
<> 157:ff67d9f36b67 3119 /* Set CRC Next Bit to send CRC */
<> 157:ff67d9f36b67 3120 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 157:ff67d9f36b67 3121 /* Disable TXE interrupt */
<> 157:ff67d9f36b67 3122 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 157:ff67d9f36b67 3123 return;
<> 144:ef7eb2e8f9f7 3124 }
<> 157:ff67d9f36b67 3125 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3126
<> 144:ef7eb2e8f9f7 3127 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3128 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3129
<> 157:ff67d9f36b67 3130 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3131 {
<> 144:ef7eb2e8f9f7 3132 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3133 }
<> 144:ef7eb2e8f9f7 3134 }
<> 144:ef7eb2e8f9f7 3135 }
<> 144:ef7eb2e8f9f7 3136
<> 144:ef7eb2e8f9f7 3137 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3138 /**
<> 144:ef7eb2e8f9f7 3139 * @brief Manage the CRC 8-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3140 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3141 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3142 * @retval None
<> 144:ef7eb2e8f9f7 3143 */
<> 144:ef7eb2e8f9f7 3144 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3145 {
<> 157:ff67d9f36b67 3146 __IO uint8_t tmpreg = 0U;
<> 157:ff67d9f36b67 3147
<> 157:ff67d9f36b67 3148 /* Read data register to flush CRC */
<> 157:ff67d9f36b67 3149 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 157:ff67d9f36b67 3150
<> 157:ff67d9f36b67 3151 /* To avoid GCC warning */
<> 157:ff67d9f36b67 3152 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3153
<> 144:ef7eb2e8f9f7 3154 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 3155
<> 157:ff67d9f36b67 3156 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 3157 {
<> 144:ef7eb2e8f9f7 3158 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3159 }
<> 144:ef7eb2e8f9f7 3160 }
<> 157:ff67d9f36b67 3161 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3162
<> 144:ef7eb2e8f9f7 3163 /**
<> 144:ef7eb2e8f9f7 3164 * @brief Manage the receive 8-bit in Interrupt context.
<> 144:ef7eb2e8f9f7 3165 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3166 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3167 * @retval None
<> 144:ef7eb2e8f9f7 3168 */
<> 144:ef7eb2e8f9f7 3169 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3170 {
<> 144:ef7eb2e8f9f7 3171 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3172 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3173
<> 144:ef7eb2e8f9f7 3174 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3175 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 3176 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3177 {
<> 157:ff67d9f36b67 3178 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3179 }
<> 157:ff67d9f36b67 3180 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 3181
<> 157:ff67d9f36b67 3182 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3183 {
<> 144:ef7eb2e8f9f7 3184 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 3185 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3186 {
<> 144:ef7eb2e8f9f7 3187 hspi->RxISR = SPI_RxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 3188 return;
<> 144:ef7eb2e8f9f7 3189 }
<> 157:ff67d9f36b67 3190 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3191 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3192 }
<> 144:ef7eb2e8f9f7 3193 }
<> 144:ef7eb2e8f9f7 3194
<> 144:ef7eb2e8f9f7 3195 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3196 /**
<> 144:ef7eb2e8f9f7 3197 * @brief Manage the CRC 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3198 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3199 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3200 * @retval None
<> 144:ef7eb2e8f9f7 3201 */
<> 144:ef7eb2e8f9f7 3202 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3203 {
<> 157:ff67d9f36b67 3204 __IO uint16_t tmpreg = 0U;
<> 157:ff67d9f36b67 3205
<> 157:ff67d9f36b67 3206 /* Read data register to flush CRC */
<> 144:ef7eb2e8f9f7 3207 tmpreg = hspi->Instance->DR;
<> 157:ff67d9f36b67 3208
<> 157:ff67d9f36b67 3209 /* To avoid GCC warning */
<> 157:ff67d9f36b67 3210 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3211
<> 144:ef7eb2e8f9f7 3212 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3213 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3214
<> 144:ef7eb2e8f9f7 3215 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3216 }
<> 157:ff67d9f36b67 3217 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3218
<> 144:ef7eb2e8f9f7 3219 /**
<> 144:ef7eb2e8f9f7 3220 * @brief Manage the 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3221 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3222 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3223 * @retval None
<> 144:ef7eb2e8f9f7 3224 */
<> 144:ef7eb2e8f9f7 3225 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3226 {
<> 144:ef7eb2e8f9f7 3227 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3228 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3229 hspi->RxXferCount--;
<> 157:ff67d9f36b67 3230
<> 144:ef7eb2e8f9f7 3231 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3232 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 3233 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3234 {
<> 157:ff67d9f36b67 3235 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3236 }
<> 157:ff67d9f36b67 3237 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 3238
<> 157:ff67d9f36b67 3239 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3240 {
<> 144:ef7eb2e8f9f7 3241 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 3242 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3243 {
<> 144:ef7eb2e8f9f7 3244 hspi->RxISR = SPI_RxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3245 return;
<> 144:ef7eb2e8f9f7 3246 }
<> 157:ff67d9f36b67 3247 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3248 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3249 }
<> 144:ef7eb2e8f9f7 3250 }
<> 144:ef7eb2e8f9f7 3251
<> 144:ef7eb2e8f9f7 3252 /**
<> 144:ef7eb2e8f9f7 3253 * @brief Handle the data 8-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 3254 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3255 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3256 * @retval None
<> 144:ef7eb2e8f9f7 3257 */
<> 144:ef7eb2e8f9f7 3258 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3259 {
<> 144:ef7eb2e8f9f7 3260 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3261 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3262
<> 157:ff67d9f36b67 3263 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3264 {
<> 144:ef7eb2e8f9f7 3265 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 3266 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3267 {
<> 144:ef7eb2e8f9f7 3268 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 3269 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3270 }
<> 157:ff67d9f36b67 3271 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3272 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3273 }
<> 144:ef7eb2e8f9f7 3274 }
<> 144:ef7eb2e8f9f7 3275
<> 144:ef7eb2e8f9f7 3276 /**
<> 144:ef7eb2e8f9f7 3277 * @brief Handle the data 16-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 3278 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3279 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3280 * @retval None
<> 144:ef7eb2e8f9f7 3281 */
<> 144:ef7eb2e8f9f7 3282 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3283 {
<> 144:ef7eb2e8f9f7 3284 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3285 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3286 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3287 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3288
<> 157:ff67d9f36b67 3289 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3290 {
<> 144:ef7eb2e8f9f7 3291 #if (USE_SPI_CRC != 0U)
<> 157:ff67d9f36b67 3292 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3293 {
<> 144:ef7eb2e8f9f7 3294 /* Enable CRC Transmission */
<> 157:ff67d9f36b67 3295 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3296 }
<> 157:ff67d9f36b67 3297 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3298 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3299 }
<> 144:ef7eb2e8f9f7 3300 }
<> 144:ef7eb2e8f9f7 3301
<> 144:ef7eb2e8f9f7 3302 /**
<> 144:ef7eb2e8f9f7 3303 * @brief Handle SPI Communication Timeout.
<> 157:ff67d9f36b67 3304 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 157:ff67d9f36b67 3305 * the configuration information for SPI module.
<> 157:ff67d9f36b67 3306 * @param Flag: SPI flag to check
<> 157:ff67d9f36b67 3307 * @param State: flag state to check
<> 157:ff67d9f36b67 3308 * @param Timeout: Timeout duration
<> 157:ff67d9f36b67 3309 * @param Tickstart: tick start value
<> 144:ef7eb2e8f9f7 3310 * @retval HAL status
<> 144:ef7eb2e8f9f7 3311 */
<> 157:ff67d9f36b67 3312 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
<> 157:ff67d9f36b67 3313 uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3314 {
<> 157:ff67d9f36b67 3315 while ((hspi->Instance->SR & Flag) != State)
<> 144:ef7eb2e8f9f7 3316 {
<> 157:ff67d9f36b67 3317 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 3318 {
<> 157:ff67d9f36b67 3319 if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 3320 {
<> 144:ef7eb2e8f9f7 3321 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 3322 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 3323 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 3324
<> 144:ef7eb2e8f9f7 3325 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 3326 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3327
<> 157:ff67d9f36b67 3328 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 157:ff67d9f36b67 3329 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3330 {
<> 144:ef7eb2e8f9f7 3331 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3332 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3333 }
<> 144:ef7eb2e8f9f7 3334
<> 144:ef7eb2e8f9f7 3335 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 3336 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3337 {
<> 144:ef7eb2e8f9f7 3338 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 3339 }
<> 144:ef7eb2e8f9f7 3340
<> 144:ef7eb2e8f9f7 3341 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3342
<> 144:ef7eb2e8f9f7 3343 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3344 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 3345
<> 144:ef7eb2e8f9f7 3346 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3347 }
<> 144:ef7eb2e8f9f7 3348 }
<> 144:ef7eb2e8f9f7 3349 }
<> 157:ff67d9f36b67 3350
<> 144:ef7eb2e8f9f7 3351 return HAL_OK;
<> 144:ef7eb2e8f9f7 3352 }
<> 144:ef7eb2e8f9f7 3353
<> 144:ef7eb2e8f9f7 3354 /**
<> 157:ff67d9f36b67 3355 * @brief Handle SPI FIFO Communication Timeout.
<> 157:ff67d9f36b67 3356 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 157:ff67d9f36b67 3357 * the configuration information for SPI module.
<> 157:ff67d9f36b67 3358 * @param Fifo: Fifo to check
<> 157:ff67d9f36b67 3359 * @param State: Fifo state to check
<> 157:ff67d9f36b67 3360 * @param Timeout: Timeout duration
<> 157:ff67d9f36b67 3361 * @param Tickstart: tick start value
<> 157:ff67d9f36b67 3362 * @retval HAL status
<> 157:ff67d9f36b67 3363 */
<> 157:ff67d9f36b67 3364 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
<> 157:ff67d9f36b67 3365 uint32_t Timeout, uint32_t Tickstart)
<> 157:ff67d9f36b67 3366 {
<> 157:ff67d9f36b67 3367 __IO uint8_t tmpreg;
<> 157:ff67d9f36b67 3368
<> 157:ff67d9f36b67 3369 while ((hspi->Instance->SR & Fifo) != State)
<> 157:ff67d9f36b67 3370 {
<> 157:ff67d9f36b67 3371 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
<> 157:ff67d9f36b67 3372 {
<> 157:ff67d9f36b67 3373 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 157:ff67d9f36b67 3374 /* To avoid GCC warning */
<> 157:ff67d9f36b67 3375 UNUSED(tmpreg);
<> 157:ff67d9f36b67 3376 }
<> 157:ff67d9f36b67 3377
<> 157:ff67d9f36b67 3378 if (Timeout != HAL_MAX_DELAY)
<> 157:ff67d9f36b67 3379 {
<> 157:ff67d9f36b67 3380 if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout))
<> 157:ff67d9f36b67 3381 {
<> 157:ff67d9f36b67 3382 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 157:ff67d9f36b67 3383 on both master and slave sides in order to resynchronize the master
<> 157:ff67d9f36b67 3384 and slave for their respective CRC calculation */
<> 157:ff67d9f36b67 3385
<> 157:ff67d9f36b67 3386 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 157:ff67d9f36b67 3387 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 157:ff67d9f36b67 3388
<> 157:ff67d9f36b67 3389 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 157:ff67d9f36b67 3390 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 157:ff67d9f36b67 3391 {
<> 157:ff67d9f36b67 3392 /* Disable SPI peripheral */
<> 157:ff67d9f36b67 3393 __HAL_SPI_DISABLE(hspi);
<> 157:ff67d9f36b67 3394 }
<> 157:ff67d9f36b67 3395
<> 157:ff67d9f36b67 3396 /* Reset CRC Calculation */
<> 157:ff67d9f36b67 3397 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 157:ff67d9f36b67 3398 {
<> 157:ff67d9f36b67 3399 SPI_RESET_CRC(hspi);
<> 157:ff67d9f36b67 3400 }
<> 157:ff67d9f36b67 3401
<> 157:ff67d9f36b67 3402 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 3403
<> 157:ff67d9f36b67 3404 /* Process Unlocked */
<> 157:ff67d9f36b67 3405 __HAL_UNLOCK(hspi);
<> 157:ff67d9f36b67 3406
<> 157:ff67d9f36b67 3407 return HAL_TIMEOUT;
<> 157:ff67d9f36b67 3408 }
<> 157:ff67d9f36b67 3409 }
<> 157:ff67d9f36b67 3410 }
<> 157:ff67d9f36b67 3411
<> 157:ff67d9f36b67 3412 return HAL_OK;
<> 157:ff67d9f36b67 3413 }
<> 157:ff67d9f36b67 3414
<> 157:ff67d9f36b67 3415 /**
<> 157:ff67d9f36b67 3416 * @brief Handle the check of the RX transaction complete.
<> 144:ef7eb2e8f9f7 3417 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3418 * the configuration information for SPI module.
<> 157:ff67d9f36b67 3419 * @param Timeout: Timeout duration
<> 157:ff67d9f36b67 3420 * @param Tickstart: tick start value
<> 157:ff67d9f36b67 3421 * @retval None.
<> 144:ef7eb2e8f9f7 3422 */
<> 157:ff67d9f36b67 3423 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3424 {
<> 157:ff67d9f36b67 3425 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 157:ff67d9f36b67 3426 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3427 {
<> 144:ef7eb2e8f9f7 3428 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3429 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3430 }
<> 144:ef7eb2e8f9f7 3431
<> 144:ef7eb2e8f9f7 3432 /* Control the BSY flag */
<> 157:ff67d9f36b67 3433 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3434 {
<> 157:ff67d9f36b67 3435 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3436 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3437 }
<> 144:ef7eb2e8f9f7 3438
<> 157:ff67d9f36b67 3439 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 157:ff67d9f36b67 3440 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3441 {
<> 144:ef7eb2e8f9f7 3442 /* Empty the FRLVL fifo */
<> 157:ff67d9f36b67 3443 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3444 {
<> 157:ff67d9f36b67 3445 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3446 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3447 }
<> 144:ef7eb2e8f9f7 3448 }
<> 144:ef7eb2e8f9f7 3449 return HAL_OK;
<> 144:ef7eb2e8f9f7 3450 }
<> 144:ef7eb2e8f9f7 3451
<> 144:ef7eb2e8f9f7 3452 /**
<> 144:ef7eb2e8f9f7 3453 * @brief Handle the check of the RXTX or TX transaction complete.
<> 144:ef7eb2e8f9f7 3454 * @param hspi: SPI handle
<> 157:ff67d9f36b67 3455 * @param Timeout: Timeout duration
<> 157:ff67d9f36b67 3456 * @param Tickstart: tick start value
<> 144:ef7eb2e8f9f7 3457 */
<> 157:ff67d9f36b67 3458 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3459 {
<> 157:ff67d9f36b67 3460 /* Control if the TX fifo is empty */
<> 157:ff67d9f36b67 3461 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3462 {
<> 157:ff67d9f36b67 3463 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3464 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3465 }
<> 144:ef7eb2e8f9f7 3466 /* Control the BSY flag */
<> 157:ff67d9f36b67 3467 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3468 {
<> 157:ff67d9f36b67 3469 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 157:ff67d9f36b67 3470 return HAL_TIMEOUT;
<> 157:ff67d9f36b67 3471 }
<> 157:ff67d9f36b67 3472 /* Control if the RX fifo is empty */
<> 157:ff67d9f36b67 3473 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 157:ff67d9f36b67 3474 {
<> 157:ff67d9f36b67 3475 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3476 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3477 }
<> 144:ef7eb2e8f9f7 3478 return HAL_OK;
<> 144:ef7eb2e8f9f7 3479 }
<> 144:ef7eb2e8f9f7 3480
<> 144:ef7eb2e8f9f7 3481 /**
<> 157:ff67d9f36b67 3482 * @brief Handle the end of the RXTX transaction.
<> 144:ef7eb2e8f9f7 3483 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3484 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3485 * @retval None
<> 144:ef7eb2e8f9f7 3486 */
<> 144:ef7eb2e8f9f7 3487 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3488 {
<> 157:ff67d9f36b67 3489 uint32_t tickstart = 0U;
<> 157:ff67d9f36b67 3490
<> 157:ff67d9f36b67 3491 /* Init tickstart for timeout managment*/
<> 157:ff67d9f36b67 3492 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 3493
<> 144:ef7eb2e8f9f7 3494 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 3495 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 3496
<> 144:ef7eb2e8f9f7 3497 /* Check the end of the transaction */
<> 157:ff67d9f36b67 3498 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3499 {
<> 157:ff67d9f36b67 3500 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3501 }
<> 144:ef7eb2e8f9f7 3502
<> 144:ef7eb2e8f9f7 3503 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3504 /* Check if CRC error occurred */
<> 157:ff67d9f36b67 3505 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 3506 {
<> 144:ef7eb2e8f9f7 3507 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 3508 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 3509 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3510 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3511 }
<> 144:ef7eb2e8f9f7 3512 else
<> 144:ef7eb2e8f9f7 3513 {
<> 157:ff67d9f36b67 3514 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 3515 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3516 {
<> 157:ff67d9f36b67 3517 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 3518 {
<> 144:ef7eb2e8f9f7 3519 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3520 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3521 }
<> 144:ef7eb2e8f9f7 3522 else
<> 144:ef7eb2e8f9f7 3523 {
<> 144:ef7eb2e8f9f7 3524 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3525 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3526 }
<> 144:ef7eb2e8f9f7 3527 }
<> 144:ef7eb2e8f9f7 3528 else
<> 144:ef7eb2e8f9f7 3529 {
<> 144:ef7eb2e8f9f7 3530 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3531 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3532 }
<> 144:ef7eb2e8f9f7 3533 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3534 }
<> 157:ff67d9f36b67 3535 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3536 }
<> 144:ef7eb2e8f9f7 3537
<> 144:ef7eb2e8f9f7 3538 /**
<> 157:ff67d9f36b67 3539 * @brief Handle the end of the RX transaction.
<> 144:ef7eb2e8f9f7 3540 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3541 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3542 * @retval None
<> 144:ef7eb2e8f9f7 3543 */
<> 144:ef7eb2e8f9f7 3544 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3545 {
<> 144:ef7eb2e8f9f7 3546 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3547 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3548
<> 144:ef7eb2e8f9f7 3549 /* Check the end of the transaction */
<> 157:ff67d9f36b67 3550 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 144:ef7eb2e8f9f7 3551 {
<> 157:ff67d9f36b67 3552 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3553 }
<> 144:ef7eb2e8f9f7 3554 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 3555
<> 144:ef7eb2e8f9f7 3556 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3557 /* Check if CRC error occurred */
<> 157:ff67d9f36b67 3558 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 3559 {
<> 157:ff67d9f36b67 3560 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 3561 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3562 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3563 }
<> 144:ef7eb2e8f9f7 3564 else
<> 144:ef7eb2e8f9f7 3565 {
<> 157:ff67d9f36b67 3566 #endif /* USE_SPI_CRC */
<> 157:ff67d9f36b67 3567 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3568 {
<> 144:ef7eb2e8f9f7 3569 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3570 }
<> 144:ef7eb2e8f9f7 3571 else
<> 144:ef7eb2e8f9f7 3572 {
<> 144:ef7eb2e8f9f7 3573 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3574 }
<> 144:ef7eb2e8f9f7 3575 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3576 }
<> 157:ff67d9f36b67 3577 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3578 }
<> 144:ef7eb2e8f9f7 3579
<> 144:ef7eb2e8f9f7 3580 /**
<> 157:ff67d9f36b67 3581 * @brief Handle the end of the TX transaction.
<> 144:ef7eb2e8f9f7 3582 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3583 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3584 * @retval None
<> 144:ef7eb2e8f9f7 3585 */
<> 144:ef7eb2e8f9f7 3586 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3587 {
<> 157:ff67d9f36b67 3588 uint32_t tickstart = 0U;
<> 157:ff67d9f36b67 3589
<> 157:ff67d9f36b67 3590 /* Init tickstart for timeout management*/
<> 157:ff67d9f36b67 3591 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 3592
<> 144:ef7eb2e8f9f7 3593 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3594 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3595
<> 144:ef7eb2e8f9f7 3596 /* Check the end of the transaction */
<> 157:ff67d9f36b67 3597 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3598 {
<> 157:ff67d9f36b67 3599 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3600 }
<> 144:ef7eb2e8f9f7 3601
<> 144:ef7eb2e8f9f7 3602 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 157:ff67d9f36b67 3603 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 3604 {
<> 144:ef7eb2e8f9f7 3605 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3606 }
<> 144:ef7eb2e8f9f7 3607
<> 144:ef7eb2e8f9f7 3608 hspi->State = HAL_SPI_STATE_READY;
<> 157:ff67d9f36b67 3609 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3610 {
<> 144:ef7eb2e8f9f7 3611 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3612 }
<> 144:ef7eb2e8f9f7 3613 else
<> 144:ef7eb2e8f9f7 3614 {
<> 144:ef7eb2e8f9f7 3615 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3616 }
<> 144:ef7eb2e8f9f7 3617 }
<> 144:ef7eb2e8f9f7 3618
<> 144:ef7eb2e8f9f7 3619 /**
<> 157:ff67d9f36b67 3620 * @brief Handle abort a Rx transaction.
<> 157:ff67d9f36b67 3621 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 157:ff67d9f36b67 3622 * the configuration information for SPI module.
<> 157:ff67d9f36b67 3623 * @retval None
<> 157:ff67d9f36b67 3624 */
<> 157:ff67d9f36b67 3625 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
<> 157:ff67d9f36b67 3626 {
<> 157:ff67d9f36b67 3627 /* Disable SPI Peripheral */
<> 157:ff67d9f36b67 3628 __HAL_SPI_DISABLE(hspi);
<> 157:ff67d9f36b67 3629
<> 157:ff67d9f36b67 3630 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 157:ff67d9f36b67 3631 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
<> 157:ff67d9f36b67 3632
<> 157:ff67d9f36b67 3633 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
<> 157:ff67d9f36b67 3634
<> 157:ff67d9f36b67 3635 /* Control the BSY flag */
<> 157:ff67d9f36b67 3636 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 3637 {
<> 157:ff67d9f36b67 3638 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 3639 }
<> 157:ff67d9f36b67 3640
<> 157:ff67d9f36b67 3641 /* Empty the FRLVL fifo */
<> 157:ff67d9f36b67 3642 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 3643 {
<> 157:ff67d9f36b67 3644 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 3645 }
<> 157:ff67d9f36b67 3646
<> 157:ff67d9f36b67 3647 hspi->State = HAL_SPI_STATE_ABORT;
<> 157:ff67d9f36b67 3648 }
<> 157:ff67d9f36b67 3649
<> 157:ff67d9f36b67 3650 /**
<> 157:ff67d9f36b67 3651 * @brief Handle abort a Tx or Rx/Tx transaction.
<> 157:ff67d9f36b67 3652 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 157:ff67d9f36b67 3653 * the configuration information for SPI module.
<> 157:ff67d9f36b67 3654 * @retval None
<> 157:ff67d9f36b67 3655 */
<> 157:ff67d9f36b67 3656 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
<> 157:ff67d9f36b67 3657 {
<> 157:ff67d9f36b67 3658 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 157:ff67d9f36b67 3659 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
<> 157:ff67d9f36b67 3660
<> 157:ff67d9f36b67 3661 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
<> 157:ff67d9f36b67 3662
<> 157:ff67d9f36b67 3663 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 3664 {
<> 157:ff67d9f36b67 3665 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 3666 }
<> 157:ff67d9f36b67 3667
<> 157:ff67d9f36b67 3668 /* Disable SPI Peripheral */
<> 157:ff67d9f36b67 3669 __HAL_SPI_DISABLE(hspi);
<> 157:ff67d9f36b67 3670
<> 157:ff67d9f36b67 3671 /* Empty the FRLVL fifo */
<> 157:ff67d9f36b67 3672 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 157:ff67d9f36b67 3673 {
<> 157:ff67d9f36b67 3674 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 157:ff67d9f36b67 3675 }
<> 157:ff67d9f36b67 3676
<> 157:ff67d9f36b67 3677 hspi->State = HAL_SPI_STATE_ABORT;
<> 157:ff67d9f36b67 3678 }
<> 157:ff67d9f36b67 3679
<> 157:ff67d9f36b67 3680 /**
<> 144:ef7eb2e8f9f7 3681 * @}
<> 144:ef7eb2e8f9f7 3682 */
<> 144:ef7eb2e8f9f7 3683
<> 144:ef7eb2e8f9f7 3684 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 3685
<> 144:ef7eb2e8f9f7 3686 /**
<> 144:ef7eb2e8f9f7 3687 * @}
<> 144:ef7eb2e8f9f7 3688 */
<> 144:ef7eb2e8f9f7 3689
<> 144:ef7eb2e8f9f7 3690 /**
<> 144:ef7eb2e8f9f7 3691 * @}
<> 144:ef7eb2e8f9f7 3692 */
<> 144:ef7eb2e8f9f7 3693
<> 144:ef7eb2e8f9f7 3694 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/