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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:: <>
Date:: Thu Feb 02 17:01:33 2017 +0000
Revision:: 157:ff67d9f36b67
Parent:: 149:156823d33999
Child:: 161:2cc1468da177

This updates the lib to the mbed lib v135

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_irda.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	157:ff67d9f36b67	5	* @version V1.1.2
<>	157:ff67d9f36b67	6	* @date 23-September-2016
<>	144:ef7eb2e8f9f7	7	* @brief IRDA HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	157:ff67d9f36b67	9	* functionalities of the IrDA (Infrared Data Association) Peripheral
<>	157:ff67d9f36b67	10	* (IRDA)
<>	157:ff67d9f36b67	11	* + Initialization and de-initialization functions
<>	157:ff67d9f36b67	12	* + IO operation functions
<>	157:ff67d9f36b67	13	* + Peripheral State and Errors functions
<>	157:ff67d9f36b67	14	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	15	*
<>	144:ef7eb2e8f9f7	16	@verbatim
<>	144:ef7eb2e8f9f7	17	==============================================================================
<>	144:ef7eb2e8f9f7	18	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	19	==============================================================================
<>	144:ef7eb2e8f9f7	20	[..]
<>	144:ef7eb2e8f9f7	21	The IRDA HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	22
<>	157:ff67d9f36b67	23	(#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
<>	157:ff67d9f36b67	24	(#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
<>	157:ff67d9f36b67	25	in setting the associated USART or UART in IRDA mode:
<>	157:ff67d9f36b67	26	(++) Enable the USARTx/UARTx interface clock.
<>	157:ff67d9f36b67	27	(++) USARTx/UARTx pins configuration:
<>	157:ff67d9f36b67	28	(+++) Enable the clock for the USARTx/UARTx GPIOs.
<>	157:ff67d9f36b67	29	(+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
<>	157:ff67d9f36b67	30	(++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
<>	157:ff67d9f36b67	31	and HAL_IRDA_Receive_IT() APIs):
<>	157:ff67d9f36b67	32	(+++) Configure the USARTx/UARTx interrupt priority.
<>	157:ff67d9f36b67	33	(+++) Enable the NVIC USARTx/UARTx IRQ handle.
<>	157:ff67d9f36b67	34	(+++) The specific IRDA interrupts (Transmission complete interrupt,
<>	157:ff67d9f36b67	35	RXNE interrupt and Error Interrupts) will be managed using the macros
<>	157:ff67d9f36b67	36	__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<>	157:ff67d9f36b67	37
<>	157:ff67d9f36b67	38	(++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
<>	144:ef7eb2e8f9f7	39	and HAL_IRDA_Receive_DMA() APIs):
<>	157:ff67d9f36b67	40	(+++) Declare a DMA handle structure for the Tx/Rx channel.
<>	144:ef7eb2e8f9f7	41	(+++) Enable the DMAx interface clock.
<>	144:ef7eb2e8f9f7	42	(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<>	157:ff67d9f36b67	43	(+++) Configure the DMA Tx/Rx channel.
<>	144:ef7eb2e8f9f7	44	(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
<>	157:ff67d9f36b67	45	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
<>	144:ef7eb2e8f9f7	48	and Mode(Receiver/Transmitter) in the hirda Init structure.
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
<>	144:ef7eb2e8f9f7	51	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<>	157:ff67d9f36b67	52	by calling the customized HAL_IRDA_MspInit() API.
<>	157:ff67d9f36b67	53
<>	157:ff67d9f36b67	54	-@@- The specific IRDA interrupts (Transmission complete interrupt,
<>	157:ff67d9f36b67	55	RXNE interrupt and Error Interrupts) will be managed using the macros
<>	157:ff67d9f36b67	56	__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<>	157:ff67d9f36b67	57
<>	144:ef7eb2e8f9f7	58	(#) Three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	61	=================================
<>	144:ef7eb2e8f9f7	62	[..]
<>	144:ef7eb2e8f9f7	63	(+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
<>	144:ef7eb2e8f9f7	64	(+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	67	===================================
<>	144:ef7eb2e8f9f7	68	[..]
<>	144:ef7eb2e8f9f7	69	(+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
<>	144:ef7eb2e8f9f7	70	(+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	71	add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<>	144:ef7eb2e8f9f7	72	(+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
<>	144:ef7eb2e8f9f7	73	(+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	74	add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<>	144:ef7eb2e8f9f7	75	(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	76	add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	79	=============================
<>	144:ef7eb2e8f9f7	80	[..]
<>	144:ef7eb2e8f9f7	81	(+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
<>	144:ef7eb2e8f9f7	82	(+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	83	add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<>	144:ef7eb2e8f9f7	84	(+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
<>	144:ef7eb2e8f9f7	85	(+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	86	add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<>	144:ef7eb2e8f9f7	87	(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	88	add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	* IRDA HAL driver macros list *
<>	144:ef7eb2e8f9f7	91	===================================
<>	144:ef7eb2e8f9f7	92	[..]
<>	144:ef7eb2e8f9f7	93	Below the list of most used macros in IRDA HAL driver.
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	(+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
<>	144:ef7eb2e8f9f7	96	(+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
<>	144:ef7eb2e8f9f7	97	(+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
<>	144:ef7eb2e8f9f7	98	(+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
<>	144:ef7eb2e8f9f7	99	(+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
<>	144:ef7eb2e8f9f7	100	(+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102	(@) You can refer to the IRDA HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	@endverbatim
<>	144:ef7eb2e8f9f7	105	******************************************************************************
<>	144:ef7eb2e8f9f7	106	* @attention
<>	144:ef7eb2e8f9f7	107	*
<>	144:ef7eb2e8f9f7	108	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	109	*
<>	144:ef7eb2e8f9f7	110	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	111	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	112	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	113	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	114	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	115	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	116	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	117	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	118	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	119	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	120	*
<>	144:ef7eb2e8f9f7	121	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	122	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	123	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	124	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	125	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	126	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	127	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	128	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	129	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	130	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	131	*
<>	144:ef7eb2e8f9f7	132	******************************************************************************
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	136	#include "stm32f7xx_hal.h"
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	139	* @{
<>	144:ef7eb2e8f9f7	140	*/
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	/** @defgroup IRDA IRDA
<>	144:ef7eb2e8f9f7	143	* @brief HAL IRDA module driver
<>	144:ef7eb2e8f9f7	144	* @{
<>	144:ef7eb2e8f9f7	145	*/
<>	157:ff67d9f36b67	146
<>	144:ef7eb2e8f9f7	147	#ifdef HAL_IRDA_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	148
<>	144:ef7eb2e8f9f7	149	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	150	/* Private define ------------------------------------------------------------*/
<>	157:ff67d9f36b67	151	/** @defgroup IRDA_Private_Constants IRDA Private Constants
<>	144:ef7eb2e8f9f7	152	* @{
<>	144:ef7eb2e8f9f7	153	*/
<>	157:ff67d9f36b67	154	#define IRDA_TEACK_REACK_TIMEOUT 1000U
<>	144:ef7eb2e8f9f7	155	#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U
<>	144:ef7eb2e8f9f7	156	#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M \| USART_CR1_PCE \
<>	157:ff67d9f36b67	157	\| USART_CR1_PS \| USART_CR1_TE \| USART_CR1_RE)) /!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API /
<>	144:ef7eb2e8f9f7	158	/**
<>	144:ef7eb2e8f9f7	159	* @}
<>	144:ef7eb2e8f9f7	160	*/
<>	157:ff67d9f36b67	161
<>	157:ff67d9f36b67	162	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	163	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	164	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	165	/** @addtogroup IRDA_Private_Functions
<>	144:ef7eb2e8f9f7	166	* @{
<>	144:ef7eb2e8f9f7	167	*/
<>	157:ff67d9f36b67	168	static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
<>	157:ff67d9f36b67	169	static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
<>	157:ff67d9f36b67	170	static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<>	157:ff67d9f36b67	171	static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
<>	157:ff67d9f36b67	172	static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
<>	144:ef7eb2e8f9f7	173	static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	174	static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	175	static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	176	static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	177	static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	178	static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	179	static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	180	static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	181	static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	182	static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	183	static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
<>	144:ef7eb2e8f9f7	184	static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
<>	144:ef7eb2e8f9f7	185	static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
<>	144:ef7eb2e8f9f7	186	/**
<>	144:ef7eb2e8f9f7	187	* @}
<>	144:ef7eb2e8f9f7	188	*/
<>	157:ff67d9f36b67	189
<>	144:ef7eb2e8f9f7	190	/* Exported functions --------------------------------------------------------*/
<>	157:ff67d9f36b67	191
<>	157:ff67d9f36b67	192	/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
<>	144:ef7eb2e8f9f7	193	* @{
<>	144:ef7eb2e8f9f7	194	*/
<>	144:ef7eb2e8f9f7	195
<>	157:ff67d9f36b67	196	/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	197	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	198	*
<>	144:ef7eb2e8f9f7	199	@verbatim
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	===============================================================================
<>	144:ef7eb2e8f9f7	202	##### Initialization and Configuration functions #####
<>	144:ef7eb2e8f9f7	203	===============================================================================
<>	144:ef7eb2e8f9f7	204	[..]
<>	144:ef7eb2e8f9f7	205	This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<>	144:ef7eb2e8f9f7	206	in IrDA mode.
<>	144:ef7eb2e8f9f7	207	(+) For the asynchronous mode only these parameters can be configured:
<>	144:ef7eb2e8f9f7	208	(++) BaudRate
<>	144:ef7eb2e8f9f7	209	(++) WordLength
<>	144:ef7eb2e8f9f7	210	(++) Parity: If the parity is enabled, then the MSB bit of the data written
<>	144:ef7eb2e8f9f7	211	in the data register is transmitted but is changed by the parity bit.
<>	144:ef7eb2e8f9f7	212	Depending on the frame length defined by the M bit (8-bits or 9-bits),
<>	144:ef7eb2e8f9f7	213	please refer to Reference manual for possible IRDA frame formats.
<>	144:ef7eb2e8f9f7	214	(++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
<>	144:ef7eb2e8f9f7	215	not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
<>	144:ef7eb2e8f9f7	216	specification specifies a minimum of 10 ms delay between transmission and
<>	144:ef7eb2e8f9f7	217	reception (IrDA is a half duplex protocol).
<>	144:ef7eb2e8f9f7	218	(++) Mode: Receiver/transmitter modes
<>	144:ef7eb2e8f9f7	219	(++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
<>	144:ef7eb2e8f9f7	220	[..]
<>	144:ef7eb2e8f9f7	221	The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
<>	144:ef7eb2e8f9f7	222	are available in reference manual).
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	@endverbatim
<>	144:ef7eb2e8f9f7	225	* @{
<>	144:ef7eb2e8f9f7	226	*/
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	/**
<>	157:ff67d9f36b67	229	* @brief Initialize the IRDA mode according to the specified
<>	157:ff67d9f36b67	230	* parameters in the IRDA_InitTypeDef and initialize the associated handle.
<>	157:ff67d9f36b67	231	* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	232	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	233	* @retval HAL status
<>	144:ef7eb2e8f9f7	234	*/
<>	144:ef7eb2e8f9f7	235	HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	236	{
<>	157:ff67d9f36b67	237	/* Check the IRDA handle allocation */
<>	157:ff67d9f36b67	238	if(hirda == NULL)
<>	157:ff67d9f36b67	239	{
<>	157:ff67d9f36b67	240	return HAL_ERROR;
<>	157:ff67d9f36b67	241	}
<>	144:ef7eb2e8f9f7	242
<>	157:ff67d9f36b67	243	/* Check the USART/UART associated to the IRDA handle */
<>	157:ff67d9f36b67	244	assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<>	144:ef7eb2e8f9f7	245
<>	157:ff67d9f36b67	246	if(hirda->gState == HAL_IRDA_STATE_RESET)
<>	157:ff67d9f36b67	247	{
<>	157:ff67d9f36b67	248	/* Allocate lock resource and initialize it */
<>	157:ff67d9f36b67	249	hirda->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	250
<>	157:ff67d9f36b67	251	/* Init the low level hardware : GPIO, CLOCK */
<>	157:ff67d9f36b67	252	HAL_IRDA_MspInit(hirda);
<>	157:ff67d9f36b67	253	}
<>	157:ff67d9f36b67	254
<>	157:ff67d9f36b67	255	hirda->gState = HAL_IRDA_STATE_BUSY;
<>	144:ef7eb2e8f9f7	256
<>	157:ff67d9f36b67	257	/* Disable the Peripheral to update the configuration registers */
<>	157:ff67d9f36b67	258	__HAL_IRDA_DISABLE(hirda);
<>	144:ef7eb2e8f9f7	259
<>	157:ff67d9f36b67	260	/* Set the IRDA Communication parameters */
<>	157:ff67d9f36b67	261	if (IRDA_SetConfig(hirda) == HAL_ERROR)
<>	157:ff67d9f36b67	262	{
<>	157:ff67d9f36b67	263	return HAL_ERROR;
<>	157:ff67d9f36b67	264	}
<>	144:ef7eb2e8f9f7	265
<>	157:ff67d9f36b67	266	/* In IRDA mode, the following bits must be kept cleared:
<>	157:ff67d9f36b67	267	- LINEN, STOP and CLKEN bits in the USART_CR2 register,
<>	157:ff67d9f36b67	268	- SCEN and HDSEL bits in the USART_CR3 register.*/
<>	157:ff67d9f36b67	269	CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN \| USART_CR2_STOP));
<>	157:ff67d9f36b67	270	CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL));
<>	144:ef7eb2e8f9f7	271
<>	157:ff67d9f36b67	272	/* set the UART/USART in IRDA mode */
<>	157:ff67d9f36b67	273	hirda->Instance->CR3 \|= USART_CR3_IREN;
<>	144:ef7eb2e8f9f7	274
<>	157:ff67d9f36b67	275	/* Enable the Peripheral */
<>	157:ff67d9f36b67	276	__HAL_IRDA_ENABLE(hirda);
<>	144:ef7eb2e8f9f7	277
<>	157:ff67d9f36b67	278	/* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
<>	157:ff67d9f36b67	279	return (IRDA_CheckIdleState(hirda));
<>	144:ef7eb2e8f9f7	280	}
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/**
<>	157:ff67d9f36b67	283	* @brief DeInitialize the IRDA peripheral.
<>	157:ff67d9f36b67	284	* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	285	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	286	* @retval HAL status
<>	144:ef7eb2e8f9f7	287	*/
<>	144:ef7eb2e8f9f7	288	HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	289	{
<>	157:ff67d9f36b67	290	/* Check the IRDA handle allocation */
<>	157:ff67d9f36b67	291	if(hirda == NULL)
<>	157:ff67d9f36b67	292	{
<>	157:ff67d9f36b67	293	return HAL_ERROR;
<>	157:ff67d9f36b67	294	}
<>	144:ef7eb2e8f9f7	295
<>	157:ff67d9f36b67	296	/* Check the USART/UART associated to the IRDA handle */
<>	157:ff67d9f36b67	297	assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<>	144:ef7eb2e8f9f7	298
<>	157:ff67d9f36b67	299	hirda->gState = HAL_IRDA_STATE_BUSY;
<>	144:ef7eb2e8f9f7	300
<>	157:ff67d9f36b67	301	/* DeInit the low level hardware */
<>	157:ff67d9f36b67	302	HAL_IRDA_MspDeInit(hirda);
<>	157:ff67d9f36b67	303	/* Disable the Peripheral */
<>	157:ff67d9f36b67	304	__HAL_IRDA_DISABLE(hirda);
<>	144:ef7eb2e8f9f7	305
<>	157:ff67d9f36b67	306	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	307	hirda->gState = HAL_IRDA_STATE_RESET;
<>	157:ff67d9f36b67	308	hirda->RxState = HAL_IRDA_STATE_RESET;
<>	144:ef7eb2e8f9f7	309
<>	157:ff67d9f36b67	310	/* Release Lock */
<>	157:ff67d9f36b67	311	__HAL_UNLOCK(hirda);
<>	144:ef7eb2e8f9f7	312
<>	157:ff67d9f36b67	313	return HAL_OK;
<>	144:ef7eb2e8f9f7	314	}
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	/**
<>	157:ff67d9f36b67	317	* @brief Initialize the IRDA MSP.
<>	157:ff67d9f36b67	318	* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	319	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	320	* @retval None
<>	144:ef7eb2e8f9f7	321	*/
<>	144:ef7eb2e8f9f7	322	__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	323	{
<>	157:ff67d9f36b67	324	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	325	UNUSED(hirda);
<>	144:ef7eb2e8f9f7	326
<>	157:ff67d9f36b67	327	/* NOTE: This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	328	the HAL_IRDA_MspInit can be implemented in the user file
<>	157:ff67d9f36b67	329	*/
<>	144:ef7eb2e8f9f7	330	}
<>	144:ef7eb2e8f9f7	331
<>	144:ef7eb2e8f9f7	332	/**
<>	157:ff67d9f36b67	333	* @brief DeInitialize the IRDA MSP.
<>	157:ff67d9f36b67	334	* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	335	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	336	* @retval None
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338	__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	339	{
<>	157:ff67d9f36b67	340	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	341	UNUSED(hirda);
<>	144:ef7eb2e8f9f7	342
<>	157:ff67d9f36b67	343	/* NOTE: This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	344	the HAL_IRDA_MspDeInit can be implemented in the user file
<>	157:ff67d9f36b67	345	*/
<>	144:ef7eb2e8f9f7	346	}
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/**
<>	144:ef7eb2e8f9f7	349	* @}
<>	144:ef7eb2e8f9f7	350	*/
<>	144:ef7eb2e8f9f7	351
<>	144:ef7eb2e8f9f7	352	/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
<>	157:ff67d9f36b67	353	* @brief IRDA Transmit and Receive functions
<>	144:ef7eb2e8f9f7	354	*
<>	144:ef7eb2e8f9f7	355	@verbatim
<>	144:ef7eb2e8f9f7	356	===============================================================================
<>	144:ef7eb2e8f9f7	357	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	358	===============================================================================
<>	157:ff67d9f36b67	359	[..]
<>	144:ef7eb2e8f9f7	360	This subsection provides a set of functions allowing to manage the IRDA data transfers.
<>	157:ff67d9f36b67	361
<>	157:ff67d9f36b67	362	[..]
<>	144:ef7eb2e8f9f7	363	IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
<>	144:ef7eb2e8f9f7	364	on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
<>	144:ef7eb2e8f9f7	365	is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
<>	144:ef7eb2e8f9f7	366	While receiving data, transmission should be avoided as the data to be transmitted
<>	144:ef7eb2e8f9f7	367	could be corrupted.
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	(#) There are two modes of transfer:
<>	157:ff67d9f36b67	370	(++) Blocking mode: the communication is performed in polling mode.
<>	157:ff67d9f36b67	371	The HAL status of all data processing is returned by the same function
<>	157:ff67d9f36b67	372	after finishing transfer.
<>	157:ff67d9f36b67	373	(++) Non-Blocking mode: the communication is performed using Interrupts
<>	157:ff67d9f36b67	374	or DMA, these API's return the HAL status.
<>	157:ff67d9f36b67	375	The end of the data processing will be indicated through the
<>	157:ff67d9f36b67	376	dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
<>	157:ff67d9f36b67	377	using DMA mode.
<>	157:ff67d9f36b67	378	The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
<>	157:ff67d9f36b67	379	will be executed respectively at the end of the Transmit or Receive process
<>	157:ff67d9f36b67	380	The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
<>	144:ef7eb2e8f9f7	381
<>	157:ff67d9f36b67	382	(#) Blocking mode APIs are :
<>	144:ef7eb2e8f9f7	383	(++) HAL_IRDA_Transmit()
<>	144:ef7eb2e8f9f7	384	(++) HAL_IRDA_Receive()
<>	144:ef7eb2e8f9f7	385
<>	157:ff67d9f36b67	386	(#) Non-Blocking mode APIs with Interrupt are :
<>	144:ef7eb2e8f9f7	387	(++) HAL_IRDA_Transmit_IT()
<>	144:ef7eb2e8f9f7	388	(++) HAL_IRDA_Receive_IT()
<>	144:ef7eb2e8f9f7	389	(++) HAL_IRDA_IRQHandler()
<>	144:ef7eb2e8f9f7	390	(++) IRDA_Transmit_IT()
<>	144:ef7eb2e8f9f7	391	(++) IRDA_Receive_IT()
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	(#) Non-Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	394	(++) HAL_IRDA_Transmit_DMA()
<>	144:ef7eb2e8f9f7	395	(++) HAL_IRDA_Receive_DMA()
<>	157:ff67d9f36b67	396	(++) HAL_IRDA_DMAPause()
<>	157:ff67d9f36b67	397	(++) HAL_IRDA_DMAResume()
<>	157:ff67d9f36b67	398	(++) HAL_IRDA_DMAStop()
<>	144:ef7eb2e8f9f7	399
<>	157:ff67d9f36b67	400	(#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
<>	157:ff67d9f36b67	401	(++) HAL_IRDA_TxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	402	(++) HAL_IRDA_TxCpltCallback()
<>	157:ff67d9f36b67	403	(++) HAL_IRDA_RxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	404	(++) HAL_IRDA_RxCpltCallback()
<>	144:ef7eb2e8f9f7	405	(++) HAL_IRDA_ErrorCallback()
<>	144:ef7eb2e8f9f7	406
<>	157:ff67d9f36b67	407	(#) Non-Blocking mode transfers could be aborted using Abort API's :
<>	157:ff67d9f36b67	408	(+) HAL_IRDA_Abort()
<>	157:ff67d9f36b67	409	(+) HAL_IRDA_AbortTransmit()
<>	157:ff67d9f36b67	410	(+) HAL_IRDA_AbortReceive()
<>	157:ff67d9f36b67	411	(+) HAL_IRDA_Abort_IT()
<>	157:ff67d9f36b67	412	(+) HAL_IRDA_AbortTransmit_IT()
<>	157:ff67d9f36b67	413	(+) HAL_IRDA_AbortReceive_IT()
<>	157:ff67d9f36b67	414
<>	157:ff67d9f36b67	415	(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
<>	157:ff67d9f36b67	416	(+) HAL_IRDA_AbortCpltCallback()
<>	157:ff67d9f36b67	417	(+) HAL_IRDA_AbortTransmitCpltCallback()
<>	157:ff67d9f36b67	418	(+) HAL_IRDA_AbortReceiveCpltCallback()
<>	157:ff67d9f36b67	419
<>	157:ff67d9f36b67	420	(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
<>	157:ff67d9f36b67	421	Errors are handled as follows :
<>	157:ff67d9f36b67	422	(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
<>	157:ff67d9f36b67	423	to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
<>	157:ff67d9f36b67	424	Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
<>	157:ff67d9f36b67	425	and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
<>	157:ff67d9f36b67	426	If user wants to abort it, Abort services should be called by user.
<>	157:ff67d9f36b67	427	(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
<>	157:ff67d9f36b67	428	This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
<>	157:ff67d9f36b67	429	Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
<>	157:ff67d9f36b67	430
<>	144:ef7eb2e8f9f7	431	@endverbatim
<>	144:ef7eb2e8f9f7	432	* @{
<>	144:ef7eb2e8f9f7	433	*/
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435	/**
<>	157:ff67d9f36b67	436	* @brief Send an amount of data in blocking mode.
<>	157:ff67d9f36b67	437	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	438	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	439	* @param pData Pointer to data buffer.
<>	157:ff67d9f36b67	440	* @param Size Amount of data to be sent.
<>	157:ff67d9f36b67	441	* @param Timeout Specify timeout value.
<>	144:ef7eb2e8f9f7	442	* @retval HAL status
<>	144:ef7eb2e8f9f7	443	*/
<>	144:ef7eb2e8f9f7	444	HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef hirda, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	445	{
<>	157:ff67d9f36b67	446	uint16_t* tmp;
<>	157:ff67d9f36b67	447	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	448
<>	157:ff67d9f36b67	449	/* Check that a Tx process is not already ongoing */
<>	157:ff67d9f36b67	450	if(hirda->gState == HAL_IRDA_STATE_READY)
<>	157:ff67d9f36b67	451	{
<>	157:ff67d9f36b67	452	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	453	{
<>	157:ff67d9f36b67	454	return HAL_ERROR;
<>	157:ff67d9f36b67	455	}
<>	144:ef7eb2e8f9f7	456
<>	157:ff67d9f36b67	457	/* Process Locked */
<>	157:ff67d9f36b67	458	__HAL_LOCK(hirda);
<>	157:ff67d9f36b67	459
<>	157:ff67d9f36b67	460	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	461	hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	462
<>	157:ff67d9f36b67	463	/* Init tickstart for timeout managment*/
<>	157:ff67d9f36b67	464	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	465
<>	157:ff67d9f36b67	466	hirda->TxXferSize = Size;
<>	157:ff67d9f36b67	467	hirda->TxXferCount = Size;
<>	157:ff67d9f36b67	468	while(hirda->TxXferCount > 0)
<>	157:ff67d9f36b67	469	{
<>	157:ff67d9f36b67	470	hirda->TxXferCount--;
<>	144:ef7eb2e8f9f7	471
<>	157:ff67d9f36b67	472	if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	157:ff67d9f36b67	473	{
<>	157:ff67d9f36b67	474	return HAL_TIMEOUT;
<>	157:ff67d9f36b67	475	}
<>	157:ff67d9f36b67	476	if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<>	157:ff67d9f36b67	477	{
<>	157:ff67d9f36b67	478	tmp = (uint16_t*) pData;
<>	157:ff67d9f36b67	479	hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
<>	157:ff67d9f36b67	480	pData += 2;
<>	157:ff67d9f36b67	481	}
<>	157:ff67d9f36b67	482	else
<>	157:ff67d9f36b67	483	{
<>	157:ff67d9f36b67	484	hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
<>	157:ff67d9f36b67	485	}
<>	157:ff67d9f36b67	486	}
<>	144:ef7eb2e8f9f7	487
<>	157:ff67d9f36b67	488	if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	157:ff67d9f36b67	489	{
<>	157:ff67d9f36b67	490	return HAL_TIMEOUT;
<>	157:ff67d9f36b67	491	}
<>	144:ef7eb2e8f9f7	492
<>	157:ff67d9f36b67	493	/* At end of Tx process, restore hirda->gState to Ready */
<>	157:ff67d9f36b67	494	hirda->gState = HAL_IRDA_STATE_READY;
<>	144:ef7eb2e8f9f7	495
<>	157:ff67d9f36b67	496	/* Process Unlocked */
<>	157:ff67d9f36b67	497	__HAL_UNLOCK(hirda);
<>	144:ef7eb2e8f9f7	498
<>	157:ff67d9f36b67	499	return HAL_OK;
<>	157:ff67d9f36b67	500	}
<>	157:ff67d9f36b67	501	else
<>	157:ff67d9f36b67	502	{
<>	157:ff67d9f36b67	503	return HAL_BUSY;
<>	157:ff67d9f36b67	504	}
<>	144:ef7eb2e8f9f7	505	}
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/**
<>	144:ef7eb2e8f9f7	508	* @brief Receive an amount of data in blocking mode.
<>	157:ff67d9f36b67	509	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	510	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	511	* @param pData Pointer to data buffer.
<>	157:ff67d9f36b67	512	* @param Size Amount of data to be received.
<>	157:ff67d9f36b67	513	* @param Timeout Specify timeout value.
<>	144:ef7eb2e8f9f7	514	* @retval HAL status
<>	144:ef7eb2e8f9f7	515	*/
<>	144:ef7eb2e8f9f7	516	HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef hirda, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	517	{
<>	157:ff67d9f36b67	518	uint16_t* tmp;
<>	157:ff67d9f36b67	519	uint16_t uhMask;
<>	157:ff67d9f36b67	520	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	521
<>	157:ff67d9f36b67	522	/* Check that a Rx process is not already ongoing */
<>	157:ff67d9f36b67	523	if(hirda->RxState == HAL_IRDA_STATE_READY)
<>	157:ff67d9f36b67	524	{
<>	157:ff67d9f36b67	525	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	526	{
<>	157:ff67d9f36b67	527	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	528	}
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/* Process Locked */
<>	144:ef7eb2e8f9f7	531	__HAL_LOCK(hirda);
<>	144:ef7eb2e8f9f7	532
<>	157:ff67d9f36b67	533	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	534	hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<>	157:ff67d9f36b67	535
<>	157:ff67d9f36b67	536	/* Init tickstart for timeout managment*/
<>	157:ff67d9f36b67	537	tickstart = HAL_GetTick();
<>	157:ff67d9f36b67	538
<>	157:ff67d9f36b67	539	hirda->RxXferSize = Size;
<>	157:ff67d9f36b67	540	hirda->RxXferCount = Size;
<>	157:ff67d9f36b67	541
<>	157:ff67d9f36b67	542	/* Computation of the mask to apply to RDR register
<>	157:ff67d9f36b67	543	of the UART associated to the IRDA */
<>	157:ff67d9f36b67	544	IRDA_MASK_COMPUTATION(hirda);
<>	157:ff67d9f36b67	545	uhMask = hirda->Mask;
<>	157:ff67d9f36b67	546
<>	157:ff67d9f36b67	547	/* Check data remaining to be received */
<>	157:ff67d9f36b67	548	while(hirda->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	549	{
<>	157:ff67d9f36b67	550	hirda->RxXferCount--;
<>	157:ff67d9f36b67	551
<>	157:ff67d9f36b67	552	if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	157:ff67d9f36b67	553	{
<>	157:ff67d9f36b67	554	return HAL_TIMEOUT;
<>	157:ff67d9f36b67	555	}
<>	157:ff67d9f36b67	556	if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<>	157:ff67d9f36b67	557	{
<>	157:ff67d9f36b67	558	tmp = (uint16_t*) pData ;
<>	157:ff67d9f36b67	559	*tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
<>	157:ff67d9f36b67	560	pData +=2;
<>	157:ff67d9f36b67	561	}
<>	157:ff67d9f36b67	562	else
<>	157:ff67d9f36b67	563	{
<>	157:ff67d9f36b67	564	*pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
<>	157:ff67d9f36b67	565	}
<>	144:ef7eb2e8f9f7	566	}
<>	144:ef7eb2e8f9f7	567
<>	157:ff67d9f36b67	568	/* At end of Rx process, restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	569	hirda->RxState = HAL_IRDA_STATE_READY;
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	572	__HAL_UNLOCK(hirda);
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	return HAL_OK;
<>	157:ff67d9f36b67	575	}
<>	157:ff67d9f36b67	576	else
<>	157:ff67d9f36b67	577	{
<>	157:ff67d9f36b67	578	return HAL_BUSY;
<>	157:ff67d9f36b67	579	}
<>	157:ff67d9f36b67	580	}
<>	157:ff67d9f36b67	581
<>	157:ff67d9f36b67	582	/**
<>	157:ff67d9f36b67	583	* @brief Send an amount of data in interrupt mode.
<>	157:ff67d9f36b67	584	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	585	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	586	* @param pData Pointer to data buffer.
<>	157:ff67d9f36b67	587	* @param Size Amount of data to be sent.
<>	157:ff67d9f36b67	588	* @retval HAL status
<>	157:ff67d9f36b67	589	*/
<>	157:ff67d9f36b67	590	HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef hirda, uint8_t pData, uint16_t Size)
<>	157:ff67d9f36b67	591	{
<>	157:ff67d9f36b67	592	/* Check that a Tx process is not already ongoing */
<>	157:ff67d9f36b67	593	if(hirda->gState == HAL_IRDA_STATE_READY)
<>	157:ff67d9f36b67	594	{
<>	157:ff67d9f36b67	595	if((pData == NULL) \|\| (Size == 0))
<>	157:ff67d9f36b67	596	{
<>	157:ff67d9f36b67	597	return HAL_ERROR;
<>	157:ff67d9f36b67	598	}
<>	157:ff67d9f36b67	599
<>	157:ff67d9f36b67	600	/* Process Locked */
<>	157:ff67d9f36b67	601	__HAL_LOCK(hirda);
<>	157:ff67d9f36b67	602
<>	157:ff67d9f36b67	603	hirda->pTxBuffPtr = pData;
<>	157:ff67d9f36b67	604	hirda->TxXferSize = Size;
<>	157:ff67d9f36b67	605	hirda->TxXferCount = Size;
<>	157:ff67d9f36b67	606
<>	157:ff67d9f36b67	607	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	608	hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<>	157:ff67d9f36b67	609
<>	157:ff67d9f36b67	610	/* Process Unlocked */
<>	157:ff67d9f36b67	611	__HAL_UNLOCK(hirda);
<>	157:ff67d9f36b67	612
<>	157:ff67d9f36b67	613	/* Enable the IRDA Transmit Data Register Empty Interrupt */
<>	157:ff67d9f36b67	614	SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<>	157:ff67d9f36b67	615
<>	157:ff67d9f36b67	616	return HAL_OK;
<>	157:ff67d9f36b67	617	}
<>	157:ff67d9f36b67	618	else
<>	157:ff67d9f36b67	619	{
<>	157:ff67d9f36b67	620	return HAL_BUSY;
<>	157:ff67d9f36b67	621	}
<>	157:ff67d9f36b67	622	}
<>	157:ff67d9f36b67	623
<>	157:ff67d9f36b67	624	/**
<>	157:ff67d9f36b67	625	* @brief Receive an amount of data in interrupt mode.
<>	157:ff67d9f36b67	626	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	627	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	628	* @param pData Pointer to data buffer.
<>	157:ff67d9f36b67	629	* @param Size Amount of data to be received.
<>	157:ff67d9f36b67	630	* @retval HAL status
<>	157:ff67d9f36b67	631	*/
<>	157:ff67d9f36b67	632	HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef hirda, uint8_t pData, uint16_t Size)
<>	157:ff67d9f36b67	633	{
<>	157:ff67d9f36b67	634	/* Check that a Rx process is not already ongoing */
<>	157:ff67d9f36b67	635	if(hirda->RxState == HAL_IRDA_STATE_READY)
<>	157:ff67d9f36b67	636	{
<>	157:ff67d9f36b67	637	if((pData == NULL) \|\| (Size == 0))
<>	157:ff67d9f36b67	638	{
<>	157:ff67d9f36b67	639	return HAL_ERROR;
<>	157:ff67d9f36b67	640	}
<>	157:ff67d9f36b67	641
<>	157:ff67d9f36b67	642	/* Process Locked */
<>	157:ff67d9f36b67	643	__HAL_LOCK(hirda);
<>	157:ff67d9f36b67	644
<>	157:ff67d9f36b67	645	hirda->pRxBuffPtr = pData;
<>	157:ff67d9f36b67	646	hirda->RxXferSize = Size;
<>	157:ff67d9f36b67	647	hirda->RxXferCount = Size;
<>	157:ff67d9f36b67	648
<>	157:ff67d9f36b67	649	/* Computation of the mask to apply to the RDR register
<>	157:ff67d9f36b67	650	of the UART associated to the IRDA */
<>	157:ff67d9f36b67	651	IRDA_MASK_COMPUTATION(hirda);
<>	157:ff67d9f36b67	652
<>	157:ff67d9f36b67	653	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	654	hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<>	157:ff67d9f36b67	655
<>	157:ff67d9f36b67	656	/* Process Unlocked */
<>	157:ff67d9f36b67	657	__HAL_UNLOCK(hirda);
<>	157:ff67d9f36b67	658
<>	157:ff67d9f36b67	659	/* Enable the IRDA Parity Error and Data Register not empty Interrupts */
<>	157:ff67d9f36b67	660	SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE\| USART_CR1_RXNEIE);
<>	157:ff67d9f36b67	661
<>	157:ff67d9f36b67	662	/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	663	SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	664
<>	157:ff67d9f36b67	665	return HAL_OK;
<>	157:ff67d9f36b67	666	}
<>	157:ff67d9f36b67	667	else
<>	157:ff67d9f36b67	668	{
<>	157:ff67d9f36b67	669	return HAL_BUSY;
<>	157:ff67d9f36b67	670	}
<>	144:ef7eb2e8f9f7	671	}
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	/**
<>	157:ff67d9f36b67	674	* @brief Send an amount of data in DMA mode.
<>	157:ff67d9f36b67	675	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	676	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	677	* @param pData pointer to data buffer.
<>	157:ff67d9f36b67	678	* @param Size amount of data to be sent.
<>	157:ff67d9f36b67	679	* @retval HAL status
<>	157:ff67d9f36b67	680	*/
<>	157:ff67d9f36b67	681	HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef hirda, uint8_t pData, uint16_t Size)
<>	157:ff67d9f36b67	682	{
<>	157:ff67d9f36b67	683	/* Check that a Tx process is not already ongoing */
<>	157:ff67d9f36b67	684	if(hirda->gState == HAL_IRDA_STATE_READY)
<>	157:ff67d9f36b67	685	{
<>	157:ff67d9f36b67	686	if((pData == NULL) \|\| (Size == 0))
<>	157:ff67d9f36b67	687	{
<>	157:ff67d9f36b67	688	return HAL_ERROR;
<>	157:ff67d9f36b67	689	}
<>	157:ff67d9f36b67	690
<>	157:ff67d9f36b67	691	/* Process Locked */
<>	157:ff67d9f36b67	692	__HAL_LOCK(hirda);
<>	157:ff67d9f36b67	693
<>	157:ff67d9f36b67	694	hirda->pTxBuffPtr = pData;
<>	157:ff67d9f36b67	695	hirda->TxXferSize = Size;
<>	157:ff67d9f36b67	696	hirda->TxXferCount = Size;
<>	157:ff67d9f36b67	697
<>	157:ff67d9f36b67	698	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	699	hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<>	157:ff67d9f36b67	700
<>	157:ff67d9f36b67	701	/* Set the IRDA DMA transfer complete callback */
<>	157:ff67d9f36b67	702	hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
<>	157:ff67d9f36b67	703
<>	157:ff67d9f36b67	704	/* Set the IRDA DMA half transfer complete callback */
<>	157:ff67d9f36b67	705	hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
<>	157:ff67d9f36b67	706
<>	157:ff67d9f36b67	707	/* Set the DMA error callback */
<>	157:ff67d9f36b67	708	hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
<>	157:ff67d9f36b67	709
<>	157:ff67d9f36b67	710	/* Set the DMA abort callback */
<>	157:ff67d9f36b67	711	hirda->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	712
<>	157:ff67d9f36b67	713	/* Enable the IRDA transmit DMA channel */
<>	157:ff67d9f36b67	714	HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
<>	157:ff67d9f36b67	715
<>	157:ff67d9f36b67	716	/* Clear the TC flag in the ICR register */
<>	157:ff67d9f36b67	717	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
<>	157:ff67d9f36b67	718
<>	157:ff67d9f36b67	719	/* Process Unlocked */
<>	157:ff67d9f36b67	720	__HAL_UNLOCK(hirda);
<>	157:ff67d9f36b67	721
<>	157:ff67d9f36b67	722	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	157:ff67d9f36b67	723	in the USART CR3 register */
<>	157:ff67d9f36b67	724	SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	725
<>	157:ff67d9f36b67	726	return HAL_OK;
<>	157:ff67d9f36b67	727	}
<>	157:ff67d9f36b67	728	else
<>	157:ff67d9f36b67	729	{
<>	157:ff67d9f36b67	730	return HAL_BUSY;
<>	157:ff67d9f36b67	731	}
<>	157:ff67d9f36b67	732	}
<>	157:ff67d9f36b67	733
<>	157:ff67d9f36b67	734	/**
<>	157:ff67d9f36b67	735	* @brief Receive an amount of data in DMA mode.
<>	157:ff67d9f36b67	736	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	737	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	738	* @param pData Pointer to data buffer.
<>	157:ff67d9f36b67	739	* @param Size Amount of data to be received.
<>	157:ff67d9f36b67	740	* @note When the IRDA parity is enabled (PCE = 1), the received data contains
<>	157:ff67d9f36b67	741	* the parity bit (MSB position).
<>	157:ff67d9f36b67	742	* @retval HAL status
<>	157:ff67d9f36b67	743	*/
<>	157:ff67d9f36b67	744	HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef hirda, uint8_t pData, uint16_t Size)
<>	157:ff67d9f36b67	745	{
<>	157:ff67d9f36b67	746	/* Check that a Rx process is not already ongoing */
<>	157:ff67d9f36b67	747	if(hirda->RxState == HAL_IRDA_STATE_READY)
<>	157:ff67d9f36b67	748	{
<>	157:ff67d9f36b67	749	if((pData == NULL) \|\| (Size == 0))
<>	157:ff67d9f36b67	750	{
<>	157:ff67d9f36b67	751	return HAL_ERROR;
<>	157:ff67d9f36b67	752	}
<>	157:ff67d9f36b67	753
<>	157:ff67d9f36b67	754	/* Process Locked */
<>	157:ff67d9f36b67	755	__HAL_LOCK(hirda);
<>	157:ff67d9f36b67	756
<>	157:ff67d9f36b67	757	hirda->pRxBuffPtr = pData;
<>	157:ff67d9f36b67	758	hirda->RxXferSize = Size;
<>	157:ff67d9f36b67	759
<>	157:ff67d9f36b67	760	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	761	hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<>	157:ff67d9f36b67	762
<>	157:ff67d9f36b67	763	/* Set the IRDA DMA transfer complete callback */
<>	157:ff67d9f36b67	764	hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
<>	157:ff67d9f36b67	765
<>	157:ff67d9f36b67	766	/* Set the IRDA DMA half transfer complete callback */
<>	157:ff67d9f36b67	767	hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
<>	157:ff67d9f36b67	768
<>	157:ff67d9f36b67	769	/* Set the DMA error callback */
<>	157:ff67d9f36b67	770	hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
<>	157:ff67d9f36b67	771
<>	157:ff67d9f36b67	772	/* Set the DMA abort callback */
<>	157:ff67d9f36b67	773	hirda->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	774
<>	157:ff67d9f36b67	775	/* Enable the DMA channel */
<>	157:ff67d9f36b67	776	HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
<>	157:ff67d9f36b67	777
<>	157:ff67d9f36b67	778	/* Process Unlocked */
<>	157:ff67d9f36b67	779	__HAL_UNLOCK(hirda);
<>	157:ff67d9f36b67	780
<>	157:ff67d9f36b67	781	/* Enable the UART Parity Error Interrupt */
<>	157:ff67d9f36b67	782	SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	783
<>	157:ff67d9f36b67	784	/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	785	SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	786
<>	157:ff67d9f36b67	787	/* Enable the DMA transfer for the receiver request by setting the DMAR bit
<>	157:ff67d9f36b67	788	in the USART CR3 register */
<>	157:ff67d9f36b67	789	SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	790
<>	157:ff67d9f36b67	791	return HAL_OK;
<>	157:ff67d9f36b67	792	}
<>	157:ff67d9f36b67	793	else
<>	157:ff67d9f36b67	794	{
<>	157:ff67d9f36b67	795	return HAL_BUSY;
<>	157:ff67d9f36b67	796	}
<>	157:ff67d9f36b67	797	}
<>	157:ff67d9f36b67	798
<>	157:ff67d9f36b67	799
<>	157:ff67d9f36b67	800	/**
<>	157:ff67d9f36b67	801	* @brief Pause the DMA Transfer.
<>	157:ff67d9f36b67	802	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	803	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	804	* @retval HAL status
<>	157:ff67d9f36b67	805	*/
<>	157:ff67d9f36b67	806	HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	807	{
<>	157:ff67d9f36b67	808	/* Process Locked */
<>	157:ff67d9f36b67	809	__HAL_LOCK(hirda);
<>	157:ff67d9f36b67	810
<>	157:ff67d9f36b67	811	if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
<>	157:ff67d9f36b67	812	(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
<>	157:ff67d9f36b67	813	{
<>	157:ff67d9f36b67	814	/* Disable the IRDA DMA Tx request */
<>	157:ff67d9f36b67	815	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	816	}
<>	157:ff67d9f36b67	817	if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
<>	157:ff67d9f36b67	818	(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<>	157:ff67d9f36b67	819	{
<>	157:ff67d9f36b67	820	/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	821	CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	822	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	823
<>	157:ff67d9f36b67	824	/* Disable the IRDA DMA Rx request */
<>	157:ff67d9f36b67	825	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	826	}
<>	157:ff67d9f36b67	827
<>	157:ff67d9f36b67	828	/* Process Unlocked */
<>	157:ff67d9f36b67	829	__HAL_UNLOCK(hirda);
<>	157:ff67d9f36b67	830
<>	157:ff67d9f36b67	831	return HAL_OK;
<>	157:ff67d9f36b67	832	}
<>	157:ff67d9f36b67	833
<>	157:ff67d9f36b67	834	/**
<>	157:ff67d9f36b67	835	* @brief Resume the DMA Transfer.
<>	157:ff67d9f36b67	836	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	837	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	838	* @retval HAL status
<>	144:ef7eb2e8f9f7	839	*/
<>	144:ef7eb2e8f9f7	840	HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	841	{
<>	157:ff67d9f36b67	842	/* Process Locked */
<>	157:ff67d9f36b67	843	__HAL_LOCK(hirda);
<>	144:ef7eb2e8f9f7	844
<>	157:ff67d9f36b67	845	if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<>	157:ff67d9f36b67	846	{
<>	157:ff67d9f36b67	847	/* Enable the IRDA DMA Tx request */
<>	157:ff67d9f36b67	848	SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	849	}
<>	157:ff67d9f36b67	850	if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<>	157:ff67d9f36b67	851	{
<>	157:ff67d9f36b67	852	/* Clear the Overrun flag before resuming the Rx transfer*/
<>	157:ff67d9f36b67	853	__HAL_IRDA_CLEAR_OREFLAG(hirda);
<>	144:ef7eb2e8f9f7	854
<>	157:ff67d9f36b67	855	/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	856	SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	857	SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	858
<>	157:ff67d9f36b67	859	/* Enable the IRDA DMA Rx request */
<>	157:ff67d9f36b67	860	SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	861	}
<>	144:ef7eb2e8f9f7	862
<>	157:ff67d9f36b67	863	/* Process Unlocked */
<>	157:ff67d9f36b67	864	__HAL_UNLOCK(hirda);
<>	144:ef7eb2e8f9f7	865
<>	157:ff67d9f36b67	866	return HAL_OK;
<>	144:ef7eb2e8f9f7	867	}
<>	144:ef7eb2e8f9f7	868
<>	144:ef7eb2e8f9f7	869	/**
<>	157:ff67d9f36b67	870	* @brief Stop the DMA Transfer.
<>	157:ff67d9f36b67	871	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	872	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	873	* @retval HAL status
<>	144:ef7eb2e8f9f7	874	*/
<>	144:ef7eb2e8f9f7	875	HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	876	{
<>	157:ff67d9f36b67	877	/* The Lock is not implemented on this API to allow the user application
<>	157:ff67d9f36b67	878	to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
<>	157:ff67d9f36b67	879	HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
<>	157:ff67d9f36b67	880	indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
<>	157:ff67d9f36b67	881	interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
<>	157:ff67d9f36b67	882	the stream and the corresponding call back is executed. */
<>	157:ff67d9f36b67	883
<>	157:ff67d9f36b67	884	/* Stop IRDA DMA Tx request if ongoing */
<>	157:ff67d9f36b67	885	if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
<>	157:ff67d9f36b67	886	(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
<>	157:ff67d9f36b67	887	{
<>	157:ff67d9f36b67	888	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	889
<>	157:ff67d9f36b67	890	/* Abort the IRDA DMA Tx channel */
<>	157:ff67d9f36b67	891	if(hirda->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	892	{
<>	157:ff67d9f36b67	893	HAL_DMA_Abort(hirda->hdmatx);
<>	157:ff67d9f36b67	894	}
<>	157:ff67d9f36b67	895
<>	157:ff67d9f36b67	896	IRDA_EndTxTransfer(hirda);
<>	157:ff67d9f36b67	897	}
<>	144:ef7eb2e8f9f7	898
<>	157:ff67d9f36b67	899	/* Stop IRDA DMA Rx request if ongoing */
<>	157:ff67d9f36b67	900	if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
<>	157:ff67d9f36b67	901	(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<>	157:ff67d9f36b67	902	{
<>	157:ff67d9f36b67	903	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	904
<>	157:ff67d9f36b67	905	/* Abort the IRDA DMA Rx channel */
<>	157:ff67d9f36b67	906	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	907	{
<>	157:ff67d9f36b67	908	HAL_DMA_Abort(hirda->hdmarx);
<>	144:ef7eb2e8f9f7	909	}
<>	144:ef7eb2e8f9f7	910
<>	157:ff67d9f36b67	911	IRDA_EndRxTransfer(hirda);
<>	157:ff67d9f36b67	912	}
<>	157:ff67d9f36b67	913
<>	157:ff67d9f36b67	914	return HAL_OK;
<>	157:ff67d9f36b67	915	}
<>	157:ff67d9f36b67	916
<>	157:ff67d9f36b67	917	/**
<>	157:ff67d9f36b67	918	* @brief Abort ongoing transfers (blocking mode).
<>	157:ff67d9f36b67	919	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	920	* the configuration information for the specified UART module.
<>	157:ff67d9f36b67	921	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	922	* This procedure performs following operations :
<>	157:ff67d9f36b67	923	* - Disable IRDA Interrupts (Tx and Rx)
<>	157:ff67d9f36b67	924	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	925	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	926	* - Set handle State to READY
<>	157:ff67d9f36b67	927	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<>	157:ff67d9f36b67	928	* @retval HAL status
<>	157:ff67d9f36b67	929	*/
<>	157:ff67d9f36b67	930	HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	931	{
<>	157:ff67d9f36b67	932	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	933	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	157:ff67d9f36b67	934	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	935
<>	157:ff67d9f36b67	936	/* Disable the IRDA DMA Tx request if enabled */
<>	157:ff67d9f36b67	937	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	938	{
<>	157:ff67d9f36b67	939	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	940
<>	157:ff67d9f36b67	941	/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
<>	157:ff67d9f36b67	942	if(hirda->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	943	{
<>	157:ff67d9f36b67	944	/* Set the IRDA DMA Abort callback to Null.
<>	157:ff67d9f36b67	945	No call back execution at end of DMA abort procedure */
<>	157:ff67d9f36b67	946	hirda->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	947
<>	157:ff67d9f36b67	948	HAL_DMA_Abort(hirda->hdmatx);
<>	157:ff67d9f36b67	949	}
<>	157:ff67d9f36b67	950	}
<>	157:ff67d9f36b67	951
<>	157:ff67d9f36b67	952	/* Disable the IRDA DMA Rx request if enabled */
<>	157:ff67d9f36b67	953	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	954	{
<>	157:ff67d9f36b67	955	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	956
<>	157:ff67d9f36b67	957	/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
<>	157:ff67d9f36b67	958	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	959	{
<>	157:ff67d9f36b67	960	/* Set the IRDA DMA Abort callback to Null.
<>	157:ff67d9f36b67	961	No call back execution at end of DMA abort procedure */
<>	157:ff67d9f36b67	962	hirda->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	963
<>	157:ff67d9f36b67	964	HAL_DMA_Abort(hirda->hdmarx);
<>	157:ff67d9f36b67	965	}
<>	157:ff67d9f36b67	966	}
<>	157:ff67d9f36b67	967
<>	157:ff67d9f36b67	968	/* Reset Tx and Rx transfer counters */
<>	157:ff67d9f36b67	969	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	970	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	971
<>	157:ff67d9f36b67	972	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	973	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	974
<>	157:ff67d9f36b67	975	/* Restore hirda->gState and hirda->RxState to Ready */
<>	157:ff67d9f36b67	976	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	977	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	978
<>	157:ff67d9f36b67	979	/* Reset Handle ErrorCode to No Error */
<>	157:ff67d9f36b67	980	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	981
<>	157:ff67d9f36b67	982	return HAL_OK;
<>	157:ff67d9f36b67	983	}
<>	144:ef7eb2e8f9f7	984
<>	157:ff67d9f36b67	985	/**
<>	157:ff67d9f36b67	986	* @brief Abort ongoing Transmit transfer (blocking mode).
<>	157:ff67d9f36b67	987	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	988	* the configuration information for the specified UART module.
<>	157:ff67d9f36b67	989	* @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	990	* This procedure performs following operations :
<>	157:ff67d9f36b67	991	* - Disable IRDA Interrupts (Tx)
<>	157:ff67d9f36b67	992	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	993	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	994	* - Set handle State to READY
<>	157:ff67d9f36b67	995	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<>	157:ff67d9f36b67	996	* @retval HAL status
<>	157:ff67d9f36b67	997	*/
<>	157:ff67d9f36b67	998	HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	999	{
<>	157:ff67d9f36b67	1000	/* Disable TXEIE and TCIE interrupts */
<>	157:ff67d9f36b67	1001	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	157:ff67d9f36b67	1002
<>	157:ff67d9f36b67	1003	/* Disable the IRDA DMA Tx request if enabled */
<>	157:ff67d9f36b67	1004	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1005	{
<>	157:ff67d9f36b67	1006	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1007
<>	157:ff67d9f36b67	1008	/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
<>	157:ff67d9f36b67	1009	if(hirda->hdmatx != NULL)
<>	157:ff67d9f36b67	1010	{
<>	157:ff67d9f36b67	1011	/* Set the IRDA DMA Abort callback to Null.
<>	157:ff67d9f36b67	1012	No call back execution at end of DMA abort procedure */
<>	157:ff67d9f36b67	1013	hirda->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1014
<>	157:ff67d9f36b67	1015	HAL_DMA_Abort(hirda->hdmatx);
<>	144:ef7eb2e8f9f7	1016	}
<>	157:ff67d9f36b67	1017	}
<>	157:ff67d9f36b67	1018
<>	157:ff67d9f36b67	1019	/* Reset Tx transfer counter */
<>	157:ff67d9f36b67	1020	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	1021
<>	157:ff67d9f36b67	1022	/* Restore hirda->gState to Ready */
<>	157:ff67d9f36b67	1023	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1024
<>	157:ff67d9f36b67	1025	return HAL_OK;
<>	157:ff67d9f36b67	1026	}
<>	157:ff67d9f36b67	1027
<>	157:ff67d9f36b67	1028	/**
<>	157:ff67d9f36b67	1029	* @brief Abort ongoing Receive transfer (blocking mode).
<>	157:ff67d9f36b67	1030	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1031	* the configuration information for the specified UART module.
<>	157:ff67d9f36b67	1032	* @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	1033	* This procedure performs following operations :
<>	157:ff67d9f36b67	1034	* - Disable IRDA Interrupts (Rx)
<>	157:ff67d9f36b67	1035	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	1036	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	1037	* - Set handle State to READY
<>	157:ff67d9f36b67	1038	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<>	157:ff67d9f36b67	1039	* @retval HAL status
<>	157:ff67d9f36b67	1040	*/
<>	157:ff67d9f36b67	1041	HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1042	{
<>	157:ff67d9f36b67	1043	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1044	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	157:ff67d9f36b67	1045	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1046
<>	157:ff67d9f36b67	1047	/* Disable the IRDA DMA Rx request if enabled */
<>	157:ff67d9f36b67	1048	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1049	{
<>	157:ff67d9f36b67	1050	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1051
<>	157:ff67d9f36b67	1052	/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
<>	157:ff67d9f36b67	1053	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	1054	{
<>	157:ff67d9f36b67	1055	/* Set the IRDA DMA Abort callback to Null.
<>	157:ff67d9f36b67	1056	No call back execution at end of DMA abort procedure */
<>	157:ff67d9f36b67	1057	hirda->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1058
<>	157:ff67d9f36b67	1059	HAL_DMA_Abort(hirda->hdmarx);
<>	157:ff67d9f36b67	1060	}
<>	157:ff67d9f36b67	1061	}
<>	157:ff67d9f36b67	1062
<>	157:ff67d9f36b67	1063	/* Reset Rx transfer counter */
<>	157:ff67d9f36b67	1064	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	1065
<>	157:ff67d9f36b67	1066	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1067	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	1068
<>	157:ff67d9f36b67	1069	/* Restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	1070	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1071
<>	157:ff67d9f36b67	1072	return HAL_OK;
<>	144:ef7eb2e8f9f7	1073	}
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	/**
<>	157:ff67d9f36b67	1076	* @brief Abort ongoing transfers (Interrupt mode).
<>	157:ff67d9f36b67	1077	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1078	* the configuration information for the specified UART module.
<>	157:ff67d9f36b67	1079	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	1080	* This procedure performs following operations :
<>	157:ff67d9f36b67	1081	* - Disable IRDA Interrupts (Tx and Rx)
<>	157:ff67d9f36b67	1082	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	1083	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	1084	* - Set handle State to READY
<>	157:ff67d9f36b67	1085	* - At abort completion, call user abort complete callback
<>	157:ff67d9f36b67	1086	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<>	157:ff67d9f36b67	1087	* considered as completed only when user abort complete callback is executed (not when exiting function).
<>	157:ff67d9f36b67	1088	* @retval HAL status
<>	157:ff67d9f36b67	1089	*/
<>	157:ff67d9f36b67	1090	HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1091	{
<>	157:ff67d9f36b67	1092	uint32_t abortcplt = 1;
<>	157:ff67d9f36b67	1093
<>	157:ff67d9f36b67	1094	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1095	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	157:ff67d9f36b67	1096	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1097
<>	157:ff67d9f36b67	1098	/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
<>	157:ff67d9f36b67	1099	before any call to DMA Abort functions */
<>	157:ff67d9f36b67	1100	/* DMA Tx Handle is valid */
<>	157:ff67d9f36b67	1101	if(hirda->hdmatx != NULL)
<>	157:ff67d9f36b67	1102	{
<>	157:ff67d9f36b67	1103	/* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
<>	157:ff67d9f36b67	1104	Otherwise, set it to NULL */
<>	157:ff67d9f36b67	1105	if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1106	{
<>	157:ff67d9f36b67	1107	hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
<>	157:ff67d9f36b67	1108	}
<>	157:ff67d9f36b67	1109	else
<>	157:ff67d9f36b67	1110	{
<>	157:ff67d9f36b67	1111	hirda->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1112	}
<>	157:ff67d9f36b67	1113	}
<>	157:ff67d9f36b67	1114	/* DMA Rx Handle is valid */
<>	157:ff67d9f36b67	1115	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	1116	{
<>	157:ff67d9f36b67	1117	/* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
<>	157:ff67d9f36b67	1118	Otherwise, set it to NULL */
<>	157:ff67d9f36b67	1119	if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1120	{
<>	157:ff67d9f36b67	1121	hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
<>	157:ff67d9f36b67	1122	}
<>	157:ff67d9f36b67	1123	else
<>	157:ff67d9f36b67	1124	{
<>	157:ff67d9f36b67	1125	hirda->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1126	}
<>	157:ff67d9f36b67	1127	}
<>	157:ff67d9f36b67	1128
<>	157:ff67d9f36b67	1129	/* Disable the IRDA DMA Tx request if enabled */
<>	157:ff67d9f36b67	1130	if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1131	{
<>	157:ff67d9f36b67	1132	/* Disable DMA Tx at UART level */
<>	157:ff67d9f36b67	1133	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1134
<>	157:ff67d9f36b67	1135	/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
<>	157:ff67d9f36b67	1136	if(hirda->hdmatx != NULL)
<>	157:ff67d9f36b67	1137	{
<>	157:ff67d9f36b67	1138	/* IRDA Tx DMA Abort callback has already been initialised :
<>	157:ff67d9f36b67	1139	will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	1140
<>	157:ff67d9f36b67	1141	/* Abort DMA TX */
<>	157:ff67d9f36b67	1142	if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
<>	157:ff67d9f36b67	1143	{
<>	157:ff67d9f36b67	1144	hirda->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1145	}
<>	157:ff67d9f36b67	1146	else
<>	157:ff67d9f36b67	1147	{
<>	157:ff67d9f36b67	1148	abortcplt = 0;
<>	157:ff67d9f36b67	1149	}
<>	157:ff67d9f36b67	1150	}
<>	157:ff67d9f36b67	1151	}
<>	157:ff67d9f36b67	1152
<>	157:ff67d9f36b67	1153	/* Disable the IRDA DMA Rx request if enabled */
<>	157:ff67d9f36b67	1154	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1155	{
<>	157:ff67d9f36b67	1156	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1157
<>	157:ff67d9f36b67	1158	/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
<>	157:ff67d9f36b67	1159	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	1160	{
<>	157:ff67d9f36b67	1161	/* IRDA Rx DMA Abort callback has already been initialised :
<>	157:ff67d9f36b67	1162	will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<>	157:ff67d9f36b67	1163
<>	157:ff67d9f36b67	1164	/* Abort DMA RX */
<>	157:ff67d9f36b67	1165	if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<>	157:ff67d9f36b67	1166	{
<>	157:ff67d9f36b67	1167	hirda->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1168	abortcplt = 1;
<>	157:ff67d9f36b67	1169	}
<>	157:ff67d9f36b67	1170	else
<>	157:ff67d9f36b67	1171	{
<>	157:ff67d9f36b67	1172	abortcplt = 0;
<>	157:ff67d9f36b67	1173	}
<>	157:ff67d9f36b67	1174	}
<>	157:ff67d9f36b67	1175	}
<>	157:ff67d9f36b67	1176
<>	157:ff67d9f36b67	1177	/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
<>	157:ff67d9f36b67	1178	if (abortcplt == 1)
<>	157:ff67d9f36b67	1179	{
<>	157:ff67d9f36b67	1180	/* Reset Tx and Rx transfer counters */
<>	157:ff67d9f36b67	1181	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	1182	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	1183
<>	157:ff67d9f36b67	1184	/* Reset errorCode */
<>	157:ff67d9f36b67	1185	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	1186
<>	157:ff67d9f36b67	1187	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1188	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	1189
<>	157:ff67d9f36b67	1190	/* Restore hirda->gState and hirda->RxState to Ready */
<>	157:ff67d9f36b67	1191	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1192	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1193
<>	157:ff67d9f36b67	1194	/* As no DMA to be aborted, call directly user Abort complete callback */
<>	157:ff67d9f36b67	1195	HAL_IRDA_AbortCpltCallback(hirda);
<>	157:ff67d9f36b67	1196	}
<>	157:ff67d9f36b67	1197
<>	157:ff67d9f36b67	1198	return HAL_OK;
<>	144:ef7eb2e8f9f7	1199	}
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/**
<>	157:ff67d9f36b67	1202	* @brief Abort ongoing Transmit transfer (Interrupt mode).
<>	157:ff67d9f36b67	1203	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1204	* the configuration information for the specified UART module.
<>	157:ff67d9f36b67	1205	* @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	1206	* This procedure performs following operations :
<>	157:ff67d9f36b67	1207	* - Disable IRDA Interrupts (Tx)
<>	157:ff67d9f36b67	1208	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	1209	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	1210	* - Set handle State to READY
<>	157:ff67d9f36b67	1211	* - At abort completion, call user abort complete callback
<>	157:ff67d9f36b67	1212	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<>	157:ff67d9f36b67	1213	* considered as completed only when user abort complete callback is executed (not when exiting function).
<>	157:ff67d9f36b67	1214	* @retval HAL status
<>	157:ff67d9f36b67	1215	*/
<>	157:ff67d9f36b67	1216	HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1217	{
<>	157:ff67d9f36b67	1218	/* Disable TXEIE and TCIE interrupts */
<>	157:ff67d9f36b67	1219	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	157:ff67d9f36b67	1220
<>	157:ff67d9f36b67	1221	/* Disable the IRDA DMA Tx request if enabled */
<>	157:ff67d9f36b67	1222	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1223	{
<>	157:ff67d9f36b67	1224	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1225
<>	157:ff67d9f36b67	1226	/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
<>	157:ff67d9f36b67	1227	if(hirda->hdmatx != NULL)
<>	157:ff67d9f36b67	1228	{
<>	157:ff67d9f36b67	1229	/* Set the IRDA DMA Abort callback :
<>	157:ff67d9f36b67	1230	will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<>	157:ff67d9f36b67	1231	hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
<>	157:ff67d9f36b67	1232
<>	157:ff67d9f36b67	1233	/* Abort DMA TX */
<>	157:ff67d9f36b67	1234	if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
<>	157:ff67d9f36b67	1235	{
<>	157:ff67d9f36b67	1236	/* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
<>	157:ff67d9f36b67	1237	hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
<>	157:ff67d9f36b67	1238	}
<>	157:ff67d9f36b67	1239	}
<>	157:ff67d9f36b67	1240	else
<>	157:ff67d9f36b67	1241	{
<>	157:ff67d9f36b67	1242	/* Reset Tx transfer counter */
<>	157:ff67d9f36b67	1243	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	1244
<>	157:ff67d9f36b67	1245	/* Restore hirda->gState to Ready */
<>	157:ff67d9f36b67	1246	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1247
<>	157:ff67d9f36b67	1248	/* As no DMA to be aborted, call directly user Abort complete callback */
<>	157:ff67d9f36b67	1249	HAL_IRDA_AbortTransmitCpltCallback(hirda);
<>	157:ff67d9f36b67	1250	}
<>	157:ff67d9f36b67	1251	}
<>	157:ff67d9f36b67	1252	else
<>	157:ff67d9f36b67	1253	{
<>	157:ff67d9f36b67	1254	/* Reset Tx transfer counter */
<>	157:ff67d9f36b67	1255	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	1256
<>	157:ff67d9f36b67	1257	/* Restore hirda->gState to Ready */
<>	157:ff67d9f36b67	1258	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1259
<>	157:ff67d9f36b67	1260	/* As no DMA to be aborted, call directly user Abort complete callback */
<>	157:ff67d9f36b67	1261	HAL_IRDA_AbortTransmitCpltCallback(hirda);
<>	157:ff67d9f36b67	1262	}
<>	157:ff67d9f36b67	1263
<>	157:ff67d9f36b67	1264	return HAL_OK;
<>	157:ff67d9f36b67	1265	}
<>	157:ff67d9f36b67	1266
<>	157:ff67d9f36b67	1267	/**
<>	157:ff67d9f36b67	1268	* @brief Abort ongoing Receive transfer (Interrupt mode).
<>	157:ff67d9f36b67	1269	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1270	* the configuration information for the specified UART module.
<>	157:ff67d9f36b67	1271	* @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	1272	* This procedure performs following operations :
<>	157:ff67d9f36b67	1273	* - Disable IRDA Interrupts (Rx)
<>	157:ff67d9f36b67	1274	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	1275	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	1276	* - Set handle State to READY
<>	157:ff67d9f36b67	1277	* - At abort completion, call user abort complete callback
<>	157:ff67d9f36b67	1278	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<>	157:ff67d9f36b67	1279	* considered as completed only when user abort complete callback is executed (not when exiting function).
<>	157:ff67d9f36b67	1280	* @retval HAL status
<>	157:ff67d9f36b67	1281	*/
<>	157:ff67d9f36b67	1282	HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1283	{
<>	157:ff67d9f36b67	1284	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1285	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	157:ff67d9f36b67	1286	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1287
<>	157:ff67d9f36b67	1288	/* Disable the IRDA DMA Rx request if enabled */
<>	157:ff67d9f36b67	1289	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1290	{
<>	157:ff67d9f36b67	1291	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1292
<>	157:ff67d9f36b67	1293	/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
<>	157:ff67d9f36b67	1294	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	1295	{
<>	157:ff67d9f36b67	1296	/* Set the IRDA DMA Abort callback :
<>	157:ff67d9f36b67	1297	will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<>	157:ff67d9f36b67	1298	hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
<>	157:ff67d9f36b67	1299
<>	157:ff67d9f36b67	1300	/* Abort DMA RX */
<>	157:ff67d9f36b67	1301	if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<>	157:ff67d9f36b67	1302	{
<>	157:ff67d9f36b67	1303	/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
<>	157:ff67d9f36b67	1304	hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
<>	157:ff67d9f36b67	1305	}
<>	157:ff67d9f36b67	1306	}
<>	157:ff67d9f36b67	1307	else
<>	157:ff67d9f36b67	1308	{
<>	157:ff67d9f36b67	1309	/* Reset Rx transfer counter */
<>	157:ff67d9f36b67	1310	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	1311
<>	157:ff67d9f36b67	1312	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1313	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	1314
<>	157:ff67d9f36b67	1315	/* Restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	1316	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1317
<>	157:ff67d9f36b67	1318	/* As no DMA to be aborted, call directly user Abort complete callback */
<>	157:ff67d9f36b67	1319	HAL_IRDA_AbortReceiveCpltCallback(hirda);
<>	157:ff67d9f36b67	1320	}
<>	157:ff67d9f36b67	1321	}
<>	157:ff67d9f36b67	1322	else
<>	157:ff67d9f36b67	1323	{
<>	157:ff67d9f36b67	1324	/* Reset Rx transfer counter */
<>	157:ff67d9f36b67	1325	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	1326
<>	157:ff67d9f36b67	1327	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1328	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	1329
<>	157:ff67d9f36b67	1330	/* Restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	1331	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1332
<>	157:ff67d9f36b67	1333	/* As no DMA to be aborted, call directly user Abort complete callback */
<>	157:ff67d9f36b67	1334	HAL_IRDA_AbortReceiveCpltCallback(hirda);
<>	157:ff67d9f36b67	1335	}
<>	157:ff67d9f36b67	1336
<>	157:ff67d9f36b67	1337	return HAL_OK;
<>	157:ff67d9f36b67	1338	}
<>	157:ff67d9f36b67	1339
<>	157:ff67d9f36b67	1340	/**
<>	157:ff67d9f36b67	1341	* @brief Handle IRDA interrupt request.
<>	157:ff67d9f36b67	1342	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1343	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	1344	* @retval None
<>	144:ef7eb2e8f9f7	1345	*/
<>	144:ef7eb2e8f9f7	1346	void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1347	{
<>	157:ff67d9f36b67	1348	uint32_t isrflags = READ_REG(hirda->Instance->ISR);
<>	157:ff67d9f36b67	1349	uint32_t cr1its = READ_REG(hirda->Instance->CR1);
<>	157:ff67d9f36b67	1350	uint32_t cr3its;
<>	157:ff67d9f36b67	1351	uint32_t errorflags;
<>	144:ef7eb2e8f9f7	1352
<>	157:ff67d9f36b67	1353	/* If no error occurs */
<>	157:ff67d9f36b67	1354	errorflags = (isrflags & (uint32_t)(USART_ISR_PE \| USART_ISR_FE \| USART_ISR_ORE \| USART_ISR_NE));
<>	157:ff67d9f36b67	1355	if (errorflags == RESET)
<>	157:ff67d9f36b67	1356	{
<>	157:ff67d9f36b67	1357	/* IRDA in mode Receiver ---------------------------------------------------*/
<>	157:ff67d9f36b67	1358	if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	157:ff67d9f36b67	1359	{
<>	157:ff67d9f36b67	1360	IRDA_Receive_IT(hirda);
<>	157:ff67d9f36b67	1361	return;
<>	157:ff67d9f36b67	1362	}
<>	157:ff67d9f36b67	1363	}
<>	144:ef7eb2e8f9f7	1364
<>	157:ff67d9f36b67	1365	/* If some errors occur */
<>	157:ff67d9f36b67	1366	cr3its = READ_REG(hirda->Instance->CR3);
<>	157:ff67d9f36b67	1367	if( (errorflags != RESET)
<>	157:ff67d9f36b67	1368	&& ( ((cr3its & USART_CR3_EIE) != RESET)
<>	157:ff67d9f36b67	1369	\|\| ((cr1its & (USART_CR1_RXNEIE \| USART_CR1_PEIE)) != RESET)) )
<>	157:ff67d9f36b67	1370	{
<>	157:ff67d9f36b67	1371	/* IRDA parity error interrupt occurred -------------------------------------*/
<>	157:ff67d9f36b67	1372	if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<>	157:ff67d9f36b67	1373	{
<>	157:ff67d9f36b67	1374	__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
<>	157:ff67d9f36b67	1375
<>	157:ff67d9f36b67	1376	hirda->ErrorCode \|= HAL_IRDA_ERROR_PE;
<>	157:ff67d9f36b67	1377	}
<>	157:ff67d9f36b67	1378
<>	157:ff67d9f36b67	1379	/* IRDA frame error interrupt occurred --------------------------------------*/
<>	157:ff67d9f36b67	1380	if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1381	{
<>	157:ff67d9f36b67	1382	__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	1383
<>	157:ff67d9f36b67	1384	hirda->ErrorCode \|= HAL_IRDA_ERROR_FE;
<>	157:ff67d9f36b67	1385	}
<>	157:ff67d9f36b67	1386
<>	157:ff67d9f36b67	1387	/* IRDA noise error interrupt occurred --------------------------------------*/
<>	157:ff67d9f36b67	1388	if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	157:ff67d9f36b67	1389	{
<>	157:ff67d9f36b67	1390	__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
<>	157:ff67d9f36b67	1391
<>	157:ff67d9f36b67	1392	hirda->ErrorCode \|= HAL_IRDA_ERROR_NE;
<>	157:ff67d9f36b67	1393	}
<>	157:ff67d9f36b67	1394
<>	157:ff67d9f36b67	1395	/* IRDA Over-Run interrupt occurred -----------------------------------------*/
<>	157:ff67d9f36b67	1396	if(((isrflags & USART_ISR_ORE) != RESET) &&
<>	157:ff67d9f36b67	1397	(((cr1its & USART_CR1_RXNEIE) != RESET) \|\| ((cr3its & USART_CR3_EIE) != RESET)))
<>	157:ff67d9f36b67	1398	{
<>	157:ff67d9f36b67	1399	__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
<>	157:ff67d9f36b67	1400
<>	157:ff67d9f36b67	1401	hirda->ErrorCode \|= HAL_IRDA_ERROR_ORE;
<>	144:ef7eb2e8f9f7	1402	}
<>	144:ef7eb2e8f9f7	1403
<>	157:ff67d9f36b67	1404	/* Call IRDA Error Call back function if need be --------------------------*/
<>	157:ff67d9f36b67	1405	if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
<>	144:ef7eb2e8f9f7	1406	{
<>	157:ff67d9f36b67	1407	/* IRDA in mode Receiver ---------------------------------------------------*/
<>	157:ff67d9f36b67	1408	if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	157:ff67d9f36b67	1409	{
<>	157:ff67d9f36b67	1410	IRDA_Receive_IT(hirda);
<>	157:ff67d9f36b67	1411	}
<>	144:ef7eb2e8f9f7	1412
<>	157:ff67d9f36b67	1413	/* If Overrun error occurs, or if any error occurs in DMA mode reception,
<>	157:ff67d9f36b67	1414	consider error as blocking */
<>	157:ff67d9f36b67	1415	if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) \|\|
<>	157:ff67d9f36b67	1416	(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<>	157:ff67d9f36b67	1417	{
<>	157:ff67d9f36b67	1418	/* Blocking error : transfer is aborted
<>	157:ff67d9f36b67	1419	Set the IRDA state ready to be able to start again the process,
<>	157:ff67d9f36b67	1420	Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<>	157:ff67d9f36b67	1421	IRDA_EndRxTransfer(hirda);
<>	144:ef7eb2e8f9f7	1422
<>	157:ff67d9f36b67	1423	/* Disable the IRDA DMA Rx request if enabled */
<>	157:ff67d9f36b67	1424	if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<>	144:ef7eb2e8f9f7	1425	{
<>	157:ff67d9f36b67	1426	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1427
<>	157:ff67d9f36b67	1428	/* Abort the IRDA DMA Rx channel */
<>	157:ff67d9f36b67	1429	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	1430	{
<>	157:ff67d9f36b67	1431	/* Set the IRDA DMA Abort callback :
<>	157:ff67d9f36b67	1432	will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
<>	157:ff67d9f36b67	1433	hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
<>	144:ef7eb2e8f9f7	1434
<>	157:ff67d9f36b67	1435	/* Abort DMA RX */
<>	157:ff67d9f36b67	1436	if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<>	157:ff67d9f36b67	1437	{
<>	157:ff67d9f36b67	1438	/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
<>	157:ff67d9f36b67	1439	hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
<>	157:ff67d9f36b67	1440	}
<>	157:ff67d9f36b67	1441	}
<>	157:ff67d9f36b67	1442	else
<>	157:ff67d9f36b67	1443	{
<>	157:ff67d9f36b67	1444	/* Call user error callback */
<>	157:ff67d9f36b67	1445	HAL_IRDA_ErrorCallback(hirda);
<>	157:ff67d9f36b67	1446	}
<>	157:ff67d9f36b67	1447	}
<>	157:ff67d9f36b67	1448	else
<>	157:ff67d9f36b67	1449	{
<>	157:ff67d9f36b67	1450	/* Call user error callback */
<>	157:ff67d9f36b67	1451	HAL_IRDA_ErrorCallback(hirda);
<>	157:ff67d9f36b67	1452	}
<>	157:ff67d9f36b67	1453	}
<>	157:ff67d9f36b67	1454	else
<>	157:ff67d9f36b67	1455	{
<>	157:ff67d9f36b67	1456	/* Non Blocking error : transfer could go on.
<>	157:ff67d9f36b67	1457	Error is notified to user through user error callback */
<>	157:ff67d9f36b67	1458	HAL_IRDA_ErrorCallback(hirda);
<>	157:ff67d9f36b67	1459	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	1460	}
<>	157:ff67d9f36b67	1461	}
<>	157:ff67d9f36b67	1462	return;
<>	144:ef7eb2e8f9f7	1463
<>	157:ff67d9f36b67	1464	} /* End if some error occurs */
<>	144:ef7eb2e8f9f7	1465
<>	157:ff67d9f36b67	1466	/* IRDA in mode Transmitter ------------------------------------------------*/
<>	157:ff67d9f36b67	1467	if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<>	157:ff67d9f36b67	1468	{
<>	157:ff67d9f36b67	1469	IRDA_Transmit_IT(hirda);
<>	157:ff67d9f36b67	1470	return;
<>	157:ff67d9f36b67	1471	}
<>	144:ef7eb2e8f9f7	1472
<>	157:ff67d9f36b67	1473	/* IRDA in mode Transmitter (transmission end) -----------------------------*/
<>	157:ff67d9f36b67	1474	if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<>	157:ff67d9f36b67	1475	{
<>	157:ff67d9f36b67	1476	IRDA_EndTransmit_IT(hirda);
<>	157:ff67d9f36b67	1477	return;
<>	157:ff67d9f36b67	1478	}
<>	144:ef7eb2e8f9f7	1479
<>	144:ef7eb2e8f9f7	1480	}
<>	144:ef7eb2e8f9f7	1481
<>	144:ef7eb2e8f9f7	1482	/**
<>	157:ff67d9f36b67	1483	* @brief Tx Transfer completed callback.
<>	157:ff67d9f36b67	1484	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1485	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	1486	* @retval None
<>	144:ef7eb2e8f9f7	1487	*/
<>	157:ff67d9f36b67	1488	__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1489	{
<>	157:ff67d9f36b67	1490	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1491	UNUSED(hirda);
<>	144:ef7eb2e8f9f7	1492
<>	157:ff67d9f36b67	1493	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1494	the HAL_IRDA_TxCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1495	*/
<>	144:ef7eb2e8f9f7	1496	}
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/**
<>	157:ff67d9f36b67	1499	* @brief Tx Half Transfer completed callback.
<>	157:ff67d9f36b67	1500	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1501	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1502	* @retval None
<>	144:ef7eb2e8f9f7	1503	*/
<>	144:ef7eb2e8f9f7	1504	__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1505	{
<>	157:ff67d9f36b67	1506	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1507	UNUSED(hirda);
<>	144:ef7eb2e8f9f7	1508
<>	157:ff67d9f36b67	1509	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1510	the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1511	*/
<>	144:ef7eb2e8f9f7	1512	}
<>	144:ef7eb2e8f9f7	1513
<>	144:ef7eb2e8f9f7	1514	/**
<>	157:ff67d9f36b67	1515	* @brief Rx Transfer completed callback.
<>	157:ff67d9f36b67	1516	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1517	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	1518	* @retval None
<>	144:ef7eb2e8f9f7	1519	*/
<>	157:ff67d9f36b67	1520	__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1521	{
<>	157:ff67d9f36b67	1522	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1523	UNUSED(hirda);
<>	144:ef7eb2e8f9f7	1524
<>	157:ff67d9f36b67	1525	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1526	the HAL_IRDA_RxCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1527	*/
<>	144:ef7eb2e8f9f7	1528	}
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530	/**
<>	157:ff67d9f36b67	1531	* @brief Rx Half Transfer complete callback.
<>	157:ff67d9f36b67	1532	* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1533	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	1534	* @retval None
<>	144:ef7eb2e8f9f7	1535	*/
<>	144:ef7eb2e8f9f7	1536	__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1537	{
<>	157:ff67d9f36b67	1538	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1539	UNUSED(hirda);
<>	144:ef7eb2e8f9f7	1540
<>	157:ff67d9f36b67	1541	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1542	the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1543	*/
<>	144:ef7eb2e8f9f7	1544	}
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/**
<>	157:ff67d9f36b67	1547	* @brief IRDA error callback.
<>	157:ff67d9f36b67	1548	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1549	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	1550	* @retval None
<>	144:ef7eb2e8f9f7	1551	*/
<>	144:ef7eb2e8f9f7	1552	__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1553	{
<>	157:ff67d9f36b67	1554	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1555	UNUSED(hirda);
<>	157:ff67d9f36b67	1556
<>	157:ff67d9f36b67	1557	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1558	the HAL_IRDA_ErrorCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1559	*/
<>	157:ff67d9f36b67	1560	}
<>	157:ff67d9f36b67	1561
<>	157:ff67d9f36b67	1562	/**
<>	157:ff67d9f36b67	1563	* @brief IRDA Abort Complete callback.
<>	157:ff67d9f36b67	1564	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1565	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1566	* @retval None
<>	157:ff67d9f36b67	1567	*/
<>	157:ff67d9f36b67	1568	__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1569	{
<>	157:ff67d9f36b67	1570	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1571	UNUSED(hirda);
<>	157:ff67d9f36b67	1572
<>	157:ff67d9f36b67	1573	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1574	the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1575	*/
<>	157:ff67d9f36b67	1576	}
<>	144:ef7eb2e8f9f7	1577
<>	157:ff67d9f36b67	1578	/**
<>	157:ff67d9f36b67	1579	* @brief IRDA Abort Complete callback.
<>	157:ff67d9f36b67	1580	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1581	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1582	* @retval None
<>	157:ff67d9f36b67	1583	*/
<>	157:ff67d9f36b67	1584	__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1585	{
<>	157:ff67d9f36b67	1586	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1587	UNUSED(hirda);
<>	157:ff67d9f36b67	1588
<>	157:ff67d9f36b67	1589	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1590	the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1591	*/
<>	157:ff67d9f36b67	1592	}
<>	157:ff67d9f36b67	1593
<>	157:ff67d9f36b67	1594	/**
<>	157:ff67d9f36b67	1595	* @brief IRDA Abort Receive Complete callback.
<>	157:ff67d9f36b67	1596	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1597	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1598	* @retval None
<>	157:ff67d9f36b67	1599	*/
<>	157:ff67d9f36b67	1600	__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1601	{
<>	157:ff67d9f36b67	1602	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1603	UNUSED(hirda);
<>	157:ff67d9f36b67	1604
<>	157:ff67d9f36b67	1605	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1606	the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1607	*/
<>	144:ef7eb2e8f9f7	1608	}
<>	144:ef7eb2e8f9f7	1609
<>	144:ef7eb2e8f9f7	1610	/**
<>	144:ef7eb2e8f9f7	1611	* @}
<>	144:ef7eb2e8f9f7	1612	*/
<>	144:ef7eb2e8f9f7	1613
<>	157:ff67d9f36b67	1614	/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
<>	157:ff67d9f36b67	1615	* @brief IRDA State and Errors functions
<>	144:ef7eb2e8f9f7	1616	*
<>	144:ef7eb2e8f9f7	1617	@verbatim
<>	157:ff67d9f36b67	1618	==============================================================================
<>	157:ff67d9f36b67	1619	##### Peripheral State and Error functions #####
<>	157:ff67d9f36b67	1620	==============================================================================
<>	157:ff67d9f36b67	1621	[..]
<>	157:ff67d9f36b67	1622	This subsection provides a set of functions allowing to return the State of IrDA
<>	157:ff67d9f36b67	1623	communication process and also return Peripheral Errors occurred during communication process
<>	157:ff67d9f36b67	1624	(+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
<>	157:ff67d9f36b67	1625	of the IRDA peripheral handle.
<>	157:ff67d9f36b67	1626	(+) HAL_IRDA_GetError() checks in run-time errors that could occur during
<>	157:ff67d9f36b67	1627	communication.
<>	157:ff67d9f36b67	1628
<>	144:ef7eb2e8f9f7	1629	@endverbatim
<>	144:ef7eb2e8f9f7	1630	* @{
<>	144:ef7eb2e8f9f7	1631	*/
<>	144:ef7eb2e8f9f7	1632
<>	144:ef7eb2e8f9f7	1633	/**
<>	157:ff67d9f36b67	1634	* @brief Return the IRDA handle state.
<>	157:ff67d9f36b67	1635	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1636	* the configuration information for the specified IRDA module.
<>	144:ef7eb2e8f9f7	1637	* @retval HAL state
<>	144:ef7eb2e8f9f7	1638	*/
<>	144:ef7eb2e8f9f7	1639	HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1640	{
<>	157:ff67d9f36b67	1641	/* Return IRDA handle state */
<>	157:ff67d9f36b67	1642	uint32_t temp1= 0x00, temp2 = 0x00;
<>	157:ff67d9f36b67	1643	temp1 = hirda->gState;
<>	157:ff67d9f36b67	1644	temp2 = hirda->RxState;
<>	144:ef7eb2e8f9f7	1645
<>	157:ff67d9f36b67	1646	return (HAL_IRDA_StateTypeDef)(temp1 \| temp2);
<>	144:ef7eb2e8f9f7	1647	}
<>	144:ef7eb2e8f9f7	1648
<>	144:ef7eb2e8f9f7	1649	/**
<>	157:ff67d9f36b67	1650	* @brief Return the IRDA handle error code.
<>	157:ff67d9f36b67	1651	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1652	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1653	* @retval IRDA Error Code
<>	144:ef7eb2e8f9f7	1654	*/
<>	157:ff67d9f36b67	1655	uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
<>	144:ef7eb2e8f9f7	1656	{
<>	157:ff67d9f36b67	1657	return hirda->ErrorCode;
<>	144:ef7eb2e8f9f7	1658	}
<>	144:ef7eb2e8f9f7	1659
<>	144:ef7eb2e8f9f7	1660	/**
<>	144:ef7eb2e8f9f7	1661	* @}
<>	144:ef7eb2e8f9f7	1662	*/
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	/**
<>	144:ef7eb2e8f9f7	1665	* @}
<>	144:ef7eb2e8f9f7	1666	*/
<>	144:ef7eb2e8f9f7	1667
<>	157:ff67d9f36b67	1668	/** @defgroup IRDA_Private_Functions IRDA Private Functions
<>	157:ff67d9f36b67	1669	* @{
<>	157:ff67d9f36b67	1670	*/
<>	157:ff67d9f36b67	1671
<>	157:ff67d9f36b67	1672	/**
<>	157:ff67d9f36b67	1673	* @brief Configure the IRDA peripheral.
<>	157:ff67d9f36b67	1674	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1675	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1676	* @retval None
<>	157:ff67d9f36b67	1677	*/
<>	157:ff67d9f36b67	1678	static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1679	{
<>	157:ff67d9f36b67	1680	uint32_t tmpreg = 0x00000000;
<>	157:ff67d9f36b67	1681	IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
<>	157:ff67d9f36b67	1682	HAL_StatusTypeDef ret = HAL_OK;
<>	157:ff67d9f36b67	1683
<>	157:ff67d9f36b67	1684	/* Check the communication parameters */
<>	157:ff67d9f36b67	1685	assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
<>	157:ff67d9f36b67	1686	assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
<>	157:ff67d9f36b67	1687	assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
<>	157:ff67d9f36b67	1688	assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
<>	157:ff67d9f36b67	1689	assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
<>	157:ff67d9f36b67	1690	assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
<>	157:ff67d9f36b67	1691
<>	157:ff67d9f36b67	1692	/-------------------------- USART CR1 Configuration -----------------------/
<>	157:ff67d9f36b67	1693	/* Configure the IRDA Word Length, Parity and transfer Mode:
<>	157:ff67d9f36b67	1694	Set the M bits according to hirda->Init.WordLength value
<>	157:ff67d9f36b67	1695	Set PCE and PS bits according to hirda->Init.Parity value
<>	157:ff67d9f36b67	1696	Set TE and RE bits according to hirda->Init.Mode value */
<>	157:ff67d9f36b67	1697	tmpreg = (uint32_t)hirda->Init.WordLength \| hirda->Init.Parity \| hirda->Init.Mode ;
<>	157:ff67d9f36b67	1698
<>	157:ff67d9f36b67	1699	MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
<>	157:ff67d9f36b67	1700
<>	157:ff67d9f36b67	1701	/-------------------------- USART CR3 Configuration -----------------------/
<>	157:ff67d9f36b67	1702	MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
<>	157:ff67d9f36b67	1703
<>	157:ff67d9f36b67	1704	/-------------------------- USART GTPR Configuration ----------------------/
<>	157:ff67d9f36b67	1705	MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
<>	157:ff67d9f36b67	1706
<>	157:ff67d9f36b67	1707	/-------------------------- USART BRR Configuration -----------------------/
<>	157:ff67d9f36b67	1708	IRDA_GETCLOCKSOURCE(hirda, clocksource);
<>	157:ff67d9f36b67	1709	switch (clocksource)
<>	157:ff67d9f36b67	1710	{
<>	157:ff67d9f36b67	1711	case IRDA_CLOCKSOURCE_PCLK1:
<>	157:ff67d9f36b67	1712	hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<>	157:ff67d9f36b67	1713	break;
<>	157:ff67d9f36b67	1714	case IRDA_CLOCKSOURCE_PCLK2:
<>	157:ff67d9f36b67	1715	hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<>	157:ff67d9f36b67	1716	break;
<>	157:ff67d9f36b67	1717	case IRDA_CLOCKSOURCE_HSI:
<>	157:ff67d9f36b67	1718	hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<>	157:ff67d9f36b67	1719	break;
<>	157:ff67d9f36b67	1720	case IRDA_CLOCKSOURCE_SYSCLK:
<>	157:ff67d9f36b67	1721	hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<>	157:ff67d9f36b67	1722	break;
<>	157:ff67d9f36b67	1723	case IRDA_CLOCKSOURCE_LSE:
<>	157:ff67d9f36b67	1724	hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<>	157:ff67d9f36b67	1725	break;
<>	157:ff67d9f36b67	1726	case IRDA_CLOCKSOURCE_UNDEFINED:
<>	157:ff67d9f36b67	1727	default:
<>	157:ff67d9f36b67	1728	ret = HAL_ERROR;
<>	157:ff67d9f36b67	1729	break;
<>	157:ff67d9f36b67	1730	}
<>	157:ff67d9f36b67	1731
<>	157:ff67d9f36b67	1732	return ret;
<>	157:ff67d9f36b67	1733	}
<>	157:ff67d9f36b67	1734
<>	157:ff67d9f36b67	1735	/**
<>	157:ff67d9f36b67	1736	* @brief Check the IRDA Idle State.
<>	157:ff67d9f36b67	1737	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1738	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1739	* @retval HAL status
<>	157:ff67d9f36b67	1740	*/
<>	157:ff67d9f36b67	1741	static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1742	{
<>	157:ff67d9f36b67	1743	uint32_t tickstart = 0;
<>	157:ff67d9f36b67	1744
<>	157:ff67d9f36b67	1745	/* Initialize the IRDA ErrorCode */
<>	157:ff67d9f36b67	1746	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	1747
<>	157:ff67d9f36b67	1748	/* Init tickstart for timeout managment*/
<>	157:ff67d9f36b67	1749	tickstart = HAL_GetTick();
<>	157:ff67d9f36b67	1750
<>	157:ff67d9f36b67	1751	/* Check if the Transmitter is enabled */
<>	157:ff67d9f36b67	1752	if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<>	157:ff67d9f36b67	1753	{
<>	157:ff67d9f36b67	1754	/* Wait until TEACK flag is set */
<>	157:ff67d9f36b67	1755	if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
<>	157:ff67d9f36b67	1756	{
<>	157:ff67d9f36b67	1757	/* Timeout occurred */
<>	157:ff67d9f36b67	1758	return HAL_TIMEOUT;
<>	157:ff67d9f36b67	1759	}
<>	157:ff67d9f36b67	1760	}
<>	157:ff67d9f36b67	1761	/* Check if the Receiver is enabled */
<>	157:ff67d9f36b67	1762	if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<>	157:ff67d9f36b67	1763	{
<>	157:ff67d9f36b67	1764	/* Wait until REACK flag is set */
<>	157:ff67d9f36b67	1765	if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
<>	157:ff67d9f36b67	1766	{
<>	157:ff67d9f36b67	1767	/* Timeout occurred */
<>	157:ff67d9f36b67	1768	return HAL_TIMEOUT;
<>	157:ff67d9f36b67	1769	}
<>	157:ff67d9f36b67	1770	}
<>	157:ff67d9f36b67	1771
<>	157:ff67d9f36b67	1772	/* Initialize the IRDA state*/
<>	157:ff67d9f36b67	1773	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1774	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1775
<>	157:ff67d9f36b67	1776	/* Process Unlocked */
<>	157:ff67d9f36b67	1777	__HAL_UNLOCK(hirda);
<>	157:ff67d9f36b67	1778
<>	157:ff67d9f36b67	1779	return HAL_OK;
<>	157:ff67d9f36b67	1780	}
<>	157:ff67d9f36b67	1781
<>	157:ff67d9f36b67	1782	/**
<>	157:ff67d9f36b67	1783	* @brief Handle IRDA Communication Timeout.
<>	157:ff67d9f36b67	1784	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1785	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1786	* @param Flag Specifies the IRDA flag to check.
<>	157:ff67d9f36b67	1787	* @param Status Flag status (SET or RESET)
<>	157:ff67d9f36b67	1788	* @param Tickstart Tick start value
<>	157:ff67d9f36b67	1789	* @param Timeout Timeout duration
<>	157:ff67d9f36b67	1790	* @retval HAL status
<>	157:ff67d9f36b67	1791	*/
<>	157:ff67d9f36b67	1792	static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<>	157:ff67d9f36b67	1793	{
<>	157:ff67d9f36b67	1794	/* Wait until flag is set */
<>	157:ff67d9f36b67	1795	while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
<>	157:ff67d9f36b67	1796	{
<>	157:ff67d9f36b67	1797	/* Check for the Timeout */
<>	157:ff67d9f36b67	1798	if(Timeout != HAL_MAX_DELAY)
<>	157:ff67d9f36b67	1799	{
<>	157:ff67d9f36b67	1800	if((Timeout == 0) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	157:ff67d9f36b67	1801	{
<>	157:ff67d9f36b67	1802	/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<>	157:ff67d9f36b67	1803	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE));
<>	157:ff67d9f36b67	1804	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1805
<>	157:ff67d9f36b67	1806	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1807	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1808
<>	157:ff67d9f36b67	1809	/* Process Unlocked */
<>	157:ff67d9f36b67	1810	__HAL_UNLOCK(hirda);
<>	157:ff67d9f36b67	1811	return HAL_TIMEOUT;
<>	157:ff67d9f36b67	1812	}
<>	157:ff67d9f36b67	1813	}
<>	157:ff67d9f36b67	1814	}
<>	157:ff67d9f36b67	1815	return HAL_OK;
<>	157:ff67d9f36b67	1816	}
<>	157:ff67d9f36b67	1817
<>	157:ff67d9f36b67	1818
<>	157:ff67d9f36b67	1819	/**
<>	157:ff67d9f36b67	1820	* @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
<>	157:ff67d9f36b67	1821	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1822	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1823	* @retval None
<>	157:ff67d9f36b67	1824	*/
<>	157:ff67d9f36b67	1825	static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1826	{
<>	157:ff67d9f36b67	1827	/* Disable TXEIE and TCIE interrupts */
<>	157:ff67d9f36b67	1828	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	157:ff67d9f36b67	1829
<>	157:ff67d9f36b67	1830	/* At end of Tx process, restore hirda->gState to Ready */
<>	157:ff67d9f36b67	1831	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1832	}
<>	157:ff67d9f36b67	1833
<>	157:ff67d9f36b67	1834
<>	157:ff67d9f36b67	1835	/**
<>	157:ff67d9f36b67	1836	* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
<>	157:ff67d9f36b67	1837	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1838	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	1839	* @retval None
<>	157:ff67d9f36b67	1840	*/
<>	157:ff67d9f36b67	1841	static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	1842	{
<>	157:ff67d9f36b67	1843	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1844	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	157:ff67d9f36b67	1845	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1846
<>	157:ff67d9f36b67	1847	/* At end of Rx process, restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	1848	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1849	}
<>	157:ff67d9f36b67	1850
<>	157:ff67d9f36b67	1851
<>	157:ff67d9f36b67	1852	/**
<>	157:ff67d9f36b67	1853	* @brief DMA IRDA transmit process complete callback.
<>	157:ff67d9f36b67	1854	* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1855	* the configuration information for the specified DMA module.
<>	157:ff67d9f36b67	1856	* @retval None
<>	157:ff67d9f36b67	1857	*/
<>	157:ff67d9f36b67	1858	static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1859	{
<>	157:ff67d9f36b67	1860	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1861
<>	157:ff67d9f36b67	1862	/* DMA Normal mode */
<>	157:ff67d9f36b67	1863	if ( HAL_IS_BIT_CLR(hdma->Instance->CR, DMA_SxCR_CIRC) )
<>	157:ff67d9f36b67	1864	{
<>	157:ff67d9f36b67	1865	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	1866
<>	157:ff67d9f36b67	1867	/* Disable the DMA transfer for transmit request by resetting the DMAT bit
<>	157:ff67d9f36b67	1868	in the IRDA CR3 register */
<>	157:ff67d9f36b67	1869	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1870
<>	157:ff67d9f36b67	1871	/* Enable the IRDA Transmit Complete Interrupt */
<>	157:ff67d9f36b67	1872	SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<>	157:ff67d9f36b67	1873	}
<>	157:ff67d9f36b67	1874	/* DMA Circular mode */
<>	157:ff67d9f36b67	1875	else
<>	157:ff67d9f36b67	1876	{
<>	157:ff67d9f36b67	1877	HAL_IRDA_TxCpltCallback(hirda);
<>	157:ff67d9f36b67	1878	}
<>	157:ff67d9f36b67	1879
<>	157:ff67d9f36b67	1880	}
<>	157:ff67d9f36b67	1881
<>	157:ff67d9f36b67	1882	/**
<>	157:ff67d9f36b67	1883	* @brief DMA IRDA transmit process half complete callback.
<>	157:ff67d9f36b67	1884	* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1885	* the configuration information for the specified DMA module.
<>	157:ff67d9f36b67	1886	* @retval None
<>	157:ff67d9f36b67	1887	*/
<>	157:ff67d9f36b67	1888	static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1889	{
<>	157:ff67d9f36b67	1890	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1891
<>	157:ff67d9f36b67	1892	HAL_IRDA_TxHalfCpltCallback(hirda);
<>	157:ff67d9f36b67	1893	}
<>	157:ff67d9f36b67	1894
<>	157:ff67d9f36b67	1895	/**
<>	157:ff67d9f36b67	1896	* @brief DMA IRDA receive process complete callback.
<>	157:ff67d9f36b67	1897	* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1898	* the configuration information for the specified DMA module.
<>	157:ff67d9f36b67	1899	* @retval None
<>	157:ff67d9f36b67	1900	*/
<>	157:ff67d9f36b67	1901	static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1902	{
<>	157:ff67d9f36b67	1903	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1904
<>	157:ff67d9f36b67	1905	/* DMA Normal mode */
<>	157:ff67d9f36b67	1906	if ( HAL_IS_BIT_CLR(hdma->Instance->CR, DMA_SxCR_CIRC) )
<>	157:ff67d9f36b67	1907	{
<>	157:ff67d9f36b67	1908	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	1909
<>	157:ff67d9f36b67	1910	/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1911	CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	1912	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1913
<>	157:ff67d9f36b67	1914	/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
<>	157:ff67d9f36b67	1915	in the IRDA CR3 register */
<>	157:ff67d9f36b67	1916	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1917
<>	157:ff67d9f36b67	1918	/* At end of Rx process, restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	1919	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	1920	}
<>	157:ff67d9f36b67	1921
<>	157:ff67d9f36b67	1922	HAL_IRDA_RxCpltCallback(hirda);
<>	157:ff67d9f36b67	1923	}
<>	157:ff67d9f36b67	1924
<>	157:ff67d9f36b67	1925	/**
<>	157:ff67d9f36b67	1926	* @brief DMA IRDA receive process half complete callback.
<>	157:ff67d9f36b67	1927	* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1928	* the configuration information for the specified DMA module.
<>	157:ff67d9f36b67	1929	* @retval None
<>	157:ff67d9f36b67	1930	*/
<>	157:ff67d9f36b67	1931	static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1932	{
<>	157:ff67d9f36b67	1933	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1934
<>	157:ff67d9f36b67	1935	HAL_IRDA_RxHalfCpltCallback(hirda);
<>	157:ff67d9f36b67	1936	}
<>	157:ff67d9f36b67	1937
<>	157:ff67d9f36b67	1938	/**
<>	157:ff67d9f36b67	1939	* @brief DMA IRDA communication error callback.
<>	157:ff67d9f36b67	1940	* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	1941	* the configuration information for the specified DMA module.
<>	157:ff67d9f36b67	1942	* @retval None
<>	157:ff67d9f36b67	1943	*/
<>	157:ff67d9f36b67	1944	static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1945	{
<>	157:ff67d9f36b67	1946	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1947
<>	157:ff67d9f36b67	1948	/* Stop IRDA DMA Tx request if ongoing */
<>	157:ff67d9f36b67	1949	if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<>	157:ff67d9f36b67	1950	&&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
<>	157:ff67d9f36b67	1951	{
<>	157:ff67d9f36b67	1952	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	1953	IRDA_EndTxTransfer(hirda);
<>	157:ff67d9f36b67	1954	}
<>	157:ff67d9f36b67	1955
<>	157:ff67d9f36b67	1956	/* Stop IRDA DMA Rx request if ongoing */
<>	157:ff67d9f36b67	1957	if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<>	157:ff67d9f36b67	1958	&&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
<>	157:ff67d9f36b67	1959	{
<>	157:ff67d9f36b67	1960	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	1961	IRDA_EndRxTransfer(hirda);
<>	157:ff67d9f36b67	1962	}
<>	157:ff67d9f36b67	1963
<>	157:ff67d9f36b67	1964	hirda->ErrorCode \|= HAL_IRDA_ERROR_DMA;
<>	157:ff67d9f36b67	1965	HAL_IRDA_ErrorCallback(hirda);
<>	157:ff67d9f36b67	1966	}
<>	157:ff67d9f36b67	1967
<>	157:ff67d9f36b67	1968	/**
<>	157:ff67d9f36b67	1969	* @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
<>	157:ff67d9f36b67	1970	* (To be called at end of DMA Abort procedure following error occurrence).
<>	157:ff67d9f36b67	1971	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1972	* @retval None
<>	157:ff67d9f36b67	1973	*/
<>	157:ff67d9f36b67	1974	static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1975	{
<>	157:ff67d9f36b67	1976	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1977	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	1978	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	1979
<>	157:ff67d9f36b67	1980	HAL_IRDA_ErrorCallback(hirda);
<>	157:ff67d9f36b67	1981	}
<>	157:ff67d9f36b67	1982
<>	157:ff67d9f36b67	1983	/**
<>	157:ff67d9f36b67	1984	* @brief DMA IRDA Tx communication abort callback, when initiated by user
<>	157:ff67d9f36b67	1985	* (To be called at end of DMA Tx Abort procedure following user abort request).
<>	157:ff67d9f36b67	1986	* @note When this callback is executed, User Abort complete call back is called only if no
<>	157:ff67d9f36b67	1987	* Abort still ongoing for Rx DMA Handle.
<>	157:ff67d9f36b67	1988	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1989	* @retval None
<>	157:ff67d9f36b67	1990	*/
<>	157:ff67d9f36b67	1991	static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1992	{
<>	157:ff67d9f36b67	1993	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
<>	157:ff67d9f36b67	1994
<>	157:ff67d9f36b67	1995	hirda->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1996
<>	157:ff67d9f36b67	1997	/* Check if an Abort process is still ongoing */
<>	157:ff67d9f36b67	1998	if(hirda->hdmarx != NULL)
<>	157:ff67d9f36b67	1999	{
<>	157:ff67d9f36b67	2000	if(hirda->hdmarx->XferAbortCallback != NULL)
<>	157:ff67d9f36b67	2001	{
<>	157:ff67d9f36b67	2002	return;
<>	157:ff67d9f36b67	2003	}
<>	157:ff67d9f36b67	2004	}
<>	157:ff67d9f36b67	2005
<>	157:ff67d9f36b67	2006	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<>	157:ff67d9f36b67	2007	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	2008	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	2009
<>	157:ff67d9f36b67	2010	/* Reset errorCode */
<>	157:ff67d9f36b67	2011	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	2012
<>	157:ff67d9f36b67	2013	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	2014	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	2015
<>	157:ff67d9f36b67	2016	/* Restore hirda->gState and hirda->RxState to Ready */
<>	157:ff67d9f36b67	2017	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2018	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2019
<>	157:ff67d9f36b67	2020	/* Call user Abort complete callback */
<>	157:ff67d9f36b67	2021	HAL_IRDA_AbortCpltCallback(hirda);
<>	157:ff67d9f36b67	2022	}
<>	157:ff67d9f36b67	2023
<>	157:ff67d9f36b67	2024
<>	157:ff67d9f36b67	2025	/**
<>	157:ff67d9f36b67	2026	* @brief DMA IRDA Rx communication abort callback, when initiated by user
<>	157:ff67d9f36b67	2027	* (To be called at end of DMA Rx Abort procedure following user abort request).
<>	157:ff67d9f36b67	2028	* @note When this callback is executed, User Abort complete call back is called only if no
<>	157:ff67d9f36b67	2029	* Abort still ongoing for Tx DMA Handle.
<>	157:ff67d9f36b67	2030	* @param hdma DMA handle.
<>	157:ff67d9f36b67	2031	* @retval None
<>	157:ff67d9f36b67	2032	*/
<>	157:ff67d9f36b67	2033	static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	2034	{
<>	157:ff67d9f36b67	2035	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
<>	157:ff67d9f36b67	2036
<>	157:ff67d9f36b67	2037	hirda->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	2038
<>	157:ff67d9f36b67	2039	/* Check if an Abort process is still ongoing */
<>	157:ff67d9f36b67	2040	if(hirda->hdmatx != NULL)
<>	157:ff67d9f36b67	2041	{
<>	157:ff67d9f36b67	2042	if(hirda->hdmatx->XferAbortCallback != NULL)
<>	157:ff67d9f36b67	2043	{
<>	157:ff67d9f36b67	2044	return;
<>	157:ff67d9f36b67	2045	}
<>	157:ff67d9f36b67	2046	}
<>	157:ff67d9f36b67	2047
<>	157:ff67d9f36b67	2048	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<>	157:ff67d9f36b67	2049	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	2050	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	2051
<>	157:ff67d9f36b67	2052	/* Reset errorCode */
<>	157:ff67d9f36b67	2053	hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<>	157:ff67d9f36b67	2054
<>	157:ff67d9f36b67	2055	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	2056	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	2057
<>	157:ff67d9f36b67	2058	/* Restore hirda->gState and hirda->RxState to Ready */
<>	157:ff67d9f36b67	2059	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2060	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2061
<>	157:ff67d9f36b67	2062	/* Call user Abort complete callback */
<>	157:ff67d9f36b67	2063	HAL_IRDA_AbortCpltCallback(hirda);
<>	157:ff67d9f36b67	2064	}
<>	157:ff67d9f36b67	2065
<>	157:ff67d9f36b67	2066
<>	157:ff67d9f36b67	2067	/**
<>	157:ff67d9f36b67	2068	* @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
<>	157:ff67d9f36b67	2069	* HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
<>	157:ff67d9f36b67	2070	* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
<>	157:ff67d9f36b67	2071	* and leads to user Tx Abort Complete callback execution).
<>	157:ff67d9f36b67	2072	* @param hdma DMA handle.
<>	157:ff67d9f36b67	2073	* @retval None
<>	157:ff67d9f36b67	2074	*/
<>	157:ff67d9f36b67	2075	static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	2076	{
<>	157:ff67d9f36b67	2077	IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	2078
<>	157:ff67d9f36b67	2079	hirda->TxXferCount = 0;
<>	157:ff67d9f36b67	2080
<>	157:ff67d9f36b67	2081	/* Restore hirda->gState to Ready */
<>	157:ff67d9f36b67	2082	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2083
<>	157:ff67d9f36b67	2084	/* Call user Abort complete callback */
<>	157:ff67d9f36b67	2085	HAL_IRDA_AbortTransmitCpltCallback(hirda);
<>	157:ff67d9f36b67	2086	}
<>	157:ff67d9f36b67	2087
<>	157:ff67d9f36b67	2088	/**
<>	157:ff67d9f36b67	2089	* @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
<>	157:ff67d9f36b67	2090	* HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
<>	157:ff67d9f36b67	2091	* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
<>	157:ff67d9f36b67	2092	* and leads to user Rx Abort Complete callback execution).
<>	157:ff67d9f36b67	2093	* @param hdma DMA handle.
<>	157:ff67d9f36b67	2094	* @retval None
<>	157:ff67d9f36b67	2095	*/
<>	157:ff67d9f36b67	2096	static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	2097	{
<>	157:ff67d9f36b67	2098	IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	157:ff67d9f36b67	2099
<>	157:ff67d9f36b67	2100	hirda->RxXferCount = 0;
<>	157:ff67d9f36b67	2101
<>	157:ff67d9f36b67	2102	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	2103	__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF \| IRDA_CLEAR_NEF \| IRDA_CLEAR_PEF \| IRDA_CLEAR_FEF);
<>	157:ff67d9f36b67	2104
<>	157:ff67d9f36b67	2105	/* Restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	2106	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2107
<>	157:ff67d9f36b67	2108	/* Call user Abort complete callback */
<>	157:ff67d9f36b67	2109	HAL_IRDA_AbortReceiveCpltCallback(hirda);
<>	157:ff67d9f36b67	2110	}
<>	157:ff67d9f36b67	2111
<>	157:ff67d9f36b67	2112	/**
<>	157:ff67d9f36b67	2113	* @brief Send an amount of data in interrupt mode.
<>	157:ff67d9f36b67	2114	* @note Function is called under interruption only, once
<>	157:ff67d9f36b67	2115	* interruptions have been enabled by HAL_IRDA_Transmit_IT().
<>	157:ff67d9f36b67	2116	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	2117	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	2118	* @retval HAL status
<>	157:ff67d9f36b67	2119	*/
<>	157:ff67d9f36b67	2120	static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	2121	{
<>	157:ff67d9f36b67	2122	uint16_t* tmp;
<>	157:ff67d9f36b67	2123
<>	157:ff67d9f36b67	2124	/* Check that a Tx process is ongoing */
<>	157:ff67d9f36b67	2125	if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<>	157:ff67d9f36b67	2126	{
<>	157:ff67d9f36b67	2127	if(hirda->TxXferCount == 0)
<>	157:ff67d9f36b67	2128	{
<>	157:ff67d9f36b67	2129	/* Disable the IRDA Transmit Data Register Empty Interrupt */
<>	157:ff67d9f36b67	2130	CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<>	157:ff67d9f36b67	2131
<>	157:ff67d9f36b67	2132	/* Enable the IRDA Transmit Complete Interrupt */
<>	157:ff67d9f36b67	2133	SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<>	157:ff67d9f36b67	2134
<>	157:ff67d9f36b67	2135	return HAL_OK;
<>	157:ff67d9f36b67	2136	}
<>	157:ff67d9f36b67	2137	else
<>	157:ff67d9f36b67	2138	{
<>	157:ff67d9f36b67	2139	if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<>	157:ff67d9f36b67	2140	{
<>	157:ff67d9f36b67	2141	tmp = (uint16_t*) hirda->pTxBuffPtr;
<>	157:ff67d9f36b67	2142	hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
<>	157:ff67d9f36b67	2143	hirda->pTxBuffPtr += 2;
<>	157:ff67d9f36b67	2144	}
<>	157:ff67d9f36b67	2145	else
<>	157:ff67d9f36b67	2146	{
<>	157:ff67d9f36b67	2147	hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
<>	157:ff67d9f36b67	2148	}
<>	157:ff67d9f36b67	2149	hirda->TxXferCount--;
<>	157:ff67d9f36b67	2150
<>	157:ff67d9f36b67	2151	return HAL_OK;
<>	157:ff67d9f36b67	2152	}
<>	157:ff67d9f36b67	2153	}
<>	157:ff67d9f36b67	2154	else
<>	157:ff67d9f36b67	2155	{
<>	157:ff67d9f36b67	2156	return HAL_BUSY;
<>	157:ff67d9f36b67	2157	}
<>	157:ff67d9f36b67	2158	}
<>	157:ff67d9f36b67	2159
<>	157:ff67d9f36b67	2160	/**
<>	157:ff67d9f36b67	2161	* @brief Wrap up transmission in non-blocking mode.
<>	157:ff67d9f36b67	2162	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	2163	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	2164	* @retval HAL status
<>	157:ff67d9f36b67	2165	*/
<>	157:ff67d9f36b67	2166	static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	2167	{
<>	157:ff67d9f36b67	2168	/* Disable the IRDA Transmit Complete Interrupt */
<>	157:ff67d9f36b67	2169	CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<>	157:ff67d9f36b67	2170
<>	157:ff67d9f36b67	2171	/* Tx process is ended, restore hirda->gState to Ready */
<>	157:ff67d9f36b67	2172	hirda->gState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2173
<>	157:ff67d9f36b67	2174	HAL_IRDA_TxCpltCallback(hirda);
<>	157:ff67d9f36b67	2175
<>	157:ff67d9f36b67	2176	return HAL_OK;
<>	157:ff67d9f36b67	2177	}
<>	157:ff67d9f36b67	2178
<>	157:ff67d9f36b67	2179	/**
<>	157:ff67d9f36b67	2180	* @brief Receive an amount of data in interrupt mode.
<>	157:ff67d9f36b67	2181	* @note Function is called under interruption only, once
<>	157:ff67d9f36b67	2182	* interruptions have been enabled by HAL_IRDA_Receive_IT()
<>	157:ff67d9f36b67	2183	* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<>	157:ff67d9f36b67	2184	* the configuration information for the specified IRDA module.
<>	157:ff67d9f36b67	2185	* @retval HAL status
<>	157:ff67d9f36b67	2186	*/
<>	157:ff67d9f36b67	2187	static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
<>	157:ff67d9f36b67	2188	{
<>	157:ff67d9f36b67	2189	uint16_t* tmp;
<>	157:ff67d9f36b67	2190	uint16_t uhMask = hirda->Mask;
<>	157:ff67d9f36b67	2191	uint16_t uhdata;
<>	157:ff67d9f36b67	2192
<>	157:ff67d9f36b67	2193	/* Check that a Rx process is ongoing */
<>	157:ff67d9f36b67	2194	if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<>	157:ff67d9f36b67	2195	{
<>	157:ff67d9f36b67	2196	uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
<>	157:ff67d9f36b67	2197	if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<>	157:ff67d9f36b67	2198	{
<>	157:ff67d9f36b67	2199	tmp = (uint16_t*) hirda->pRxBuffPtr ;
<>	157:ff67d9f36b67	2200	*tmp = (uint16_t)(uhdata & uhMask);
<>	157:ff67d9f36b67	2201	hirda->pRxBuffPtr +=2;
<>	157:ff67d9f36b67	2202	}
<>	157:ff67d9f36b67	2203	else
<>	157:ff67d9f36b67	2204	{
<>	157:ff67d9f36b67	2205	*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
<>	157:ff67d9f36b67	2206	}
<>	157:ff67d9f36b67	2207
<>	157:ff67d9f36b67	2208	if(--hirda->RxXferCount == 0)
<>	157:ff67d9f36b67	2209	{
<>	157:ff67d9f36b67	2210	/* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
<>	157:ff67d9f36b67	2211	CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	157:ff67d9f36b67	2212
<>	157:ff67d9f36b67	2213	/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	2214	CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	2215
<>	157:ff67d9f36b67	2216	/* Rx process is completed, restore hirda->RxState to Ready */
<>	157:ff67d9f36b67	2217	hirda->RxState = HAL_IRDA_STATE_READY;
<>	157:ff67d9f36b67	2218
<>	157:ff67d9f36b67	2219	HAL_IRDA_RxCpltCallback(hirda);
<>	157:ff67d9f36b67	2220
<>	157:ff67d9f36b67	2221	return HAL_OK;
<>	157:ff67d9f36b67	2222	}
<>	157:ff67d9f36b67	2223
<>	157:ff67d9f36b67	2224	return HAL_OK;
<>	157:ff67d9f36b67	2225	}
<>	157:ff67d9f36b67	2226	else
<>	157:ff67d9f36b67	2227	{
<>	157:ff67d9f36b67	2228	/* Clear RXNE interrupt flag */
<>	157:ff67d9f36b67	2229	__HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
<>	157:ff67d9f36b67	2230
<>	157:ff67d9f36b67	2231	return HAL_BUSY;
<>	157:ff67d9f36b67	2232	}
<>	157:ff67d9f36b67	2233	}
<>	157:ff67d9f36b67	2234
<>	157:ff67d9f36b67	2235	/**
<>	157:ff67d9f36b67	2236	* @}
<>	157:ff67d9f36b67	2237	*/
<>	157:ff67d9f36b67	2238
<>	144:ef7eb2e8f9f7	2239	#endif /* HAL_IRDA_MODULE_ENABLED */
<>	157:ff67d9f36b67	2240	/**
<>	157:ff67d9f36b67	2241	* @}
<>	157:ff67d9f36b67	2242	*/
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	/**
<>	144:ef7eb2e8f9f7	2245	* @}
<>	144:ef7eb2e8f9f7	2246	*/
<>	144:ef7eb2e8f9f7	2247
<>	144:ef7eb2e8f9f7	2248	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	2249