mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 188:bcfe06ba3d64 1 /* mbed Microcontroller Library
AnnaBridge 188:bcfe06ba3d64 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 188:bcfe06ba3d64 3 *
AnnaBridge 188:bcfe06ba3d64 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 188:bcfe06ba3d64 5 * you may not use this file except in compliance with the License.
AnnaBridge 188:bcfe06ba3d64 6 * You may obtain a copy of the License at
AnnaBridge 188:bcfe06ba3d64 7 *
AnnaBridge 188:bcfe06ba3d64 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 188:bcfe06ba3d64 9 *
AnnaBridge 188:bcfe06ba3d64 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 188:bcfe06ba3d64 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 188:bcfe06ba3d64 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 188:bcfe06ba3d64 13 * See the License for the specific language governing permissions and
AnnaBridge 188:bcfe06ba3d64 14 * limitations under the License.
AnnaBridge 188:bcfe06ba3d64 15 */
AnnaBridge 188:bcfe06ba3d64 16
AnnaBridge 188:bcfe06ba3d64 17 /**
AnnaBridge 188:bcfe06ba3d64 18 * This file configures the system clock as follows:
AnnaBridge 188:bcfe06ba3d64 19 *-----------------------------------------------------------------------------
AnnaBridge 188:bcfe06ba3d64 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
AnnaBridge 188:bcfe06ba3d64 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
AnnaBridge 188:bcfe06ba3d64 22 * | 3- USE_PLL_HSI (internal 16 MHz)
AnnaBridge 188:bcfe06ba3d64 23 * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
AnnaBridge 188:bcfe06ba3d64 24 *-----------------------------------------------------------------------------
AnnaBridge 188:bcfe06ba3d64 25 * SYSCLK(MHz) | 80
AnnaBridge 188:bcfe06ba3d64 26 * AHBCLK (MHz) | 80
AnnaBridge 188:bcfe06ba3d64 27 * APB1CLK (MHz) | 80
AnnaBridge 188:bcfe06ba3d64 28 * APB2CLK (MHz) | 80
AnnaBridge 188:bcfe06ba3d64 29 * USB capable | YES
AnnaBridge 188:bcfe06ba3d64 30 *-----------------------------------------------------------------------------
AnnaBridge 188:bcfe06ba3d64 31 **/
AnnaBridge 188:bcfe06ba3d64 32
AnnaBridge 188:bcfe06ba3d64 33 #include "stm32l4xx.h"
AnnaBridge 188:bcfe06ba3d64 34 #include "nvic_addr.h"
AnnaBridge 188:bcfe06ba3d64 35 #include "mbed_assert.h"
AnnaBridge 188:bcfe06ba3d64 36
AnnaBridge 188:bcfe06ba3d64 37 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 188:bcfe06ba3d64 38 Internal SRAM. */
AnnaBridge 188:bcfe06ba3d64 39 /* #define VECT_TAB_SRAM */
AnnaBridge 188:bcfe06ba3d64 40 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
AnnaBridge 188:bcfe06ba3d64 41 This value must be a multiple of 0x200. */
AnnaBridge 188:bcfe06ba3d64 42
AnnaBridge 188:bcfe06ba3d64 43
AnnaBridge 188:bcfe06ba3d64 44 // clock source is selected with CLOCK_SOURCE in json config
AnnaBridge 188:bcfe06ba3d64 45 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
AnnaBridge 188:bcfe06ba3d64 46 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
AnnaBridge 188:bcfe06ba3d64 47 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 188:bcfe06ba3d64 48 #define USE_PLL_MSI 0x1 // Use MSI internal clock
AnnaBridge 188:bcfe06ba3d64 49
AnnaBridge 188:bcfe06ba3d64 50 #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
AnnaBridge 188:bcfe06ba3d64 51
AnnaBridge 188:bcfe06ba3d64 52 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 188:bcfe06ba3d64 53 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 188:bcfe06ba3d64 54 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 188:bcfe06ba3d64 55
AnnaBridge 188:bcfe06ba3d64 56 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 188:bcfe06ba3d64 57 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 188:bcfe06ba3d64 58 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 188:bcfe06ba3d64 59
AnnaBridge 188:bcfe06ba3d64 60 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
AnnaBridge 188:bcfe06ba3d64 61 uint8_t SetSysClock_PLL_MSI(void);
AnnaBridge 188:bcfe06ba3d64 62 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
AnnaBridge 188:bcfe06ba3d64 63
AnnaBridge 188:bcfe06ba3d64 64
AnnaBridge 188:bcfe06ba3d64 65 /**
AnnaBridge 188:bcfe06ba3d64 66 * @brief Setup the microcontroller system.
AnnaBridge 188:bcfe06ba3d64 67 * @param None
AnnaBridge 188:bcfe06ba3d64 68 * @retval None
AnnaBridge 188:bcfe06ba3d64 69 */
AnnaBridge 188:bcfe06ba3d64 70
AnnaBridge 188:bcfe06ba3d64 71 void SystemInit(void)
AnnaBridge 188:bcfe06ba3d64 72 {
AnnaBridge 188:bcfe06ba3d64 73 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 188:bcfe06ba3d64 74 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 188:bcfe06ba3d64 75 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
AnnaBridge 188:bcfe06ba3d64 76 #endif
AnnaBridge 188:bcfe06ba3d64 77 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 188:bcfe06ba3d64 78 /* Set MSION bit */
AnnaBridge 188:bcfe06ba3d64 79 RCC->CR |= RCC_CR_MSION;
AnnaBridge 188:bcfe06ba3d64 80
AnnaBridge 188:bcfe06ba3d64 81 /* Reset CFGR register */
AnnaBridge 188:bcfe06ba3d64 82 RCC->CFGR = 0x00000000;
AnnaBridge 188:bcfe06ba3d64 83
AnnaBridge 188:bcfe06ba3d64 84 /* Reset HSEON, CSSON , HSION, and PLLON bits */
AnnaBridge 188:bcfe06ba3d64 85 RCC->CR &= (uint32_t)0xEAF6FFFF;
AnnaBridge 188:bcfe06ba3d64 86
AnnaBridge 188:bcfe06ba3d64 87 /* Reset PLLCFGR register */
AnnaBridge 188:bcfe06ba3d64 88 RCC->PLLCFGR = 0x00001000;
AnnaBridge 188:bcfe06ba3d64 89
AnnaBridge 188:bcfe06ba3d64 90 /* Reset HSEBYP bit */
AnnaBridge 188:bcfe06ba3d64 91 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 188:bcfe06ba3d64 92
AnnaBridge 188:bcfe06ba3d64 93 /* Disable all interrupts */
AnnaBridge 188:bcfe06ba3d64 94 RCC->CIER = 0x00000000;
AnnaBridge 188:bcfe06ba3d64 95
AnnaBridge 188:bcfe06ba3d64 96 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 188:bcfe06ba3d64 97 #ifdef VECT_TAB_SRAM
AnnaBridge 188:bcfe06ba3d64 98 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 188:bcfe06ba3d64 99 #else
AnnaBridge 188:bcfe06ba3d64 100 SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 188:bcfe06ba3d64 101 #endif
AnnaBridge 188:bcfe06ba3d64 102
AnnaBridge 188:bcfe06ba3d64 103 }
AnnaBridge 188:bcfe06ba3d64 104
AnnaBridge 188:bcfe06ba3d64 105
AnnaBridge 188:bcfe06ba3d64 106 /**
AnnaBridge 188:bcfe06ba3d64 107 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 188:bcfe06ba3d64 108 * AHB/APBx prescalers and Flash settings
AnnaBridge 188:bcfe06ba3d64 109 * @note This function should be called only once the RCC clock configuration
AnnaBridge 188:bcfe06ba3d64 110 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 188:bcfe06ba3d64 111 * @param None
AnnaBridge 188:bcfe06ba3d64 112 * @retval None
AnnaBridge 188:bcfe06ba3d64 113 */
AnnaBridge 188:bcfe06ba3d64 114
AnnaBridge 188:bcfe06ba3d64 115 void SetSysClock(void)
AnnaBridge 188:bcfe06ba3d64 116 {
AnnaBridge 188:bcfe06ba3d64 117 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 188:bcfe06ba3d64 118 /* 1- Try to start with HSE and external clock */
AnnaBridge 188:bcfe06ba3d64 119 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 188:bcfe06ba3d64 120 #endif
AnnaBridge 188:bcfe06ba3d64 121 {
AnnaBridge 188:bcfe06ba3d64 122 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 188:bcfe06ba3d64 123 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 188:bcfe06ba3d64 124 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 188:bcfe06ba3d64 125 #endif
AnnaBridge 188:bcfe06ba3d64 126 {
AnnaBridge 188:bcfe06ba3d64 127 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 188:bcfe06ba3d64 128 /* 3- If fail start with HSI clock */
AnnaBridge 188:bcfe06ba3d64 129 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 188:bcfe06ba3d64 130 #endif
AnnaBridge 188:bcfe06ba3d64 131 {
AnnaBridge 188:bcfe06ba3d64 132 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
AnnaBridge 188:bcfe06ba3d64 133 /* 4- If fail start with MSI clock */
AnnaBridge 188:bcfe06ba3d64 134 if (SetSysClock_PLL_MSI() == 0)
AnnaBridge 188:bcfe06ba3d64 135 #endif
AnnaBridge 188:bcfe06ba3d64 136 {
AnnaBridge 188:bcfe06ba3d64 137 while (1) {
AnnaBridge 188:bcfe06ba3d64 138 MBED_ASSERT(1);
AnnaBridge 188:bcfe06ba3d64 139 }
AnnaBridge 188:bcfe06ba3d64 140 }
AnnaBridge 188:bcfe06ba3d64 141 }
AnnaBridge 188:bcfe06ba3d64 142 }
AnnaBridge 188:bcfe06ba3d64 143 }
AnnaBridge 188:bcfe06ba3d64 144
AnnaBridge 188:bcfe06ba3d64 145 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 188:bcfe06ba3d64 146 #if DEBUG_MCO == 1
AnnaBridge 188:bcfe06ba3d64 147 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
AnnaBridge 188:bcfe06ba3d64 148 #endif
AnnaBridge 188:bcfe06ba3d64 149 }
AnnaBridge 188:bcfe06ba3d64 150
AnnaBridge 188:bcfe06ba3d64 151 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 188:bcfe06ba3d64 152 /******************************************************************************/
AnnaBridge 188:bcfe06ba3d64 153 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 188:bcfe06ba3d64 154 /******************************************************************************/
AnnaBridge 188:bcfe06ba3d64 155 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 188:bcfe06ba3d64 156 {
AnnaBridge 188:bcfe06ba3d64 157 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
AnnaBridge 188:bcfe06ba3d64 158 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
AnnaBridge 188:bcfe06ba3d64 159 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
AnnaBridge 188:bcfe06ba3d64 160
AnnaBridge 188:bcfe06ba3d64 161 // Used to gain time after DeepSleep in case HSI is used
AnnaBridge 188:bcfe06ba3d64 162 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
AnnaBridge 188:bcfe06ba3d64 163 return 0;
AnnaBridge 188:bcfe06ba3d64 164 }
AnnaBridge 188:bcfe06ba3d64 165
AnnaBridge 188:bcfe06ba3d64 166 // Select MSI as system clock source to allow modification of the PLL configuration
AnnaBridge 188:bcfe06ba3d64 167 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
AnnaBridge 188:bcfe06ba3d64 168 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
AnnaBridge 188:bcfe06ba3d64 169 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
AnnaBridge 188:bcfe06ba3d64 170
AnnaBridge 188:bcfe06ba3d64 171 // Enable HSE oscillator and activate PLL with HSE as source
AnnaBridge 188:bcfe06ba3d64 172 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
AnnaBridge 188:bcfe06ba3d64 173 if (bypass == 0) {
AnnaBridge 188:bcfe06ba3d64 174 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
AnnaBridge 188:bcfe06ba3d64 175 } else {
AnnaBridge 188:bcfe06ba3d64 176 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
AnnaBridge 188:bcfe06ba3d64 177 }
AnnaBridge 188:bcfe06ba3d64 178 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
AnnaBridge 188:bcfe06ba3d64 179 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
AnnaBridge 188:bcfe06ba3d64 180 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 188:bcfe06ba3d64 181 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
AnnaBridge 188:bcfe06ba3d64 182 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
AnnaBridge 188:bcfe06ba3d64 183 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
AnnaBridge 188:bcfe06ba3d64 184 RCC_OscInitStruct.PLL.PLLQ = 2;
AnnaBridge 188:bcfe06ba3d64 185 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
AnnaBridge 188:bcfe06ba3d64 186
AnnaBridge 188:bcfe06ba3d64 187 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 188 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 189 }
AnnaBridge 188:bcfe06ba3d64 190
AnnaBridge 188:bcfe06ba3d64 191 // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 188:bcfe06ba3d64 192 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 188:bcfe06ba3d64 193 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
AnnaBridge 188:bcfe06ba3d64 194 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
AnnaBridge 188:bcfe06ba3d64 195 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
AnnaBridge 188:bcfe06ba3d64 196 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
AnnaBridge 188:bcfe06ba3d64 197 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 198 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 199 }
AnnaBridge 188:bcfe06ba3d64 200
AnnaBridge 188:bcfe06ba3d64 201 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 188:bcfe06ba3d64 202 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
AnnaBridge 188:bcfe06ba3d64 203 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
AnnaBridge 188:bcfe06ba3d64 204 RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
AnnaBridge 188:bcfe06ba3d64 205 RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
AnnaBridge 188:bcfe06ba3d64 206 RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
AnnaBridge 188:bcfe06ba3d64 207 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
AnnaBridge 188:bcfe06ba3d64 208 RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
AnnaBridge 188:bcfe06ba3d64 209 RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
AnnaBridge 188:bcfe06ba3d64 210 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 211 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 212 }
AnnaBridge 188:bcfe06ba3d64 213
AnnaBridge 188:bcfe06ba3d64 214 // Disable MSI Oscillator
AnnaBridge 188:bcfe06ba3d64 215 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
AnnaBridge 188:bcfe06ba3d64 216 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
AnnaBridge 188:bcfe06ba3d64 217 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
AnnaBridge 188:bcfe06ba3d64 218 HAL_RCC_OscConfig(&RCC_OscInitStruct);
AnnaBridge 188:bcfe06ba3d64 219
AnnaBridge 188:bcfe06ba3d64 220 /* Select HSI as clock source for LPUART1 */
AnnaBridge 188:bcfe06ba3d64 221 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
AnnaBridge 188:bcfe06ba3d64 222 RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
AnnaBridge 188:bcfe06ba3d64 223 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 224 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 225 }
AnnaBridge 188:bcfe06ba3d64 226
AnnaBridge 188:bcfe06ba3d64 227 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 188:bcfe06ba3d64 228 #if DEBUG_MCO == 2
AnnaBridge 188:bcfe06ba3d64 229 if (bypass == 0) {
AnnaBridge 188:bcfe06ba3d64 230 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
AnnaBridge 188:bcfe06ba3d64 231 } else {
AnnaBridge 188:bcfe06ba3d64 232 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
AnnaBridge 188:bcfe06ba3d64 233 }
AnnaBridge 188:bcfe06ba3d64 234 #endif
AnnaBridge 188:bcfe06ba3d64 235
AnnaBridge 188:bcfe06ba3d64 236 return 1; // OK
AnnaBridge 188:bcfe06ba3d64 237 }
AnnaBridge 188:bcfe06ba3d64 238 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 188:bcfe06ba3d64 239
AnnaBridge 188:bcfe06ba3d64 240 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 188:bcfe06ba3d64 241 /******************************************************************************/
AnnaBridge 188:bcfe06ba3d64 242 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 188:bcfe06ba3d64 243 /******************************************************************************/
AnnaBridge 188:bcfe06ba3d64 244 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 188:bcfe06ba3d64 245 {
AnnaBridge 188:bcfe06ba3d64 246 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
AnnaBridge 188:bcfe06ba3d64 247 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
AnnaBridge 188:bcfe06ba3d64 248 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
AnnaBridge 188:bcfe06ba3d64 249
AnnaBridge 188:bcfe06ba3d64 250 // Select MSI as system clock source to allow modification of the PLL configuration
AnnaBridge 188:bcfe06ba3d64 251 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
AnnaBridge 188:bcfe06ba3d64 252 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
AnnaBridge 188:bcfe06ba3d64 253 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
AnnaBridge 188:bcfe06ba3d64 254
AnnaBridge 188:bcfe06ba3d64 255 // Enable HSI oscillator and activate PLL with HSI as source
AnnaBridge 188:bcfe06ba3d64 256 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 188:bcfe06ba3d64 257 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 188:bcfe06ba3d64 258 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 188:bcfe06ba3d64 259 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 188:bcfe06ba3d64 260 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 188:bcfe06ba3d64 261 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
AnnaBridge 188:bcfe06ba3d64 262 RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
AnnaBridge 188:bcfe06ba3d64 263 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
AnnaBridge 188:bcfe06ba3d64 264 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
AnnaBridge 188:bcfe06ba3d64 265 RCC_OscInitStruct.PLL.PLLQ = 2;
AnnaBridge 188:bcfe06ba3d64 266 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
AnnaBridge 188:bcfe06ba3d64 267 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 268 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 269 }
AnnaBridge 188:bcfe06ba3d64 270
AnnaBridge 188:bcfe06ba3d64 271 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 188:bcfe06ba3d64 272 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 188:bcfe06ba3d64 273 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
AnnaBridge 188:bcfe06ba3d64 274 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
AnnaBridge 188:bcfe06ba3d64 275 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
AnnaBridge 188:bcfe06ba3d64 276 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
AnnaBridge 188:bcfe06ba3d64 277 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 278 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 279 }
AnnaBridge 188:bcfe06ba3d64 280
AnnaBridge 188:bcfe06ba3d64 281 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 188:bcfe06ba3d64 282 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
AnnaBridge 188:bcfe06ba3d64 283 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
AnnaBridge 188:bcfe06ba3d64 284 RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
AnnaBridge 188:bcfe06ba3d64 285 RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
AnnaBridge 188:bcfe06ba3d64 286 RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
AnnaBridge 188:bcfe06ba3d64 287 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
AnnaBridge 188:bcfe06ba3d64 288 RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
AnnaBridge 188:bcfe06ba3d64 289 RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
AnnaBridge 188:bcfe06ba3d64 290 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 291 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 292 }
AnnaBridge 188:bcfe06ba3d64 293
AnnaBridge 188:bcfe06ba3d64 294 // Disable MSI Oscillator
AnnaBridge 188:bcfe06ba3d64 295 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
AnnaBridge 188:bcfe06ba3d64 296 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
AnnaBridge 188:bcfe06ba3d64 297 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
AnnaBridge 188:bcfe06ba3d64 298 HAL_RCC_OscConfig(&RCC_OscInitStruct);
AnnaBridge 188:bcfe06ba3d64 299
AnnaBridge 188:bcfe06ba3d64 300 /* Select HSI as clock source for LPUART1 */
AnnaBridge 188:bcfe06ba3d64 301 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
AnnaBridge 188:bcfe06ba3d64 302 RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
AnnaBridge 188:bcfe06ba3d64 303 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 304 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 305 }
AnnaBridge 188:bcfe06ba3d64 306
AnnaBridge 188:bcfe06ba3d64 307 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 188:bcfe06ba3d64 308 #if DEBUG_MCO == 3
AnnaBridge 188:bcfe06ba3d64 309 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 188:bcfe06ba3d64 310 #endif
AnnaBridge 188:bcfe06ba3d64 311
AnnaBridge 188:bcfe06ba3d64 312 return 1; // OK
AnnaBridge 188:bcfe06ba3d64 313 }
AnnaBridge 188:bcfe06ba3d64 314 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 188:bcfe06ba3d64 315
AnnaBridge 188:bcfe06ba3d64 316 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
AnnaBridge 188:bcfe06ba3d64 317 /******************************************************************************/
AnnaBridge 188:bcfe06ba3d64 318 /* PLL (clocked by MSI) used as System clock source */
AnnaBridge 188:bcfe06ba3d64 319 /******************************************************************************/
AnnaBridge 188:bcfe06ba3d64 320 uint8_t SetSysClock_PLL_MSI(void)
AnnaBridge 188:bcfe06ba3d64 321 {
AnnaBridge 188:bcfe06ba3d64 322 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
AnnaBridge 188:bcfe06ba3d64 323 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
AnnaBridge 188:bcfe06ba3d64 324 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
AnnaBridge 188:bcfe06ba3d64 325
AnnaBridge 188:bcfe06ba3d64 326 // Enable LSE Oscillator to automatically calibrate the MSI clock
AnnaBridge 188:bcfe06ba3d64 327 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
AnnaBridge 188:bcfe06ba3d64 328 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
AnnaBridge 188:bcfe06ba3d64 329 RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
AnnaBridge 188:bcfe06ba3d64 330 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 331 RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
AnnaBridge 188:bcfe06ba3d64 332 }
AnnaBridge 188:bcfe06ba3d64 333
AnnaBridge 188:bcfe06ba3d64 334 HAL_RCCEx_DisableLSECSS();
AnnaBridge 188:bcfe06ba3d64 335 /* Enable MSI Oscillator and activate PLL with MSI as source */
AnnaBridge 188:bcfe06ba3d64 336 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 188:bcfe06ba3d64 337 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
AnnaBridge 188:bcfe06ba3d64 338 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 188:bcfe06ba3d64 339 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
AnnaBridge 188:bcfe06ba3d64 340 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
AnnaBridge 188:bcfe06ba3d64 341 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
AnnaBridge 188:bcfe06ba3d64 342 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 188:bcfe06ba3d64 343 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
AnnaBridge 188:bcfe06ba3d64 344 RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
AnnaBridge 188:bcfe06ba3d64 345 RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
AnnaBridge 188:bcfe06ba3d64 346 RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
AnnaBridge 188:bcfe06ba3d64 347 RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
AnnaBridge 188:bcfe06ba3d64 348 RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
AnnaBridge 188:bcfe06ba3d64 349 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 350 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 351 }
AnnaBridge 188:bcfe06ba3d64 352 /* Enable MSI Auto-calibration through LSE */
AnnaBridge 188:bcfe06ba3d64 353 HAL_RCCEx_EnableMSIPLLMode();
AnnaBridge 188:bcfe06ba3d64 354 /* Select MSI output as USB clock source */
AnnaBridge 188:bcfe06ba3d64 355 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 188:bcfe06ba3d64 356 PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
AnnaBridge 188:bcfe06ba3d64 357 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 188:bcfe06ba3d64 358
AnnaBridge 188:bcfe06ba3d64 359 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 188:bcfe06ba3d64 360 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 188:bcfe06ba3d64 361 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
AnnaBridge 188:bcfe06ba3d64 362 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
AnnaBridge 188:bcfe06ba3d64 363 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
AnnaBridge 188:bcfe06ba3d64 364 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
AnnaBridge 188:bcfe06ba3d64 365 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 366 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 367 }
AnnaBridge 188:bcfe06ba3d64 368
AnnaBridge 188:bcfe06ba3d64 369 /* Select LSE as clock source for LPUART1 */
AnnaBridge 188:bcfe06ba3d64 370 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
AnnaBridge 188:bcfe06ba3d64 371 PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
AnnaBridge 188:bcfe06ba3d64 372 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 373 return 0; // FAIL
AnnaBridge 188:bcfe06ba3d64 374 }
AnnaBridge 188:bcfe06ba3d64 375
AnnaBridge 188:bcfe06ba3d64 376 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 188:bcfe06ba3d64 377 #if DEBUG_MCO == 4
AnnaBridge 188:bcfe06ba3d64 378 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
AnnaBridge 188:bcfe06ba3d64 379 #endif
AnnaBridge 188:bcfe06ba3d64 380
AnnaBridge 188:bcfe06ba3d64 381 return 1; // OK
AnnaBridge 188:bcfe06ba3d64 382 }
AnnaBridge 188:bcfe06ba3d64 383 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */