mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 170:19eb464bc2be 1 /**
Kojto 170:19eb464bc2be 2 ******************************************************************************
Kojto 170:19eb464bc2be 3 * @file system_stm32l4xx.c
Kojto 170:19eb464bc2be 4 * @author MCD Application Team
Kojto 170:19eb464bc2be 5 * @version V1.3.1
Kojto 170:19eb464bc2be 6 * @date 21-April-2017
Kojto 170:19eb464bc2be 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
Kojto 170:19eb464bc2be 8 *
Kojto 170:19eb464bc2be 9 * This file provides two functions and one global variable to be called from
Kojto 170:19eb464bc2be 10 * user application:
Kojto 170:19eb464bc2be 11 * - SystemInit(): This function is called at startup just after reset and
Kojto 170:19eb464bc2be 12 * before branch to main program. This call is made inside
Kojto 170:19eb464bc2be 13 * the "startup_stm32l4xx.s" file.
Kojto 170:19eb464bc2be 14 *
Kojto 170:19eb464bc2be 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
Kojto 170:19eb464bc2be 16 * by the user application to setup the SysTick
Kojto 170:19eb464bc2be 17 * timer or configure other parameters.
Kojto 170:19eb464bc2be 18 *
Kojto 170:19eb464bc2be 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
Kojto 170:19eb464bc2be 20 * be called whenever the core clock is changed
Kojto 170:19eb464bc2be 21 * during program execution.
Kojto 170:19eb464bc2be 22 *
Kojto 170:19eb464bc2be 23 * After each device reset the MSI (4 MHz) is used as system clock source.
Kojto 170:19eb464bc2be 24 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
Kojto 170:19eb464bc2be 25 * configure the system clock before to branch to main program.
Kojto 170:19eb464bc2be 26 *
Kojto 170:19eb464bc2be 27 * This file configures the system clock as follows:
Kojto 170:19eb464bc2be 28 *=============================================================================
Kojto 170:19eb464bc2be 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
Kojto 170:19eb464bc2be 30 * | (external 8 MHz clock) | (internal 16 MHz)
Kojto 170:19eb464bc2be 31 * | 2- PLL_HSE_XTAL | or PLL_MSI
Kojto 170:19eb464bc2be 32 * | (external 8 MHz xtal) | (internal 4 MHz)
Kojto 170:19eb464bc2be 33 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 34 * SYSCLK(MHz) | 48 | 80
Kojto 170:19eb464bc2be 35 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 36 * AHBCLK (MHz) | 48 | 80
Kojto 170:19eb464bc2be 37 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 38 * APB1CLK (MHz) | 48 | 80
Kojto 170:19eb464bc2be 39 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 40 * APB2CLK (MHz) | 48 | 80
Kojto 170:19eb464bc2be 41 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 42 * USB capable (48 MHz precise clock) | YES | NO
Kojto 170:19eb464bc2be 43 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 44 **/
Kojto 170:19eb464bc2be 45
Kojto 170:19eb464bc2be 46 #include "stm32l4xx.h"
Kojto 170:19eb464bc2be 47 #include "nvic_addr.h"
AnnaBridge 187:0387e8f68319 48 #include "mbed_error.h"
Kojto 170:19eb464bc2be 49
Kojto 170:19eb464bc2be 50 /*!< Uncomment the following line if you need to relocate your vector Table in
Kojto 170:19eb464bc2be 51 Internal SRAM. */
Kojto 170:19eb464bc2be 52 /* #define VECT_TAB_SRAM */
Kojto 170:19eb464bc2be 53 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
Kojto 170:19eb464bc2be 54 This value must be a multiple of 0x200. */
Kojto 170:19eb464bc2be 55
Kojto 170:19eb464bc2be 56
Kojto 170:19eb464bc2be 57 // clock source is selected with CLOCK_SOURCE in json config
Kojto 170:19eb464bc2be 58 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
Kojto 170:19eb464bc2be 59 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
Kojto 170:19eb464bc2be 60 #define USE_PLL_HSI 0x2 // Use HSI internal clock
Kojto 170:19eb464bc2be 61 #define USE_PLL_MSI 0x1 // Use MSI internal clock
Kojto 170:19eb464bc2be 62
Kojto 170:19eb464bc2be 63 #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
Kojto 170:19eb464bc2be 64
Kojto 170:19eb464bc2be 65 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 66 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
Kojto 170:19eb464bc2be 67 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 68
Kojto 170:19eb464bc2be 69 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 70 uint8_t SetSysClock_PLL_HSI(void);
Kojto 170:19eb464bc2be 71 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
Kojto 170:19eb464bc2be 72
Kojto 170:19eb464bc2be 73 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
Kojto 170:19eb464bc2be 74 uint8_t SetSysClock_PLL_MSI(void);
Kojto 170:19eb464bc2be 75 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
Kojto 170:19eb464bc2be 76
Kojto 170:19eb464bc2be 77
Kojto 170:19eb464bc2be 78 /**
Kojto 170:19eb464bc2be 79 * @brief Setup the microcontroller system.
Kojto 170:19eb464bc2be 80 * @param None
Kojto 170:19eb464bc2be 81 * @retval None
Kojto 170:19eb464bc2be 82 */
Kojto 170:19eb464bc2be 83
Kojto 170:19eb464bc2be 84 void SystemInit(void)
Kojto 170:19eb464bc2be 85 {
Kojto 170:19eb464bc2be 86 /* FPU settings ------------------------------------------------------------*/
Kojto 170:19eb464bc2be 87 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 88 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
Kojto 170:19eb464bc2be 89 #endif
Kojto 170:19eb464bc2be 90 /* Reset the RCC clock configuration to the default reset state ------------*/
Kojto 170:19eb464bc2be 91 /* Set MSION bit */
Kojto 170:19eb464bc2be 92 RCC->CR |= RCC_CR_MSION;
Kojto 170:19eb464bc2be 93
Kojto 170:19eb464bc2be 94 /* Reset CFGR register */
Kojto 170:19eb464bc2be 95 RCC->CFGR = 0x00000000;
Kojto 170:19eb464bc2be 96
Kojto 170:19eb464bc2be 97 /* Reset HSEON, CSSON , HSION, and PLLON bits */
Kojto 170:19eb464bc2be 98 RCC->CR &= (uint32_t)0xEAF6FFFF;
Kojto 170:19eb464bc2be 99
Kojto 170:19eb464bc2be 100 /* Reset PLLCFGR register */
Kojto 170:19eb464bc2be 101 RCC->PLLCFGR = 0x00001000;
Kojto 170:19eb464bc2be 102
Kojto 170:19eb464bc2be 103 /* Reset HSEBYP bit */
Kojto 170:19eb464bc2be 104 RCC->CR &= (uint32_t)0xFFFBFFFF;
Kojto 170:19eb464bc2be 105
Kojto 170:19eb464bc2be 106 /* Disable all interrupts */
Kojto 170:19eb464bc2be 107 RCC->CIER = 0x00000000;
Kojto 170:19eb464bc2be 108
Kojto 170:19eb464bc2be 109 /* Configure the Vector Table location add offset address ------------------*/
Kojto 170:19eb464bc2be 110 #ifdef VECT_TAB_SRAM
Kojto 170:19eb464bc2be 111 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
Kojto 170:19eb464bc2be 112 #else
Anna Bridge 180:96ed750bd169 113 SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
Kojto 170:19eb464bc2be 114 #endif
Kojto 170:19eb464bc2be 115
Kojto 170:19eb464bc2be 116 }
Kojto 170:19eb464bc2be 117
Kojto 170:19eb464bc2be 118
Kojto 170:19eb464bc2be 119 /**
Kojto 170:19eb464bc2be 120 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
Kojto 170:19eb464bc2be 121 * AHB/APBx prescalers and Flash settings
Kojto 170:19eb464bc2be 122 * @note This function should be called only once the RCC clock configuration
Kojto 170:19eb464bc2be 123 * is reset to the default reset state (done in SystemInit() function).
Kojto 170:19eb464bc2be 124 * @param None
Kojto 170:19eb464bc2be 125 * @retval None
Kojto 170:19eb464bc2be 126 */
Kojto 170:19eb464bc2be 127
Kojto 170:19eb464bc2be 128 void SetSysClock(void)
Kojto 170:19eb464bc2be 129 {
Kojto 170:19eb464bc2be 130 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
Kojto 170:19eb464bc2be 131 /* 1- Try to start with HSE and external clock */
Kojto 170:19eb464bc2be 132 if (SetSysClock_PLL_HSE(1) == 0)
Kojto 170:19eb464bc2be 133 #endif
Kojto 170:19eb464bc2be 134 {
Kojto 170:19eb464bc2be 135 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
Kojto 170:19eb464bc2be 136 /* 2- If fail try to start with HSE and external xtal */
Kojto 170:19eb464bc2be 137 if (SetSysClock_PLL_HSE(0) == 0)
Kojto 170:19eb464bc2be 138 #endif
Kojto 170:19eb464bc2be 139 {
Kojto 170:19eb464bc2be 140 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 141 /* 3- If fail start with HSI clock */
AnnaBridge 187:0387e8f68319 142 if (SetSysClock_PLL_HSI() == 0)
Kojto 170:19eb464bc2be 143 #endif
Kojto 170:19eb464bc2be 144 {
Kojto 170:19eb464bc2be 145 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
Kojto 170:19eb464bc2be 146 /* 4- If fail start with MSI clock */
Kojto 170:19eb464bc2be 147 if (SetSysClock_PLL_MSI() == 0)
Kojto 170:19eb464bc2be 148 #endif
Kojto 170:19eb464bc2be 149 {
AnnaBridge 187:0387e8f68319 150 {
AnnaBridge 187:0387e8f68319 151 error("SetSysClock failed\n");
Kojto 170:19eb464bc2be 152 }
Kojto 170:19eb464bc2be 153 }
Kojto 170:19eb464bc2be 154 }
Kojto 170:19eb464bc2be 155 }
Kojto 170:19eb464bc2be 156 }
Kojto 170:19eb464bc2be 157
Kojto 170:19eb464bc2be 158 // Output clock on MCO1 pin(PA8) for debugging purpose
Kojto 170:19eb464bc2be 159 #if DEBUG_MCO == 1
Kojto 170:19eb464bc2be 160 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
Kojto 170:19eb464bc2be 161 #endif
Kojto 170:19eb464bc2be 162 }
Kojto 170:19eb464bc2be 163
Kojto 170:19eb464bc2be 164 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 165 /******************************************************************************/
Kojto 170:19eb464bc2be 166 /* PLL (clocked by HSE) used as System clock source */
Kojto 170:19eb464bc2be 167 /******************************************************************************/
Kojto 170:19eb464bc2be 168 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
Kojto 170:19eb464bc2be 169 {
Kojto 170:19eb464bc2be 170 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
Kojto 170:19eb464bc2be 171 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
Kojto 170:19eb464bc2be 172 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
Kojto 170:19eb464bc2be 173
Kojto 170:19eb464bc2be 174 // Used to gain time after DeepSleep in case HSI is used
Kojto 170:19eb464bc2be 175 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
Kojto 170:19eb464bc2be 176 return 0;
Kojto 170:19eb464bc2be 177 }
Kojto 170:19eb464bc2be 178
Kojto 170:19eb464bc2be 179 // Select MSI as system clock source to allow modification of the PLL configuration
Kojto 170:19eb464bc2be 180 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
Kojto 170:19eb464bc2be 181 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
Kojto 170:19eb464bc2be 182 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
Kojto 170:19eb464bc2be 183
Kojto 170:19eb464bc2be 184 // Enable HSE oscillator and activate PLL with HSE as source
Kojto 170:19eb464bc2be 185 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
Kojto 170:19eb464bc2be 186 if (bypass == 0) {
Kojto 170:19eb464bc2be 187 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
Kojto 170:19eb464bc2be 188 } else {
Kojto 170:19eb464bc2be 189 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
Kojto 170:19eb464bc2be 190 }
Kojto 170:19eb464bc2be 191 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
Kojto 170:19eb464bc2be 192 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
Kojto 170:19eb464bc2be 193 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 194 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
Kojto 170:19eb464bc2be 195 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
Kojto 170:19eb464bc2be 196 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
Kojto 170:19eb464bc2be 197 RCC_OscInitStruct.PLL.PLLQ = 2;
Kojto 170:19eb464bc2be 198 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
Kojto 170:19eb464bc2be 199
Kojto 170:19eb464bc2be 200 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 201 return 0; // FAIL
Kojto 170:19eb464bc2be 202 }
Kojto 170:19eb464bc2be 203
Kojto 170:19eb464bc2be 204 // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
Kojto 170:19eb464bc2be 205 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 206 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
Kojto 170:19eb464bc2be 207 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
Kojto 170:19eb464bc2be 208 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
Kojto 170:19eb464bc2be 209 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
Kojto 170:19eb464bc2be 210 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
Kojto 170:19eb464bc2be 211 return 0; // FAIL
Kojto 170:19eb464bc2be 212 }
Kojto 170:19eb464bc2be 213
Kojto 170:19eb464bc2be 214 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
Kojto 170:19eb464bc2be 215 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
Kojto 170:19eb464bc2be 216 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
Kojto 170:19eb464bc2be 217 RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
Kojto 170:19eb464bc2be 218 RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
Kojto 170:19eb464bc2be 219 RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
Kojto 170:19eb464bc2be 220 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
Kojto 170:19eb464bc2be 221 RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
Kojto 170:19eb464bc2be 222 RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
Kojto 170:19eb464bc2be 223 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
Kojto 170:19eb464bc2be 224 return 0; // FAIL
Kojto 170:19eb464bc2be 225 }
Kojto 170:19eb464bc2be 226
Kojto 170:19eb464bc2be 227 // Disable MSI Oscillator
Kojto 170:19eb464bc2be 228 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
Kojto 170:19eb464bc2be 229 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
Kojto 170:19eb464bc2be 230 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
Kojto 170:19eb464bc2be 231 HAL_RCC_OscConfig(&RCC_OscInitStruct);
Kojto 170:19eb464bc2be 232
Kojto 170:19eb464bc2be 233 // Output clock on MCO1 pin(PA8) for debugging purpose
Kojto 170:19eb464bc2be 234 #if DEBUG_MCO == 2
AnnaBridge 187:0387e8f68319 235 if (bypass == 0) {
AnnaBridge 187:0387e8f68319 236 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
AnnaBridge 187:0387e8f68319 237 } else {
AnnaBridge 187:0387e8f68319 238 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
AnnaBridge 187:0387e8f68319 239 }
Kojto 170:19eb464bc2be 240 #endif
Kojto 170:19eb464bc2be 241
Kojto 170:19eb464bc2be 242 return 1; // OK
Kojto 170:19eb464bc2be 243 }
Kojto 170:19eb464bc2be 244 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 245
Kojto 170:19eb464bc2be 246 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 247 /******************************************************************************/
Kojto 170:19eb464bc2be 248 /* PLL (clocked by HSI) used as System clock source */
Kojto 170:19eb464bc2be 249 /******************************************************************************/
Kojto 170:19eb464bc2be 250 uint8_t SetSysClock_PLL_HSI(void)
Kojto 170:19eb464bc2be 251 {
Kojto 170:19eb464bc2be 252 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
Kojto 170:19eb464bc2be 253 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
Kojto 170:19eb464bc2be 254 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
Kojto 170:19eb464bc2be 255
Kojto 170:19eb464bc2be 256 // Select MSI as system clock source to allow modification of the PLL configuration
Kojto 170:19eb464bc2be 257 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
Kojto 170:19eb464bc2be 258 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
Kojto 170:19eb464bc2be 259 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
Kojto 170:19eb464bc2be 260
Kojto 170:19eb464bc2be 261 // Enable HSI oscillator and activate PLL with HSI as source
Kojto 170:19eb464bc2be 262 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
Kojto 170:19eb464bc2be 263 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
Kojto 170:19eb464bc2be 264 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Kojto 170:19eb464bc2be 265 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
Kojto 170:19eb464bc2be 266 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 267 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
Kojto 170:19eb464bc2be 268 RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
Kojto 170:19eb464bc2be 269 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
Kojto 170:19eb464bc2be 270 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
Kojto 170:19eb464bc2be 271 RCC_OscInitStruct.PLL.PLLQ = 2;
Kojto 170:19eb464bc2be 272 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
Kojto 170:19eb464bc2be 273 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 274 return 0; // FAIL
Kojto 170:19eb464bc2be 275 }
Kojto 170:19eb464bc2be 276
Kojto 170:19eb464bc2be 277 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
Kojto 170:19eb464bc2be 278 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 279 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
Kojto 170:19eb464bc2be 280 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
Kojto 170:19eb464bc2be 281 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
Kojto 170:19eb464bc2be 282 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
Kojto 170:19eb464bc2be 283 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
Kojto 170:19eb464bc2be 284 return 0; // FAIL
Kojto 170:19eb464bc2be 285 }
Kojto 170:19eb464bc2be 286
Kojto 170:19eb464bc2be 287 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
Kojto 170:19eb464bc2be 288 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
Kojto 170:19eb464bc2be 289 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
Kojto 170:19eb464bc2be 290 RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
Kojto 170:19eb464bc2be 291 RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
Kojto 170:19eb464bc2be 292 RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
Kojto 170:19eb464bc2be 293 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
Kojto 170:19eb464bc2be 294 RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
Kojto 170:19eb464bc2be 295 RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
Kojto 170:19eb464bc2be 296 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
Kojto 170:19eb464bc2be 297 return 0; // FAIL
Kojto 170:19eb464bc2be 298 }
Kojto 170:19eb464bc2be 299
Kojto 170:19eb464bc2be 300 // Disable MSI Oscillator
Kojto 170:19eb464bc2be 301 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
Kojto 170:19eb464bc2be 302 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
Kojto 170:19eb464bc2be 303 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
Kojto 170:19eb464bc2be 304 HAL_RCC_OscConfig(&RCC_OscInitStruct);
Kojto 170:19eb464bc2be 305
Kojto 170:19eb464bc2be 306 // Output clock on MCO1 pin(PA8) for debugging purpose
Kojto 170:19eb464bc2be 307 #if DEBUG_MCO == 3
Kojto 170:19eb464bc2be 308 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
Kojto 170:19eb464bc2be 309 #endif
Kojto 170:19eb464bc2be 310
Kojto 170:19eb464bc2be 311 return 1; // OK
Kojto 170:19eb464bc2be 312 }
Kojto 170:19eb464bc2be 313 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
Kojto 170:19eb464bc2be 314
Kojto 170:19eb464bc2be 315 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
Kojto 170:19eb464bc2be 316 /******************************************************************************/
Kojto 170:19eb464bc2be 317 /* PLL (clocked by MSI) used as System clock source */
Kojto 170:19eb464bc2be 318 /******************************************************************************/
Kojto 170:19eb464bc2be 319 uint8_t SetSysClock_PLL_MSI(void)
Kojto 170:19eb464bc2be 320 {
Kojto 170:19eb464bc2be 321 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
Kojto 170:19eb464bc2be 322 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
Kojto 170:19eb464bc2be 323 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
Kojto 170:19eb464bc2be 324
AnnaBridge 188:bcfe06ba3d64 325 #if MBED_CONF_TARGET_LSE_AVAILABLE
Kojto 170:19eb464bc2be 326 // Enable LSE Oscillator to automatically calibrate the MSI clock
Kojto 170:19eb464bc2be 327 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
Kojto 170:19eb464bc2be 328 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
Kojto 170:19eb464bc2be 329 RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
AnnaBridge 188:bcfe06ba3d64 330 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 331 return 0; // FAIL
Kojto 170:19eb464bc2be 332 }
Kojto 170:19eb464bc2be 333
AnnaBridge 188:bcfe06ba3d64 334 /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
Kojto 170:19eb464bc2be 335 HAL_RCCEx_DisableLSECSS();
AnnaBridge 188:bcfe06ba3d64 336 #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
AnnaBridge 188:bcfe06ba3d64 337
Kojto 170:19eb464bc2be 338 /* Enable MSI Oscillator and activate PLL with MSI as source */
Kojto 170:19eb464bc2be 339 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
Kojto 170:19eb464bc2be 340 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
Kojto 170:19eb464bc2be 341 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
Kojto 170:19eb464bc2be 342 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
Kojto 170:19eb464bc2be 343
Kojto 170:19eb464bc2be 344 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
Kojto 170:19eb464bc2be 345 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
Kojto 170:19eb464bc2be 346 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 347 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
Kojto 170:19eb464bc2be 348 RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
Kojto 170:19eb464bc2be 349 RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
Kojto 170:19eb464bc2be 350 RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
Kojto 170:19eb464bc2be 351 RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
Kojto 170:19eb464bc2be 352 RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
Kojto 170:19eb464bc2be 353 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 354 return 0; // FAIL
Kojto 170:19eb464bc2be 355 }
AnnaBridge 188:bcfe06ba3d64 356
AnnaBridge 188:bcfe06ba3d64 357 #if MBED_CONF_TARGET_LSE_AVAILABLE
Kojto 170:19eb464bc2be 358 /* Enable MSI Auto-calibration through LSE */
Kojto 170:19eb464bc2be 359 HAL_RCCEx_EnableMSIPLLMode();
AnnaBridge 188:bcfe06ba3d64 360 #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
AnnaBridge 188:bcfe06ba3d64 361
Kojto 170:19eb464bc2be 362 /* Select MSI output as USB clock source */
Kojto 170:19eb464bc2be 363 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
Kojto 170:19eb464bc2be 364 PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
Kojto 170:19eb464bc2be 365 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
Kojto 170:19eb464bc2be 366 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
Kojto 170:19eb464bc2be 367 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 368 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
Kojto 170:19eb464bc2be 369 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
Kojto 170:19eb464bc2be 370 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
Kojto 170:19eb464bc2be 371 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
Kojto 170:19eb464bc2be 372 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
Kojto 170:19eb464bc2be 373 return 0; // FAIL
Kojto 170:19eb464bc2be 374 }
Kojto 170:19eb464bc2be 375
Kojto 170:19eb464bc2be 376 // Output clock on MCO1 pin(PA8) for debugging purpose
Kojto 170:19eb464bc2be 377 #if DEBUG_MCO == 4
Kojto 170:19eb464bc2be 378 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
Kojto 170:19eb464bc2be 379 #endif
Kojto 170:19eb464bc2be 380
Kojto 170:19eb464bc2be 381 return 1; // OK
Kojto 170:19eb464bc2be 382 }
Kojto 170:19eb464bc2be 383 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */